ia64/xen-unstable

changeset 4844:cd6c145a8f97

bitkeeper revision 1.1389.15.9 (4281c2ffL85lCEE0o1Tvr8CCJWkhGw)

Remove generic pci.h and ioport.h header files.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Wed May 11 08:31:59 2005 +0000 (2005-05-11)
parents fd1fca8ffc95
children 28e8f35313bb ddd290cc8f0d
files .rootkeys xen/arch/x86/mtrr/main.c xen/arch/x86/setup.c xen/common/resource.c xen/include/xen/ioport.h xen/include/xen/pci.h
line diff
     1.1 --- a/.rootkeys	Wed May 11 08:19:17 2005 +0000
     1.2 +++ b/.rootkeys	Wed May 11 08:31:59 2005 +0000
     1.3 @@ -1264,7 +1264,6 @@ 3ddb79bduhSEZI8xa7IbGQCpap5y2A xen/commo
     1.4  41a61536SZbR6cj1ukWTb0DYU-vz9w xen/common/multicall.c
     1.5  3ddb79bdD4SLmmdMD7yLW5HcUWucXw xen/common/page_alloc.c
     1.6  3e54c38dkHAev597bPr71-hGzTdocg xen/common/perfc.c
     1.7 -3ddb79bdHqdQpATqC0rmUZNbsb6L6A xen/common/resource.c
     1.8  40589968dD2D1aejwSOvrROg7fOvGQ xen/common/sched_bvt.c
     1.9  41ebbfe9oF1BF3cH5v7yE3eOL9uPbA xen/common/sched_sedf.c
    1.10  3e397e6619PgAfBbw2XFbXkewvUWgw xen/common/schedule.c
    1.11 @@ -1452,7 +1451,6 @@ 3ddb79c1W0lQca8gRV7sN6j3iY4Luw xen/inclu
    1.12  41262590CyJy4vd42dnqzsn8-eeGvw xen/include/xen/grant_table.h
    1.13  3ddb79c0GurNF9tDWqQbAwJFH8ugfA xen/include/xen/init.h
    1.14  428084e41zemtCAtYLcD9bUzwE35SA xen/include/xen/inttypes.h
    1.15 -3ddb79c1nzaWu8NoF4xCCMSFJR4MlA xen/include/xen/ioport.h
    1.16  3ddb79c2qAxCOABlkKtD8Txohe-qEw xen/include/xen/irq.h
    1.17  3ddb79c2b3qe-6Ann09FqZBF4IrJaQ xen/include/xen/irq_cpustat.h
    1.18  3e4540ccPHqIIv2pvnQ1gV8LUnoHIg xen/include/xen/kernel.h
    1.19 @@ -1462,7 +1460,6 @@ 3ddb79c18Ajy7micDGQQfJ0zWgEHtA xen/inclu
    1.20  3ddb79c1gs2VbLbQlw0dcDUXYIepDA xen/include/xen/mm.h
    1.21  3ddb79c1ieLZfGSFwfvvSQ2NK1BMSg xen/include/xen/multiboot.h
    1.22  41a61536ii6j2lJ2rXwMOLaG1CHPvw xen/include/xen/multicall.h
    1.23 -3ddb79c2Fg44_PBPVxHSC0gTOMq4Ow xen/include/xen/pci.h
    1.24  3ddb79c0MOVXq8qZDQRGb6z64_xAwg xen/include/xen/pci_ids.h
    1.25  3e54c38dlSCVdyVM4PKcrSfzLLxWUQ xen/include/xen/perfc.h
    1.26  3e54c38de9SUSYSAwxDf_DwkpAnQFA xen/include/xen/perfc_defn.h
     2.1 --- a/xen/arch/x86/mtrr/main.c	Wed May 11 08:19:17 2005 +0000
     2.2 +++ b/xen/arch/x86/mtrr/main.c	Wed May 11 08:31:59 2005 +0000
     2.3 @@ -33,7 +33,6 @@
     2.4  
     2.5  #include <xen/config.h>
     2.6  #include <xen/init.h>
     2.7 -#include <xen/pci.h>
     2.8  #include <xen/slab.h>
     2.9  #include <xen/smp.h>
    2.10  #include <xen/spinlock.h>
    2.11 @@ -97,25 +96,6 @@ void set_mtrr_ops(struct mtrr_ops * ops)
    2.12  /*  Returns non-zero if we have the write-combining memory type  */
    2.13  static int have_wrcomb(void)
    2.14  {
    2.15 -	struct pci_dev *dev;
    2.16 -	
    2.17 -	if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
    2.18 -		/* ServerWorks LE chipsets have problems with write-combining 
    2.19 -		   Don't allow it and leave room for other chipsets to be tagged */
    2.20 -		if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
    2.21 -		    dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
    2.22 -			printk(KERN_INFO "mtrr: Serverworks LE detected. Write-combining disabled.\n");
    2.23 -			return 0;
    2.24 -		}
    2.25 -		/* Intel 450NX errata # 23. Non ascending cachline evictions to
    2.26 -		   write combining memory may resulting in data corruption */
    2.27 -		if (dev->vendor == PCI_VENDOR_ID_INTEL &&
    2.28 -		    dev->device == PCI_DEVICE_ID_INTEL_82451NX)
    2.29 -		{
    2.30 -			printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
    2.31 -			return 0;
    2.32 -		}
    2.33 -	}		
    2.34  	return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0);
    2.35  }
    2.36  
     3.1 --- a/xen/arch/x86/setup.c	Wed May 11 08:19:17 2005 +0000
     3.2 +++ b/xen/arch/x86/setup.c	Wed May 11 08:31:59 2005 +0000
     3.3 @@ -3,7 +3,6 @@
     3.4  #include <xen/init.h>
     3.5  #include <xen/lib.h>
     3.6  #include <xen/sched.h>
     3.7 -#include <xen/pci.h>
     3.8  #include <xen/serial.h>
     3.9  #include <xen/softirq.h>
    3.10  #include <xen/acpi.h>
     4.1 --- a/xen/common/resource.c	Wed May 11 08:19:17 2005 +0000
     4.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.3 @@ -1,329 +0,0 @@
     4.4 -/*
     4.5 - *	linux/kernel/resource.c
     4.6 - *
     4.7 - * Copyright (C) 1999	Linus Torvalds
     4.8 - * Copyright (C) 1999	Martin Mares <mj@ucw.cz>
     4.9 - *
    4.10 - * Arbitrary resource management.
    4.11 - */
    4.12 -
    4.13 -#include <xen/config.h>
    4.14 -#include <xen/lib.h>
    4.15 -#include <xen/sched.h>
    4.16 -#include <xen/errno.h>
    4.17 -#include <xen/ioport.h>
    4.18 -#include <xen/init.h>
    4.19 -#include <xen/slab.h>
    4.20 -#include <xen/spinlock.h>
    4.21 -#include <asm/io.h>
    4.22 -
    4.23 -struct resource ioport_resource = { "PCI IO", 0x0000, IO_SPACE_LIMIT, IORESOURCE_IO };
    4.24 -struct resource iomem_resource = { "PCI mem", 0x00000000, 0xffffffff, IORESOURCE_MEM };
    4.25 -
    4.26 -static rwlock_t resource_lock = RW_LOCK_UNLOCKED;
    4.27 -
    4.28 -/*
    4.29 - * This generates reports for /proc/ioports and /proc/iomem
    4.30 - */
    4.31 -static char * do_resource_list(struct resource *entry, const char *fmt, int offset, char *buf, char *end)
    4.32 -{
    4.33 -	if (offset < 0)
    4.34 -		offset = 0;
    4.35 -
    4.36 -	while (entry) {
    4.37 -		const char *name = entry->name;
    4.38 -		unsigned long from, to;
    4.39 -
    4.40 -		if ((int) (end-buf) < 80)
    4.41 -			return buf;
    4.42 -
    4.43 -		from = entry->start;
    4.44 -		to = entry->end;
    4.45 -		if (!name)
    4.46 -			name = "<BAD>";
    4.47 -
    4.48 -		buf += sprintf(buf, fmt + offset, from, to, name);
    4.49 -		if (entry->child)
    4.50 -			buf = do_resource_list(entry->child, fmt, offset-2, buf, end);
    4.51 -		entry = entry->sibling;
    4.52 -	}
    4.53 -
    4.54 -	return buf;
    4.55 -}
    4.56 -
    4.57 -int get_resource_list(struct resource *root, char *buf, int size)
    4.58 -{
    4.59 -	char *fmt;
    4.60 -	int retval;
    4.61 -
    4.62 -	fmt = "        %08lx-%08lx : %s\n";
    4.63 -	if (root->end < 0x10000)
    4.64 -		fmt = "        %04lx-%04lx : %s\n";
    4.65 -	read_lock(&resource_lock);
    4.66 -	retval = do_resource_list(root->child, fmt, 8, buf, buf + size) - buf;
    4.67 -	read_unlock(&resource_lock);
    4.68 -	return retval;
    4.69 -}	
    4.70 -
    4.71 -/* Return the conflict entry if you can't request it */
    4.72 -static struct resource * __request_resource(struct resource *root, struct resource *new)
    4.73 -{
    4.74 -	unsigned long start = new->start;
    4.75 -	unsigned long end = new->end;
    4.76 -	struct resource *tmp, **p;
    4.77 -
    4.78 -	if (end < start)
    4.79 -		return root;
    4.80 -	if (start < root->start)
    4.81 -		return root;
    4.82 -	if (end > root->end)
    4.83 -		return root;
    4.84 -	p = &root->child;
    4.85 -	for (;;) {
    4.86 -		tmp = *p;
    4.87 -		if (!tmp || tmp->start > end) {
    4.88 -			new->sibling = tmp;
    4.89 -			*p = new;
    4.90 -			new->parent = root;
    4.91 -			return NULL;
    4.92 -		}
    4.93 -		p = &tmp->sibling;
    4.94 -		if (tmp->end < start)
    4.95 -			continue;
    4.96 -		return tmp;
    4.97 -	}
    4.98 -}
    4.99 -
   4.100 -static int __release_resource(struct resource *old)
   4.101 -{
   4.102 -	struct resource *tmp, **p;
   4.103 -
   4.104 -	p = &old->parent->child;
   4.105 -	for (;;) {
   4.106 -		tmp = *p;
   4.107 -		if (!tmp)
   4.108 -			break;
   4.109 -		if (tmp == old) {
   4.110 -			*p = tmp->sibling;
   4.111 -			old->parent = NULL;
   4.112 -			return 0;
   4.113 -		}
   4.114 -		p = &tmp->sibling;
   4.115 -	}
   4.116 -	return -EINVAL;
   4.117 -}
   4.118 -
   4.119 -int request_resource(struct resource *root, struct resource *new)
   4.120 -{
   4.121 -	struct resource *conflict;
   4.122 -
   4.123 -	write_lock(&resource_lock);
   4.124 -	conflict = __request_resource(root, new);
   4.125 -	write_unlock(&resource_lock);
   4.126 -	return conflict ? -EBUSY : 0;
   4.127 -}
   4.128 -
   4.129 -int release_resource(struct resource *old)
   4.130 -{
   4.131 -	int retval;
   4.132 -
   4.133 -	write_lock(&resource_lock);
   4.134 -	retval = __release_resource(old);
   4.135 -	write_unlock(&resource_lock);
   4.136 -	return retval;
   4.137 -}
   4.138 -
   4.139 -int check_resource(struct resource *root, unsigned long start, unsigned long len)
   4.140 -{
   4.141 -	struct resource *conflict, tmp;
   4.142 -
   4.143 -	tmp.start = start;
   4.144 -	tmp.end = start + len - 1;
   4.145 -	write_lock(&resource_lock);
   4.146 -	conflict = __request_resource(root, &tmp);
   4.147 -	if (!conflict)
   4.148 -		__release_resource(&tmp);
   4.149 -	write_unlock(&resource_lock);
   4.150 -	return conflict ? -EBUSY : 0;
   4.151 -}
   4.152 -
   4.153 -/*
   4.154 - * Find empty slot in the resource tree given range and alignment.
   4.155 - */
   4.156 -static int find_resource(struct resource *root, struct resource *new,
   4.157 -			 unsigned long size,
   4.158 -			 unsigned long min, unsigned long max,
   4.159 -			 unsigned long align,
   4.160 -			 void (*alignf)(void *, struct resource *,
   4.161 -					unsigned long, unsigned long),
   4.162 -			 void *alignf_data)
   4.163 -{
   4.164 -	struct resource *this = root->child;
   4.165 -
   4.166 -	new->start = root->start;
   4.167 -	for(;;) {
   4.168 -		if (this)
   4.169 -			new->end = this->start;
   4.170 -		else
   4.171 -			new->end = root->end;
   4.172 -		if (new->start < min)
   4.173 -			new->start = min;
   4.174 -		if (new->end > max)
   4.175 -			new->end = max;
   4.176 -		new->start = (new->start + align - 1) & ~(align - 1);
   4.177 -		if (alignf)
   4.178 -			alignf(alignf_data, new, size, align);
   4.179 -		if (new->start < new->end && new->end - new->start + 1 >= size) {
   4.180 -			new->end = new->start + size - 1;
   4.181 -			return 0;
   4.182 -		}
   4.183 -		if (!this)
   4.184 -			break;
   4.185 -		new->start = this->end + 1;
   4.186 -		this = this->sibling;
   4.187 -	}
   4.188 -	return -EBUSY;
   4.189 -}
   4.190 -
   4.191 -/*
   4.192 - * Allocate empty slot in the resource tree given range and alignment.
   4.193 - */
   4.194 -int allocate_resource(struct resource *root, struct resource *new,
   4.195 -		      unsigned long size,
   4.196 -		      unsigned long min, unsigned long max,
   4.197 -		      unsigned long align,
   4.198 -		      void (*alignf)(void *, struct resource *,
   4.199 -				     unsigned long, unsigned long),
   4.200 -		      void *alignf_data)
   4.201 -{
   4.202 -	int err;
   4.203 -
   4.204 -	write_lock(&resource_lock);
   4.205 -	err = find_resource(root, new, size, min, max, align, alignf, alignf_data);
   4.206 -	if (err >= 0 && __request_resource(root, new))
   4.207 -		err = -EBUSY;
   4.208 -	write_unlock(&resource_lock);
   4.209 -	return err;
   4.210 -}
   4.211 -
   4.212 -/*
   4.213 - * This is compatibility stuff for IO resources.
   4.214 - *
   4.215 - * Note how this, unlike the above, knows about
   4.216 - * the IO flag meanings (busy etc).
   4.217 - *
   4.218 - * Request-region creates a new busy region.
   4.219 - *
   4.220 - * Check-region returns non-zero if the area is already busy
   4.221 - *
   4.222 - * Release-region releases a matching busy region.
   4.223 - */
   4.224 -struct resource * __request_region(struct resource *parent, unsigned long start, unsigned long n, const char *name)
   4.225 -{
   4.226 -	struct resource *res = xmalloc(struct resource);
   4.227 -
   4.228 -	if (res) {
   4.229 -		memset(res, 0, sizeof(*res));
   4.230 -		res->name = name;
   4.231 -		res->start = start;
   4.232 -		res->end = start + n - 1;
   4.233 -		res->flags = IORESOURCE_BUSY;
   4.234 -
   4.235 -		write_lock(&resource_lock);
   4.236 -
   4.237 -		for (;;) {
   4.238 -			struct resource *conflict;
   4.239 -
   4.240 -			conflict = __request_resource(parent, res);
   4.241 -			if (!conflict)
   4.242 -				break;
   4.243 -			if (conflict != parent) {
   4.244 -				parent = conflict;
   4.245 -				if (!(conflict->flags & IORESOURCE_BUSY))
   4.246 -					continue;
   4.247 -			}
   4.248 -
   4.249 -			/* Uhhuh, that didn't work out.. */
   4.250 -			xfree(res);
   4.251 -			res = NULL;
   4.252 -			break;
   4.253 -		}
   4.254 -		write_unlock(&resource_lock);
   4.255 -	}
   4.256 -	return res;
   4.257 -}
   4.258 -
   4.259 -void __release_region(struct resource *parent, unsigned long start, unsigned long n)
   4.260 -{
   4.261 -	struct resource **p;
   4.262 -	unsigned long end;
   4.263 -
   4.264 -	p = &parent->child;
   4.265 -	end = start + n - 1;
   4.266 -
   4.267 -	for (;;) {
   4.268 -		struct resource *res = *p;
   4.269 -
   4.270 -		if (!res)
   4.271 -			break;
   4.272 -		if (res->start <= start && res->end >= end) {
   4.273 -			if (!(res->flags & IORESOURCE_BUSY)) {
   4.274 -				p = &res->child;
   4.275 -				continue;
   4.276 -			}
   4.277 -			if (res->start != start || res->end != end)
   4.278 -				break;
   4.279 -			*p = res->sibling;
   4.280 -			xfree(res);
   4.281 -			return;
   4.282 -		}
   4.283 -		p = &res->sibling;
   4.284 -	}
   4.285 -	printk("Trying to free nonexistent resource <%08lx-%08lx>\n", start, end);
   4.286 -}
   4.287 -
   4.288 -
   4.289 -#if 0
   4.290 -/*
   4.291 - * Called from init/main.c to reserve IO ports.
   4.292 - */
   4.293 -#define MAXRESERVE 4
   4.294 -static int __init reserve_setup(char *str)
   4.295 -{
   4.296 -	static int reserved = 0;
   4.297 -	static struct resource reserve[MAXRESERVE];
   4.298 -
   4.299 -	for (;;) {
   4.300 -		int io_start, io_num;
   4.301 -		int x = reserved;
   4.302 -
   4.303 -		if (get_option (&str, &io_start) != 2)
   4.304 -			break;
   4.305 -		if (get_option (&str, &io_num)   == 0)
   4.306 -			break;
   4.307 -		if (x < MAXRESERVE) {
   4.308 -			struct resource *res = reserve + x;
   4.309 -			res->name = "reserved";
   4.310 -			res->start = io_start;
   4.311 -			res->end = io_start + io_num - 1;
   4.312 -			res->flags = IORESOURCE_BUSY;
   4.313 -			res->child = NULL;
   4.314 -			if (request_resource(res->start >= 0x10000 ? &iomem_resource : &ioport_resource, res) == 0)
   4.315 -				reserved = x+1;
   4.316 -		}
   4.317 -	}
   4.318 -	return 1;
   4.319 -}
   4.320 -
   4.321 -__setup("reserve=", reserve_setup);
   4.322 -#endif
   4.323 -
   4.324 -/*
   4.325 - * Local variables:
   4.326 - * mode: C
   4.327 - * c-set-style: "BSD"
   4.328 - * c-basic-offset: 8
   4.329 - * tab-width: 8
   4.330 - * indent-tabs-mode: t
   4.331 - * End:
   4.332 - */
     5.1 --- a/xen/include/xen/ioport.h	Wed May 11 08:19:17 2005 +0000
     5.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.3 @@ -1,117 +0,0 @@
     5.4 -/*
     5.5 - * ioport.h	Definitions of routines for detecting, reserving and
     5.6 - *		allocating system resources.
     5.7 - *
     5.8 - * Authors:	Linus Torvalds
     5.9 - */
    5.10 -
    5.11 -#ifndef _LINUX_IOPORT_H
    5.12 -#define _LINUX_IOPORT_H
    5.13 -
    5.14 -/*
    5.15 - * Resources are tree-like, allowing
    5.16 - * nesting etc..
    5.17 - */
    5.18 -struct resource {
    5.19 -	const char *name;
    5.20 -	unsigned long start, end;
    5.21 -	unsigned long flags;
    5.22 -	struct resource *parent, *sibling, *child;
    5.23 -};
    5.24 -
    5.25 -struct resource_list {
    5.26 -	struct resource_list *next;
    5.27 -	struct resource *res;
    5.28 -	struct pci_dev *dev;
    5.29 -};
    5.30 -
    5.31 -/*
    5.32 - * IO resources have these defined flags.
    5.33 - */
    5.34 -#define IORESOURCE_BITS		0x000000ff	/* Bus-specific bits */
    5.35 -
    5.36 -#define IORESOURCE_IO		0x00000100	/* Resource type */
    5.37 -#define IORESOURCE_MEM		0x00000200
    5.38 -#define IORESOURCE_IRQ		0x00000400
    5.39 -#define IORESOURCE_DMA		0x00000800
    5.40 -
    5.41 -#define IORESOURCE_PREFETCH	0x00001000	/* No side effects */
    5.42 -#define IORESOURCE_READONLY	0x00002000
    5.43 -#define IORESOURCE_CACHEABLE	0x00004000
    5.44 -#define IORESOURCE_RANGELENGTH	0x00008000
    5.45 -#define IORESOURCE_SHADOWABLE	0x00010000
    5.46 -#define IORESOURCE_BUS_HAS_VGA	0x00080000
    5.47 -
    5.48 -#define IORESOURCE_UNSET	0x20000000
    5.49 -#define IORESOURCE_AUTO		0x40000000
    5.50 -#define IORESOURCE_BUSY		0x80000000	/* Driver has marked this resource busy */
    5.51 -
    5.52 -/* ISA PnP IRQ specific bits (IORESOURCE_BITS) */
    5.53 -#define IORESOURCE_IRQ_HIGHEDGE		(1<<0)
    5.54 -#define IORESOURCE_IRQ_LOWEDGE		(1<<1)
    5.55 -#define IORESOURCE_IRQ_HIGHLEVEL	(1<<2)
    5.56 -#define IORESOURCE_IRQ_LOWLEVEL		(1<<3)
    5.57 -
    5.58 -/* ISA PnP DMA specific bits (IORESOURCE_BITS) */
    5.59 -#define IORESOURCE_DMA_TYPE_MASK	(3<<0)
    5.60 -#define IORESOURCE_DMA_8BIT		(0<<0)
    5.61 -#define IORESOURCE_DMA_8AND16BIT	(1<<0)
    5.62 -#define IORESOURCE_DMA_16BIT		(2<<0)
    5.63 -
    5.64 -#define IORESOURCE_DMA_MASTER		(1<<2)
    5.65 -#define IORESOURCE_DMA_BYTE		(1<<3)
    5.66 -#define IORESOURCE_DMA_WORD		(1<<4)
    5.67 -
    5.68 -#define IORESOURCE_DMA_SPEED_MASK	(3<<6)
    5.69 -#define IORESOURCE_DMA_COMPATIBLE	(0<<6)
    5.70 -#define IORESOURCE_DMA_TYPEA		(1<<6)
    5.71 -#define IORESOURCE_DMA_TYPEB		(2<<6)
    5.72 -#define IORESOURCE_DMA_TYPEF		(3<<6)
    5.73 -
    5.74 -/* ISA PnP memory I/O specific bits (IORESOURCE_BITS) */
    5.75 -#define IORESOURCE_MEM_WRITEABLE	(1<<0)	/* dup: IORESOURCE_READONLY */
    5.76 -#define IORESOURCE_MEM_CACHEABLE	(1<<1)	/* dup: IORESOURCE_CACHEABLE */
    5.77 -#define IORESOURCE_MEM_RANGELENGTH	(1<<2)	/* dup: IORESOURCE_RANGELENGTH */
    5.78 -#define IORESOURCE_MEM_TYPE_MASK	(3<<3)
    5.79 -#define IORESOURCE_MEM_8BIT		(0<<3)
    5.80 -#define IORESOURCE_MEM_16BIT		(1<<3)
    5.81 -#define IORESOURCE_MEM_8AND16BIT	(2<<3)
    5.82 -#define IORESOURCE_MEM_SHADOWABLE	(1<<5)	/* dup: IORESOURCE_SHADOWABLE */
    5.83 -#define IORESOURCE_MEM_EXPANSIONROM	(1<<6)
    5.84 -
    5.85 -/* PC/ISA/whatever - the normal PC address spaces: IO and memory */
    5.86 -extern struct resource ioport_resource;
    5.87 -extern struct resource iomem_resource;
    5.88 -
    5.89 -extern int get_resource_list(struct resource *, char *buf, int size);
    5.90 -
    5.91 -extern int check_resource(struct resource *root, unsigned long, unsigned long);
    5.92 -extern int request_resource(struct resource *root, struct resource *new);
    5.93 -extern int release_resource(struct resource *new);
    5.94 -extern int allocate_resource(struct resource *root, struct resource *new,
    5.95 -			     unsigned long size,
    5.96 -			     unsigned long min, unsigned long max,
    5.97 -			     unsigned long align,
    5.98 -			     void (*alignf)(void *, struct resource *,
    5.99 -					    unsigned long, unsigned long),
   5.100 -			     void *alignf_data);
   5.101 -
   5.102 -/* Convenience shorthand with allocation */
   5.103 -#define request_region(start,n,name)	__request_region(&ioport_resource, (start), (n), (name))
   5.104 -#define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name))
   5.105 -
   5.106 -#define release_region(start,n)	__release_region(&ioport_resource, (start), (n))
   5.107 -#define release_mem_region(start,n)	__release_region(&iomem_resource, (start), (n))
   5.108 -
   5.109 -extern void __release_region(struct resource *, unsigned long, unsigned long);
   5.110 -
   5.111 -extern struct resource * __request_region(struct resource *, unsigned long start, unsigned long n, const char *name);
   5.112 -
   5.113 -#define get_ioport_list(buf)	get_resource_list(&ioport_resource, buf, PAGE_SIZE)
   5.114 -#define get_mem_list(buf)	get_resource_list(&iomem_resource, buf, PAGE_SIZE)
   5.115 -
   5.116 -#define HAVE_AUTOIRQ
   5.117 -extern void autoirq_setup(int waittime);
   5.118 -extern int autoirq_report(int waittime);
   5.119 -
   5.120 -#endif	/* _LINUX_IOPORT_H */
     6.1 --- a/xen/include/xen/pci.h	Wed May 11 08:19:17 2005 +0000
     6.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.3 @@ -1,834 +0,0 @@
     6.4 -/*
     6.5 - *	$Id: pci.h,v 1.87 1998/10/11 15:13:12 mj Exp $
     6.6 - *
     6.7 - *	PCI defines and function prototypes
     6.8 - *	Copyright 1994, Drew Eckhardt
     6.9 - *	Copyright 1997--1999 Martin Mares <mj@ucw.cz>
    6.10 - *
    6.11 - *	For more information, please consult the following manuals (look at
    6.12 - *	http://www.pcisig.com/ for how to get them):
    6.13 - *
    6.14 - *	PCI BIOS Specification
    6.15 - *	PCI Local Bus Specification
    6.16 - *	PCI to PCI Bridge Specification
    6.17 - *	PCI System Design Guide
    6.18 - */
    6.19 -
    6.20 -#ifndef LINUX_PCI_H
    6.21 -#define LINUX_PCI_H
    6.22 -
    6.23 -/*
    6.24 - * Under PCI, each device has 256 bytes of configuration address space,
    6.25 - * of which the first 64 bytes are standardized as follows:
    6.26 - */
    6.27 -#define PCI_VENDOR_ID		0x00	/* 16 bits */
    6.28 -#define PCI_DEVICE_ID		0x02	/* 16 bits */
    6.29 -#define PCI_COMMAND		0x04	/* 16 bits */
    6.30 -#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
    6.31 -#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
    6.32 -#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
    6.33 -#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
    6.34 -#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
    6.35 -#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
    6.36 -#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
    6.37 -#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
    6.38 -#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
    6.39 -#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
    6.40 -
    6.41 -#define PCI_STATUS		0x06	/* 16 bits */
    6.42 -#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
    6.43 -#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
    6.44 -#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
    6.45 -#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
    6.46 -#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
    6.47 -#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
    6.48 -#define  PCI_STATUS_DEVSEL_FAST	0x000	
    6.49 -#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
    6.50 -#define  PCI_STATUS_DEVSEL_SLOW 0x400
    6.51 -#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
    6.52 -#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
    6.53 -#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
    6.54 -#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
    6.55 -#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
    6.56 -
    6.57 -#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
    6.58 -					   revision */
    6.59 -#define PCI_REVISION_ID         0x08    /* Revision ID */
    6.60 -#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
    6.61 -#define PCI_CLASS_DEVICE        0x0a    /* Device class */
    6.62 -
    6.63 -#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
    6.64 -#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
    6.65 -#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
    6.66 -#define  PCI_HEADER_TYPE_NORMAL	0
    6.67 -#define  PCI_HEADER_TYPE_BRIDGE 1
    6.68 -#define  PCI_HEADER_TYPE_CARDBUS 2
    6.69 -
    6.70 -#define PCI_BIST		0x0f	/* 8 bits */
    6.71 -#define  PCI_BIST_CODE_MASK	0x0f	/* Return result */
    6.72 -#define  PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
    6.73 -#define  PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
    6.74 -
    6.75 -/*
    6.76 - * Base addresses specify locations in memory or I/O space.
    6.77 - * Decoded size can be determined by writing a value of 
    6.78 - * 0xffffffff to the register, and reading it back.  Only 
    6.79 - * 1 bits are decoded.
    6.80 - */
    6.81 -#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
    6.82 -#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
    6.83 -#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
    6.84 -#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
    6.85 -#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
    6.86 -#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
    6.87 -#define  PCI_BASE_ADDRESS_SPACE	0x01	/* 0 = memory, 1 = I/O */
    6.88 -#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
    6.89 -#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
    6.90 -#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
    6.91 -#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
    6.92 -#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
    6.93 -#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
    6.94 -#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
    6.95 -#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
    6.96 -#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
    6.97 -/* bit 1 is reserved if address_space = 1 */
    6.98 -
    6.99 -/* Header type 0 (normal devices) */
   6.100 -#define PCI_CARDBUS_CIS		0x28
   6.101 -#define PCI_SUBSYSTEM_VENDOR_ID	0x2c
   6.102 -#define PCI_SUBSYSTEM_ID	0x2e  
   6.103 -#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
   6.104 -#define  PCI_ROM_ADDRESS_ENABLE	0x01
   6.105 -#define PCI_ROM_ADDRESS_MASK	(~0x7ffUL)
   6.106 -
   6.107 -#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
   6.108 -
   6.109 -/* 0x35-0x3b are reserved */
   6.110 -#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
   6.111 -#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
   6.112 -#define PCI_MIN_GNT		0x3e	/* 8 bits */
   6.113 -#define PCI_MAX_LAT		0x3f	/* 8 bits */
   6.114 -
   6.115 -/* Header type 1 (PCI-to-PCI bridges) */
   6.116 -#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
   6.117 -#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
   6.118 -#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
   6.119 -#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
   6.120 -#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
   6.121 -#define PCI_IO_LIMIT		0x1d
   6.122 -#define  PCI_IO_RANGE_TYPE_MASK	0x0fUL	/* I/O bridging type */
   6.123 -#define  PCI_IO_RANGE_TYPE_16	0x00
   6.124 -#define  PCI_IO_RANGE_TYPE_32	0x01
   6.125 -#define  PCI_IO_RANGE_MASK	(~0x0fUL)
   6.126 -#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
   6.127 -#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
   6.128 -#define PCI_MEMORY_LIMIT	0x22
   6.129 -#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
   6.130 -#define  PCI_MEMORY_RANGE_MASK	(~0x0fUL)
   6.131 -#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
   6.132 -#define PCI_PREF_MEMORY_LIMIT	0x26
   6.133 -#define  PCI_PREF_RANGE_TYPE_MASK 0x0fUL
   6.134 -#define  PCI_PREF_RANGE_TYPE_32	0x00
   6.135 -#define  PCI_PREF_RANGE_TYPE_64	0x01
   6.136 -#define  PCI_PREF_RANGE_MASK	(~0x0fUL)
   6.137 -#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
   6.138 -#define PCI_PREF_LIMIT_UPPER32	0x2c
   6.139 -#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
   6.140 -#define PCI_IO_LIMIT_UPPER16	0x32
   6.141 -/* 0x34 same as for htype 0 */
   6.142 -/* 0x35-0x3b is reserved */
   6.143 -#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
   6.144 -/* 0x3c-0x3d are same as for htype 0 */
   6.145 -#define PCI_BRIDGE_CONTROL	0x3e
   6.146 -#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
   6.147 -#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
   6.148 -#define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */
   6.149 -#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
   6.150 -#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
   6.151 -#define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
   6.152 -#define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */
   6.153 -
   6.154 -/* Header type 2 (CardBus bridges) */
   6.155 -#define PCI_CB_CAPABILITY_LIST	0x14
   6.156 -/* 0x15 reserved */
   6.157 -#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
   6.158 -#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
   6.159 -#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
   6.160 -#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
   6.161 -#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
   6.162 -#define PCI_CB_MEMORY_BASE_0	0x1c
   6.163 -#define PCI_CB_MEMORY_LIMIT_0	0x20
   6.164 -#define PCI_CB_MEMORY_BASE_1	0x24
   6.165 -#define PCI_CB_MEMORY_LIMIT_1	0x28
   6.166 -#define PCI_CB_IO_BASE_0	0x2c
   6.167 -#define PCI_CB_IO_BASE_0_HI	0x2e
   6.168 -#define PCI_CB_IO_LIMIT_0	0x30
   6.169 -#define PCI_CB_IO_LIMIT_0_HI	0x32
   6.170 -#define PCI_CB_IO_BASE_1	0x34
   6.171 -#define PCI_CB_IO_BASE_1_HI	0x36
   6.172 -#define PCI_CB_IO_LIMIT_1	0x38
   6.173 -#define PCI_CB_IO_LIMIT_1_HI	0x3a
   6.174 -#define  PCI_CB_IO_RANGE_MASK	(~0x03UL)
   6.175 -/* 0x3c-0x3d are same as for htype 0 */
   6.176 -#define PCI_CB_BRIDGE_CONTROL	0x3e
   6.177 -#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
   6.178 -#define  PCI_CB_BRIDGE_CTL_SERR		0x02
   6.179 -#define  PCI_CB_BRIDGE_CTL_ISA		0x04
   6.180 -#define  PCI_CB_BRIDGE_CTL_VGA		0x08
   6.181 -#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT	0x20
   6.182 -#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
   6.183 -#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
   6.184 -#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
   6.185 -#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
   6.186 -#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
   6.187 -#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
   6.188 -#define PCI_CB_SUBSYSTEM_ID	0x42
   6.189 -#define PCI_CB_LEGACY_MODE_BASE	0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
   6.190 -/* 0x48-0x7f reserved */
   6.191 -
   6.192 -/* Capability lists */
   6.193 -
   6.194 -#define PCI_CAP_LIST_ID		0	/* Capability ID */
   6.195 -#define  PCI_CAP_ID_PM		0x01	/* Power Management */
   6.196 -#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
   6.197 -#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
   6.198 -#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
   6.199 -#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
   6.200 -#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
   6.201 -#define  PCI_CAP_ID_PCIX	0x07	/* PCI-X */
   6.202 -#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
   6.203 -#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
   6.204 -#define PCI_CAP_SIZEOF		4
   6.205 -
   6.206 -/* Power Management Registers */
   6.207 -
   6.208 -#define PCI_PM_PMC              2       /* PM Capabilities Register */
   6.209 -#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
   6.210 -#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
   6.211 -#define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
   6.212 -#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
   6.213 -#define  PCI_PM_CAP_AUX_POWER	0x01C0	/* Auxilliary power support mask */
   6.214 -#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
   6.215 -#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
   6.216 -#define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
   6.217 -#define  PCI_PM_CAP_PME_MASK    0xF800  /* PME Mask of all supported states */
   6.218 -#define  PCI_PM_CAP_PME_D0      0x0800  /* PME# from D0 */
   6.219 -#define  PCI_PM_CAP_PME_D1      0x1000  /* PME# from D1 */
   6.220 -#define  PCI_PM_CAP_PME_D2      0x2000  /* PME# from D2 */
   6.221 -#define  PCI_PM_CAP_PME_D3      0x4000  /* PME# from D3 (hot) */
   6.222 -#define  PCI_PM_CAP_PME_D3cold  0x8000  /* PME# from D3 (cold) */
   6.223 -#define PCI_PM_CTRL		4	/* PM control and status register */
   6.224 -#define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
   6.225 -#define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
   6.226 -#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
   6.227 -#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
   6.228 -#define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
   6.229 -#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
   6.230 -#define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
   6.231 -#define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
   6.232 -#define PCI_PM_DATA_REGISTER	7	/* (??) */
   6.233 -#define PCI_PM_SIZEOF		8
   6.234 -
   6.235 -/* AGP registers */
   6.236 -
   6.237 -#define PCI_AGP_VERSION		2	/* BCD version number */
   6.238 -#define PCI_AGP_RFU		3	/* Rest of capability flags */
   6.239 -#define PCI_AGP_STATUS		4	/* Status register */
   6.240 -#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
   6.241 -#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
   6.242 -#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
   6.243 -#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
   6.244 -#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
   6.245 -#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
   6.246 -#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
   6.247 -#define PCI_AGP_COMMAND		8	/* Control register */
   6.248 -#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
   6.249 -#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
   6.250 -#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
   6.251 -#define  PCI_AGP_COMMAND_64BIT	0x0020 	/* Allow processing of 64-bit addresses */
   6.252 -#define  PCI_AGP_COMMAND_FW	0x0010 	/* Force FW transfers */
   6.253 -#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
   6.254 -#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 2x rate */
   6.255 -#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 1x rate */
   6.256 -#define PCI_AGP_SIZEOF		12
   6.257 -
   6.258 -/* Slot Identification */
   6.259 -
   6.260 -#define PCI_SID_ESR		2	/* Expansion Slot Register */
   6.261 -#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
   6.262 -#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
   6.263 -#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
   6.264 -
   6.265 -/* Message Signalled Interrupts registers */
   6.266 -
   6.267 -#define PCI_MSI_FLAGS		2	/* Various flags */
   6.268 -#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
   6.269 -#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
   6.270 -#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
   6.271 -#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
   6.272 -#define PCI_MSI_RFU		3	/* Rest of capability flags */
   6.273 -#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
   6.274 -#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
   6.275 -#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
   6.276 -#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
   6.277 -
   6.278 -/* CompactPCI Hotswap Register */
   6.279 -
   6.280 -#define PCI_CHSWP_CSR		2	/* Control and Status Register */
   6.281 -#define  PCI_CHSWP_DHA		0x01	/* Device Hiding Arm */
   6.282 -#define  PCI_CHSWP_EIM		0x02	/* ENUM# Signal Mask */
   6.283 -#define  PCI_CHSWP_PIE		0x04	/* Pending Insert or Extract */
   6.284 -#define  PCI_CHSWP_LOO		0x08	/* LED On / Off */
   6.285 -#define  PCI_CHSWP_PI		0x30	/* Programming Interface */
   6.286 -#define  PCI_CHSWP_EXT		0x40	/* ENUM# status - extraction */
   6.287 -#define  PCI_CHSWP_INS		0x80	/* ENUM# status - insertion */
   6.288 -
   6.289 -/* PCI-X registers */
   6.290 -
   6.291 -#define PCI_X_CMD		2	/* Modes & Features */
   6.292 -#define  PCI_X_CMD_DPERR_E	0x0001	/* Data Parity Error Recovery Enable */
   6.293 -#define  PCI_X_CMD_ERO		0x0002	/* Enable Relaxed Ordering */
   6.294 -#define  PCI_X_CMD_MAX_READ	0x000c	/* Max Memory Read Byte Count */
   6.295 -#define  PCI_X_CMD_MAX_SPLIT	0x0070	/* Max Outstanding Split Transactions */
   6.296 -#define PCI_X_DEVFN		4	/* A copy of devfn. */
   6.297 -#define PCI_X_BUSNR		5	/* Bus segment number */
   6.298 -#define PCI_X_STATUS		6	/* PCI-X capabilities */
   6.299 -#define  PCI_X_STATUS_64BIT	0x0001	/* 64-bit device */
   6.300 -#define  PCI_X_STATUS_133MHZ	0x0002	/* 133 MHz capable */
   6.301 -#define  PCI_X_STATUS_SPL_DISC	0x0004	/* Split Completion Discarded */
   6.302 -#define  PCI_X_STATUS_UNX_SPL	0x0008	/* Unexpected Split Completion */
   6.303 -#define  PCI_X_STATUS_COMPLEX	0x0010	/* Device Complexity */
   6.304 -#define  PCI_X_STATUS_MAX_READ	0x0060	/* Designed Maximum Memory Read Count */
   6.305 -#define  PCI_X_STATUS_MAX_SPLIT	0x0380	/* Design Max Outstanding Split Trans */
   6.306 -#define  PCI_X_STATUS_MAX_CUM	0x1c00	/* Designed Max Cumulative Read Size */
   6.307 -#define  PCI_X_STATUS_SPL_ERR	0x2000	/* Rcvd Split Completion Error Msg */
   6.308 -
   6.309 -/* Include the ID list */
   6.310 -
   6.311 -#include <xen/pci_ids.h>
   6.312 -
   6.313 -/*
   6.314 - * The PCI interface treats multi-function devices as independent
   6.315 - * devices.  The slot/function address of each device is encoded
   6.316 - * in a single byte as follows:
   6.317 - *
   6.318 - *	7:3 = slot
   6.319 - *	2:0 = function
   6.320 - */
   6.321 -#define PCI_DEVFN(slot,func)	((((slot) & 0x1f) << 3) | ((func) & 0x07))
   6.322 -#define PCI_SLOT(devfn)		(((devfn) >> 3) & 0x1f)
   6.323 -#define PCI_FUNC(devfn)		((devfn) & 0x07)
   6.324 -
   6.325 -/* Ioctls for /proc/bus/pci/X/Y nodes. */
   6.326 -#define PCIIOC_BASE		('P' << 24 | 'C' << 16 | 'I' << 8)
   6.327 -#define PCIIOC_CONTROLLER	(PCIIOC_BASE | 0x00)	/* Get controller for PCI device. */
   6.328 -#define PCIIOC_MMAP_IS_IO	(PCIIOC_BASE | 0x01)	/* Set mmap state to I/O space. */
   6.329 -#define PCIIOC_MMAP_IS_MEM	(PCIIOC_BASE | 0x02)	/* Set mmap state to MEM space. */
   6.330 -#define PCIIOC_WRITE_COMBINE	(PCIIOC_BASE | 0x03)	/* Enable/disable write-combining. */
   6.331 -
   6.332 -#include <xen/types.h>
   6.333 -#include <xen/config.h>
   6.334 -#include <xen/ioport.h>
   6.335 -#include <xen/list.h>
   6.336 -#include <xen/errno.h>
   6.337 -
   6.338 -/* File state for mmap()s on /proc/bus/pci/X/Y */
   6.339 -enum pci_mmap_state {
   6.340 -	pci_mmap_io,
   6.341 -	pci_mmap_mem
   6.342 -};
   6.343 -
   6.344 -/* This defines the direction arg to the DMA mapping routines. */
   6.345 -#define PCI_DMA_BIDIRECTIONAL	0
   6.346 -#define PCI_DMA_TODEVICE	1
   6.347 -#define PCI_DMA_FROMDEVICE	2
   6.348 -#define PCI_DMA_NONE		3
   6.349 -
   6.350 -#define DEVICE_COUNT_COMPATIBLE	4
   6.351 -#define DEVICE_COUNT_IRQ	2
   6.352 -#define DEVICE_COUNT_DMA	2
   6.353 -#define DEVICE_COUNT_RESOURCE	12
   6.354 -
   6.355 -#define PCI_ANY_ID (~0)
   6.356 -
   6.357 -#define pci_present pcibios_present
   6.358 -
   6.359 -
   6.360 -#define pci_for_each_dev_reverse(dev) \
   6.361 -	for(dev = pci_dev_g(pci_devices.prev); dev != pci_dev_g(&pci_devices); dev = pci_dev_g(dev->global_list.prev))
   6.362 -
   6.363 -#define pci_for_each_bus(bus) \
   6.364 -	list_for_each_entry(bus, &pci_root_buses, node)
   6.365 -
   6.366 -/*
   6.367 - * The pci_dev structure is used to describe both PCI and ISAPnP devices.
   6.368 - */
   6.369 -struct pci_dev {
   6.370 -	struct list_head global_list;	/* node in list of all PCI devices */
   6.371 -	struct list_head bus_list;	/* node in per-bus list */
   6.372 -	struct pci_bus	*bus;		/* bus this device is on */
   6.373 -	struct pci_bus	*subordinate;	/* bus this device bridges to */
   6.374 -
   6.375 -	void		*sysdata;	/* hook for sys-specific extension */
   6.376 -	struct proc_dir_entry *procent;	/* device entry in /proc/bus/pci */
   6.377 -
   6.378 -	unsigned int	devfn;		/* encoded device & function index */
   6.379 -	unsigned short	vendor;
   6.380 -	unsigned short	device;
   6.381 -	unsigned short	subsystem_vendor;
   6.382 -	unsigned short	subsystem_device;
   6.383 -	unsigned int	class;		/* 3 bytes: (base,sub,prog-if) */
   6.384 -	u8		hdr_type;	/* PCI header type (`multi' flag masked out) */
   6.385 -	u8		rom_base_reg;	/* which config register controls the ROM */
   6.386 -
   6.387 -	struct pci_driver *driver;	/* which driver has allocated this device */
   6.388 -	void		*driver_data;	/* data private to the driver */
   6.389 -	u64		dma_mask;	/* Mask of the bits of bus address this
   6.390 -					   device implements.  Normally this is
   6.391 -					   0xffffffff.  You only need to change
   6.392 -					   this if your device has broken DMA
   6.393 -					   or supports 64-bit transfers.  */
   6.394 -
   6.395 -	u32             current_state;  /* Current operating state. In ACPI-speak,
   6.396 -					   this is D0-D3, D0 being fully functional,
   6.397 -					   and D3 being off. */
   6.398 -
   6.399 -#ifdef LINUX_2_6
   6.400 -	struct device dev;		/* Generic device interface */
   6.401 -#endif
   6.402 -
   6.403 -	/* device is compatible with these IDs */
   6.404 -	unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
   6.405 -	unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
   6.406 -
   6.407 -	/*
   6.408 -	 * Instead of touching interrupt line and base address registers
   6.409 -	 * directly, use the values stored here. They might be different!
   6.410 -	 */
   6.411 -	unsigned int	irq;
   6.412 -	struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
   6.413 -	struct resource dma_resource[DEVICE_COUNT_DMA];
   6.414 -	struct resource irq_resource[DEVICE_COUNT_IRQ];
   6.415 -
   6.416 -	char		name[90];	/* device name */
   6.417 -	char		slot_name[8];	/* slot name */
   6.418 -	int		active;		/* ISAPnP: device is active */
   6.419 -	int		ro;		/* ISAPnP: read only */
   6.420 -	unsigned short	regs;		/* ISAPnP: supported registers */
   6.421 -
   6.422 -	/* These fields are used by common fixups */
   6.423 -	unsigned short	transparent:1;	/* Transparent PCI bridge */
   6.424 -
   6.425 -	int (*prepare)(struct pci_dev *dev);	/* ISAPnP hooks */
   6.426 -	int (*activate)(struct pci_dev *dev);
   6.427 -	int (*deactivate)(struct pci_dev *dev);
   6.428 -};
   6.429 -
   6.430 -#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
   6.431 -#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
   6.432 -
   6.433 -/*
   6.434 - *  For PCI devices, the region numbers are assigned this way:
   6.435 - *
   6.436 - *	0-5	standard PCI regions
   6.437 - *	6	expansion ROM
   6.438 - *	7-10	bridges: address space assigned to buses behind the bridge
   6.439 - */
   6.440 -
   6.441 -#define PCI_ROM_RESOURCE 6
   6.442 -#define PCI_BRIDGE_RESOURCES 7
   6.443 -#define PCI_NUM_RESOURCES 11
   6.444 -  
   6.445 -#define PCI_REGION_FLAG_MASK 0x0fU	/* These bits of resource flags tell us the PCI region flags */
   6.446 -
   6.447 -struct pci_bus {
   6.448 -	struct list_head node;		/* node in list of buses */
   6.449 -	struct pci_bus	*parent;	/* parent bus this bridge is on */
   6.450 -	struct list_head children;	/* list of child buses */
   6.451 -	struct list_head devices;	/* list of devices on this bus */
   6.452 -	struct pci_dev	*self;		/* bridge device as seen by parent */
   6.453 -	struct resource	*resource[4];	/* address space routed to this bus */
   6.454 -
   6.455 -	struct pci_ops	*ops;		/* configuration access functions */
   6.456 -	void		*sysdata;	/* hook for sys-specific extension */
   6.457 -	struct proc_dir_entry *procdir;	/* directory entry in /proc/bus/pci */
   6.458 -
   6.459 -	unsigned char	number;		/* bus number */
   6.460 -	unsigned char	primary;	/* number of primary bridge */
   6.461 -	unsigned char	secondary;	/* number of secondary bridge */
   6.462 -	unsigned char	subordinate;	/* max number of subordinate buses */
   6.463 -
   6.464 -	char		name[48];
   6.465 -	unsigned short	vendor;
   6.466 -	unsigned short	device;
   6.467 -	unsigned int	serial;		/* serial number */
   6.468 -	unsigned char	pnpver;		/* Plug & Play version */
   6.469 -	unsigned char	productver;	/* product version */
   6.470 -	unsigned char	checksum;	/* if zero - checksum passed */
   6.471 -	unsigned char	pad1;
   6.472 -};
   6.473 -
   6.474 -#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
   6.475 -
   6.476 -extern struct list_head pci_root_buses;	/* list of all known PCI buses */
   6.477 -extern struct list_head pci_devices;	/* list of all devices */
   6.478 -
   6.479 -extern struct proc_dir_entry *proc_bus_pci_dir;
   6.480 -/*
   6.481 - * Error values that may be returned by PCI functions.
   6.482 - */
   6.483 -#define PCIBIOS_SUCCESSFUL		0x00
   6.484 -#define PCIBIOS_FUNC_NOT_SUPPORTED	0x81
   6.485 -#define PCIBIOS_BAD_VENDOR_ID		0x83
   6.486 -#define PCIBIOS_DEVICE_NOT_FOUND	0x86
   6.487 -#define PCIBIOS_BAD_REGISTER_NUMBER	0x87
   6.488 -#define PCIBIOS_SET_FAILED		0x88
   6.489 -#define PCIBIOS_BUFFER_TOO_SMALL	0x89
   6.490 -
   6.491 -/* Low-level architecture-dependent routines */
   6.492 -
   6.493 -struct pci_ops {
   6.494 -	int (*read_byte)(struct pci_dev *, int where, u8 *val);
   6.495 -	int (*read_word)(struct pci_dev *, int where, u16 *val);
   6.496 -	int (*read_dword)(struct pci_dev *, int where, u32 *val);
   6.497 -	int (*write_byte)(struct pci_dev *, int where, u8 val);
   6.498 -	int (*write_word)(struct pci_dev *, int where, u16 val);
   6.499 -	int (*write_dword)(struct pci_dev *, int where, u32 val);
   6.500 -};
   6.501 -
   6.502 -struct pbus_set_ranges_data
   6.503 -{
   6.504 -	unsigned long io_start, io_end;
   6.505 -	unsigned long mem_start, mem_end;
   6.506 -	unsigned long prefetch_start, prefetch_end;
   6.507 -};
   6.508 -
   6.509 -struct pci_device_id {
   6.510 -	unsigned int vendor, device;		/* Vendor and device ID or PCI_ANY_ID */
   6.511 -	unsigned int subvendor, subdevice;	/* Subsystem ID's or PCI_ANY_ID */
   6.512 -	unsigned int class, class_mask;		/* (class,subclass,prog-if) triplet */
   6.513 -	unsigned long driver_data;		/* Data private to the driver */
   6.514 -};
   6.515 -
   6.516 -struct pci_driver {
   6.517 -	struct list_head node;
   6.518 -	char *name;
   6.519 -	const struct pci_device_id *id_table;	/* NULL if wants all devices */
   6.520 -	int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);	/* New device inserted */
   6.521 -	void (*remove) (struct pci_dev *dev);	/* Device removed (NULL if not a hot-plug capable driver) */
   6.522 -	int  (*save_state) (struct pci_dev *dev, u32 state);    /* Save Device Context */
   6.523 -	int  (*suspend) (struct pci_dev *dev, u32 state);	/* Device suspended */
   6.524 -	int  (*resume) (struct pci_dev *dev);	                /* Device woken up */
   6.525 -	int  (*enable_wake) (struct pci_dev *dev, u32 state, int enable);   /* Enable wake event */
   6.526 -};
   6.527 -
   6.528 -/**
   6.529 - * PCI_DEVICE - macro used to describe a specific pci device
   6.530 - * @vend: the 16 bit PCI Vendor ID
   6.531 - * @dev: the 16 bit PCI Device ID
   6.532 - *
   6.533 - * This macro is used to create a struct pci_device_id that matches a
   6.534 - * specific device.  The subvendor and subdevice fields will be set to
   6.535 - * PCI_ANY_ID.
   6.536 - */
   6.537 -#define PCI_DEVICE(vend,dev) \
   6.538 -	.vendor = (vend), .device = (dev), \
   6.539 -	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
   6.540 -
   6.541 -/**
   6.542 - * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
   6.543 - * @dev_class: the class, subclass, prog-if triple for this device
   6.544 - * @dev_class_mask: the class mask for this device
   6.545 - *
   6.546 - * This macro is used to create a struct pci_device_id that matches a
   6.547 - * specific PCI class.  The vendor, device, subvendor, and subdevice 
   6.548 - * fields will be set to PCI_ANY_ID.
   6.549 - */
   6.550 -#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
   6.551 -	.class = (dev_class), .class_mask = (dev_class_mask), \
   6.552 -	.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
   6.553 -	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
   6.554 -
   6.555 -/* these external functions are only available when PCI support is enabled */
   6.556 -#ifdef CONFIG_PCI
   6.557 -
   6.558 -#define pci_for_each_dev(dev) \
   6.559 -	for(dev = pci_dev_g(pci_devices.next); dev != pci_dev_g(&pci_devices); dev = pci_dev_g(dev->global_list.next))
   6.560 -
   6.561 -void pcibios_init(void);
   6.562 -void pcibios_fixup_bus(struct pci_bus *);
   6.563 -int pcibios_enable_device(struct pci_dev *, int mask);
   6.564 -char *pcibios_setup (char *str);
   6.565 -
   6.566 -/* Used only when drivers/pci/setup.c is used */
   6.567 -void pcibios_align_resource(void *, struct resource *,
   6.568 -			    unsigned long, unsigned long);
   6.569 -void pcibios_update_resource(struct pci_dev *, struct resource *,
   6.570 -			     struct resource *, int);
   6.571 -void pcibios_update_irq(struct pci_dev *, int irq);
   6.572 -void pcibios_fixup_pbus_ranges(struct pci_bus *, struct pbus_set_ranges_data *);
   6.573 -
   6.574 -/* Backward compatibility, don't use in new code! */
   6.575 -
   6.576 -int pcibios_present(void);
   6.577 -int pcibios_read_config_byte (unsigned char bus, unsigned char dev_fn,
   6.578 -			      unsigned char where, unsigned char *val);
   6.579 -int pcibios_read_config_word (unsigned char bus, unsigned char dev_fn,
   6.580 -			      unsigned char where, unsigned short *val);
   6.581 -int pcibios_read_config_dword (unsigned char bus, unsigned char dev_fn,
   6.582 -			       unsigned char where, unsigned int *val);
   6.583 -int pcibios_write_config_byte (unsigned char bus, unsigned char dev_fn,
   6.584 -			       unsigned char where, unsigned char val);
   6.585 -int pcibios_write_config_word (unsigned char bus, unsigned char dev_fn,
   6.586 -			       unsigned char where, unsigned short val);
   6.587 -int pcibios_write_config_dword (unsigned char bus, unsigned char dev_fn,
   6.588 -				unsigned char where, unsigned int val);
   6.589 -int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn);
   6.590 -int pcibios_find_device (unsigned short vendor, unsigned short dev_id,
   6.591 -			 unsigned short index, unsigned char *bus,
   6.592 -			 unsigned char *dev_fn);
   6.593 -
   6.594 -/* Generic PCI functions used internally */
   6.595 -
   6.596 -void pci_init(void);
   6.597 -int pci_bus_exists(const struct list_head *list, int nr);
   6.598 -struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
   6.599 -struct pci_bus *pci_alloc_primary_bus(int bus);
   6.600 -struct pci_dev *pci_scan_slot(struct pci_dev *temp);
   6.601 -int pci_proc_attach_device(struct pci_dev *dev);
   6.602 -int pci_proc_detach_device(struct pci_dev *dev);
   6.603 -int pci_proc_attach_bus(struct pci_bus *bus);
   6.604 -int pci_proc_detach_bus(struct pci_bus *bus);
   6.605 -void pci_name_device(struct pci_dev *dev);
   6.606 -char *pci_class_name(u32 class);
   6.607 -void pci_read_bridge_bases(struct pci_bus *child);
   6.608 -struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
   6.609 -int pci_setup_device(struct pci_dev *dev);
   6.610 -int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
   6.611 -
   6.612 -/* Generic PCI functions exported to card drivers */
   6.613 -
   6.614 -struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
   6.615 -struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device,
   6.616 -				 unsigned int ss_vendor, unsigned int ss_device,
   6.617 -				 const struct pci_dev *from);
   6.618 -struct pci_dev *pci_find_class (unsigned int class, const struct pci_dev *from);
   6.619 -struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
   6.620 -int pci_find_capability (struct pci_dev *dev, int cap);
   6.621 -
   6.622 -int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val);
   6.623 -int pci_read_config_word(struct pci_dev *dev, int where, u16 *val);
   6.624 -int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val);
   6.625 -int pci_write_config_byte(struct pci_dev *dev, int where, u8 val);
   6.626 -int pci_write_config_word(struct pci_dev *dev, int where, u16 val);
   6.627 -int pci_write_config_dword(struct pci_dev *dev, int where, u32 val);
   6.628 -
   6.629 -int pci_enable_device(struct pci_dev *dev);
   6.630 -int pci_enable_device_bars(struct pci_dev *dev, int mask);
   6.631 -void pci_disable_device(struct pci_dev *dev);
   6.632 -void pci_set_master(struct pci_dev *dev);
   6.633 -#define HAVE_PCI_SET_MWI
   6.634 -int pci_set_mwi(struct pci_dev *dev);
   6.635 -void pci_clear_mwi(struct pci_dev *dev);
   6.636 -int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
   6.637 -int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask);
   6.638 -int pci_assign_resource(struct pci_dev *dev, int i);
   6.639 -
   6.640 -/* Power management related routines */
   6.641 -int pci_save_state(struct pci_dev *dev, u32 *buffer);
   6.642 -int pci_restore_state(struct pci_dev *dev, u32 *buffer);
   6.643 -int pci_set_power_state(struct pci_dev *dev, int state);
   6.644 -int pci_enable_wake(struct pci_dev *dev, u32 state, int enable);
   6.645 -
   6.646 -/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
   6.647 -
   6.648 -int pci_claim_resource(struct pci_dev *, int);
   6.649 -void pci_assign_unassigned_resources(void);
   6.650 -void pdev_enable_device(struct pci_dev *);
   6.651 -void pdev_sort_resources(struct pci_dev *, struct resource_list *);
   6.652 -unsigned long pci_bridge_check_io(struct pci_dev *);
   6.653 -void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
   6.654 -		    int (*)(struct pci_dev *, u8, u8));
   6.655 -#define HAVE_PCI_REQ_REGIONS	2
   6.656 -int pci_request_regions(struct pci_dev *, char *);
   6.657 -void pci_release_regions(struct pci_dev *);
   6.658 -int pci_request_region(struct pci_dev *, int, char *);
   6.659 -void pci_release_region(struct pci_dev *, int);
   6.660 -
   6.661 -/* New-style probing supporting hot-pluggable devices */
   6.662 -int pci_register_driver(struct pci_driver *);
   6.663 -void pci_unregister_driver(struct pci_driver *);
   6.664 -void pci_insert_device(struct pci_dev *, struct pci_bus *);
   6.665 -void pci_remove_device(struct pci_dev *);
   6.666 -struct pci_driver *pci_dev_driver(const struct pci_dev *);
   6.667 -const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev);
   6.668 -void pci_announce_device_to_drivers(struct pci_dev *);
   6.669 -unsigned int pci_do_scan_bus(struct pci_bus *bus);
   6.670 -struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr);
   6.671 -
   6.672 -#if 0
   6.673 -/* xmem_cache style wrapper around pci_alloc_consistent() */
   6.674 -struct pci_pool *pci_pool_create (const char *name, struct pci_dev *dev,
   6.675 -		size_t size, size_t align, size_t allocation, int flags);
   6.676 -void pci_pool_destroy (struct pci_pool *pool);
   6.677 -
   6.678 -void *pci_pool_alloc (struct pci_pool *pool, int flags, dma_addr_t *handle);
   6.679 -void pci_pool_free (struct pci_pool *pool, void *vaddr, dma_addr_t addr);
   6.680 -#endif
   6.681 -
   6.682 -#endif /* CONFIG_PCI */
   6.683 -
   6.684 -/*
   6.685 - *  If the system does not have PCI, clearly these return errors.  Define
   6.686 - *  these as simple inline functions to avoid hair in drivers.
   6.687 - */
   6.688 -
   6.689 -#ifndef CONFIG_PCI
   6.690 -static inline int pcibios_present(void) { return 0; }
   6.691 -static inline int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn) 
   6.692 -{ 	return PCIBIOS_DEVICE_NOT_FOUND; }
   6.693 -
   6.694 -#define _PCI_NOP(o,s,t) \
   6.695 -	static inline int pcibios_##o##_config_##s (u8 bus, u8 dfn, u8 where, t val) \
   6.696 -		{ return PCIBIOS_FUNC_NOT_SUPPORTED; } \
   6.697 -	static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
   6.698 -		{ return PCIBIOS_FUNC_NOT_SUPPORTED; }
   6.699 -#define _PCI_NOP_ALL(o,x)	_PCI_NOP(o,byte,u8 x) \
   6.700 -				_PCI_NOP(o,word,u16 x) \
   6.701 -				_PCI_NOP(o,dword,u32 x)
   6.702 -_PCI_NOP_ALL(read, *)
   6.703 -_PCI_NOP_ALL(write,)
   6.704 -
   6.705 -static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
   6.706 -{ return NULL; }
   6.707 -
   6.708 -static inline struct pci_dev *pci_find_class(unsigned int class, const struct pci_dev *from)
   6.709 -{ return NULL; }
   6.710 -
   6.711 -static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
   6.712 -{ return NULL; }
   6.713 -
   6.714 -static inline struct pci_dev *pci_find_subsys(unsigned int vendor, unsigned int device,
   6.715 -unsigned int ss_vendor, unsigned int ss_device, const struct pci_dev *from)
   6.716 -{ return NULL; }
   6.717 -
   6.718 -static inline void pci_set_master(struct pci_dev *dev) { }
   6.719 -static inline int pci_enable_device_bars(struct pci_dev *dev, int mask) { return -EBUSY; }
   6.720 -static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
   6.721 -static inline void pci_disable_device(struct pci_dev *dev) { }
   6.722 -static inline int pci_module_init(struct pci_driver *drv) { return -ENODEV; }
   6.723 -static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
   6.724 -static inline int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
   6.725 -static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
   6.726 -static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
   6.727 -static inline void pci_unregister_driver(struct pci_driver *drv) { }
   6.728 -static inline int scsi_to_pci_dma_dir(unsigned char scsi_dir) { return scsi_dir; }
   6.729 -static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
   6.730 -static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
   6.731 -
   6.732 -/* Power management related routines */
   6.733 -static inline int pci_save_state(struct pci_dev *dev, u32 *buffer) { return 0; }
   6.734 -static inline int pci_restore_state(struct pci_dev *dev, u32 *buffer) { return 0; }
   6.735 -static inline int pci_set_power_state(struct pci_dev *dev, int state) { return 0; }
   6.736 -static inline int pci_enable_wake(struct pci_dev *dev, u32 state, int enable) { return 0; }
   6.737 -
   6.738 -#define pci_for_each_dev(dev) \
   6.739 -	for(dev = NULL; 0; )
   6.740 -
   6.741 -#else
   6.742 -
   6.743 -/*
   6.744 - * a helper function which helps ensure correct pci_driver
   6.745 - * setup and cleanup for commonly-encountered hotplug/modular cases
   6.746 - *
   6.747 - * This MUST stay in a header, as it checks for -DMODULE
   6.748 - */
   6.749 -static inline int pci_module_init(struct pci_driver *drv)
   6.750 -{
   6.751 -	int rc = pci_register_driver (drv);
   6.752 -
   6.753 -	if (rc > 0)
   6.754 -		return 0;
   6.755 -
   6.756 -	/* iff CONFIG_HOTPLUG and built into kernel, we should
   6.757 -	 * leave the driver around for future hotplug events.
   6.758 -	 * For the module case, a hotplug daemon of some sort
   6.759 -	 * should load a module in response to an insert event. */
   6.760 -#if defined(CONFIG_HOTPLUG) && !defined(MODULE)
   6.761 -	if (rc == 0)
   6.762 -		return 0;
   6.763 -#else
   6.764 -	if (rc == 0)
   6.765 -		rc = -ENODEV;		
   6.766 -#endif
   6.767 -
   6.768 -	/* if we get here, we need to clean up pci driver instance
   6.769 -	 * and return some sort of error */
   6.770 -	pci_unregister_driver (drv);
   6.771 -	
   6.772 -	return rc;
   6.773 -}
   6.774 -
   6.775 -#endif /* !CONFIG_PCI */
   6.776 -
   6.777 -/* these helpers provide future and backwards compatibility
   6.778 - * for accessing popular PCI BAR info */
   6.779 -#define pci_resource_start(dev,bar)   ((dev)->resource[(bar)].start)
   6.780 -#define pci_resource_end(dev,bar)     ((dev)->resource[(bar)].end)
   6.781 -#define pci_resource_flags(dev,bar)   ((dev)->resource[(bar)].flags)
   6.782 -#define pci_resource_len(dev,bar) \
   6.783 -	((pci_resource_start((dev),(bar)) == 0 &&	\
   6.784 -	  pci_resource_end((dev),(bar)) ==		\
   6.785 -	  pci_resource_start((dev),(bar))) ? 0 :	\
   6.786 -	  						\
   6.787 -	 (pci_resource_end((dev),(bar)) -		\
   6.788 -	  pci_resource_start((dev),(bar)) + 1))
   6.789 -
   6.790 -/* Similar to the helpers above, these manipulate per-pci_dev
   6.791 - * driver-specific data.  Currently stored as pci_dev::driver_data,
   6.792 - * a void pointer, but it is not present on older kernels.
   6.793 - */
   6.794 -static inline void *pci_get_drvdata (struct pci_dev *pdev)
   6.795 -{
   6.796 -	return pdev->driver_data;
   6.797 -}
   6.798 -
   6.799 -static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
   6.800 -{
   6.801 -	pdev->driver_data = data;
   6.802 -}
   6.803 -
   6.804 -static inline char *pci_name(struct pci_dev *pdev)
   6.805 -{
   6.806 -        return pdev->slot_name;
   6.807 -}
   6.808 -
   6.809 -/*
   6.810 - *  The world is not perfect and supplies us with broken PCI devices.
   6.811 - *  For at least a part of these bugs we need a work-around, so both
   6.812 - *  generic (drivers/pci/quirks.c) and per-architecture code can define
   6.813 - *  fixup hooks to be called for particular buggy devices.
   6.814 - */
   6.815 -
   6.816 -struct pci_fixup {
   6.817 -	int pass;
   6.818 -	u16 vendor, device;			/* You can use PCI_ANY_ID here of course */
   6.819 -	void (*hook)(struct pci_dev *dev);
   6.820 -};
   6.821 -
   6.822 -extern struct pci_fixup pcibios_fixups[];
   6.823 -
   6.824 -#define PCI_FIXUP_HEADER	1		/* Called immediately after reading configuration header */
   6.825 -#define PCI_FIXUP_FINAL		2		/* Final phase of device fixups */
   6.826 -
   6.827 -void pci_fixup_device(int pass, struct pci_dev *dev);
   6.828 -
   6.829 -extern int pci_pci_problems;
   6.830 -#define PCIPCI_FAIL		1
   6.831 -#define PCIPCI_TRITON		2
   6.832 -#define PCIPCI_NATOMA		4
   6.833 -#define PCIPCI_VIAETBF		8
   6.834 -#define PCIPCI_VSFX		16
   6.835 -#define PCIPCI_ALIMAGIK		32
   6.836 -
   6.837 -#endif /* LINUX_PCI_H */