ia64/xen-unstable

changeset 16357:cb6675149af8

x86, vt-d: Clean up utils code.
Signed-off-by: Weidong Han <weidong.han@intel.com>
author Keir Fraser <keir@xensource.com>
date Thu Nov 08 13:14:03 2007 +0000 (2007-11-08)
parents 8ff5bb70136d
children c0bdfda5183d
files xen/arch/x86/hvm/vmx/vtd/intel-iommu.c xen/arch/x86/hvm/vmx/vtd/utils.c xen/include/asm-x86/hvm/vmx/intel-iommu.h
line diff
     1.1 --- a/xen/arch/x86/hvm/vmx/vtd/intel-iommu.c	Thu Nov 08 10:33:18 2007 +0000
     1.2 +++ b/xen/arch/x86/hvm/vmx/vtd/intel-iommu.c	Thu Nov 08 13:14:03 2007 +0000
     1.3 @@ -115,18 +115,6 @@ static int device_context_mapped(struct 
     1.4      return ret;
     1.5  }
     1.6  
     1.7 -/* page table handling */
     1.8 -#define LEVEL_STRIDE        (9)
     1.9 -#define LEVEL_MASK        ((1 << LEVEL_STRIDE) - 1)
    1.10 -#define agaw_to_level(val) ((val) + 2)
    1.11 -#define agaw_to_width(val) (30 + val * LEVEL_STRIDE)
    1.12 -#define width_to_agaw(w)  ((w - 30)/LEVEL_STRIDE)
    1.13 -#define level_to_offset_bits(l) (12 + (l - 1) * LEVEL_STRIDE)
    1.14 -#define address_level_offset(addr, level) \
    1.15 -    ((addr >> level_to_offset_bits(level)) & LEVEL_MASK)
    1.16 -#define level_mask(l) (((u64)(-1)) << level_to_offset_bits(l))
    1.17 -#define level_size(l) (1 << level_to_offset_bits(l))
    1.18 -#define align_to_level(addr, l) ((addr + level_size(l) - 1) & level_mask(l))
    1.19  static struct page_info *addr_to_dma_page(struct domain *domain, u64 addr)
    1.20  {
    1.21      struct hvm_iommu *hd = domain_hvm_iommu(domain);
     2.1 --- a/xen/arch/x86/hvm/vmx/vtd/utils.c	Thu Nov 08 10:33:18 2007 +0000
     2.2 +++ b/xen/arch/x86/hvm/vmx/vtd/utils.c	Thu Nov 08 13:14:03 2007 +0000
     2.3 @@ -32,8 +32,9 @@
     2.4  
     2.5  #include <xen/mm.h>
     2.6  #include <xen/xmalloc.h>
     2.7 +#include <xen/inttypes.h>
     2.8  
     2.9 -#define VTDPREFIX "[VT-D]" 
    2.10 +#define VTDPREFIX "[VT-D]"
    2.11  #define INTEL   0x8086
    2.12  #define SEABURG 0x4000
    2.13  #define C_STEP  2
    2.14 @@ -93,47 +94,57 @@ void disable_pmr(struct iommu *iommu)
    2.15              "Disabled protected memory registers\n");
    2.16  }
    2.17  
    2.18 -#if defined(__x86_64__)
    2.19 +
    2.20  void print_iommu_regs(struct acpi_drhd_unit *drhd)
    2.21  {
    2.22      struct iommu *iommu = drhd->iommu;
    2.23 - 
    2.24 -    printk("---- print_iommu_regs ----\n"); 
    2.25 +
    2.26 +    printk("---- print_iommu_regs ----\n");
    2.27      printk("print_iommu_regs: drhd->address = %lx\n", drhd->address);
    2.28      printk("print_iommu_regs: DMAR_VER_REG = %x\n",
    2.29 -                   dmar_readl(iommu->reg,DMAR_VER_REG));
    2.30 -    printk("print_iommu_regs: DMAR_CAP_REG = %lx\n",
    2.31 -                   dmar_readq(iommu->reg,DMAR_CAP_REG));
    2.32 -    printk("print_iommu_regs: n_fault_reg = %lx\n",
    2.33 -                   cap_num_fault_regs(dmar_readq(iommu->reg, DMAR_CAP_REG)));
    2.34 -    printk("print_iommu_regs: fault_recording_offset_l = %lx\n",
    2.35 -                   cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)));
    2.36 -    printk("print_iommu_regs: fault_recording_offset_h = %lx\n",
    2.37 -                   cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)) + 8);
    2.38 -    printk("print_iommu_regs: fault_recording_reg_l = %lx\n",
    2.39 -        dmar_readq(iommu->reg, cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG))));
    2.40 -    printk("print_iommu_regs: fault_recording_reg_h = %lx\n",
    2.41 -        dmar_readq(iommu->reg, cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)) + 8));
    2.42 -    printk("print_iommu_regs: DMAR_ECAP_REG = %lx\n",
    2.43 -                   dmar_readq(iommu->reg,DMAR_ECAP_REG));
    2.44 +           dmar_readl(iommu->reg,DMAR_VER_REG));
    2.45 +    printk("print_iommu_regs: DMAR_CAP_REG = %"PRIx64"\n",
    2.46 +           dmar_readq(iommu->reg,DMAR_CAP_REG));
    2.47 +    printk("print_iommu_regs: n_fault_reg = %"PRIx64"\n",
    2.48 +           cap_num_fault_regs(dmar_readq(iommu->reg, DMAR_CAP_REG)));
    2.49 +    printk("print_iommu_regs: fault_recording_offset_l = %"PRIx64"\n",
    2.50 +           cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)));
    2.51 +    printk("print_iommu_regs: fault_recording_offset_h = %"PRIx64"\n",
    2.52 +           cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)) + 8);
    2.53 +    printk("print_iommu_regs: fault_recording_reg_l = %"PRIx64"\n",
    2.54 +           dmar_readq(iommu->reg,
    2.55 +               cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG))));
    2.56 +    printk("print_iommu_regs: fault_recording_reg_h = %"PRIx64"\n",
    2.57 +           dmar_readq(iommu->reg,
    2.58 +               cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)) + 8));
    2.59 +    printk("print_iommu_regs: DMAR_ECAP_REG = %"PRIx64"\n",
    2.60 +           dmar_readq(iommu->reg,DMAR_ECAP_REG));
    2.61      printk("print_iommu_regs: DMAR_GCMD_REG = %x\n",
    2.62 -                   dmar_readl(iommu->reg,DMAR_GCMD_REG));
    2.63 +           dmar_readl(iommu->reg,DMAR_GCMD_REG));
    2.64      printk("print_iommu_regs: DMAR_GSTS_REG = %x\n",
    2.65 -                   dmar_readl(iommu->reg,DMAR_GSTS_REG));
    2.66 -    printk("print_iommu_regs: DMAR_RTADDR_REG = %lx\n",
    2.67 -                   dmar_readq(iommu->reg,DMAR_RTADDR_REG));
    2.68 -    printk("print_iommu_regs: DMAR_CCMD_REG = %lx\n",
    2.69 -                   dmar_readq(iommu->reg,DMAR_CCMD_REG));
    2.70 +           dmar_readl(iommu->reg,DMAR_GSTS_REG));
    2.71 +    printk("print_iommu_regs: DMAR_RTADDR_REG = %"PRIx64"\n",
    2.72 +           dmar_readq(iommu->reg,DMAR_RTADDR_REG));
    2.73 +    printk("print_iommu_regs: DMAR_CCMD_REG = %"PRIx64"\n",
    2.74 +           dmar_readq(iommu->reg,DMAR_CCMD_REG));
    2.75      printk("print_iommu_regs: DMAR_FSTS_REG = %x\n",
    2.76 -                   dmar_readl(iommu->reg,DMAR_FSTS_REG));
    2.77 +           dmar_readl(iommu->reg,DMAR_FSTS_REG));
    2.78      printk("print_iommu_regs: DMAR_FECTL_REG = %x\n",
    2.79 -                   dmar_readl(iommu->reg,DMAR_FECTL_REG));
    2.80 +           dmar_readl(iommu->reg,DMAR_FECTL_REG));
    2.81      printk("print_iommu_regs: DMAR_FEDATA_REG = %x\n",
    2.82 -                   dmar_readl(iommu->reg,DMAR_FEDATA_REG));
    2.83 +           dmar_readl(iommu->reg,DMAR_FEDATA_REG));
    2.84      printk("print_iommu_regs: DMAR_FEADDR_REG = %x\n",
    2.85 -                   dmar_readl(iommu->reg,DMAR_FEADDR_REG));
    2.86 +           dmar_readl(iommu->reg,DMAR_FEADDR_REG));
    2.87      printk("print_iommu_regs: DMAR_FEUADDR_REG = %x\n",
    2.88 -                   dmar_readl(iommu->reg,DMAR_FEUADDR_REG));
    2.89 +           dmar_readl(iommu->reg,DMAR_FEUADDR_REG));
    2.90 +}
    2.91 +
    2.92 +u32 get_level_index(unsigned long gmfn, int level)
    2.93 +{
    2.94 +    while ( --level )
    2.95 +        gmfn = gmfn >> LEVEL_STRIDE;
    2.96 +
    2.97 +    return gmfn & LEVEL_MASK;
    2.98  }
    2.99  
   2.100  void print_vtd_entries(struct domain *d, int bus, int devfn,
   2.101 @@ -144,219 +155,120 @@ void print_vtd_entries(struct domain *d,
   2.102      struct iommu *iommu;
   2.103      struct context_entry *ctxt_entry;
   2.104      struct root_entry *root_entry;
   2.105 -    u64 *l3, *l2, *l1;
   2.106 -    u32 l3_index, l2_index, l1_index;
   2.107 +    u64 *l4 = NULL, *l3, *l2, *l1;
   2.108 +    u32 l4_index = 0, l3_index, l2_index, l1_index;
   2.109      u32 i = 0;
   2.110 +    int level = agaw_to_level(hd->agaw);
   2.111  
   2.112 -    printk("print_vtd_entries: domain_id = %x bdf = %x:%x:%x devfn = %x, gmfn = %lx\n", d->domain_id, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), devfn, gmfn);
   2.113 +    printk("print_vtd_entries: domain_id = %x bdf = %x:%x:%x gmfn = %lx\n",
   2.114 +           d->domain_id, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), gmfn);
   2.115  
   2.116 -    for_each_drhd_unit(drhd) {
   2.117 -        printk("---- print_vtd_entries %d ----\n", i++);
   2.118 +    if ( hd->pgd == NULL )
   2.119 +    {
   2.120 +        printk("    hg->pgd == NULL\n");
   2.121 +        return;
   2.122 +    }
   2.123 +    printk("    d->pgd = %p virt_to_maddr(hd->pgd) = %lx\n",
   2.124 +           hd->pgd, virt_to_maddr(hd->pgd));
   2.125  
   2.126 -        if (hd->pgd == NULL) {
   2.127 -            printk("    hg->pgd == NULL\n");
   2.128 -            return;
   2.129 -        }
   2.130 +    for_each_drhd_unit ( drhd )
   2.131 +    {
   2.132 +        printk("---- print_vtd_entries %d ----\n", i++);
   2.133  
   2.134          iommu = drhd->iommu;
   2.135          root_entry = iommu->root_entry;
   2.136 -        printk("    hd->pgd = %p virt_to_maddr(hd->pgd) = %lx\n",
   2.137 -               hd->pgd, virt_to_maddr(hd->pgd));
   2.138 -
   2.139          printk("    root_entry = %p\n", root_entry);
   2.140 -        if (root_entry == NULL) {
   2.141 +        if ( root_entry == NULL )
   2.142 +        {
   2.143              printk("    root_entry == NULL\n");
   2.144 -            return;
   2.145 +            continue;
   2.146          }
   2.147  
   2.148 -        printk("    root_entry[%x] = %lx\n", bus, root_entry[bus].val);
   2.149 +        printk("    root_entry[%x] = %"PRIx64"\n", bus, root_entry[bus].val);
   2.150          printk("    maddr_to_virt(root_entry[%x]) = %p\n",
   2.151 -            bus, maddr_to_virt(root_entry[bus].val));
   2.152 +               bus, maddr_to_virt(root_entry[bus].val));
   2.153  
   2.154 -        if (root_entry[bus].val == 0) {
   2.155 +        if ( root_entry[bus].val == 0 )
   2.156 +        {
   2.157              printk("    root_entry[%x].lo == 0\n", bus);
   2.158 -            return;
   2.159 -        }
   2.160 - 
   2.161 -        ctxt_entry = maddr_to_virt((root_entry[bus].val >> PAGE_SHIFT) << PAGE_SHIFT);
   2.162 -        if (ctxt_entry == NULL) {
   2.163 -            printk("    ctxt_entry == NULL\n");
   2.164 -            return;
   2.165 +            continue;
   2.166          }
   2.167  
   2.168 -        if (ctxt_entry[devfn].lo == 0) {
   2.169 +        ctxt_entry =
   2.170 +            maddr_to_virt((root_entry[bus].val >> PAGE_SHIFT) << PAGE_SHIFT);
   2.171 +        if ( ctxt_entry == NULL )
   2.172 +        {
   2.173 +            printk("    ctxt_entry == NULL\n");
   2.174 +            continue;
   2.175 +        }
   2.176 +
   2.177 +        if ( ctxt_entry[devfn].lo == 0 )
   2.178 +        {
   2.179              printk("    ctxt_entry[%x].lo == 0\n", devfn);
   2.180 -            return;
   2.181 +            continue;
   2.182          }
   2.183  
   2.184          printk("    context = %p\n", ctxt_entry);
   2.185 -        printk("    context[%x] = %lx %lx\n",
   2.186 +        printk("    context[%x] = %"PRIx64" %"PRIx64"\n",
   2.187                 devfn, ctxt_entry[devfn].hi, ctxt_entry[devfn].lo);
   2.188          printk("    maddr_to_virt(context[%x].lo) = %p\n",
   2.189                 devfn, maddr_to_virt(ctxt_entry[devfn].lo));
   2.190 -        printk("    context[%x] = %lx\n", devfn, ctxt_entry[devfn].lo); 
   2.191 +        printk("    context[%x] = %"PRIx64"\n", devfn, ctxt_entry[devfn].lo);
   2.192 +
   2.193 +        switch ( level )
   2.194 +        {
   2.195 +        case VTD_PAGE_TABLE_LEVEL_3:
   2.196 +            l3 = maddr_to_virt(ctxt_entry[devfn].lo);
   2.197 +            l3 = (u64*)(((unsigned long)l3 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
   2.198 +            printk("    l3 = %p\n", l3);
   2.199 +            if ( l3 == NULL )
   2.200 +                continue;
   2.201 +            l3_index = get_level_index(gmfn, 3);
   2.202 +            printk("    l3_index = %x\n", l3_index);
   2.203 +            printk("    l3[%x] = %"PRIx64"\n", l3_index, l3[l3_index]);
   2.204  
   2.205 -        l3 = maddr_to_virt(ctxt_entry[devfn].lo);
   2.206 -        l3 = (u64*)(((u64) l3 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
   2.207 -        printk("    l3 = %p\n", l3); 
   2.208 -        if (l3 == NULL) return;
   2.209 +            break;
   2.210 +        case VTD_PAGE_TABLE_LEVEL_4:
   2.211 +            l4 = maddr_to_virt(ctxt_entry[devfn].lo);
   2.212 +            l4 = (u64*)(((unsigned long)l4 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
   2.213 +            printk("    l4 = %p\n", l4);
   2.214 +            if ( l4 == NULL )
   2.215 +                continue;
   2.216 +            l4_index = get_level_index(gmfn, 4);
   2.217 +            printk("    l4_index = %x\n", l4_index);
   2.218 +            printk("    l4[%x] = %"PRIx64"\n", l4_index, l4[l4_index]);
   2.219  
   2.220 -        l3_index = (gmfn >> 9 >> 9) & 0x1ff;
   2.221 -        printk("    l3_index = %x\n", l3_index);
   2.222 -        printk("    l3[%x] = %lx\n", l3_index, l3[l3_index]);
   2.223 +            l3 = maddr_to_virt(l4[l4_index]);
   2.224 +            l3 = (u64*)(((unsigned long)l3 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
   2.225 +            printk("    l3 = %p\n", l3);
   2.226 +            if ( l3 == NULL )
   2.227 +                continue;
   2.228 +            l3_index = get_level_index(gmfn, 3);
   2.229 +            printk("    l3_index = %x\n", l3_index);
   2.230 +            printk("    l3[%x] = %"PRIx64"\n", l3_index, l3[l3_index]);
   2.231 +
   2.232 +            break;
   2.233 +        default:
   2.234 +            printk("Unsupported VTD page table level (%d)!\n", level);
   2.235 +            continue;
   2.236 +        }
   2.237  
   2.238          l2 = maddr_to_virt(l3[l3_index]);
   2.239 -        l2 = (u64*)(((u64) l2 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
   2.240 -        printk("    l2 = %p\n", l2); 
   2.241 -        if (l2 == NULL) return;
   2.242 -
   2.243 -        l2_index = (gmfn >> 9) & 0x1ff;
   2.244 -        printk("    gmfn = %lx\n", gmfn);
   2.245 -        printk("    gmfn >> 9= %lx\n", gmfn >> 9);
   2.246 +        l2 = (u64*)(((unsigned long)l2 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
   2.247 +        printk("    l2 = %p\n", l2);
   2.248 +        if ( l2 == NULL )
   2.249 +            continue;
   2.250 +        l2_index = get_level_index(gmfn, 2);
   2.251          printk("    l2_index = %x\n", l2_index);
   2.252 -        printk("    l2[%x] = %lx\n", l2_index, l2[l2_index]);
   2.253 +        printk("    l2[%x] = %"PRIx64"\n", l2_index, l2[l2_index]);
   2.254  
   2.255          l1 = maddr_to_virt(l2[l2_index]);
   2.256 -        l1 = (u64*)(((u64) l1 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
   2.257 -        if (l1 == NULL) return;
   2.258 -        l1_index = gmfn & 0x1ff;
   2.259 -        printk("    l1 = %p\n", l1); 
   2.260 +        l1 = (u64*)(((unsigned long)l1 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
   2.261 +        printk("    l1 = %p\n", l1);
   2.262 +        if ( l1 == NULL )
   2.263 +            continue;
   2.264 +        l1_index = get_level_index(gmfn, 1);
   2.265          printk("    l1_index = %x\n", l1_index);
   2.266 -        printk("    l1[%x] = %lx\n", l1_index, l1[l1_index]); 
   2.267 -    }
   2.268 -}
   2.269 -
   2.270 -#else    // !m64
   2.271 -
   2.272 -void print_iommu_regs(struct acpi_drhd_unit *drhd)
   2.273 -{
   2.274 -    struct iommu *iommu = drhd->iommu;
   2.275 - 
   2.276 -    printk("---- print_iommu_regs ----\n"); 
   2.277 -    printk("print_iommu_regs: drhd->address = %lx\n", drhd->address);
   2.278 -    printk("print_iommu_regs: DMAR_VER_REG = %x\n",
   2.279 -                   dmar_readl(iommu->reg,DMAR_VER_REG));
   2.280 -    printk("print_iommu_regs: DMAR_CAP_REG = %llx\n",
   2.281 -                   dmar_readq(iommu->reg,DMAR_CAP_REG));
   2.282 -    printk("print_iommu_regs: n_fault_reg = %llx\n",
   2.283 -                   cap_num_fault_regs(dmar_readq(iommu->reg, DMAR_CAP_REG)));
   2.284 -    printk("print_iommu_regs: fault_recording_offset_l = %llx\n",
   2.285 -                   cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)));
   2.286 -    printk("print_iommu_regs: fault_recording_offset_h = %llx\n",
   2.287 -                   cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)) + 8);
   2.288 -    printk("print_iommu_regs: fault_recording_reg_l = %llx\n",
   2.289 -        dmar_readq(iommu->reg, cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG))));
   2.290 -    printk("print_iommu_regs: fault_recording_reg_h = %llx\n",
   2.291 -        dmar_readq(iommu->reg, cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)) + 8));
   2.292 -    printk("print_iommu_regs: DMAR_ECAP_REG = %llx\n",
   2.293 -                   dmar_readq(iommu->reg,DMAR_ECAP_REG));
   2.294 -    printk("print_iommu_regs: DMAR_GCMD_REG = %x\n",
   2.295 -                   dmar_readl(iommu->reg,DMAR_GCMD_REG));
   2.296 -    printk("print_iommu_regs: DMAR_GSTS_REG = %x\n",
   2.297 -                   dmar_readl(iommu->reg,DMAR_GSTS_REG));
   2.298 -    printk("print_iommu_regs: DMAR_RTADDR_REG = %llx\n",
   2.299 -                   dmar_readq(iommu->reg,DMAR_RTADDR_REG));
   2.300 -    printk("print_iommu_regs: DMAR_CCMD_REG = %llx\n",
   2.301 -                   dmar_readq(iommu->reg,DMAR_CCMD_REG));
   2.302 -    printk("print_iommu_regs: DMAR_FSTS_REG = %x\n",
   2.303 -                   dmar_readl(iommu->reg,DMAR_FSTS_REG));
   2.304 -    printk("print_iommu_regs: DMAR_FECTL_REG = %x\n",
   2.305 -                   dmar_readl(iommu->reg,DMAR_FECTL_REG));
   2.306 -    printk("print_iommu_regs: DMAR_FEDATA_REG = %x\n",
   2.307 -                   dmar_readl(iommu->reg,DMAR_FEDATA_REG));
   2.308 -    printk("print_iommu_regs: DMAR_FEADDR_REG = %x\n",
   2.309 -                   dmar_readl(iommu->reg,DMAR_FEADDR_REG));
   2.310 -    printk("print_iommu_regs: DMAR_FEUADDR_REG = %x\n",
   2.311 -                   dmar_readl(iommu->reg,DMAR_FEUADDR_REG));
   2.312 +        printk("    l1[%x] = %"PRIx64"\n", l1_index, l1[l1_index]);
   2.313 +   }
   2.314  }
   2.315 -
   2.316 -void print_vtd_entries(struct domain *d, int bus, int devfn,
   2.317 -                       unsigned long gmfn)
   2.318 -{
   2.319 -    struct hvm_iommu *hd = domain_hvm_iommu(d);
   2.320 -    struct acpi_drhd_unit *drhd;
   2.321 -    struct iommu *iommu;
   2.322 -    struct context_entry *ctxt_entry;
   2.323 -    struct root_entry *root_entry;
   2.324 -    u64 *l3, *l2, *l1;
   2.325 -    u32 l3_index, l2_index, l1_index;
   2.326 -    u32 i = 0;
   2.327 -
   2.328 -    printk("print_vtd_entries: domain_id = %x bdf = %x:%x:%x devfn = %x, gmfn = %lx\n", d->domain_id, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), devfn, gmfn);
   2.329 -
   2.330 -    for_each_drhd_unit(drhd) {
   2.331 -        printk("---- print_vtd_entries %d ----\n", i++);
   2.332 -
   2.333 -        if (hd->pgd == NULL) {
   2.334 -            printk("    hg->pgd == NULL\n");
   2.335 -            return;
   2.336 -        }
   2.337 -
   2.338 -        iommu = drhd->iommu;
   2.339 -        root_entry = iommu->root_entry;
   2.340 -        printk("    d->pgd = %p virt_to_maddr(hd->pgd) = %lx\n",
   2.341 -               hd->pgd, virt_to_maddr(hd->pgd));
   2.342 -
   2.343 -        printk("    root_entry = %p\n", root_entry);
   2.344 -        if (root_entry == NULL) {
   2.345 -            printk("    root_entry == NULL\n");
   2.346 -            return;
   2.347 -        }
   2.348 -
   2.349 -        printk("    root_entry[%x] = %llx\n", bus, root_entry[bus].val);
   2.350 -        printk("    maddr_to_virt(root_entry[%x]) = %p\n",
   2.351 -            bus, maddr_to_virt(root_entry[bus].val));
   2.352 -
   2.353 -        if (root_entry[bus].val == 0) {
   2.354 -            printk("    root_entry[%x].lo == 0\n", bus);
   2.355 -            return;
   2.356 -        }
   2.357 - 
   2.358 -        ctxt_entry = maddr_to_virt((root_entry[bus].val >> PAGE_SHIFT) << PAGE_SHIFT);
   2.359 -        if (ctxt_entry == NULL) {
   2.360 -            printk("    ctxt_entry == NULL\n");
   2.361 -            return;
   2.362 -        }
   2.363 -
   2.364 -        if (ctxt_entry[devfn].lo == 0) {
   2.365 -            printk("    ctxt_entry[%x].lo == 0\n", devfn);
   2.366 -            return;
   2.367 -        }
   2.368 -
   2.369 -        printk("    context = %p\n", ctxt_entry);
   2.370 -        printk("    context[%x] = %llx %llx\n",
   2.371 -               devfn, ctxt_entry[devfn].hi, ctxt_entry[devfn].lo);
   2.372 -        printk("    maddr_to_virt(context[%x].lo) = %p\n",
   2.373 -               devfn, maddr_to_virt(ctxt_entry[devfn].lo));
   2.374 -        printk("    context[%x] = %llx\n", devfn, ctxt_entry[devfn].lo); 
   2.375 -
   2.376 -        l3 = maddr_to_virt(ctxt_entry[devfn].lo);
   2.377 -        l3 = (u64*)(((u32) l3 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
   2.378 -        printk("    l3 = %p\n", l3); 
   2.379 -        if (l3 == NULL) return;
   2.380 -
   2.381 -        l3_index = (gmfn >> 9 >> 9) & 0x1ff;
   2.382 -        printk("    l3_index = %x\n", l3_index);
   2.383 -        printk("    l3[%x] = %llx\n", l3_index, l3[l3_index]);
   2.384 -
   2.385 -        l2 = maddr_to_virt(l3[l3_index]);
   2.386 -        l2 = (u64*)(((u32) l2 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
   2.387 -        printk("    l2 = %p\n", l2); 
   2.388 -        if (l2 == NULL) return;
   2.389 -
   2.390 -        l2_index = (gmfn >> 9) & 0x1ff;
   2.391 -        printk("    gmfn = %lx\n", gmfn);
   2.392 -        printk("    gmfn >> 9= %lx\n", gmfn >> 9);
   2.393 -        printk("    l2_index = %x\n", l2_index);
   2.394 -        printk("    l2[%x] = %llx\n", l2_index, l2[l2_index]);
   2.395 -
   2.396 -        l1 = maddr_to_virt(l2[l2_index]);
   2.397 -        l1 = (u64*)(((u32) l1 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
   2.398 -        if (l1 == NULL) return;
   2.399 -        l1_index = gmfn & 0x1ff;
   2.400 -        printk("    l1 = %p\n", l1); 
   2.401 -        printk("    l1_index = %x\n", l1_index);
   2.402 -        printk("    l1[%x] = %llx\n", l1_index, l1[l1_index]); 
   2.403 -    }
   2.404 -}
   2.405 -#endif    // !m64
     3.1 --- a/xen/include/asm-x86/hvm/vmx/intel-iommu.h	Thu Nov 08 10:33:18 2007 +0000
     3.2 +++ b/xen/include/asm-x86/hvm/vmx/intel-iommu.h	Thu Nov 08 13:14:03 2007 +0000
     3.3 @@ -230,6 +230,19 @@ struct context_entry {
     3.4      do {(c).hi &= 0xff; (c).hi |= ((val + 1) & ((1 << 16) - 1)) << 8;} while(0)
     3.5  #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while(0)
     3.6  
     3.7 +/* page table handling */
     3.8 +#define LEVEL_STRIDE       (9)
     3.9 +#define LEVEL_MASK         ((1 << LEVEL_STRIDE) - 1)
    3.10 +#define agaw_to_level(val) ((val) + 2)
    3.11 +#define agaw_to_width(val) (30 + val * LEVEL_STRIDE)
    3.12 +#define width_to_agaw(w)   ((w - 30)/LEVEL_STRIDE)
    3.13 +#define level_to_offset_bits(l) (12 + (l - 1) * LEVEL_STRIDE)
    3.14 +#define address_level_offset(addr, level) \
    3.15 +            ((addr >> level_to_offset_bits(level)) & LEVEL_MASK)
    3.16 +#define level_mask(l) (((u64)(-1)) << level_to_offset_bits(l))
    3.17 +#define level_size(l) (1 << level_to_offset_bits(l))
    3.18 +#define align_to_level(addr, l) ((addr + level_size(l) - 1) & level_mask(l))
    3.19 +
    3.20  /*
    3.21   * 0: readable
    3.22   * 1: writable