ia64/xen-unstable

changeset 5409:ca1fb1af953d

bitkeeper revision 1.1706 (42a8be4bKG9EZTToo_Pa4wDcO7VpRw)

Merge http://xen-ia64.bkbits.net/xeno-unstable-ia64.bk
into sportsman.spdomain:/home/djm/xeno-unstable-ia64.bk
author djm@sportsman.spdomain
date Thu Jun 09 22:10:19 2005 +0000 (2005-06-09)
parents 8d70990f0858 a871bb5722c7
children 4e3360378112
files .rootkeys xen/arch/ia64/Makefile xen/arch/ia64/acpi.c xen/arch/ia64/asm-offsets.c xen/arch/ia64/dom_fw.c xen/arch/ia64/domain.c xen/arch/ia64/hyperprivop.S xen/arch/ia64/ivt.S xen/arch/ia64/patch/linux-2.6.11/efi.c xen/arch/ia64/patch/linux-2.6.11/pgalloc.h xen/arch/ia64/patch/linux-2.6.11/sn_sal.h xen/arch/ia64/pcdp.c xen/arch/ia64/privop.c xen/arch/ia64/process.c xen/arch/ia64/regionreg.c xen/arch/ia64/sn_console.c xen/arch/ia64/tools/mkbuildtree xen/arch/ia64/vcpu.c xen/arch/ia64/xensetup.c xen/include/asm-ia64/config.h xen/include/asm-ia64/domain.h xen/include/asm-ia64/xensystem.h xen/include/public/arch-ia64.h
line diff
     1.1 --- a/.rootkeys	Thu Jun 09 20:07:33 2005 +0000
     1.2 +++ b/.rootkeys	Thu Jun 09 22:10:19 2005 +0000
     1.3 @@ -1146,6 +1146,7 @@ 425ae516EWaNOBEnc1xnphTbRmNZsw xen/arch/
     1.4  428bb037KSxe7_UyqseK5bWhGe3KwA xen/arch/ia64/patch/linux-2.6.11/ptrace.h
     1.5  425ae516LecDyXlwh3NLBtHZKXmMcA xen/arch/ia64/patch/linux-2.6.11/series
     1.6  425ae516RFiPn2CGkpJ21LM-1lJcQg xen/arch/ia64/patch/linux-2.6.11/setup.c
     1.7 +42a8bcc8E6zmTKC5xgOcFLcnzbhVEw xen/arch/ia64/patch/linux-2.6.11/sn_sal.h
     1.8  425ae516p4ICTkjqNYEfYFxqULj4dw xen/arch/ia64/patch/linux-2.6.11/system.h
     1.9  425ae516juUB257qrwUdsL9AsswrqQ xen/arch/ia64/patch/linux-2.6.11/time.c
    1.10  425ae5167zQn7zYcgKtDUDX2v-e8mw xen/arch/ia64/patch/linux-2.6.11/tlb.c
    1.11 @@ -1201,6 +1202,7 @@ 41a26ebc4BOHDUsT0TSnryPeV2xfRA xen/arch/
    1.12  41a26ebcJ30TFl1v2kR8rqpEBvOtVw xen/arch/ia64/regionreg.c
    1.13  421098b69pUiIJrqu_w0JMUnZ2uc2A xen/arch/ia64/smp.c
    1.14  421098b6_ToSGrf6Pk1Uwg5aMAIBxg xen/arch/ia64/smpboot.c
    1.15 +42a8bd43dIEIsS-EoQqt5Df1RTr5Hg xen/arch/ia64/sn_console.c
    1.16  428b9f38JJDW35iDn5DlfXTu700rkQ xen/arch/ia64/tools/README.RunVT
    1.17  421098b6AUdbxR3wyn1ATcmNuTao_Q xen/arch/ia64/tools/README.xenia64
    1.18  42376c6dfyY0eq8MS2dK3BW2rFuEGg xen/arch/ia64/tools/README.xenia64linux
     2.1 --- a/xen/arch/ia64/Makefile	Thu Jun 09 20:07:33 2005 +0000
     2.2 +++ b/xen/arch/ia64/Makefile	Thu Jun 09 22:10:19 2005 +0000
     2.3 @@ -9,7 +9,8 @@ OBJS = xensetup.o setup.o time.o irq.o i
     2.4  	xenmem.o sal.o cmdline.o mm_init.o tlb.o smpboot.o \
     2.5  	extable.o linuxextable.o xenirq.o xentime.o \
     2.6  	regionreg.o entry.o unaligned.o privop.o vcpu.o \
     2.7 -	irq_ia64.o irq_lsapic.o vhpt.o xenasm.o hyperprivop.o dom_fw.o
     2.8 +	irq_ia64.o irq_lsapic.o vhpt.o xenasm.o hyperprivop.o dom_fw.o \
     2.9 +	sn_console.o
    2.10  
    2.11  ifeq ($(CONFIG_VTI),y)
    2.12  OBJS += vmx_init.o vmx_virt.o vmx_vcpu.o vmx_process.o vmx_vsa.o vmx_ivt.o \
     3.1 --- a/xen/arch/ia64/acpi.c	Thu Jun 09 20:07:33 2005 +0000
     3.2 +++ b/xen/arch/ia64/acpi.c	Thu Jun 09 22:10:19 2005 +0000
     3.3 @@ -68,7 +68,7 @@ unsigned char acpi_legacy_devices;
     3.4  const char *
     3.5  acpi_get_sysname (void)
     3.6  {
     3.7 -#ifdef CONFIG_IA64_GENERIC
     3.8 +/* #ifdef CONFIG_IA64_GENERIC */
     3.9  	unsigned long rsdp_phys;
    3.10  	struct acpi20_table_rsdp *rsdp;
    3.11  	struct acpi_table_xsdt *xsdt;
    3.12 @@ -101,6 +101,7 @@ acpi_get_sysname (void)
    3.13  	}
    3.14  
    3.15  	return "dig";
    3.16 +/*
    3.17  #else
    3.18  # if defined (CONFIG_IA64_HP_SIM)
    3.19  	return "hpsim";
    3.20 @@ -114,6 +115,7 @@ acpi_get_sysname (void)
    3.21  #	error Unknown platform.  Fix acpi.c.
    3.22  # endif
    3.23  #endif
    3.24 +*/
    3.25  }
    3.26  
    3.27  #ifdef CONFIG_ACPI_BOOT
     4.1 --- a/xen/arch/ia64/asm-offsets.c	Thu Jun 09 20:07:33 2005 +0000
     4.2 +++ b/xen/arch/ia64/asm-offsets.c	Thu Jun 09 22:10:19 2005 +0000
     4.3 @@ -46,12 +46,19 @@ void foo(void)
     4.4  	DEFINE(XSI_PSR_IC, (SHAREDINFO_ADDR+offsetof(vcpu_info_t, arch.interrupt_collection_enabled)));
     4.5  	DEFINE(XSI_PSR_I_OFS, offsetof(vcpu_info_t, arch.interrupt_delivery_enabled));
     4.6  	DEFINE(XSI_IIP_OFS, offsetof(vcpu_info_t, arch.iip));
     4.7 +	DEFINE(XSI_IPSR, (SHAREDINFO_ADDR+offsetof(vcpu_info_t, arch.ipsr)));
     4.8  	DEFINE(XSI_IPSR_OFS, offsetof(vcpu_info_t, arch.ipsr));
     4.9  	DEFINE(XSI_IFS_OFS, offsetof(vcpu_info_t, arch.ifs));
    4.10 +	DEFINE(XSI_ISR_OFS, offsetof(vcpu_info_t, arch.isr));
    4.11 +	DEFINE(XSI_IIM_OFS, offsetof(vcpu_info_t, arch.iim));
    4.12  	DEFINE(XSI_BANKNUM_OFS, offsetof(vcpu_info_t, arch.banknum));
    4.13 +	DEFINE(XSI_BANK0_OFS, offsetof(vcpu_info_t, arch.bank0_regs[0]));
    4.14 +	DEFINE(XSI_BANK1_OFS, offsetof(vcpu_info_t, arch.bank1_regs[0]));
    4.15  	DEFINE(XSI_METAPHYS_OFS, offsetof(vcpu_info_t, arch.metaphysical_mode));
    4.16 +	DEFINE(XSI_PRECOVER_IFS_OFS, offsetof(vcpu_info_t, arch.precover_ifs));
    4.17  	DEFINE(XSI_INCOMPL_REG_OFS, offsetof(vcpu_info_t, arch.incomplete_regframe));
    4.18  	DEFINE(XSI_PEND_OFS, offsetof(vcpu_info_t, arch.pending_interruption));
    4.19 +	DEFINE(XSI_RR0_OFS, offsetof(vcpu_info_t, arch.rrs[0]));
    4.20  	//DEFINE(IA64_TASK_BLOCKED_OFFSET,offsetof (struct task_struct, blocked));
    4.21  	//DEFINE(IA64_TASK_CLEAR_CHILD_TID_OFFSET,offsetof (struct task_struct, clear_child_tid));
    4.22  	//DEFINE(IA64_TASK_GROUP_LEADER_OFFSET, offsetof (struct task_struct, group_leader));
    4.23 @@ -64,6 +71,11 @@ void foo(void)
    4.24  	DEFINE(IA64_TASK_THREAD_KSP_OFFSET, offsetof (struct vcpu, arch._thread.ksp));
    4.25  	DEFINE(IA64_TASK_THREAD_ON_USTACK_OFFSET, offsetof (struct vcpu, arch._thread.on_ustack));
    4.26  
    4.27 +	DEFINE(IA64_VCPU_META_RR0_OFFSET, offsetof (struct vcpu, arch.metaphysical_rr0));
    4.28 +	DEFINE(IA64_VCPU_META_SAVED_RR0_OFFSET, offsetof (struct vcpu, arch.metaphysical_saved_rr0));
    4.29 +	DEFINE(IA64_VCPU_BREAKIMM_OFFSET, offsetof (struct vcpu, arch.breakimm));
    4.30 +	DEFINE(IA64_VCPU_IVA_OFFSET, offsetof (struct vcpu, arch.iva));
    4.31 +
    4.32  	BLANK();
    4.33  
    4.34  	//DEFINE(IA64_SIGHAND_SIGLOCK_OFFSET,offsetof (struct sighand_struct, siglock));
     5.1 --- a/xen/arch/ia64/dom_fw.c	Thu Jun 09 20:07:33 2005 +0000
     5.2 +++ b/xen/arch/ia64/dom_fw.c	Thu Jun 09 22:10:19 2005 +0000
     5.3 @@ -50,7 +50,7 @@ void dom_efi_hypercall_patch(struct doma
     5.4  
     5.5  	if (d == dom0) paddr += dom0_start;
     5.6  	imva = domain_mpa_to_imva(d,paddr);
     5.7 -	build_hypercall_bundle(imva,d->breakimm,hypercall,1);
     5.8 +	build_hypercall_bundle(imva,d->arch.breakimm,hypercall,1);
     5.9  }
    5.10  
    5.11  
    5.12 @@ -61,7 +61,7 @@ void dom_fw_hypercall_patch(struct domai
    5.13  
    5.14  	if (d == dom0) paddr += dom0_start;
    5.15  	imva = domain_mpa_to_imva(d,paddr);
    5.16 -	build_hypercall_bundle(imva,d->breakimm,hypercall,ret);
    5.17 +	build_hypercall_bundle(imva,d->arch.breakimm,hypercall,ret);
    5.18  }
    5.19  
    5.20  
     6.1 --- a/xen/arch/ia64/domain.c	Thu Jun 09 20:07:33 2005 +0000
     6.2 +++ b/xen/arch/ia64/domain.c	Thu Jun 09 22:10:19 2005 +0000
     6.3 @@ -210,7 +210,7 @@ void arch_do_createdomain(struct vcpu *v
     6.4  	 */
     6.5  	d->xen_vastart = 0xf000000000000000;
     6.6  	d->xen_vaend = 0xf300000000000000;
     6.7 -	d->breakimm = 0x1000;
     6.8 +	d->arch.breakimm = 0x1000;
     6.9  
    6.10  	// stay on kernel stack because may get interrupts!
    6.11  	// ia64_ret_from_clone (which b0 gets in new_thread) switches
    6.12 @@ -244,9 +244,11 @@ void arch_do_createdomain(struct vcpu *v
    6.13  	}
    6.14  #endif
    6.15  	d->max_pages = (128*1024*1024)/PAGE_SIZE; // 128MB default // FIXME
    6.16 -	if ((d->metaphysical_rid = allocate_metaphysical_rid()) == -1UL)
    6.17 +	if ((d->arch.metaphysical_rr0 = allocate_metaphysical_rr0()) == -1UL)
    6.18  		BUG();
    6.19  	v->vcpu_info->arch.metaphysical_mode = 1;
    6.20 +	v->arch.metaphysical_rr0 = d->arch.metaphysical_rr0;
    6.21 +	v->arch.metaphysical_saved_rr0 = d->arch.metaphysical_rr0;
    6.22  #define DOMAIN_RID_BITS_DEFAULT 18
    6.23  	if (!allocate_rid_range(d,DOMAIN_RID_BITS_DEFAULT)) // FIXME
    6.24  		BUG();
    6.25 @@ -254,7 +256,8 @@ void arch_do_createdomain(struct vcpu *v
    6.26  	d->xen_vastart = 0xf000000000000000;
    6.27  	d->xen_vaend = 0xf300000000000000;
    6.28  	d->shared_info_va = 0xf100000000000000;
    6.29 -	d->breakimm = 0x1000;
    6.30 +	d->arch.breakimm = 0x1000;
    6.31 +	v->arch.breakimm = d->arch.breakimm;
    6.32  	// stay on kernel stack because may get interrupts!
    6.33  	// ia64_ret_from_clone (which b0 gets in new_thread) switches
    6.34  	// to user stack
    6.35 @@ -403,6 +406,7 @@ printk("new_thread, about to call dom_fw
    6.36  printk("new_thread, done with dom_fw_setup\n");
    6.37  	// don't forget to set this!
    6.38  	v->vcpu_info->arch.banknum = 1;
    6.39 +	memset(v->arch._thread.fph,0,sizeof(struct ia64_fpreg)*96);
    6.40  }
    6.41  #endif // CONFIG_VTI
    6.42  
    6.43 @@ -450,7 +454,11 @@ extern unsigned long vhpt_paddr, vhpt_pe
    6.44  		if (d == dom0) p = map_new_domain0_page(mpaddr);
    6.45  		else
    6.46  #endif
    6.47 +		{
    6.48  			p = alloc_domheap_page(d);
    6.49 +			// zero out pages for security reasons
    6.50 +			memset(__va(page_to_phys(p)),0,PAGE_SIZE);
    6.51 +		}
    6.52  		if (unlikely(!p)) {
    6.53  printf("map_new_domain_page: Can't alloc!!!! Aaaargh!\n");
    6.54  			return(p);
    6.55 @@ -509,7 +517,6 @@ tryagain:
    6.56  	}
    6.57  	/* if lookup fails and mpaddr is "legal", "create" the page */
    6.58  	if ((mpaddr >> PAGE_SHIFT) < d->max_pages) {
    6.59 -		// FIXME: should zero out pages for security reasons
    6.60  		if (map_new_domain_page(d,mpaddr)) goto tryagain;
    6.61  	}
    6.62  	printk("lookup_domain_mpa: bad mpa %p (> %p\n",
     7.1 --- a/xen/arch/ia64/hyperprivop.S	Thu Jun 09 20:07:33 2005 +0000
     7.2 +++ b/xen/arch/ia64/hyperprivop.S	Thu Jun 09 22:10:19 2005 +0000
     7.3 @@ -14,6 +14,25 @@
     7.4  #include <asm/system.h>
     7.5  #include <public/arch-ia64.h>
     7.6  
     7.7 +#define FAST_HYPERPRIVOP_CNT
     7.8 +#define FAST_REFLECT_CNT
     7.9 +
    7.10 +// Should be included from common header file (also in process.c)
    7.11 +//  NO PSR_CLR IS DIFFERENT! (CPL)
    7.12 +#define IA64_PSR_CPL1	(__IA64_UL(1) << IA64_PSR_CPL1_BIT)
    7.13 +#define IA64_PSR_CPL0	(__IA64_UL(1) << IA64_PSR_CPL0_BIT)
    7.14 +// note IA64_PSR_PK removed from following, why is this necessary?
    7.15 +#define	DELIVER_PSR_SET	(IA64_PSR_IC | IA64_PSR_I | \
    7.16 +			IA64_PSR_DT | IA64_PSR_RT | IA64_PSR_CPL1 | \
    7.17 +			IA64_PSR_IT | IA64_PSR_BN)
    7.18 +
    7.19 +#define	DELIVER_PSR_CLR	(IA64_PSR_AC | IA64_PSR_DFL | IA64_PSR_DFH | \
    7.20 +			IA64_PSR_SP | IA64_PSR_DI | IA64_PSR_SI |	\
    7.21 +			IA64_PSR_DB | IA64_PSR_LP | IA64_PSR_TB | \
    7.22 +			IA64_PSR_MC | IA64_PSR_IS | \
    7.23 +			IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \
    7.24 +			IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | IA64_PSR_IA)
    7.25 +
    7.26  // Note: not hand-scheduled for now
    7.27  //  Registers at entry
    7.28  //	r16 == cr.isr
    7.29 @@ -22,7 +41,13 @@
    7.30  //	r19 == vpsr.ic (low 32 bits) | vpsr.i (high 32 bits)
    7.31  //	r31 == pr
    7.32  GLOBAL_ENTRY(fast_hyperprivop)
    7.33 -	//cover;;
    7.34 +#if 1
    7.35 +	// HYPERPRIVOP_SSM_I?
    7.36 +	// assumes domain interrupts pending, so just do it
    7.37 +	cmp.eq p7,p6=XEN_HYPER_SSM_I,r17
    7.38 +(p7)	br.sptk.many hyper_ssm_i;;
    7.39 +#endif
    7.40 +#if 1
    7.41  	// if domain interrupts pending, give up for now and do it the slow way
    7.42  	adds r20=XSI_PEND_OFS-XSI_PSR_IC_OFS,r18 ;;
    7.43  	ld8 r20=[r20] ;;
    7.44 @@ -32,11 +57,291 @@ GLOBAL_ENTRY(fast_hyperprivop)
    7.45  	// HYPERPRIVOP_RFI?
    7.46  	cmp.eq p7,p6=XEN_HYPER_RFI,r17
    7.47  (p7)	br.sptk.many hyper_rfi;;
    7.48 -	// if not rfi, give up for now and do it the slow way
    7.49 +
    7.50 +// hard to test, because only called from rbs_switch
    7.51 +	// HYPERPRIVOP_COVER?
    7.52 +	cmp.eq p7,p6=XEN_HYPER_COVER,r17
    7.53 +(p7)	br.sptk.many hyper_cover;;
    7.54 +#endif
    7.55 +
    7.56 +#if 1
    7.57 +	// HYPERPRIVOP_SSM_DT?
    7.58 +	cmp.eq p7,p6=XEN_HYPER_SSM_DT,r17
    7.59 +(p7)	br.sptk.many hyper_ssm_dt;;
    7.60 +#endif
    7.61 +
    7.62 +#if 1
    7.63 +	// HYPERPRIVOP_RSM_DT?
    7.64 +	cmp.eq p7,p6=XEN_HYPER_RSM_DT,r17
    7.65 +(p7)	br.sptk.many hyper_rsm_dt;;
    7.66 +#endif
    7.67 +
    7.68 +	// if not one of the above, give up for now and do it the slow way
    7.69  	br.sptk.many dispatch_break_fault ;;
    7.70  
    7.71 +
    7.72 +// give up for now if: ipsr.be==1, ipsr.pp==1
    7.73 +// from reflect_interruption, don't need to:
    7.74 +//  - printf first extint (debug only)
    7.75 +//  - check for interrupt collection enabled (routine will force on)
    7.76 +//  - set ifa (not valid for extint)
    7.77 +//  - set iha (not valid for extint)
    7.78 +//  - set itir (not valid for extint)
    7.79 +// DO need to
    7.80 +//  - increment the HYPER_SSM_I fast_hyperprivop counter
    7.81 +//  - set shared_mem iip to instruction after HYPER_SSM_I
    7.82 +//  - set cr.iip to guest iva+0x3000
    7.83 +//  - set shared_mem ipsr to [vcpu_get_ipsr_int_state]
    7.84 +//     be = pp = bn = 0; dt = it = rt = 1; cpl = 3 or 0;
    7.85 +//     i = shared_mem interrupt_delivery_enabled
    7.86 +//     ic = shared_mem interrupt_collection_enabled
    7.87 +//     ri = instruction after HYPER_SSM_I
    7.88 +//     all other bits unchanged from real cr.ipsr
    7.89 +//  - set cr.ipsr (DELIVER_PSR_SET/CLEAR, don't forget cpl!)
    7.90 +//  - set shared_mem isr: isr.ei to instr following HYPER_SSM_I
    7.91 +//	and isr.ri to cr.isr.ri (all other bits zero)
    7.92 +//  - cover and set shared_mem precover_ifs to cr.ifs
    7.93 +//		^^^ MISSED THIS FOR fast_break??
    7.94 +//  - set shared_mem ifs and incomplete_regframe to 0
    7.95 +//  - set shared_mem interrupt_delivery_enabled to 0
    7.96 +//  - set shared_mem interrupt_collection_enabled to 0
    7.97 +//  - set r31 to SHAREDINFO_ADDR
    7.98 +//  - virtual bank switch 0
    7.99 +// maybe implement later
   7.100 +//  - verify that there really IS a deliverable interrupt pending
   7.101 +//  - set shared_mem iva
   7.102 +// needs to be done but not implemented (in reflect_interruption)
   7.103 +//  - set shared_mem iipa
   7.104 +// don't know for sure
   7.105 +//  - set shared_mem unat
   7.106 +//	r16 == cr.isr
   7.107 +//	r17 == cr.iim
   7.108 +//	r18 == XSI_PSR_IC
   7.109 +//	r19 == vpsr.ic (low 32 bits) | vpsr.i (high 32 bits)
   7.110 +//	r31 == pr
   7.111 +ENTRY(hyper_ssm_i)
   7.112 +	// give up for now if: ipsr.be==1, ipsr.pp==1
   7.113 +	mov r30=cr.ipsr;;
   7.114 +	mov r29=cr.iip;;
   7.115 +	extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
   7.116 +	cmp.ne p7,p0=r21,r0
   7.117 +(p7)	br.sptk.many dispatch_break_fault ;;
   7.118 +	extr.u r21=r30,IA64_PSR_PP_BIT,1 ;;
   7.119 +	cmp.ne p7,p0=r21,r0
   7.120 +(p7)	br.sptk.many dispatch_break_fault ;;
   7.121 +#ifdef FAST_HYPERPRIVOP_CNT
   7.122 +	movl r20=fast_hyperpriv_cnt+(8*XEN_HYPER_SSM_I);;
   7.123 +	ld8 r21=[r20];;
   7.124 +	adds r21=1,r21;;
   7.125 +	st8 [r20]=r21;;
   7.126 +#endif
   7.127 +	// set shared_mem iip to instruction after HYPER_SSM_I
   7.128 +	extr.u r20=r30,41,2 ;;
   7.129 +	cmp.eq p6,p7=2,r20 ;;
   7.130 +(p6)	mov r20=0
   7.131 +(p6)	adds r29=16,r29
   7.132 +(p7)	adds r20=1,r20 ;;
   7.133 +	dep r30=r20,r30,41,2;;	// adjust cr.ipsr.ri but don't save yet
   7.134 +	adds r21=XSI_IIP_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.135 +	st8 [r21]=r29 ;;
   7.136 +	// set shared_mem isr
   7.137 +	extr.u r16=r16,38,1;;	// grab cr.isr.ir bit
   7.138 +	dep r16=r16,r0,38,1 ;;	// insert into cr.isr (rest of bits zero)
   7.139 +	dep r16=r20,r16,41,2 ;; // deposit cr.isr.ri
   7.140 +	adds r21=XSI_ISR_OFS-XSI_PSR_IC_OFS,r18 ;; 
   7.141 +	st8 [r21]=r16 ;;
   7.142 +	// set cr.ipsr
   7.143 +	mov r29=r30 ;;
   7.144 +	movl r28=DELIVER_PSR_SET;;
   7.145 +	movl r27=~DELIVER_PSR_CLR;;
   7.146 +	or r29=r29,r28;;
   7.147 +	and r29=r29,r27;;
   7.148 +	mov cr.ipsr=r29;;
   7.149 +	// set shared_mem ipsr (from ipsr in r30 with ipsr.ri already set)
   7.150 +	extr.u r29=r30,IA64_PSR_CPL0_BIT,2;;
   7.151 +	cmp.eq p6,p7=3,r29;;
   7.152 +(p6)	dep r30=-1,r30,IA64_PSR_CPL0_BIT,2
   7.153 +(p7)	dep r30=0,r30,IA64_PSR_CPL0_BIT,2
   7.154 +	;;
   7.155 +	// FOR SSM_I ONLY, also turn on psr.i and psr.ic
   7.156 +	movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT|IA64_PSR_I|IA64_PSR_IC);;
   7.157 +	movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN);;
   7.158 +	or r30=r30,r28;;
   7.159 +	and r30=r30,r27;;
   7.160 +	adds r21=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.161 +	st8 [r21]=r30 ;;
   7.162 +	// set shared_mem interrupt_delivery_enabled to 0
   7.163 +	// set shared_mem interrupt_collection_enabled to 0
   7.164 +	st8 [r18]=r0;;
   7.165 +	// cover and set shared_mem precover_ifs to cr.ifs
   7.166 +	// set shared_mem ifs and incomplete_regframe to 0
   7.167 +	cover ;;
   7.168 +	mov r20=cr.ifs;;
   7.169 +	adds r21=XSI_INCOMPL_REG_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.170 +	st4 [r21]=r0 ;;
   7.171 +	adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.172 +	st8 [r21]=r0 ;;
   7.173 +	adds r21=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.174 +	st8 [r21]=r20 ;;
   7.175 +	// leave cr.ifs alone for later rfi
   7.176 +	// set iip to go to domain IVA break instruction vector
   7.177 +	mov r22=IA64_KR(CURRENT);;
   7.178 +	adds r22=IA64_VCPU_IVA_OFFSET,r22;;
   7.179 +	ld8 r23=[r22];;
   7.180 +	movl r24=0x3000;;
   7.181 +	add r24=r24,r23;;
   7.182 +	mov cr.iip=r24;;
   7.183 +	// OK, now all set to go except for switch to virtual bank0
   7.184 +	mov r30=r2; mov r29=r3;;
   7.185 +	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
   7.186 +	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
   7.187 +	bsw.1;;
   7.188 +	st8 [r2]=r16,16; st8 [r3]=r17,16 ;;
   7.189 +	st8 [r2]=r18,16; st8 [r3]=r19,16 ;;
   7.190 +	st8 [r2]=r20,16; st8 [r3]=r21,16 ;;
   7.191 +	st8 [r2]=r22,16; st8 [r3]=r23,16 ;;
   7.192 +	st8 [r2]=r24,16; st8 [r3]=r25,16 ;;
   7.193 +	st8 [r2]=r26,16; st8 [r3]=r27,16 ;;
   7.194 +	st8 [r2]=r28,16; st8 [r3]=r29,16 ;;
   7.195 +	st8 [r2]=r30,16; st8 [r3]=r31,16 ;;
   7.196 +	movl r31=XSI_IPSR;;
   7.197 +	bsw.0 ;;
   7.198 +	mov r2=r30; mov r3=r29;;
   7.199 +	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.200 +	st4 [r20]=r0 ;;
   7.201 +	mov pr=r31,-1 ;;
   7.202 +	rfi
   7.203 +	;;
   7.204 +
   7.205 +// reflect domain breaks directly to domain
   7.206 +// FIXME: DOES NOT WORK YET
   7.207 +//	r16 == cr.isr
   7.208 +//	r17 == cr.iim
   7.209 +//	r18 == XSI_PSR_IC
   7.210 +//	r19 == vpsr.ic (low 32 bits) | vpsr.i (high 32 bits)
   7.211 +//	r31 == pr
   7.212 +GLOBAL_ENTRY(fast_break_reflect)
   7.213 +#define FAST_BREAK
   7.214 +#ifndef FAST_BREAK
   7.215 +	br.sptk.many dispatch_break_fault ;;
   7.216 +#endif
   7.217 +	mov r30=cr.ipsr;;
   7.218 +	mov r29=cr.iip;;
   7.219 +	extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
   7.220 +	cmp.ne p7,p0=r21,r0 ;;
   7.221 +(p7)	br.sptk.many dispatch_break_fault ;;
   7.222 +	extr.u r21=r30,IA64_PSR_PP_BIT,1 ;;
   7.223 +	cmp.ne p7,p0=r21,r0 ;;
   7.224 +(p7)	br.sptk.many dispatch_break_fault ;;
   7.225 +#if 1 /* special handling in case running on simulator */
   7.226 +	movl r20=first_break;;
   7.227 +	ld4 r23=[r20];;
   7.228 +	movl r21=0x80001;
   7.229 +	movl r22=0x80002;;
   7.230 +	cmp.ne p7,p0=r23,r0;;
   7.231 +(p7)	br.sptk.many dispatch_break_fault ;;
   7.232 +	cmp.eq p7,p0=r21,r17;
   7.233 +(p7)	br.sptk.many dispatch_break_fault ;;
   7.234 +	cmp.eq p7,p0=r22,r17;
   7.235 +(p7)	br.sptk.many dispatch_break_fault ;;
   7.236 +#endif
   7.237 +#ifdef FAST_REFLECT_CNT
   7.238 +	movl r20=fast_reflect_count+((0x2c00>>8)*8);;
   7.239 +	ld8 r21=[r20];;
   7.240 +	adds r21=1,r21;;
   7.241 +	st8 [r20]=r21;;
   7.242 +#endif
   7.243 +	// save iim in shared_info
   7.244 +	adds r21=XSI_IIM_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.245 +	st8 [r21]=r17;;
   7.246 +	// save iip in shared_info (DON'T POINT TO NEXT INSTRUCTION!)
   7.247 +	adds r21=XSI_IIP_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.248 +	st8 [r21]=r29;;
   7.249 +	// set shared_mem isr
   7.250 +	adds r21=XSI_ISR_OFS-XSI_PSR_IC_OFS,r18 ;; 
   7.251 +	st8 [r21]=r16 ;;
   7.252 +	// set cr.ipsr
   7.253 +	mov r29=r30 ;;
   7.254 +	movl r28=DELIVER_PSR_SET;;
   7.255 +	movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0);;
   7.256 +	or r29=r29,r28;;
   7.257 +	and r29=r29,r27;;
   7.258 +	mov cr.ipsr=r29;;
   7.259 +	// set shared_mem ipsr (from ipsr in r30 with ipsr.ri already set)
   7.260 +	extr.u r29=r30,IA64_PSR_CPL0_BIT,2;;
   7.261 +	cmp.eq p6,p7=3,r29;;
   7.262 +(p6)	dep r30=-1,r30,IA64_PSR_CPL0_BIT,2
   7.263 +(p7)	dep r30=0,r30,IA64_PSR_CPL0_BIT,2
   7.264 +	;;
   7.265 +	movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT);;
   7.266 +	movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN);;
   7.267 +	or r30=r30,r28;;
   7.268 +	and r30=r30,r27;;
   7.269 +	// also set shared_mem ipsr.i and ipsr.ic appropriately
   7.270 +	ld8 r20=[r18];;
   7.271 +	extr.u r22=r20,32,32
   7.272 +	cmp4.eq p6,p7=r20,r0;;
   7.273 +(p6)	dep r30=0,r30,IA64_PSR_IC_BIT,1
   7.274 +(p7)	dep r30=-1,r30,IA64_PSR_IC_BIT,1 ;;
   7.275 +	cmp4.eq p6,p7=r22,r0;;
   7.276 +(p6)	dep r30=0,r30,IA64_PSR_I_BIT,1
   7.277 +(p7)	dep r30=-1,r30,IA64_PSR_I_BIT,1 ;;
   7.278 +	adds r21=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.279 +	st8 [r21]=r30 ;;
   7.280 +	// set shared_mem interrupt_delivery_enabled to 0
   7.281 +	// set shared_mem interrupt_collection_enabled to 0
   7.282 +	st8 [r18]=r0;;
   7.283 +	// cover and set shared_mem precover_ifs to cr.ifs
   7.284 +	// set shared_mem ifs and incomplete_regframe to 0
   7.285 +	cover ;;
   7.286 +	mov r20=cr.ifs;;
   7.287 +	adds r21=XSI_INCOMPL_REG_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.288 +	st4 [r21]=r0 ;;
   7.289 +	adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.290 +	st8 [r21]=r0 ;;
   7.291 +	adds r21=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.292 +	st8 [r21]=r20 ;;
   7.293 +	// vpsr.i = vpsr.ic = 0 on delivery of interruption
   7.294 +	st8 [r18]=r0;;
   7.295 +	// FIXME: need to save iipa and isr to be arch-compliant
   7.296 +	// set iip to go to domain IVA break instruction vector
   7.297 +	mov r22=IA64_KR(CURRENT);;
   7.298 +	adds r22=IA64_VCPU_IVA_OFFSET,r22;;
   7.299 +	ld8 r23=[r22];;
   7.300 +	movl r24=0x2c00;;
   7.301 +	add r24=r24,r23;;
   7.302 +	mov cr.iip=r24;;
   7.303 +	// OK, now all set to go except for switch to virtual bank0
   7.304 +	mov r30=r2; mov r29=r3;;
   7.305 +	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
   7.306 +	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
   7.307 +	bsw.1;;
   7.308 +	st8 [r2]=r16,16; st8 [r3]=r17,16 ;;
   7.309 +	st8 [r2]=r18,16; st8 [r3]=r19,16 ;;
   7.310 +	st8 [r2]=r20,16; st8 [r3]=r21,16 ;;
   7.311 +	st8 [r2]=r22,16; st8 [r3]=r23,16 ;;
   7.312 +	st8 [r2]=r24,16; st8 [r3]=r25,16 ;;
   7.313 +	st8 [r2]=r26,16; st8 [r3]=r27,16 ;;
   7.314 +	st8 [r2]=r28,16; st8 [r3]=r29,16 ;;
   7.315 +	st8 [r2]=r30,16; st8 [r3]=r31,16 ;;
   7.316 +	movl r31=XSI_IPSR;;
   7.317 +	bsw.0 ;;
   7.318 +	mov r2=r30; mov r3=r29;;
   7.319 +	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.320 +	st4 [r20]=r0 ;;
   7.321 +	mov pr=r31,-1 ;;
   7.322 +	rfi
   7.323 +	;;
   7.324 +
   7.325 +
   7.326  // ensure that, if giving up, registers at entry to fast_hyperprivop unchanged
   7.327  ENTRY(hyper_rfi)
   7.328 +#ifdef FAST_HYPERPRIVOP_CNT
   7.329 +	movl r20=fast_hyperpriv_cnt+(8*XEN_HYPER_RFI);;
   7.330 +	ld8 r21=[r20];;
   7.331 +	adds r21=1,r21;;
   7.332 +	st8 [r20]=r21;;
   7.333 +#endif
   7.334  	adds r20=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.335  	ld8 r21=[r20];;		// r21 = vcr.ipsr
   7.336  	extr.u r22=r21,IA64_PSR_BE_BIT,1 ;;
   7.337 @@ -78,8 +383,6 @@ ENTRY(hyper_rfi)
   7.338  	ld8 r20=[r20];;
   7.339  	dep r20=0,r20,38,25;; // ensure ifs has no reserved bits set
   7.340  	mov cr.ifs=r20 ;;
   7.341 -// TODO: increment a counter so we can count how many rfi's go the fast way
   7.342 -//    but where?  counter must be pinned
   7.343  	// ipsr.cpl == (vcr.ipsr.cpl == 0) 2 : 3;
   7.344  	dep r21=-1,r21,IA64_PSR_CPL1_BIT,1 ;;
   7.345  	// vpsr.i = vcr.ipsr.i; vpsr.ic = vcr.ipsr.ic
   7.346 @@ -101,3 +404,110 @@ ENTRY(hyper_rfi)
   7.347  	;;
   7.348  	rfi
   7.349  	;;
   7.350 +
   7.351 +ENTRY(hyper_cover)
   7.352 +#ifdef FAST_HYPERPRIVOP_CNT
   7.353 +	movl r20=fast_hyperpriv_cnt+(8*XEN_HYPER_COVER);;
   7.354 +	ld8 r21=[r20];;
   7.355 +	adds r21=1,r21;;
   7.356 +	st8 [r20]=r21;;
   7.357 +#endif
   7.358 +	mov r24=cr.ipsr
   7.359 +	mov r25=cr.iip;;
   7.360 +	// skip test for vpsr.ic.. it's a prerequisite for hyperprivops
   7.361 +	cover ;;
   7.362 +	adds r20=XSI_INCOMPL_REG_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.363 +	mov r30=cr.ifs;;
   7.364 +	adds r22=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18
   7.365 +	ld4 r21=[r20] ;;
   7.366 +	cmp.eq p6,p7=r21,r0 ;;
   7.367 +(p6)	st8 [r22]=r30;;
   7.368 +(p7)	st4 [r20]=r0;;
   7.369 +	mov cr.ifs=r0;;
   7.370 +	// adjust return address to skip over break instruction
   7.371 +	extr.u r26=r24,41,2 ;;
   7.372 +	cmp.eq p6,p7=2,r26 ;;
   7.373 +(p6)	mov r26=0
   7.374 +(p6)	adds r25=16,r25
   7.375 +(p7)	adds r26=1,r26
   7.376 +	;;
   7.377 +	dep r24=r26,r24,41,2
   7.378 +	;;
   7.379 +	mov cr.ipsr=r24
   7.380 +	mov cr.iip=r25
   7.381 +	mov pr=r31,-1 ;;
   7.382 +	rfi
   7.383 +	;;
   7.384 +
   7.385 +#if 1
   7.386 +// return from metaphysical mode (meta=1) to virtual mode (meta=0)
   7.387 +ENTRY(hyper_ssm_dt)
   7.388 +#ifdef FAST_HYPERPRIVOP_CNT
   7.389 +	movl r20=fast_hyperpriv_cnt+(8*XEN_HYPER_SSM_DT);;
   7.390 +	ld8 r21=[r20];;
   7.391 +	adds r21=1,r21;;
   7.392 +	st8 [r20]=r21;;
   7.393 +#endif
   7.394 +	mov r24=cr.ipsr
   7.395 +	mov r25=cr.iip;;
   7.396 +	adds r20=XSI_METAPHYS_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.397 +	ld4 r21=[r20];;
   7.398 +	cmp.eq p7,p0=r21,r0	// meta==0?
   7.399 +(p7)	br.spnt.many	1f ;;	// already in virtual mode
   7.400 +	mov r22=IA64_KR(CURRENT);;
   7.401 +	adds r22=IA64_VCPU_META_SAVED_RR0_OFFSET,r22;;
   7.402 +	ld4 r23=[r22];;
   7.403 +	mov rr[r0]=r23;;
   7.404 +	srlz.i;;
   7.405 +	st4 [r20]=r0 ;;
   7.406 +	// adjust return address to skip over break instruction
   7.407 +1:	extr.u r26=r24,41,2 ;;
   7.408 +	cmp.eq p6,p7=2,r26 ;;
   7.409 +(p6)	mov r26=0
   7.410 +(p6)	adds r25=16,r25
   7.411 +(p7)	adds r26=1,r26
   7.412 +	;;
   7.413 +	dep r24=r26,r24,41,2
   7.414 +	;;
   7.415 +	mov cr.ipsr=r24
   7.416 +	mov cr.iip=r25
   7.417 +	mov pr=r31,-1 ;;
   7.418 +	rfi
   7.419 +	;;
   7.420 +
   7.421 +// go to metaphysical mode (meta=1) from virtual mode (meta=0)
   7.422 +ENTRY(hyper_rsm_dt)
   7.423 +#ifdef FAST_HYPERPRIVOP_CNT
   7.424 +	movl r20=fast_hyperpriv_cnt+(8*XEN_HYPER_RSM_DT);;
   7.425 +	ld8 r21=[r20];;
   7.426 +	adds r21=1,r21;;
   7.427 +	st8 [r20]=r21;;
   7.428 +#endif
   7.429 +	mov r24=cr.ipsr
   7.430 +	mov r25=cr.iip;;
   7.431 +	adds r20=XSI_METAPHYS_OFS-XSI_PSR_IC_OFS,r18 ;;
   7.432 +	ld4 r21=[r20];;
   7.433 +	cmp.ne p7,p0=r21,r0	// meta==0?
   7.434 +(p7)	br.spnt.many	1f ;;	// already in metaphysical mode
   7.435 +	mov r22=IA64_KR(CURRENT);;
   7.436 +	adds r22=IA64_VCPU_META_RR0_OFFSET,r22;;
   7.437 +	ld4 r23=[r22];;
   7.438 +	mov rr[r0]=r23;;
   7.439 +	srlz.i;;
   7.440 +	adds r21=1,r0 ;;
   7.441 +	st4 [r20]=r21 ;;
   7.442 +	// adjust return address to skip over break instruction
   7.443 +1:	extr.u r26=r24,41,2 ;;
   7.444 +	cmp.eq p6,p7=2,r26 ;;
   7.445 +(p6)	mov r26=0
   7.446 +(p6)	adds r25=16,r25
   7.447 +(p7)	adds r26=1,r26
   7.448 +	;;
   7.449 +	dep r24=r26,r24,41,2
   7.450 +	;;
   7.451 +	mov cr.ipsr=r24
   7.452 +	mov cr.iip=r25
   7.453 +	mov pr=r31,-1 ;;
   7.454 +	rfi
   7.455 +	;;
   7.456 +#endif
     8.1 --- a/xen/arch/ia64/ivt.S	Thu Jun 09 20:07:33 2005 +0000
     8.2 +++ b/xen/arch/ia64/ivt.S	Thu Jun 09 22:10:19 2005 +0000
     8.3 @@ -783,21 +783,22 @@ ENTRY(break_fault)
     8.4  	ld8 r19=[r18]
     8.5  	;;
     8.6  	cmp.eq p7,p0=r0,r17			// is this a psuedo-cover?
     8.7 -(p7)	br.sptk.many dispatch_privop_fault
     8.8 +(p7)	br.spnt.many dispatch_privop_fault
     8.9  	;;
    8.10 -	cmp4.ne p7,p0=r0,r19
    8.11 -(p7)	br.sptk.many dispatch_break_fault
    8.12 -	// If we get to here, we have a hyperprivop
    8.13 -	// For now, hyperprivops are handled through the break mechanism
    8.14 -	// Later, they will be fast hand-coded assembly with psr.ic off
    8.15 +	// if vpsr.ic is off, we have a hyperprivop
    8.16 +	// A hyperprivop is hand-coded assembly with psr.ic off
    8.17  	// which means no calls, no use of r1-r15 and no memory accesses
    8.18  	// except to pinned addresses!
    8.19 -#define FAST_HYPERPRIVOPS
    8.20 -#ifdef FAST_HYPERPRIVOPS
    8.21 -	br.sptk.many fast_hyperprivop
    8.22 -#else
    8.23 -	br.sptk.many dispatch_break_fault
    8.24 -#endif
    8.25 +	cmp4.eq p7,p0=r0,r19
    8.26 +(p7)	br.sptk.many fast_hyperprivop
    8.27 +	;;
    8.28 +	mov r22=IA64_KR(CURRENT);;
    8.29 +	adds r22=IA64_VCPU_BREAKIMM_OFFSET,r22;;
    8.30 +	ld4 r23=[r22];;
    8.31 +	cmp4.eq p6,p7=r23,r17			// Xen-reserved breakimm?
    8.32 +(p6)	br.spnt.many dispatch_break_fault
    8.33 +	;;
    8.34 +	br.sptk.many fast_break_reflect
    8.35  	;;
    8.36  #endif
    8.37  	mov r16=IA64_KR(CURRENT)		// r16 = current task; 12 cycle read lat.
     9.1 --- a/xen/arch/ia64/patch/linux-2.6.11/efi.c	Thu Jun 09 20:07:33 2005 +0000
     9.2 +++ b/xen/arch/ia64/patch/linux-2.6.11/efi.c	Thu Jun 09 22:10:19 2005 +0000
     9.3 @@ -1,17 +1,23 @@
     9.4  --- ../../linux-2.6.11/arch/ia64/kernel/efi.c	2005-03-02 00:37:47.000000000 -0700
     9.5 -+++ arch/ia64/efi.c	2005-04-29 14:09:24.000000000 -0600
     9.6 -@@ -320,6 +320,10 @@
     9.7 ++++ arch/ia64/efi.c	2005-06-09 06:15:36.000000000 -0600
     9.8 +@@ -320,6 +320,16 @@
     9.9   		if (!(md->attribute & EFI_MEMORY_WB))
    9.10   			continue;
    9.11   
    9.12  +#ifdef XEN
    9.13 ++// this works around a problem in the ski bootloader
    9.14 ++{
    9.15 ++		extern long running_on_sim;
    9.16 ++		if (running_on_sim && md->type != EFI_CONVENTIONAL_MEMORY)
    9.17 ++			continue;
    9.18 ++}
    9.19  +// this is a temporary hack to avoid CONFIG_VIRTUAL_MEM_MAP
    9.20  +		if (md->phys_addr >= 0x100000000) continue;
    9.21  +#endif
    9.22   		/*
    9.23   		 * granule_addr is the base of md's first granule.
    9.24   		 * [granule_addr - first_non_wb_addr) is guaranteed to
    9.25 -@@ -719,6 +723,30 @@
    9.26 +@@ -719,6 +729,30 @@
    9.27   	return 0;
    9.28   }
    9.29   
    10.1 --- a/xen/arch/ia64/patch/linux-2.6.11/pgalloc.h	Thu Jun 09 20:07:33 2005 +0000
    10.2 +++ b/xen/arch/ia64/patch/linux-2.6.11/pgalloc.h	Thu Jun 09 22:10:19 2005 +0000
    10.3 @@ -1,54 +1,58 @@
    10.4  --- ../../linux-2.6.11/include/asm-ia64/pgalloc.h	2005-03-02 00:37:31.000000000 -0700
    10.5 -+++ include/asm-ia64/pgalloc.h	2005-04-29 17:09:20.000000000 -0600
    10.6 -@@ -61,7 +61,11 @@
    10.7 ++++ include/asm-ia64/pgalloc.h	2005-06-09 13:40:48.000000000 -0600
    10.8 +@@ -61,7 +61,12 @@
    10.9   	pgd_t *pgd = pgd_alloc_one_fast(mm);
   10.10   
   10.11   	if (unlikely(pgd == NULL)) {
   10.12  +#ifdef XEN
   10.13  +		pgd = (pgd_t *)alloc_xenheap_page();
   10.14 ++		memset(pgd,0,PAGE_SIZE);
   10.15  +#else
   10.16   		pgd = (pgd_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
   10.17  +#endif
   10.18   	}
   10.19   	return pgd;
   10.20   }
   10.21 -@@ -104,7 +108,11 @@
   10.22 +@@ -104,7 +109,12 @@
   10.23   static inline pmd_t*
   10.24   pmd_alloc_one (struct mm_struct *mm, unsigned long addr)
   10.25   {
   10.26  +#ifdef XEN
   10.27  +	pmd_t *pmd = (pmd_t *)alloc_xenheap_page();
   10.28 ++	memset(pmd,0,PAGE_SIZE);
   10.29  +#else
   10.30   	pmd_t *pmd = (pmd_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
   10.31  +#endif
   10.32   
   10.33   	return pmd;
   10.34   }
   10.35 -@@ -136,7 +144,11 @@
   10.36 +@@ -136,7 +146,12 @@
   10.37   static inline struct page *
   10.38   pte_alloc_one (struct mm_struct *mm, unsigned long addr)
   10.39   {
   10.40  +#ifdef XEN
   10.41  +	struct page *pte = alloc_xenheap_page();
   10.42 ++	memset(pte,0,PAGE_SIZE);
   10.43  +#else
   10.44   	struct page *pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
   10.45  +#endif
   10.46   
   10.47   	return pte;
   10.48   }
   10.49 -@@ -144,7 +156,11 @@
   10.50 +@@ -144,7 +159,12 @@
   10.51   static inline pte_t *
   10.52   pte_alloc_one_kernel (struct mm_struct *mm, unsigned long addr)
   10.53   {
   10.54  +#ifdef XEN
   10.55  +	pte_t *pte = (pte_t *)alloc_xenheap_page();
   10.56 ++	memset(pte,0,PAGE_SIZE);
   10.57  +#else
   10.58   	pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
   10.59  +#endif
   10.60   
   10.61   	return pte;
   10.62   }
   10.63 -@@ -152,13 +168,21 @@
   10.64 +@@ -152,13 +172,21 @@
   10.65   static inline void
   10.66   pte_free (struct page *pte)
   10.67   {
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/xen/arch/ia64/patch/linux-2.6.11/sn_sal.h	Thu Jun 09 22:10:19 2005 +0000
    11.3 @@ -0,0 +1,33 @@
    11.4 +--- /data/lwork/attica1/edwardsg/linux-2.6.11/include/asm-ia64/sn/sn_sal.h	2005-03-02 01:38:33 -06:00
    11.5 ++++ include/asm-ia64/sn/sn_sal.h	2005-06-01 14:31:47 -05:00
    11.6 +@@ -123,6 +123,7 @@
    11.7 + #define SALRET_ERROR		(-3)
    11.8 +
    11.9 +
   11.10 ++#ifndef XEN
   11.11 + /**
   11.12 +  * sn_sal_rev_major - get the major SGI SAL revision number
   11.13 +  *
   11.14 +@@ -226,6 +227,7 @@ ia64_sn_get_klconfig_addr(nasid_t nasid)
   11.15 + 	}
   11.16 + 	return ret_stuff.v0 ? __va(ret_stuff.v0) : NULL;
   11.17 + }
   11.18 ++#endif /* !XEN */
   11.19 +
   11.20 + /*
   11.21 +  * Returns the next console character.
   11.22 +@@ -304,6 +306,7 @@ ia64_sn_console_putb(const char *buf, in
   11.23 + 	return (u64)0;
   11.24 + }
   11.25 +
   11.26 ++#ifndef XEN
   11.27 + /*
   11.28 +  * Print a platform error record
   11.29 +  */
   11.30 +@@ -987,5 +990,5 @@ ia64_sn_hwperf_op(nasid_t nasid, u64 opc
   11.31 + 		*v0 = (int) rv.v0;
   11.32 + 	return (int) rv.status;
   11.33 + }
   11.34 +-
   11.35 ++#endif /* !XEN */
   11.36 + #endif /* _ASM_IA64_SN_SN_SAL_H */
    12.1 --- a/xen/arch/ia64/pcdp.c	Thu Jun 09 20:07:33 2005 +0000
    12.2 +++ b/xen/arch/ia64/pcdp.c	Thu Jun 09 22:10:19 2005 +0000
    12.3 @@ -26,9 +26,9 @@ setup_serial_console(struct pcdp_uart *u
    12.4  #ifdef XEN
    12.5  	extern char opt_com1[1];
    12.6  	if (opt_com1[0]) return 0;
    12.7 -	sprintf(&opt_com1[0], "0x%lx,%lu,%dn1",
    12.8 -		uart->addr.address, uart->baud,
    12.9 -		uart->bits ? uart->bits : 8);
   12.10 +	sprintf(&opt_com1[0], "%lu,%dn1,0x%lx,9",
   12.11 +		uart->baud, uart->bits ? uart->bits : 8,
   12.12 +		uart->addr.address);
   12.13  	return 0;
   12.14  #else
   12.15  #ifdef CONFIG_SERIAL_8250_CONSOLE
    13.1 --- a/xen/arch/ia64/privop.c	Thu Jun 09 20:07:33 2005 +0000
    13.2 +++ b/xen/arch/ia64/privop.c	Thu Jun 09 22:10:19 2005 +0000
    13.3 @@ -747,14 +747,16 @@ priv_emulate(VCPU *vcpu, REGS *regs, UIN
    13.4  #define HYPERPRIVOP_COVER		0x4
    13.5  #define HYPERPRIVOP_ITC_D		0x5
    13.6  #define HYPERPRIVOP_ITC_I		0x6
    13.7 -#define HYPERPRIVOP_MAX			0x6
    13.8 +#define HYPERPRIVOP_SSM_I		0x7
    13.9 +#define HYPERPRIVOP_MAX			0x7
   13.10  
   13.11  char *hyperpriv_str[HYPERPRIVOP_MAX+1] = {
   13.12 -	0, "rfi", "rsm.dt", "ssm.dt", "cover", "itc.d", "itc.i",
   13.13 +	0, "rfi", "rsm.dt", "ssm.dt", "cover", "itc.d", "itc.i", "ssm.i",
   13.14  	0
   13.15  };
   13.16  
   13.17 -unsigned long hyperpriv_cnt[HYPERPRIVOP_MAX+1] = { 0 };
   13.18 +unsigned long slow_hyperpriv_cnt[HYPERPRIVOP_MAX+1] = { 0 };
   13.19 +unsigned long fast_hyperpriv_cnt[HYPERPRIVOP_MAX+1] = { 0 };
   13.20  
   13.21  /* hyperprivops are generally executed in assembly (with physical psr.ic off)
   13.22   * so this code is primarily used for debugging them */
   13.23 @@ -765,13 +767,12 @@ ia64_hyperprivop(unsigned long iim, REGS
   13.24  	INST64 inst;
   13.25  	UINT64 val;
   13.26  
   13.27 -// FIXME: Add instrumentation for these
   13.28  // FIXME: Handle faults appropriately for these
   13.29  	if (!iim || iim > HYPERPRIVOP_MAX) {
   13.30  		printf("bad hyperprivop; ignored\n");
   13.31  		return 1;
   13.32  	}
   13.33 -	hyperpriv_cnt[iim]++;
   13.34 +	slow_hyperpriv_cnt[iim]++;
   13.35  	switch(iim) {
   13.36  	    case HYPERPRIVOP_RFI:
   13.37  		(void)vcpu_rfi(v);
   13.38 @@ -793,6 +794,9 @@ ia64_hyperprivop(unsigned long iim, REGS
   13.39  		inst.inst = 0;
   13.40  		(void)priv_itc_i(v,inst);
   13.41  		return 1;
   13.42 +	    case HYPERPRIVOP_SSM_I:
   13.43 +		(void)vcpu_set_psr_i(v);
   13.44 +		return 1;
   13.45  	}
   13.46  	return 0;
   13.47  }
   13.48 @@ -981,18 +985,28 @@ int dump_hyperprivop_counts(char *buf)
   13.49  {
   13.50  	int i;
   13.51  	char *s = buf;
   13.52 -	s += sprintf(s,"Slow hyperprivops:\n");
   13.53 +	unsigned long total = 0;
   13.54 +	for (i = 1; i <= HYPERPRIVOP_MAX; i++) total += slow_hyperpriv_cnt[i];
   13.55 +	s += sprintf(s,"Slow hyperprivops (total %d):\n",total);
   13.56  	for (i = 1; i <= HYPERPRIVOP_MAX; i++)
   13.57 -		if (hyperpriv_cnt[i])
   13.58 +		if (slow_hyperpriv_cnt[i])
   13.59  			s += sprintf(s,"%10d %s\n",
   13.60 -				hyperpriv_cnt[i], hyperpriv_str[i]);
   13.61 +				slow_hyperpriv_cnt[i], hyperpriv_str[i]);
   13.62 +	total = 0;
   13.63 +	for (i = 1; i <= HYPERPRIVOP_MAX; i++) total += fast_hyperpriv_cnt[i];
   13.64 +	s += sprintf(s,"Fast hyperprivops (total %d):\n",total);
   13.65 +	for (i = 1; i <= HYPERPRIVOP_MAX; i++)
   13.66 +		if (fast_hyperpriv_cnt[i])
   13.67 +			s += sprintf(s,"%10d %s\n",
   13.68 +				fast_hyperpriv_cnt[i], hyperpriv_str[i]);
   13.69  	return s - buf;
   13.70  }
   13.71  
   13.72  void zero_hyperprivop_counts(void)
   13.73  {
   13.74  	int i;
   13.75 -	for (i = 0; i <= HYPERPRIVOP_MAX; i++) hyperpriv_cnt[i] = 0;
   13.76 +	for (i = 0; i <= HYPERPRIVOP_MAX; i++) slow_hyperpriv_cnt[i] = 0;
   13.77 +	for (i = 0; i <= HYPERPRIVOP_MAX; i++) fast_hyperpriv_cnt[i] = 0;
   13.78  }
   13.79  
   13.80  #define TMPBUFLEN 8*1024
   13.81 @@ -1002,6 +1016,7 @@ int dump_privop_counts_to_user(char __us
   13.82  	int n = dump_privop_counts(buf);
   13.83  
   13.84  	n += dump_hyperprivop_counts(buf + n);
   13.85 +	n += dump_reflect_counts(buf + n);
   13.86  #ifdef PRIVOP_ADDR_COUNT
   13.87  	n += dump_privop_addrs(buf + n);
   13.88  #endif
   13.89 @@ -1019,6 +1034,7 @@ int zero_privop_counts_to_user(char __us
   13.90  #ifdef PRIVOP_ADDR_COUNT
   13.91  	zero_privop_addrs();
   13.92  #endif
   13.93 +	zero_reflect_counts();
   13.94  	if (len < TMPBUFLEN) return -1;
   13.95  	if (__copy_to_user(ubuf,buf,n)) return -1;
   13.96  	return n;
    14.1 --- a/xen/arch/ia64/process.c	Thu Jun 09 20:07:33 2005 +0000
    14.2 +++ b/xen/arch/ia64/process.c	Thu Jun 09 22:10:19 2005 +0000
    14.3 @@ -130,6 +130,42 @@ unsigned long translate_domain_mpaddr(un
    14.4  	return ((pteval & _PAGE_PPN_MASK) | (mpaddr & ~PAGE_MASK));
    14.5  }
    14.6  
    14.7 +unsigned long slow_reflect_count[0x80] = { 0 };
    14.8 +unsigned long fast_reflect_count[0x80] = { 0 };
    14.9 +
   14.10 +#define inc_slow_reflect_count(vec) slow_reflect_count[vec>>8]++;
   14.11 +
   14.12 +void zero_reflect_counts(void)
   14.13 +{
   14.14 +	int i;
   14.15 +	for (i=0; i<0x80; i++) slow_reflect_count[i] = 0;
   14.16 +	for (i=0; i<0x80; i++) fast_reflect_count[i] = 0;
   14.17 +}
   14.18 +
   14.19 +int dump_reflect_counts(char *buf)
   14.20 +{
   14.21 +	int i,j,cnt;
   14.22 +	char *s = buf;
   14.23 +
   14.24 +	s += sprintf(s,"Slow reflections by vector:\n");
   14.25 +	for (i = 0, j = 0; i < 0x80; i++) {
   14.26 +		if (cnt = slow_reflect_count[i]) {
   14.27 +			s += sprintf(s,"0x%02x00:%10d, ",i,cnt);
   14.28 +			if ((j++ & 3) == 3) s += sprintf(s,"\n");
   14.29 +		}
   14.30 +	}
   14.31 +	if (j & 3) s += sprintf(s,"\n");
   14.32 +	s += sprintf(s,"Fast reflections by vector:\n");
   14.33 +	for (i = 0, j = 0; i < 0x80; i++) {
   14.34 +		if (cnt = fast_reflect_count[i]) {
   14.35 +			s += sprintf(s,"0x%02x00:%10d, ",i,cnt);
   14.36 +			if ((j++ & 3) == 3) s += sprintf(s,"\n");
   14.37 +		}
   14.38 +	}
   14.39 +	if (j & 3) s += sprintf(s,"\n");
   14.40 +	return s - buf;
   14.41 +}
   14.42 +
   14.43  void reflect_interruption(unsigned long ifa, unsigned long isr, unsigned long itiriim, struct pt_regs *regs, unsigned long vector)
   14.44  {
   14.45  	unsigned long vcpu_get_ipsr_int_state(struct vcpu *,unsigned long);
   14.46 @@ -165,6 +201,7 @@ panic_domain(regs,"psr.ic off, deliverin
   14.47  		regs->cr_ipsr = (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
   14.48  // NOTE: nested trap must NOT pass PSCB address
   14.49  		//regs->r31 = (unsigned long) &PSCB(v);
   14.50 +		inc_slow_reflect_count(vector);
   14.51  		return;
   14.52  
   14.53  	}
   14.54 @@ -195,10 +232,14 @@ panic_domain(regs,"psr.ic off, deliverin
   14.55  
   14.56  	PSCB(v,interrupt_delivery_enabled) = 0;
   14.57  	PSCB(v,interrupt_collection_enabled) = 0;
   14.58 +
   14.59 +	inc_slow_reflect_count(vector);
   14.60  }
   14.61  
   14.62  void foodpi(void) {}
   14.63  
   14.64 +unsigned long pending_false_positive = 0;
   14.65 +
   14.66  // ONLY gets called from ia64_leave_kernel
   14.67  // ONLY call with interrupts disabled?? (else might miss one?)
   14.68  // NEVER successful if already reflecting a trap/fault because psr.i==0
   14.69 @@ -215,6 +256,8 @@ void deliver_pending_interrupt(struct pt
   14.70  printf("*#*#*#* about to deliver early timer to domain %d!!!\n",v->domain->domain_id);
   14.71  			reflect_interruption(0,isr,0,regs,IA64_EXTINT_VECTOR);
   14.72  		}
   14.73 +		else if (PSCB(v,pending_interruption))
   14.74 +			++pending_false_positive;
   14.75  	}
   14.76  }
   14.77  
   14.78 @@ -725,30 +768,31 @@ if (!running_on_sim) { printf("SSC_OPEN,
   14.79  		vcpu_set_gr(current,8,-1L);
   14.80  		break;
   14.81  	    default:
   14.82 -		printf("ia64_handle_break: bad ssc code %lx\n",ssc);
   14.83 +		printf("ia64_handle_break: bad ssc code %lx, iip=%p\n",ssc,regs->cr_iip);
   14.84  		break;
   14.85  	}
   14.86  	vcpu_increment_iip(current);
   14.87  }
   14.88  
   14.89 +int first_break = 1;
   14.90 +
   14.91  void
   14.92  ia64_handle_break (unsigned long ifa, struct pt_regs *regs, unsigned long isr, unsigned long iim)
   14.93  {
   14.94 -	static int first_time = 1;
   14.95  	struct domain *d = (struct domain *) current->domain;
   14.96  	struct vcpu *v = (struct domain *) current;
   14.97  	extern unsigned long running_on_sim;
   14.98  
   14.99 -	if (first_time) {
  14.100 +	if (first_break) {
  14.101  		if (platform_is_hp_ski()) running_on_sim = 1;
  14.102  		else running_on_sim = 0;
  14.103 -		first_time = 0;
  14.104 +		first_break = 0;
  14.105  	}
  14.106  	if (iim == 0x80001 || iim == 0x80002) {	//FIXME: don't hardcode constant
  14.107  		if (running_on_sim) do_ssc(vcpu_get_gr(current,36), regs);
  14.108  		else do_ssc(vcpu_get_gr(current,36), regs);
  14.109  	}
  14.110 -	else if (iim == d->breakimm) {
  14.111 +	else if (iim == d->arch.breakimm) {
  14.112  		if (ia64_hypercall(regs))
  14.113  			vcpu_increment_iip(current);
  14.114  	}
  14.115 @@ -811,7 +855,8 @@ ia64_handle_reflection (unsigned long if
  14.116  		check_lazy_cover = 1;
  14.117  		vector = IA64_DATA_ACCESS_RIGHTS_VECTOR; break;
  14.118  	    case 25:
  14.119 -		vector = IA64_DISABLED_FPREG_VECTOR; break;
  14.120 +		vector = IA64_DISABLED_FPREG_VECTOR;
  14.121 +		break;
  14.122  	    case 26:
  14.123  printf("*** NaT fault... attempting to handle as privop\n");
  14.124  		vector = priv_emulate(v,regs,isr);
    15.1 --- a/xen/arch/ia64/regionreg.c	Thu Jun 09 20:07:33 2005 +0000
    15.2 +++ b/xen/arch/ia64/regionreg.c	Thu Jun 09 22:10:19 2005 +0000
    15.3 @@ -63,9 +63,14 @@ unsigned long allocate_reserved_rid(void
    15.4  
    15.5  
    15.6  // returns -1 if none available
    15.7 -unsigned long allocate_metaphysical_rid(void)
    15.8 +unsigned long allocate_metaphysical_rr0(void)
    15.9  {
   15.10 -	unsigned long rid = allocate_reserved_rid();
   15.11 +	ia64_rr rrv;
   15.12 +
   15.13 +	rrv.rid = allocate_reserved_rid();
   15.14 +	rrv.ps = PAGE_SHIFT;
   15.15 +	rrv.ve = 0;
   15.16 +	return rrv.rrval;
   15.17  }
   15.18  
   15.19  int deallocate_metaphysical_rid(unsigned long rid)
   15.20 @@ -282,22 +287,20 @@ int set_one_rr(unsigned long rr, unsigne
   15.21  		if (rreg == 6) newrrv.ve = VHPT_ENABLED_REGION_7;
   15.22  		else newrrv.ve = VHPT_ENABLED_REGION_0_TO_6;
   15.23  		newrrv.ps = PAGE_SHIFT;
   15.24 +		if (rreg == 0) v->arch.metaphysical_saved_rr0 = newrrv.rrval;
   15.25  		set_rr(rr,newrrv.rrval);
   15.26  	}
   15.27  	return 1;
   15.28  }
   15.29  
   15.30  // set rr0 to the passed rid (for metaphysical mode so don't use domain offset
   15.31 -int set_metaphysical_rr(unsigned long rr, unsigned long rid)
   15.32 +int set_metaphysical_rr0(void)
   15.33  {
   15.34 +	struct vcpu *v = current;
   15.35  	ia64_rr rrv;
   15.36  	
   15.37 -	rrv.rrval = 0;
   15.38 -	rrv.rid = rid;
   15.39 -	rrv.ps = PAGE_SHIFT;
   15.40  //	rrv.ve = 1; 	FIXME: TURN ME BACK ON WHEN VHPT IS WORKING
   15.41 -	rrv.ve = 0;
   15.42 -	set_rr(rr,rrv.rrval);
   15.43 +	set_rr(0,v->arch.metaphysical_rr0);
   15.44  }
   15.45  
   15.46  // validates/changes region registers 0-6 in the currently executing domain
   15.47 @@ -322,7 +325,7 @@ void init_all_rr(struct vcpu *v)
   15.48  	ia64_rr rrv;
   15.49  
   15.50  	rrv.rrval = 0;
   15.51 -	rrv.rid = v->domain->metaphysical_rid;
   15.52 +	rrv.rrval = v->domain->arch.metaphysical_rr0;
   15.53  	rrv.ps = PAGE_SHIFT;
   15.54  	rrv.ve = 1;
   15.55  if (!v->vcpu_info) { printf("Stopping in init_all_rr\n"); dummy(); }
   15.56 @@ -376,7 +379,7 @@ unsigned long load_region_regs(struct vc
   15.57  		ia64_rr rrv;
   15.58  
   15.59  		rrv.rrval = 0;
   15.60 -		rrv.rid = v->domain->metaphysical_rid;
   15.61 +		rrv.rid = v->domain->arch.metaphysical_rr0;
   15.62  		rrv.ps = PAGE_SHIFT;
   15.63  		rrv.ve = 1;
   15.64  		rr0 = rrv.rrval;
    16.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    16.2 +++ b/xen/arch/ia64/sn_console.c	Thu Jun 09 22:10:19 2005 +0000
    16.3 @@ -0,0 +1,84 @@
    16.4 +/*
    16.5 + * C-Brick Serial Port (and console) driver for SGI Altix machines.
    16.6 + *
    16.7 + * Copyright (c) 2005 Silicon Graphics, Inc.  All Rights Reserved.
    16.8 + */
    16.9 +
   16.10 +#include <asm/acpi.h>
   16.11 +#include <asm/sn/sn_sal.h>
   16.12 +#include <xen/serial.h>
   16.13 +
   16.14 +void sn_putc(struct serial_port *, char);
   16.15 +
   16.16 +static struct uart_driver sn_sal_console = {
   16.17 +	.putc = sn_putc,
   16.18 +};
   16.19 +
   16.20 +/**
   16.21 + * early_sn_setup - early setup routine for SN platforms
   16.22 + *
   16.23 + * pulled from arch/ia64/sn/kernel/setup.c
   16.24 + */
   16.25 +static void __init early_sn_setup(void)
   16.26 +{
   16.27 +	efi_system_table_t *efi_systab;
   16.28 +	efi_config_table_t *config_tables;
   16.29 +	struct ia64_sal_systab *sal_systab;
   16.30 +	struct ia64_sal_desc_entry_point *ep;
   16.31 +	char *p;
   16.32 +	int i, j;
   16.33 +
   16.34 +	/*
   16.35 +	 * Parse enough of the SAL tables to locate the SAL entry point. Since, console
   16.36 +	 * IO on SN2 is done via SAL calls, early_printk won't work without this.
   16.37 +	 *
   16.38 +	 * This code duplicates some of the ACPI table parsing that is in efi.c & sal.c.
   16.39 +	 * Any changes to those file may have to be made hereas well.
   16.40 +	 */
   16.41 +	efi_systab = (efi_system_table_t *) __va(ia64_boot_param->efi_systab);
   16.42 +	config_tables = __va(efi_systab->tables);
   16.43 +	for (i = 0; i < efi_systab->nr_tables; i++) {
   16.44 +		if (efi_guidcmp(config_tables[i].guid, SAL_SYSTEM_TABLE_GUID) ==
   16.45 +		    0) {
   16.46 +			sal_systab = __va(config_tables[i].table);
   16.47 +			p = (char *)(sal_systab + 1);
   16.48 +			for (j = 0; j < sal_systab->entry_count; j++) {
   16.49 +				if (*p == SAL_DESC_ENTRY_POINT) {
   16.50 +					ep = (struct ia64_sal_desc_entry_point
   16.51 +					      *)p;
   16.52 +					ia64_sal_handler_init(__va
   16.53 +							      (ep->sal_proc),
   16.54 +							      __va(ep->gp));
   16.55 +					return;
   16.56 +				}
   16.57 +				p += SAL_DESC_SIZE(*p);
   16.58 +			}
   16.59 +		}
   16.60 +	}
   16.61 +	/* Uh-oh, SAL not available?? */
   16.62 +	printk(KERN_ERR "failed to find SAL entry point\n");
   16.63 +}
   16.64 +
   16.65 +/**
   16.66 + * sn_serial_console_early_setup - Sets up early console output support
   16.67 + *
   16.68 + * pulled from drivers/serial/sn_console.c
   16.69 + */
   16.70 +int __init sn_serial_console_early_setup(void)
   16.71 +{
   16.72 +	if (strcmp("sn2",acpi_get_sysname()))
   16.73 +		return -1;
   16.74 +
   16.75 +	early_sn_setup();	/* Find SAL entry points */
   16.76 +	serial_register_uart(0, &sn_sal_console, NULL);
   16.77 +
   16.78 +	return 0;
   16.79 +}
   16.80 +
   16.81 +/*
   16.82 + * sn_putc - Send a character to the console, polled or interrupt mode
   16.83 + */
   16.84 +void sn_putc(struct serial_port *port, char c)
   16.85 +{
   16.86 +	return ia64_sn_console_putc(c);
   16.87 +}
    17.1 --- a/xen/arch/ia64/tools/mkbuildtree	Thu Jun 09 20:07:33 2005 +0000
    17.2 +++ b/xen/arch/ia64/tools/mkbuildtree	Thu Jun 09 22:10:19 2005 +0000
    17.3 @@ -45,6 +45,7 @@ fi
    17.4  mkdir include/asm-generic
    17.5  mkdir include/asm-ia64/linux
    17.6  mkdir include/asm-ia64/linux/byteorder
    17.7 +mkdir include/asm-ia64/sn
    17.8  # use "gcc -Iinclude/asm-ia64" to find these linux includes
    17.9  #ln -s $XEN/include/xen $XEN/include/linux
   17.10  #ln -s $XEN/include/asm-ia64/linux $XEN/include/asm-ia64/xen 
   17.11 @@ -198,6 +199,12 @@ null include/asm-ia64/module.h
   17.12  null include/asm-ia64/ia32.h
   17.13  null include/asm-ia64/tlbflush.h
   17.14  
   17.15 +null include/asm-ia64/sn/arch.h
   17.16 +null include/asm-ia64/sn/geo.h
   17.17 +null include/asm-ia64/sn/nodepda.h
   17.18 +null include/asm-ia64/sn/sn_cpuid.h
   17.19 +cp_patch include/asm-ia64/sn/sn_sal.h include/asm-ia64/sn/sn_sal.h sn_sal.h
   17.20 +
   17.21  softlink include/asm-ia64/acpi.h include/asm-ia64/acpi.h
   17.22  softlink include/asm-ia64/asmmacro.h include/asm-ia64/asmmacro.h
   17.23  softlink include/asm-ia64/atomic.h include/asm-ia64/atomic.h
    18.1 --- a/xen/arch/ia64/vcpu.c	Thu Jun 09 20:07:33 2005 +0000
    18.2 +++ b/xen/arch/ia64/vcpu.c	Thu Jun 09 22:10:19 2005 +0000
    18.3 @@ -117,7 +117,7 @@ void vcpu_set_metaphysical_mode(VCPU *vc
    18.4  {
    18.5  	/* only do something if mode changes */
    18.6  	if (!!newmode ^ !!PSCB(vcpu,metaphysical_mode)) {
    18.7 -		if (newmode) set_metaphysical_rr(0,vcpu->domain->metaphysical_rid);
    18.8 +		if (newmode) set_metaphysical_rr0();
    18.9  		else if (PSCB(vcpu,rrs[0]) != -1)
   18.10  			set_one_rr(0, PSCB(vcpu,rrs[0]));
   18.11  		PSCB(vcpu,metaphysical_mode) = newmode;
   18.12 @@ -170,6 +170,13 @@ IA64FAULT vcpu_set_psr_dt(VCPU *vcpu)
   18.13  	return IA64_NO_FAULT;
   18.14  }
   18.15  
   18.16 +IA64FAULT vcpu_set_psr_i(VCPU *vcpu)
   18.17 +{
   18.18 +	PSCB(vcpu,interrupt_delivery_enabled) = 1;
   18.19 +	PSCB(vcpu,interrupt_collection_enabled) = 1;
   18.20 +	return IA64_NO_FAULT;
   18.21 +}
   18.22 +
   18.23  IA64FAULT vcpu_set_psr_sm(VCPU *vcpu, UINT64 imm24)
   18.24  {
   18.25  	struct ia64_psr psr, imm, *ipsr;
   18.26 @@ -643,6 +650,7 @@ IA64FAULT vcpu_get_ivr(VCPU *vcpu, UINT6
   18.27  #ifdef HEARTBEAT_FREQ
   18.28  #define N_DOMS 16	// period in seconds
   18.29  	static long count[N_DOMS] = { 0 };
   18.30 +	static long nonclockcount[N_DOMS] = { 0 };
   18.31  	REGS *regs = vcpu_regs(vcpu);
   18.32  	unsigned domid = vcpu->domain->domain_id;
   18.33  #endif
   18.34 @@ -664,15 +672,15 @@ IA64FAULT vcpu_get_ivr(VCPU *vcpu, UINT6
   18.35  	}
   18.36  #ifdef HEARTBEAT_FREQ
   18.37  	if (domid >= N_DOMS) domid = N_DOMS-1;
   18.38 -	if (vector == (PSCB(vcpu,itv) & 0xff) &&
   18.39 -	    !(++count[domid] & ((HEARTBEAT_FREQ*1024)-1))) {
   18.40 -		printf("Dom%d heartbeat... iip=%p,psr.i=%d,pend=%d\n",
   18.41 -			domid, regs->cr_iip,
   18.42 -			current->vcpu_info->arch.interrupt_delivery_enabled,
   18.43 -			current->vcpu_info->arch.pending_interruption);
   18.44 -		count[domid] = 0;
   18.45 -		dump_runq();
   18.46 +	if (vector == (PSCB(vcpu,itv) & 0xff)) {
   18.47 +	    if (!(++count[domid] & ((HEARTBEAT_FREQ*1024)-1))) {
   18.48 +		printf("Dom%d heartbeat... ticks=%lx,nonticks=%lx\n",
   18.49 +			domid, count[domid], nonclockcount[domid]);
   18.50 +		//count[domid] = 0;
   18.51 +		//dump_runq();
   18.52 +	    }
   18.53  	}
   18.54 +	else nonclockcount[domid]++;
   18.55  #endif
   18.56  	// now have an unmasked, pending, deliverable vector!
   18.57  	// getting ivr has "side effects"
    19.1 --- a/xen/arch/ia64/xensetup.c	Thu Jun 09 20:07:33 2005 +0000
    19.2 +++ b/xen/arch/ia64/xensetup.c	Thu Jun 09 22:10:19 2005 +0000
    19.3 @@ -214,6 +214,9 @@ void start_kernel(void)
    19.4  
    19.5      init_frametable();
    19.6  
    19.7 +    ia64_fph_enable();
    19.8 +    __ia64_init_fpu();
    19.9 +
   19.10      alloc_dom0();
   19.11  #ifdef DOMU_BUILD_STAGING
   19.12      alloc_domU_staging();
    20.1 --- a/xen/include/asm-ia64/config.h	Thu Jun 09 20:07:33 2005 +0000
    20.2 +++ b/xen/include/asm-ia64/config.h	Thu Jun 09 22:10:19 2005 +0000
    20.3 @@ -19,6 +19,7 @@
    20.4  #define	CONFIG_IA64_GRANULE_16MB
    20.5  
    20.6  #define CONFIG_EFI_PCDP
    20.7 +#define CONFIG_SERIAL_SGI_L1_CONSOLE
    20.8  
    20.9  #ifndef __ASSEMBLY__
   20.10  
    21.1 --- a/xen/include/asm-ia64/domain.h	Thu Jun 09 20:07:33 2005 +0000
    21.2 +++ b/xen/include/asm-ia64/domain.h	Thu Jun 09 22:10:19 2005 +0000
    21.3 @@ -27,7 +27,7 @@ struct trap_bounce {
    21.4  struct arch_domain {
    21.5      struct mm_struct *active_mm;
    21.6      struct mm_struct *mm;
    21.7 -    int metaphysical_rid;
    21.8 +    int metaphysical_rr0;
    21.9      int starting_rid;		/* first RID assigned to domain */
   21.10      int ending_rid;		/* one beyond highest RID assigned to domain */
   21.11      int rid_bits;		/* number of virtual rid bits (default: 18) */
   21.12 @@ -47,11 +47,9 @@ struct arch_domain {
   21.13      u64 entry;
   21.14  #endif
   21.15  };
   21.16 -#define metaphysical_rid arch.metaphysical_rid
   21.17  #define starting_rid arch.starting_rid
   21.18  #define ending_rid arch.ending_rid
   21.19  #define rid_bits arch.rid_bits
   21.20 -#define breakimm arch.breakimm
   21.21  #define xen_vastart arch.xen_vastart
   21.22  #define xen_vaend arch.xen_vaend
   21.23  #define shared_info_va arch.shared_info_va
   21.24 @@ -75,6 +73,9 @@ struct arch_vcpu {
   21.25  	unsigned long xen_timer_interval;
   21.26  #endif
   21.27      void *regs;	/* temporary until find a better way to do privops */
   21.28 +    int metaphysical_rr0;		// from arch_domain (so is pinned)
   21.29 +    int metaphysical_saved_rr0;		// from arch_domain (so is pinned)
   21.30 +    int breakimm;			// from arch_domain (so is pinned)
   21.31      struct mm_struct *active_mm;
   21.32      struct thread_struct _thread;	// this must be last
   21.33  #ifdef CONFIG_VTI
    22.1 --- a/xen/include/asm-ia64/xensystem.h	Thu Jun 09 20:07:33 2005 +0000
    22.2 +++ b/xen/include/asm-ia64/xensystem.h	Thu Jun 09 22:10:19 2005 +0000
    22.3 @@ -50,6 +50,8 @@ extern struct task_struct *vmx_ia64_swit
    22.4  } while (0)
    22.5  #else // CONFIG_VTI
    22.6  #define __switch_to(prev,next,last) do {							 \
    22.7 +	ia64_save_fpu(prev->arch._thread.fph);							\
    22.8 +	ia64_load_fpu(next->arch._thread.fph);							\
    22.9  	if (IA64_HAS_EXTRA_STATE(prev))								 \
   22.10  		ia64_save_extra(prev);								 \
   22.11  	if (IA64_HAS_EXTRA_STATE(next))								 \
    23.1 --- a/xen/include/public/arch-ia64.h	Thu Jun 09 20:07:33 2005 +0000
    23.2 +++ b/xen/include/public/arch-ia64.h	Thu Jun 09 22:10:19 2005 +0000
    23.3 @@ -81,10 +81,11 @@ typedef struct vcpu_guest_context {
    23.4  #endif /* !__ASSEMBLY__ */
    23.5  
    23.6  #define	XEN_HYPER_RFI			1
    23.7 -#define	XEN_HYPER_RSM_PSR_DT		2
    23.8 -#define	XEN_HYPER_SSM_PSR_DT		3
    23.9 +#define	XEN_HYPER_RSM_DT		2
   23.10 +#define	XEN_HYPER_SSM_DT		3
   23.11  #define	XEN_HYPER_COVER			4
   23.12  #define	XEN_HYPER_ITC_D			5
   23.13  #define	XEN_HYPER_ITC_I			6
   23.14 +#define	XEN_HYPER_SSM_I			7
   23.15  
   23.16  #endif /* __HYPERVISOR_IF_IA64_H__ */