1.1 --- a/xen/arch/x86/hvm/hvm.c	Wed Oct 03 15:47:47 2007 +0100
     1.2 +++ b/xen/arch/x86/hvm/hvm.c	Wed Oct 03 16:33:23 2007 +0100
     1.3 @@ -232,7 +232,10 @@ int hvm_domain_initialise(struct domain 
     1.4          return rc;
     1.5  
     1.6      vpic_init(d);
     1.7 -    vioapic_init(d);
     1.8 +
     1.9 +    rc = vioapic_init(d);
    1.10 +    if ( rc != 0 )
    1.11 +        return rc;
    1.12  
    1.13      hvm_init_ioreq_page(d, &d->arch.hvm_domain.ioreq);
    1.14      hvm_init_ioreq_page(d, &d->arch.hvm_domain.buf_ioreq);
    1.15 @@ -254,6 +257,7 @@ void hvm_domain_relinquish_resources(str
    1.16  void hvm_domain_destroy(struct domain *d)
    1.17  {
    1.18      hvm_funcs.domain_destroy(d);
    1.19 +    vioapic_deinit(d);
    1.20  }
    1.21  
    1.22  static int hvm_save_cpu_ctxt(struct domain *d, hvm_domain_context_t *h)

     2.1 --- a/xen/arch/x86/hvm/i8254.c	Wed Oct 03 15:47:47 2007 +0100
     2.2 +++ b/xen/arch/x86/hvm/i8254.c	Wed Oct 03 16:33:23 2007 +0100
     2.3 @@ -185,7 +185,6 @@ static void pit_load_count(PITState *pit
     2.4  {
     2.5      u32 period;
     2.6      struct hvm_hw_pit_channel *s = &pit->hw.channels[channel];
     2.7 -    struct periodic_time *pt = &pit->pt[channel];
     2.8      struct vcpu *v = vpit_vcpu(pit);
     2.9  
    2.10      ASSERT(spin_is_locked(&pit->lock));
    2.11 @@ -207,16 +206,16 @@ static void pit_load_count(PITState *pit
    2.12      {
    2.13          case 2:
    2.14              /* Periodic timer. */
    2.15 -            create_periodic_time(v, pt, period, 0, 0, pit_time_fired, 
    2.16 +            create_periodic_time(v, &pit->pt0, period, 0, 0, pit_time_fired, 
    2.17                                   &pit->count_load_time[channel]);
    2.18              break;
    2.19          case 1:
    2.20              /* One-shot timer. */
    2.21 -            create_periodic_time(v, pt, period, 0, 1, pit_time_fired,
    2.22 +            create_periodic_time(v, &pit->pt0, period, 0, 1, pit_time_fired,
    2.23                                   &pit->count_load_time[channel]);
    2.24              break;
    2.25          default:
    2.26 -            destroy_periodic_time(pt);
    2.27 +            destroy_periodic_time(&pit->pt0);
    2.28              break;
    2.29      }
    2.30  }
    2.31 @@ -396,7 +395,7 @@ static uint32_t pit_ioport_read(struct P
    2.32  void pit_stop_channel0_irq(PITState *pit)
    2.33  {
    2.34      spin_lock(&pit->lock);
    2.35 -    destroy_periodic_time(&pit->pt[0]);
    2.36 +    destroy_periodic_time(&pit->pt0);
    2.37      spin_unlock(&pit->lock);
    2.38  }
    2.39  
    2.40 @@ -425,21 +424,18 @@ static void pit_info(PITState *pit)
    2.41          printk("pit 0x%x.\n", s->gate);
    2.42          printk("pit %"PRId64"\n", pit->count_load_time[i]);
    2.43  
    2.44 -        pt = &pit->pt[i];
    2.45 -        if ( pt )
    2.46 -        {
    2.47 -            printk("pit channel %d has a periodic timer:\n", i);
    2.48 -            printk("pt %d.\n", pt->enabled);
    2.49 -            printk("pt %d.\n", pt->one_shot);
    2.50 -            printk("pt %d.\n", pt->irq);
    2.51 -            printk("pt %d.\n", pt->first_injected);
    2.52 +    }
    2.53  
    2.54 -            printk("pt %d.\n", pt->pending_intr_nr);
    2.55 -            printk("pt %d.\n", pt->period);
    2.56 -            printk("pt %"PRId64"\n", pt->period_cycles);
    2.57 -            printk("pt %"PRId64"\n", pt->last_plt_gtime);
    2.58 -        }
    2.59 -    }
    2.60 +    pt = &pit->pt0;
    2.61 +    printk("pit channel 0 periodic timer:\n", i);
    2.62 +    printk("pt %d.\n", pt->enabled);
    2.63 +    printk("pt %d.\n", pt->one_shot);
    2.64 +    printk("pt %d.\n", pt->irq);
    2.65 +    printk("pt %d.\n", pt->first_injected);
    2.66 +    printk("pt %d.\n", pt->pending_intr_nr);
    2.67 +    printk("pt %d.\n", pt->period);
    2.68 +    printk("pt %"PRId64"\n", pt->period_cycles);
    2.69 +    printk("pt %"PRId64"\n", pt->last_plt_gtime);
    2.70  }
    2.71  #else
    2.72  static void pit_info(PITState *pit)
    2.73 @@ -481,11 +477,9 @@ static int pit_load(struct domain *d, hv
    2.74      /* Recreate platform timers from hardware state.  There will be some 
    2.75       * time jitter here, but the wall-clock will have jumped massively, so 
    2.76       * we hope the guest can handle it. */
    2.77 +    pit->pt0.last_plt_gtime = hvm_get_guest_time(d->vcpu[0]);
    2.78      for ( i = 0; i < 3; i++ )
    2.79 -    {
    2.80          pit_load_count(pit, i, pit->hw.channels[i].count);
    2.81 -        pit->pt[i].last_plt_gtime = hvm_get_guest_time(d->vcpu[0]);
    2.82 -    }
    2.83  
    2.84      pit_info(pit);
    2.85  
    2.86 @@ -525,7 +519,7 @@ void pit_init(struct vcpu *v, unsigned l
    2.87  void pit_deinit(struct domain *d)
    2.88  {
    2.89      PITState *pit = domain_vpit(d);
    2.90 -    destroy_periodic_time(&pit->pt[0]);
    2.91 +    destroy_periodic_time(&pit->pt0);
    2.92  }
    2.93  
    2.94  /* the intercept action for PIT DM retval:0--not handled; 1--handled */  

     3.1 --- a/xen/arch/x86/hvm/vioapic.c	Wed Oct 03 15:47:47 2007 +0100
     3.2 +++ b/xen/arch/x86/hvm/vioapic.c	Wed Oct 03 16:33:23 2007 +0100
     3.3 @@ -300,8 +300,7 @@ static uint32_t ioapic_get_delivery_bitm
     3.4  static inline int pit_channel0_enabled(void)
     3.5  {
     3.6      PITState *pit = &current->domain->arch.hvm_domain.pl_time.vpit;
     3.7 -    struct periodic_time *pt = &pit->pt[0];
     3.8 -    return pt->enabled;
     3.9 +    return pit->pt0.enabled;
    3.10  }
    3.11  
    3.12  static void vioapic_deliver(struct hvm_hw_vioapic *vioapic, int irq)
    3.13 @@ -517,13 +516,27 @@ static int ioapic_load(struct domain *d,
    3.14  
    3.15  HVM_REGISTER_SAVE_RESTORE(IOAPIC, ioapic_save, ioapic_load, 1, HVMSR_PER_DOM);
    3.16  
    3.17 -void vioapic_init(struct domain *d)
    3.18 +int vioapic_init(struct domain *d)
    3.19  {
    3.20 -    struct hvm_hw_vioapic *vioapic = domain_vioapic(d);
    3.21 +    struct hvm_vioapic *vioapic;
    3.22      int i;
    3.23  
    3.24 -    memset(vioapic, 0, sizeof(*vioapic));
    3.25 +    vioapic = d->arch.hvm_domain.vioapic = xmalloc(struct hvm_vioapic);
    3.26 +    if ( vioapic == NULL )
    3.27 +        return -ENOMEM;
    3.28 +
    3.29 +    vioapic->domain = d;
    3.30 +
    3.31 +    memset(&vioapic->hvm_hw_vioapic, 0, sizeof(vioapic->hvm_hw_vioapic));
    3.32      for ( i = 0; i < VIOAPIC_NUM_PINS; i++ )
    3.33 -        vioapic->redirtbl[i].fields.mask = 1;
    3.34 -    vioapic->base_address = VIOAPIC_DEFAULT_BASE_ADDRESS;
    3.35 +        vioapic->hvm_hw_vioapic.redirtbl[i].fields.mask = 1;
    3.36 +    vioapic->hvm_hw_vioapic.base_address = VIOAPIC_DEFAULT_BASE_ADDRESS;
    3.37 +
    3.38 +    return 0;
    3.39  }
    3.40 +
    3.41 +void vioapic_deinit(struct domain *d)
    3.42 +{
    3.43 +    xfree(d->arch.hvm_domain.vioapic);
    3.44 +    d->arch.hvm_domain.vioapic = NULL;
    3.45 +}

     4.1 --- a/xen/include/asm-x86/hvm/domain.h	Wed Oct 03 15:47:47 2007 +0100
     4.2 +++ b/xen/include/asm-x86/hvm/domain.h	Wed Oct 03 16:33:23 2007 +0100
     4.3 @@ -25,6 +25,7 @@
     4.4  #include <asm/hvm/irq.h>
     4.5  #include <asm/hvm/vpt.h>
     4.6  #include <asm/hvm/vlapic.h>
     4.7 +#include <asm/hvm/vioapic.h>
     4.8  #include <asm/hvm/io.h>
     4.9  #include <asm/hvm/iommu.h>
    4.10  #include <public/hvm/params.h>
    4.11 @@ -49,7 +50,7 @@ struct hvm_domain {
    4.12      spinlock_t             irq_lock;
    4.13      struct hvm_irq         irq;
    4.14      struct hvm_hw_vpic     vpic[2]; /* 0=master; 1=slave */
    4.15 -    struct hvm_hw_vioapic  vioapic;
    4.16 +    struct hvm_vioapic    *vioapic;
    4.17  
    4.18      /* hvm_print_line() logging. */
    4.19      char                   pbuf[80];

     5.1 --- a/xen/include/asm-x86/hvm/vioapic.h	Wed Oct 03 15:47:47 2007 +0100
     5.2 +++ b/xen/include/asm-x86/hvm/vioapic.h	Wed Oct 03 16:33:23 2007 +0100
     5.3 @@ -52,11 +52,17 @@
     5.4  #define VIOAPIC_REG_VERSION 0x01
     5.5  #define VIOAPIC_REG_ARB_ID  0x02 /* x86 IOAPIC only */
     5.6  
     5.7 -#define domain_vioapic(d) (&(d)->arch.hvm_domain.vioapic)
     5.8 -#define vioapic_domain(v) (container_of((v), struct domain, \
     5.9 -                                        arch.hvm_domain.vioapic))
    5.10 +struct hvm_vioapic {
    5.11 +    struct hvm_hw_vioapic hvm_hw_vioapic;
    5.12 +    struct domain *domain;
    5.13 +};
    5.14  
    5.15 -void vioapic_init(struct domain *d);
    5.16 +#define domain_vioapic(d) (&(d)->arch.hvm_domain.vioapic->hvm_hw_vioapic)
    5.17 +#define vioapic_domain(v) (container_of((v), struct hvm_vioapic, \
    5.18 +                                        hvm_hw_vioapic)->domain)
    5.19 +
    5.20 +int vioapic_init(struct domain *d);
    5.21 +void vioapic_deinit(struct domain *d);
    5.22  void vioapic_irq_positive_edge(struct domain *d, unsigned int irq);
    5.23  void vioapic_update_EOI(struct domain *d, int vector);
    5.24  

     6.1 --- a/xen/include/asm-x86/hvm/vpt.h	Wed Oct 03 15:47:47 2007 +0100
     6.2 +++ b/xen/include/asm-x86/hvm/vpt.h	Wed Oct 03 16:33:23 2007 +0100
     6.3 @@ -95,8 +95,8 @@ typedef struct PITState {
     6.4      struct hvm_hw_pit hw;
     6.5      /* Last time the counters read zero, for calcuating counter reads */
     6.6      int64_t count_load_time[3];
     6.7 -    /* irq handling */
     6.8 -    struct periodic_time pt[3];
     6.9 +    /* Channel 0 IRQ handling. */
    6.10 +    struct periodic_time pt0;
    6.11      spinlock_t lock;
    6.12  } PITState;
    6.13