ia64/xen-unstable

changeset 11806:c8fa605f131f

[IA64] Accelerate mov to rr

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Sat Oct 14 16:34:41 2006 -0600 (2006-10-14)
parents 7c2a5f96a192
children 435e2275ea62
files xen/arch/ia64/asm-offsets.c xen/arch/ia64/vmx/optvfault.S xen/arch/ia64/vmx/vmx_ivt.S
line diff
     1.1 --- a/xen/arch/ia64/asm-offsets.c	Sat Oct 14 16:28:32 2006 -0600
     1.2 +++ b/xen/arch/ia64/asm-offsets.c	Sat Oct 14 16:34:41 2006 -0600
     1.3 @@ -141,6 +141,7 @@ void foo(void)
     1.4  	DEFINE(SWITCH_MPTA_OFFSET,offsetof(struct vcpu ,arch.arch_vmx.mpta));
     1.5  	DEFINE(IA64_PT_REGS_R16_SLOT, (((offsetof(struct pt_regs, r16)-sizeof(struct pt_regs))>>3)&0x3f));
     1.6  	DEFINE(IA64_VCPU_FLAGS_OFFSET,offsetof(struct vcpu ,arch.arch_vmx.flags));
     1.7 +	DEFINE(IA64_VCPU_MODE_FLAGS_OFFSET,offsetof(struct vcpu, arch.mode_flags));
     1.8  
     1.9  	BLANK();
    1.10  
     2.1 --- a/xen/arch/ia64/vmx/optvfault.S	Sat Oct 14 16:28:32 2006 -0600
     2.2 +++ b/xen/arch/ia64/vmx/optvfault.S	Sat Oct 14 16:34:41 2006 -0600
     2.3 @@ -18,11 +18,12 @@
     2.4  
     2.5  #define ACCE_MOV_FROM_AR
     2.6  #define ACCE_MOV_FROM_RR
     2.7 +#define ACCE_MOV_TO_RR
     2.8  
     2.9  //mov r1=ar3
    2.10 -GLOBAL_ENTRY(asm_mov_from_ar)
    2.11 +GLOBAL_ENTRY(vmx_asm_mov_from_ar)
    2.12  #ifndef ACCE_MOV_FROM_AR
    2.13 -    br.many vmx_vitualization_fault_back
    2.14 +    br.many vmx_virtualization_fault_back
    2.15  #endif
    2.16      add r18=VCPU_VTM_OFFSET_OFS,r21
    2.17      mov r19=ar.itc
    2.18 @@ -39,19 +40,19 @@ GLOBAL_ENTRY(asm_mov_from_ar)
    2.19      mov b0=r17
    2.20      br.sptk.few b0
    2.21      ;;
    2.22 -END(asm_mov_from_ar)
    2.23 +END(vmx_asm_mov_from_ar)
    2.24  
    2.25  
    2.26  // mov r1=rr[r3]
    2.27 -GLOBAL_ENTRY(asm_mov_from_rr)
    2.28 +GLOBAL_ENTRY(vmx_asm_mov_from_rr)
    2.29  #ifndef ACCE_MOV_FROM_RR
    2.30 -    br.many vmx_vitualization_fault_back
    2.31 +    br.many vmx_virtualization_fault_back
    2.32  #endif
    2.33      extr.u r16=r25,20,7
    2.34      extr.u r17=r25,6,7
    2.35      movl r20=asm_mov_from_reg
    2.36      ;;
    2.37 -    adds r30=asm_mov_from_rr_back_1-asm_mov_from_reg,r20
    2.38 +    adds r30=vmx_asm_mov_from_rr_back_1-asm_mov_from_reg,r20
    2.39      shladd r16=r16,4,r20
    2.40      mov r24=b0
    2.41      ;;
    2.42 @@ -59,7 +60,7 @@ GLOBAL_ENTRY(asm_mov_from_rr)
    2.43      mov b0=r16
    2.44      br.many b0
    2.45      ;;   
    2.46 -asm_mov_from_rr_back_1:  
    2.47 +vmx_asm_mov_from_rr_back_1:  
    2.48      adds r30=vmx_resume_to_guest-asm_mov_from_reg,r20
    2.49      adds r22=asm_mov_to_reg-asm_mov_from_reg,r20
    2.50      shr.u r26=r19,61
    2.51 @@ -70,7 +71,86 @@ asm_mov_from_rr_back_1:
    2.52      ld8 r19=[r27]
    2.53      mov b0=r17
    2.54      br.many b0
    2.55 -END(asm_mov_from_rr)
    2.56 +END(vmx_asm_mov_from_rr)
    2.57 +
    2.58 +
    2.59 +// mov rr[r3]=r2
    2.60 +GLOBAL_ENTRY(vmx_asm_mov_to_rr)
    2.61 +#ifndef ACCE_MOV_TO_RR
    2.62 +    br.many vmx_virtualization_fault_back
    2.63 +#endif
    2.64 +    extr.u r16=r25,20,7
    2.65 +    extr.u r17=r25,13,7
    2.66 +    movl r20=asm_mov_from_reg
    2.67 +    ;;
    2.68 +    adds r30=vmx_asm_mov_to_rr_back_1-asm_mov_from_reg,r20
    2.69 +    shladd r16=r16,4,r20
    2.70 +    mov r22=b0
    2.71 +    ;;
    2.72 +    add r27=VCPU_VRR0_OFS,r21
    2.73 +    mov b0=r16
    2.74 +    br.many b0
    2.75 +    ;;   
    2.76 +vmx_asm_mov_to_rr_back_1:
    2.77 +    adds r30=vmx_asm_mov_to_rr_back_2-asm_mov_from_reg,r20
    2.78 +    shr.u r23=r19,61
    2.79 +    shladd r17=r17,4,r20
    2.80 +    ;;
    2.81 +    //if rr7, go back
    2.82 +    cmp.eq p6,p0=7,r23
    2.83 +    (p6) br.cond.dpnt.many vmx_virtualization_fault_back
    2.84 +    ;;
    2.85 +    mov r28=r19
    2.86 +    mov b0=r17
    2.87 +    br.many b0
    2.88 +vmx_asm_mov_to_rr_back_2: 
    2.89 +    adds r30=vmx_resume_to_guest-asm_mov_from_reg,r20
    2.90 +    shladd r27=r23,3,r27
    2.91 +    ;; // +starting_rid
    2.92 +    st8 [r27]=r19
    2.93 +    mov b0=r30
    2.94 +    ;;
    2.95 +    adds r16=IA64_VCPU_STARTING_RID_OFFSET,r21
    2.96 +    ;;
    2.97 +    ld4 r16=[r16]
    2.98 +    ;;
    2.99 +    shl r16=r16,8
   2.100 +    ;;
   2.101 +    add r19=r19,r16
   2.102 +    ;; //mangling rid 1 and 3
   2.103 +    extr.u r16=r19,8,8
   2.104 +    extr.u r17=r19,24,8
   2.105 +    extr.u r18=r19,2,6
   2.106 +    ;;
   2.107 +    dep r19=r16,r19,24,8
   2.108 +    ;;
   2.109 +    dep r19=r17,r19,8,8
   2.110 +    ;; //set ve 1
   2.111 +    dep r19=-1,r19,0,1  
   2.112 +    cmp.lt p6,p0=14,r18
   2.113 +    ;;
   2.114 +    (p6) mov r18=14
   2.115 +    ;;
   2.116 +    (p6) dep r19=r18,r19,2,6
   2.117 +    ;;
   2.118 +    cmp.eq p6,p0=0,r23
   2.119 +    ;;
   2.120 +    cmp.eq.or p6,p0=4,r23
   2.121 +    ;;
   2.122 +    adds r16=IA64_VCPU_MODE_FLAGS_OFFSET,r21
   2.123 +    (p6) adds r17=IA64_VCPU_META_SAVED_RR0_OFFSET,r21
   2.124 +    ;;
   2.125 +    ld8 r16=[r16]
   2.126 +    cmp.eq p7,p0=r0,r0
   2.127 +    (p6) shladd r17=r23,1,r17
   2.128 +    ;;
   2.129 +    (p6) st8 [r17]=r19
   2.130 +    (p6) tbit.nz p6,p7=r16,0
   2.131 +    ;;
   2.132 +    (p7) mov rr[r28]=r19
   2.133 +    mov r24=r22
   2.134 +    br.many b0
   2.135 +END(vmx_asm_mov_from_rr)
   2.136  
   2.137  
   2.138  #define MOV_TO_REG0	\
   2.139 @@ -346,20 +426,17 @@ ENTRY(vmx_resume_to_guest)
   2.140      dep r16=r17,r16,IA64_PSR_RI_BIT,2
   2.141      ;;
   2.142      mov cr.ipsr=r16
   2.143 -    mov r17=cr.isr
   2.144      adds r19= VPD_VPSR_START_OFFSET,r25
   2.145 -    ld8 r26=[r25]
   2.146 -    add r29=PAL_VPS_RESUME_NORMAL,r20
   2.147 -    add r28=PAL_VPS_RESUME_HANDLER,r20
   2.148 +    add r28=PAL_VPS_RESUME_NORMAL,r20
   2.149 +    add r29=PAL_VPS_RESUME_HANDLER,r20
   2.150      ;;
   2.151      ld8 r19=[r19]
   2.152      mov b0=r29
   2.153      cmp.ne p6,p7 = r0,r0
   2.154      ;;
   2.155 -    tbit.nz.or.andcm p6,p7 = r19,IA64_PSR_IC_BIT		// p1=vpsr.ic
   2.156 -    tbit.nz.or.andcm p6,p7 = r17,IA64_ISR_IR_BIT		//p1=cr.isr.ir
   2.157 +    tbit.z p6,p7 = r19,IA64_PSR_IC_BIT		// p1=vpsr.ic
   2.158      ;;
   2.159 -    (p6) mov b0=r29
   2.160 +    (p6) ld8 r26=[r25]
   2.161      (p7) mov b0=r28
   2.162      mov pr=r31,-2
   2.163      br.sptk.many b0             // call pal service
     3.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Sat Oct 14 16:28:32 2006 -0600
     3.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Sat Oct 14 16:34:41 2006 -0600
     3.3 @@ -782,8 +782,10 @@ ENTRY(vmx_virtualization_fault)
     3.4      ;;
     3.5      cmp.eq p6,p0=EVENT_MOV_FROM_AR,r24
     3.6      cmp.eq p7,p0=EVENT_MOV_FROM_RR,r24
     3.7 -    (p6) br.dptk.many asm_mov_from_ar
     3.8 -    (p7) br.dptk.many asm_mov_from_rr
     3.9 +    cmp.eq p8,p0=EVENT_MOV_TO_RR,r24
    3.10 +    (p6) br.dptk.many vmx_asm_mov_from_ar
    3.11 +    (p7) br.dptk.many vmx_asm_mov_from_rr
    3.12 +    (p8) br.dptk.many vmx_asm_mov_to_rr
    3.13      ;;
    3.14  vmx_virtualization_fault_back:
    3.15      mov r19=37