ia64/xen-unstable

changeset 17288:c7a58a81c4b8

[IA64] Fix TLB miss behavior with physical mode

The emulation of physical mode will be more precise with this patch.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
author Alex Williamson <alex.williamson@hp.com>
date Thu Mar 20 14:06:46 2008 -0600 (2008-03-20)
parents 42f6c206c951
children 6bdb34397701
files xen/arch/ia64/vmx/vmx_fault.c
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmx_fault.c	Thu Mar 20 12:35:40 2008 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmx_fault.c	Thu Mar 20 14:06:46 2008 -0600
     1.3 @@ -339,7 +339,6 @@ vmx_hpw_miss(u64 vadr, u64 vec, REGS* re
     1.4  {
     1.5      IA64_PSR vpsr;
     1.6      int type;
     1.7 -    unsigned int mmu_mode;
     1.8      u64 vhpt_adr, gppa, pteval, rr, itir;
     1.9      ISR misr;
    1.10      PTA vpta;
    1.11 @@ -356,33 +355,44 @@ vmx_hpw_miss(u64 vadr, u64 vec, REGS* re
    1.12      else
    1.13          panic_domain(regs, "wrong vec:%lx\n", vec);
    1.14  
    1.15 -    /* Physical mode and region is 0 or 4.  */
    1.16 -    mmu_mode = VMX_MMU_MODE(v);
    1.17 -    if ((mmu_mode == VMX_MMU_PHY_DT
    1.18 -         || (mmu_mode == VMX_MMU_PHY_D && type == DSIDE_TLB))
    1.19 -        && (REGION_NUMBER(vadr) & 3) == 0) {
    1.20 -        if (type == DSIDE_TLB) {
    1.21 -            u64 pte;
    1.22 -            /* DTLB miss.  */
    1.23 -            if (misr.sp) /* Refer to SDM Vol2 Table 4-11,4-12 */
    1.24 -                return vmx_handle_lds(regs);
    1.25 -            if (unlikely(unimpl_phys_addr(vadr))) {
    1.26 -                unimpl_daddr(v);
    1.27 -                return IA64_FAULT;
    1.28 -            }
    1.29 -            pte = lookup_domain_mpa(v->domain, pa_clear_uc(vadr), NULL);
    1.30 -            if (v->domain != dom0 && (pte & GPFN_IO_MASK)) {
    1.31 -                emulate_io_inst(v, pa_clear_uc(vadr), 4, pte);
    1.32 -                return IA64_FAULT;
    1.33 -            }
    1.34 -        } else {
    1.35 +    /* Physical mode. */
    1.36 +    if (type == ISIDE_TLB) {
    1.37 +        if (!vpsr.it) {
    1.38              if (unlikely(unimpl_phys_addr(vadr))) {
    1.39                  unimpl_iaddr_trap(v, vadr);
    1.40                  return IA64_FAULT;
    1.41              }
    1.42 +            physical_tlb_miss(v, vadr, type);
    1.43 +            return IA64_FAULT;
    1.44          }
    1.45 -        physical_tlb_miss(v, vadr, type);
    1.46 -        return IA64_FAULT;
    1.47 +    } else { /* DTLB miss. */
    1.48 +        if (!misr.rs) {
    1.49 +            if (!vpsr.dt) {
    1.50 +                u64 pte;
    1.51 +                if (misr.sp) /* Refer to SDM Vol2 Table 4-11,4-12 */
    1.52 +                    return vmx_handle_lds(regs);
    1.53 +                if (unlikely(unimpl_phys_addr(vadr))) {
    1.54 +                    unimpl_daddr(v);
    1.55 +                    return IA64_FAULT;
    1.56 +                }
    1.57 +                pte = lookup_domain_mpa(v->domain, pa_clear_uc(vadr), NULL);
    1.58 +                if (v->domain != dom0 && (pte & GPFN_IO_MASK)) {
    1.59 +                    emulate_io_inst(v, pa_clear_uc(vadr), 4, pte);
    1.60 +                    return IA64_FAULT;
    1.61 +                }
    1.62 +                physical_tlb_miss(v, vadr, type);
    1.63 +                return IA64_FAULT;
    1.64 +            }
    1.65 +        } else { /* RSE fault. */
    1.66 +            if (!vpsr.rt) {
    1.67 +                if (unlikely(unimpl_phys_addr(vadr))) {
    1.68 +                    unimpl_daddr(v);
    1.69 +                    return IA64_FAULT;
    1.70 +                }
    1.71 +                physical_tlb_miss(v, vadr, type);
    1.72 +                return IA64_FAULT;
    1.73 +            }
    1.74 +        }
    1.75      }
    1.76      
    1.77  try_again:
    1.78 @@ -498,7 +508,7 @@ try_again:
    1.79          /* Don't bother with PHY_D mode (will require rr0+rr4 switches,
    1.80             and certainly used only within nested TLB handler (hence TR mapped
    1.81             and ic=0).  */
    1.82 -        if (mmu_mode == VMX_MMU_PHY_D)
    1.83 +        if (!vpsr.dt)
    1.84              goto inject_itlb_fault;
    1.85  
    1.86          if (!vhpt_enabled(v, vadr, INST_REF)) {