ia64/xen-unstable

changeset 133:c6a174401978

bitkeeper revision 1.22.2.9 (3e45a0dcXfnuLyTWlogSmga6jbpG3w)

Merge labyrinth.cl.cam.ac.uk:/usr/groups/xeno/BK/xeno
into labyrinth.cl.cam.ac.uk:/anfs/scratch/labyrinth/iap10/xeno-e1000/xeno.bk
author iap10@labyrinth.cl.cam.ac.uk
date Sun Feb 09 00:29:16 2003 +0000 (2003-02-09)
parents 643a74d7c497 c710f555d13a
children dcbfc020bfa9
files .rootkeys xen-2.4.16/drivers/net/tg3.c xen-2.4.16/drivers/net/tg3.h xen-2.4.16/include/asm-i386/pci.h xen-2.4.16/include/xeno/netdevice.h xen-2.4.16/include/xeno/pci_ids.h
line diff
     1.1 --- a/.rootkeys	Sat Feb 08 19:32:15 2003 +0000
     1.2 +++ b/.rootkeys	Sun Feb 09 00:29:16 2003 +0000
     1.3 @@ -86,6 +86,8 @@ 3ddb79c0GejJrp1U6W4G6dYi-RiH4A xen-2.4.1
     1.4  3ddb79bfKvn9mt0kofpkw0QaWjxO6A xen-2.4.16/drivers/net/net_init.c
     1.5  3ddb79c0fQgORkFlqWZdP-6cDHyFIQ xen-2.4.16/drivers/net/pcnet32.c
     1.6  3ddb79bf_CBcu3QWYwq4bNAOnM2RqQ xen-2.4.16/drivers/net/setup.c
     1.7 +3e45a0c6u66EL2AI36eLOmf_abXs7g xen-2.4.16/drivers/net/tg3.c
     1.8 +3e45a0c6yrXj5pmQT0PvVSJ01YLABQ xen-2.4.16/drivers/net/tg3.h
     1.9  3ddb79bfh8ucmq_HqRSaURalpeAmPg xen-2.4.16/drivers/net/tulip/.depend
    1.10  3ddb79bfsJ-hdQ17EXTFiUOHisjNgQ xen-2.4.16/drivers/net/tulip/21142.c
    1.11  3ddb79bf0lzTL-ywAdOO7vctTYAmJA xen-2.4.16/drivers/net/tulip/ChangeLog
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/xen-2.4.16/drivers/net/tg3.c	Sun Feb 09 00:29:16 2003 +0000
     2.3 @@ -0,0 +1,6879 @@
     2.4 +/* $Id: tg3.c,v 1.43.2.80 2002/03/14 00:10:04 davem Exp $
     2.5 + * tg3.c: Broadcom Tigon3 ethernet driver.
     2.6 + *
     2.7 + * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
     2.8 + * Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@pobox.com)
     2.9 + */
    2.10 +
    2.11 +#include <linux/config.h>
    2.12 +
    2.13 +#include <linux/module.h>
    2.14 +
    2.15 +//#include <linux/kernel.h>
    2.16 +#include <linux/types.h>
    2.17 +//#include <linux/compiler.h>
    2.18 +#include <linux/slab.h>
    2.19 +#include <linux/delay.h>
    2.20 +#include <linux/init.h>
    2.21 +#include <linux/ioport.h>
    2.22 +#include <linux/pci.h>
    2.23 +#include <linux/netdevice.h>
    2.24 +#include <linux/etherdevice.h>
    2.25 +#include <linux/skbuff.h>
    2.26 +#include <linux/ethtool.h>
    2.27 +#include <linux/mii.h>
    2.28 +#include <linux/if_vlan.h>
    2.29 +
    2.30 +#include <asm/system.h>
    2.31 +#include <asm/io.h>
    2.32 +#include <asm/byteorder.h>
    2.33 +#include <asm/uaccess.h>
    2.34 +
    2.35 +#ifndef PCI_DMA_BUS_IS_PHYS
    2.36 +#define PCI_DMA_BUS_IS_PHYS 1
    2.37 +#endif
    2.38 +
    2.39 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
    2.40 +#define TG3_VLAN_TAG_USED 1
    2.41 +#else
    2.42 +#define TG3_VLAN_TAG_USED 0
    2.43 +#endif
    2.44 +
    2.45 +#ifdef NETIF_F_TSO
    2.46 +/* XXX some bug in tso firmware hangs tx cpu, disabled until fixed */
    2.47 +#define TG3_DO_TSO	0
    2.48 +#else
    2.49 +#define TG3_DO_TSO	0
    2.50 +#endif
    2.51 +
    2.52 +#include "tg3.h"
    2.53 +
    2.54 +#define DRV_MODULE_NAME		"tg3"
    2.55 +#define PFX DRV_MODULE_NAME	": "
    2.56 +#define DRV_MODULE_VERSION	"1.2a"
    2.57 +#define DRV_MODULE_RELDATE	"Dec 9, 2002"
    2.58 +
    2.59 +#define TG3_DEF_MAC_MODE	0
    2.60 +#define TG3_DEF_RX_MODE		0
    2.61 +#define TG3_DEF_TX_MODE		0
    2.62 +#define TG3_DEF_MSG_ENABLE	  \
    2.63 +	(NETIF_MSG_DRV		| \
    2.64 +	 NETIF_MSG_PROBE	| \
    2.65 +	 NETIF_MSG_LINK		| \
    2.66 +	 NETIF_MSG_TIMER	| \
    2.67 +	 NETIF_MSG_IFDOWN	| \
    2.68 +	 NETIF_MSG_IFUP		| \
    2.69 +	 NETIF_MSG_RX_ERR	| \
    2.70 +	 NETIF_MSG_TX_ERR)
    2.71 +
    2.72 +/* length of time before we decide the hardware is borked,
    2.73 + * and dev->tx_timeout() should be called to fix the problem
    2.74 + */
    2.75 +#define TG3_TX_TIMEOUT			(5 * HZ)
    2.76 +
    2.77 +/* hardware minimum and maximum for a single frame's data payload */
    2.78 +#define TG3_MIN_MTU			60
    2.79 +#define TG3_MAX_MTU			9000
    2.80 +
    2.81 +/* These numbers seem to be hard coded in the NIC firmware somehow.
    2.82 + * You can't change the ring sizes, but you can change where you place
    2.83 + * them in the NIC onboard memory.
    2.84 + */
    2.85 +#define TG3_RX_RING_SIZE		512
    2.86 +#define TG3_DEF_RX_RING_PENDING		200
    2.87 +#define TG3_RX_JUMBO_RING_SIZE		256
    2.88 +#define TG3_DEF_RX_JUMBO_RING_PENDING	100
    2.89 +#define TG3_RX_RCB_RING_SIZE		1024
    2.90 +#define TG3_TX_RING_SIZE		512
    2.91 +#define TG3_DEF_TX_RING_PENDING		(TG3_TX_RING_SIZE - 1)
    2.92 +
    2.93 +#define TG3_RX_RING_BYTES	(sizeof(struct tg3_rx_buffer_desc) * \
    2.94 +				 TG3_RX_RING_SIZE)
    2.95 +#define TG3_RX_JUMBO_RING_BYTES	(sizeof(struct tg3_rx_buffer_desc) * \
    2.96 +			         TG3_RX_JUMBO_RING_SIZE)
    2.97 +#define TG3_RX_RCB_RING_BYTES	(sizeof(struct tg3_rx_buffer_desc) * \
    2.98 +			         TG3_RX_RCB_RING_SIZE)
    2.99 +#define TG3_TX_RING_BYTES	(sizeof(struct tg3_tx_buffer_desc) * \
   2.100 +				 TG3_TX_RING_SIZE)
   2.101 +#define TX_RING_GAP(TP)	\
   2.102 +	(TG3_TX_RING_SIZE - (TP)->tx_pending)
   2.103 +#define TX_BUFFS_AVAIL(TP)						\
   2.104 +	(((TP)->tx_cons <= (TP)->tx_prod) ?				\
   2.105 +	  (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod :		\
   2.106 +	  (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
   2.107 +#define NEXT_TX(N)		(((N) + 1) & (TG3_TX_RING_SIZE - 1))
   2.108 +
   2.109 +#define RX_PKT_BUF_SZ		(1536 + tp->rx_offset + 64)
   2.110 +#define RX_JUMBO_PKT_BUF_SZ	(9046 + tp->rx_offset + 64)
   2.111 +
   2.112 +/* minimum number of free TX descriptors required to wake up TX process */
   2.113 +#define TG3_TX_WAKEUP_THRESH		(TG3_TX_RING_SIZE / 4)
   2.114 +
   2.115 +static char version[] __devinitdata =
   2.116 +	DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
   2.117 +
   2.118 +MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
   2.119 +MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
   2.120 +MODULE_LICENSE("GPL");
   2.121 +MODULE_PARM(tg3_debug, "i");
   2.122 +MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
   2.123 +
   2.124 +static int tg3_debug = -1;	/* -1 == use TG3_DEF_MSG_ENABLE as value */
   2.125 +
   2.126 +static struct pci_device_id tg3_pci_tbl[] __devinitdata = {
   2.127 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
   2.128 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.129 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
   2.130 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.131 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
   2.132 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.133 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
   2.134 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.135 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
   2.136 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.137 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
   2.138 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.139 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
   2.140 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.141 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
   2.142 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.143 +	{ PCI_VENDOR_ID_SYSKONNECT, 0x4400,
   2.144 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.145 +	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
   2.146 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.147 +	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
   2.148 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.149 +	{ 0, }
   2.150 +};
   2.151 +
   2.152 +MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
   2.153 +
   2.154 +static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
   2.155 +{
   2.156 +	if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
   2.157 +		unsigned long flags;
   2.158 +
   2.159 +		spin_lock_irqsave(&tp->indirect_lock, flags);
   2.160 +		pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
   2.161 +		pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
   2.162 +		spin_unlock_irqrestore(&tp->indirect_lock, flags);
   2.163 +	} else {
   2.164 +		writel(val, tp->regs + off);
   2.165 +	}
   2.166 +}
   2.167 +
   2.168 +#define tw32(reg,val)		tg3_write_indirect_reg32(tp,(reg),(val))
   2.169 +#define tw32_mailbox(reg, val)	writel(((val) & 0xffffffff), tp->regs + (reg))
   2.170 +#define tw16(reg,val)		writew(((val) & 0xffff), tp->regs + (reg))
   2.171 +#define tw8(reg,val)		writeb(((val) & 0xff), tp->regs + (reg))
   2.172 +#define tr32(reg)		readl(tp->regs + (reg))
   2.173 +#define tr16(reg)		readw(tp->regs + (reg))
   2.174 +#define tr8(reg)		readb(tp->regs + (reg))
   2.175 +
   2.176 +static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
   2.177 +{
   2.178 +	unsigned long flags;
   2.179 +
   2.180 +	spin_lock_irqsave(&tp->indirect_lock, flags);
   2.181 +	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
   2.182 +	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
   2.183 +
   2.184 +	/* Always leave this as zero. */
   2.185 +	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
   2.186 +	spin_unlock_irqrestore(&tp->indirect_lock, flags);
   2.187 +}
   2.188 +
   2.189 +static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
   2.190 +{
   2.191 +	unsigned long flags;
   2.192 +
   2.193 +	spin_lock_irqsave(&tp->indirect_lock, flags);
   2.194 +	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
   2.195 +	pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
   2.196 +
   2.197 +	/* Always leave this as zero. */
   2.198 +	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
   2.199 +	spin_unlock_irqrestore(&tp->indirect_lock, flags);
   2.200 +}
   2.201 +
   2.202 +static void tg3_disable_ints(struct tg3 *tp)
   2.203 +{
   2.204 +	tw32(TG3PCI_MISC_HOST_CTRL,
   2.205 +	     (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
   2.206 +	tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
   2.207 +	tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
   2.208 +}
   2.209 +
   2.210 +static void tg3_enable_ints(struct tg3 *tp)
   2.211 +{
   2.212 +	tw32(TG3PCI_MISC_HOST_CTRL,
   2.213 +	     (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
   2.214 +	tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000);
   2.215 +	tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
   2.216 +
   2.217 +	if (tp->hw_status->status & SD_STATUS_UPDATED)
   2.218 +		tw32(GRC_LOCAL_CTRL,
   2.219 +		     tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
   2.220 +}
   2.221 +
   2.222 +static void tg3_switch_clocks(struct tg3 *tp)
   2.223 +{
   2.224 +	if (tr32(TG3PCI_CLOCK_CTRL) & CLOCK_CTRL_44MHZ_CORE) {
   2.225 +		tw32(TG3PCI_CLOCK_CTRL,
   2.226 +		     (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
   2.227 +		tr32(TG3PCI_CLOCK_CTRL);
   2.228 +		udelay(40);
   2.229 +		tw32(TG3PCI_CLOCK_CTRL,
   2.230 +		     (CLOCK_CTRL_ALTCLK));
   2.231 +		tr32(TG3PCI_CLOCK_CTRL);
   2.232 +		udelay(40);
   2.233 +	}
   2.234 +	tw32(TG3PCI_CLOCK_CTRL, 0);
   2.235 +	tr32(TG3PCI_CLOCK_CTRL);
   2.236 +	udelay(40);
   2.237 +}
   2.238 +
   2.239 +#define PHY_BUSY_LOOPS	5000
   2.240 +
   2.241 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
   2.242 +{
   2.243 +	u32 frame_val;
   2.244 +	int loops, ret;
   2.245 +
   2.246 +	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
   2.247 +		tw32(MAC_MI_MODE,
   2.248 +		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
   2.249 +		tr32(MAC_MI_MODE);
   2.250 +		udelay(40);
   2.251 +	}
   2.252 +
   2.253 +	*val = 0xffffffff;
   2.254 +
   2.255 +	frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
   2.256 +		      MI_COM_PHY_ADDR_MASK);
   2.257 +	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
   2.258 +		      MI_COM_REG_ADDR_MASK);
   2.259 +	frame_val |= (MI_COM_CMD_READ | MI_COM_START);
   2.260 +	
   2.261 +	tw32(MAC_MI_COM, frame_val);
   2.262 +	tr32(MAC_MI_COM);
   2.263 +
   2.264 +	loops = PHY_BUSY_LOOPS;
   2.265 +	while (loops-- > 0) {
   2.266 +		udelay(10);
   2.267 +		frame_val = tr32(MAC_MI_COM);
   2.268 +
   2.269 +		if ((frame_val & MI_COM_BUSY) == 0) {
   2.270 +			udelay(5);
   2.271 +			frame_val = tr32(MAC_MI_COM);
   2.272 +			break;
   2.273 +		}
   2.274 +	}
   2.275 +
   2.276 +	ret = -EBUSY;
   2.277 +	if (loops > 0) {
   2.278 +		*val = frame_val & MI_COM_DATA_MASK;
   2.279 +		ret = 0;
   2.280 +	}
   2.281 +
   2.282 +	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
   2.283 +		tw32(MAC_MI_MODE, tp->mi_mode);
   2.284 +		tr32(MAC_MI_MODE);
   2.285 +		udelay(40);
   2.286 +	}
   2.287 +
   2.288 +	return ret;
   2.289 +}
   2.290 +
   2.291 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
   2.292 +{
   2.293 +	u32 frame_val;
   2.294 +	int loops, ret;
   2.295 +
   2.296 +	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
   2.297 +		tw32(MAC_MI_MODE,
   2.298 +		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
   2.299 +		tr32(MAC_MI_MODE);
   2.300 +		udelay(40);
   2.301 +	}
   2.302 +
   2.303 +	frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
   2.304 +		      MI_COM_PHY_ADDR_MASK);
   2.305 +	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
   2.306 +		      MI_COM_REG_ADDR_MASK);
   2.307 +	frame_val |= (val & MI_COM_DATA_MASK);
   2.308 +	frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
   2.309 +	
   2.310 +	tw32(MAC_MI_COM, frame_val);
   2.311 +	tr32(MAC_MI_COM);
   2.312 +
   2.313 +	loops = PHY_BUSY_LOOPS;
   2.314 +	while (loops-- > 0) {
   2.315 +		udelay(10);
   2.316 +		frame_val = tr32(MAC_MI_COM);
   2.317 +		if ((frame_val & MI_COM_BUSY) == 0) {
   2.318 +			udelay(5);
   2.319 +			frame_val = tr32(MAC_MI_COM);
   2.320 +			break;
   2.321 +		}
   2.322 +	}
   2.323 +
   2.324 +	ret = -EBUSY;
   2.325 +	if (loops > 0)
   2.326 +		ret = 0;
   2.327 +
   2.328 +	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
   2.329 +		tw32(MAC_MI_MODE, tp->mi_mode);
   2.330 +		tr32(MAC_MI_MODE);
   2.331 +		udelay(40);
   2.332 +	}
   2.333 +
   2.334 +	return ret;
   2.335 +}
   2.336 +
   2.337 +/* This will reset the tigon3 PHY if there is no valid
   2.338 + * link unless the FORCE argument is non-zero.
   2.339 + */
   2.340 +static int tg3_phy_reset(struct tg3 *tp, int force)
   2.341 +{
   2.342 +	u32 phy_status, phy_control;
   2.343 +	int err, limit;
   2.344 +
   2.345 +	err  = tg3_readphy(tp, MII_BMSR, &phy_status);
   2.346 +	err |= tg3_readphy(tp, MII_BMSR, &phy_status);
   2.347 +	if (err != 0)
   2.348 +		return -EBUSY;
   2.349 +
   2.350 +	/* If we have link, and not forcing a reset, then nothing
   2.351 +	 * to do.
   2.352 +	 */
   2.353 +	if ((phy_status & BMSR_LSTATUS) != 0 && (force == 0))
   2.354 +		return 0;
   2.355 +
   2.356 +	/* OK, reset it, and poll the BMCR_RESET bit until it
   2.357 +	 * clears or we time out.
   2.358 +	 */
   2.359 +	phy_control = BMCR_RESET;
   2.360 +	err = tg3_writephy(tp, MII_BMCR, phy_control);
   2.361 +	if (err != 0)
   2.362 +		return -EBUSY;
   2.363 +
   2.364 +	limit = 5000;
   2.365 +	while (limit--) {
   2.366 +		err = tg3_readphy(tp, MII_BMCR, &phy_control);
   2.367 +		if (err != 0)
   2.368 +			return -EBUSY;
   2.369 +
   2.370 +		if ((phy_control & BMCR_RESET) == 0) {
   2.371 +			udelay(40);
   2.372 +			return 0;
   2.373 +		}
   2.374 +		udelay(10);
   2.375 +	}
   2.376 +
   2.377 +	return -EBUSY;
   2.378 +}
   2.379 +
   2.380 +static int tg3_setup_phy(struct tg3 *);
   2.381 +static int tg3_halt(struct tg3 *);
   2.382 +
   2.383 +static int tg3_set_power_state(struct tg3 *tp, int state)
   2.384 +{
   2.385 +	u32 misc_host_ctrl;
   2.386 +	u16 power_control, power_caps;
   2.387 +	int pm = tp->pm_cap;
   2.388 +
   2.389 +	/* Make sure register accesses (indirect or otherwise)
   2.390 +	 * will function correctly.
   2.391 +	 */
   2.392 +	pci_write_config_dword(tp->pdev,
   2.393 +			       TG3PCI_MISC_HOST_CTRL,
   2.394 +			       tp->misc_host_ctrl);
   2.395 +
   2.396 +	pci_read_config_word(tp->pdev,
   2.397 +			     pm + PCI_PM_CTRL,
   2.398 +			     &power_control);
   2.399 +	power_control |= PCI_PM_CTRL_PME_STATUS;
   2.400 +	power_control &= ~(PCI_PM_CTRL_STATE_MASK);
   2.401 +	switch (state) {
   2.402 +	case 0:
   2.403 +		power_control |= 0;
   2.404 +		pci_write_config_word(tp->pdev,
   2.405 +				      pm + PCI_PM_CTRL,
   2.406 +				      power_control);
   2.407 +		tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
   2.408 +		tr32(GRC_LOCAL_CTRL);
   2.409 +		udelay(100);
   2.410 +
   2.411 +		return 0;
   2.412 +
   2.413 +	case 1:
   2.414 +		power_control |= 1;
   2.415 +		break;
   2.416 +
   2.417 +	case 2:
   2.418 +		power_control |= 2;
   2.419 +		break;
   2.420 +
   2.421 +	case 3:
   2.422 +		power_control |= 3;
   2.423 +		break;
   2.424 +
   2.425 +	default:
   2.426 +		printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
   2.427 +		       "requested.\n",
   2.428 +		       tp->dev->name, state);
   2.429 +		return -EINVAL;
   2.430 +	};
   2.431 +
   2.432 +	power_control |= PCI_PM_CTRL_PME_ENABLE;
   2.433 +
   2.434 +	misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
   2.435 +	tw32(TG3PCI_MISC_HOST_CTRL,
   2.436 +	     misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
   2.437 +
   2.438 +	if (tp->link_config.phy_is_low_power == 0) {
   2.439 +		tp->link_config.phy_is_low_power = 1;
   2.440 +		tp->link_config.orig_speed = tp->link_config.speed;
   2.441 +		tp->link_config.orig_duplex = tp->link_config.duplex;
   2.442 +		tp->link_config.orig_autoneg = tp->link_config.autoneg;
   2.443 +	}
   2.444 +
   2.445 +	if (tp->phy_id != PHY_ID_SERDES) {
   2.446 +		tp->link_config.speed = SPEED_10;
   2.447 +		tp->link_config.duplex = DUPLEX_HALF;
   2.448 +		tp->link_config.autoneg = AUTONEG_ENABLE;
   2.449 +		tg3_setup_phy(tp);
   2.450 +	}
   2.451 +
   2.452 +	tg3_halt(tp);
   2.453 +
   2.454 +	pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
   2.455 +
   2.456 +	if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
   2.457 +		u32 mac_mode;
   2.458 +
   2.459 +		if (tp->phy_id != PHY_ID_SERDES) {
   2.460 +			tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
   2.461 +			udelay(40);
   2.462 +
   2.463 +			mac_mode = MAC_MODE_PORT_MODE_MII;
   2.464 +
   2.465 +			if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
   2.466 +			    !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
   2.467 +				mac_mode |= MAC_MODE_LINK_POLARITY;
   2.468 +		} else {
   2.469 +			mac_mode = MAC_MODE_PORT_MODE_TBI;
   2.470 +		}
   2.471 +
   2.472 +
   2.473 +		if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
   2.474 +		     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
   2.475 +			mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
   2.476 +
   2.477 +		tw32(MAC_MODE, mac_mode);
   2.478 +		tr32(MAC_MODE);
   2.479 +		udelay(100);
   2.480 +
   2.481 +		tw32(MAC_RX_MODE, RX_MODE_ENABLE);
   2.482 +		tr32(MAC_RX_MODE);
   2.483 +		udelay(10);
   2.484 +	}
   2.485 +
   2.486 +	if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) {
   2.487 +		u32 base_val;
   2.488 +
   2.489 +		base_val = 0;
   2.490 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
   2.491 +		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
   2.492 +			base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
   2.493 +				     CLOCK_CTRL_TXCLK_DISABLE);
   2.494 +
   2.495 +		tw32(TG3PCI_CLOCK_CTRL, base_val |
   2.496 +		     CLOCK_CTRL_ALTCLK);
   2.497 +		tr32(TG3PCI_CLOCK_CTRL);
   2.498 +		udelay(40);
   2.499 +
   2.500 +		tw32(TG3PCI_CLOCK_CTRL, base_val |
   2.501 +		     CLOCK_CTRL_ALTCLK |
   2.502 +		     CLOCK_CTRL_44MHZ_CORE);
   2.503 +		tr32(TG3PCI_CLOCK_CTRL);
   2.504 +		udelay(40);
   2.505 +
   2.506 +		tw32(TG3PCI_CLOCK_CTRL, base_val |
   2.507 +		     CLOCK_CTRL_44MHZ_CORE);
   2.508 +		tr32(TG3PCI_CLOCK_CTRL);
   2.509 +		udelay(40);
   2.510 +	} else {
   2.511 +		u32 base_val;
   2.512 +
   2.513 +		base_val = 0;
   2.514 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
   2.515 +		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
   2.516 +			base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
   2.517 +				     CLOCK_CTRL_TXCLK_DISABLE);
   2.518 +
   2.519 +		tw32(TG3PCI_CLOCK_CTRL, base_val |
   2.520 +		     CLOCK_CTRL_ALTCLK |
   2.521 +		     CLOCK_CTRL_PWRDOWN_PLL133);
   2.522 +		tr32(TG3PCI_CLOCK_CTRL);
   2.523 +		udelay(40);
   2.524 +	}
   2.525 +
   2.526 +	if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) &&
   2.527 +	    (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
   2.528 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
   2.529 +		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
   2.530 +			tw32(GRC_LOCAL_CTRL,
   2.531 +			     (GRC_LCLCTRL_GPIO_OE0 |
   2.532 +			      GRC_LCLCTRL_GPIO_OE1 |
   2.533 +			      GRC_LCLCTRL_GPIO_OE2 |
   2.534 +			      GRC_LCLCTRL_GPIO_OUTPUT0 |
   2.535 +			      GRC_LCLCTRL_GPIO_OUTPUT1));
   2.536 +			tr32(GRC_LOCAL_CTRL);
   2.537 +			udelay(100);
   2.538 +		} else {
   2.539 +			tw32(GRC_LOCAL_CTRL,
   2.540 +			     (GRC_LCLCTRL_GPIO_OE0 |
   2.541 +			      GRC_LCLCTRL_GPIO_OE1 |
   2.542 +			      GRC_LCLCTRL_GPIO_OE2 |
   2.543 +			      GRC_LCLCTRL_GPIO_OUTPUT1 |
   2.544 +			      GRC_LCLCTRL_GPIO_OUTPUT2));
   2.545 +			tr32(GRC_LOCAL_CTRL);
   2.546 +			udelay(100);
   2.547 +
   2.548 +			tw32(GRC_LOCAL_CTRL,
   2.549 +			     (GRC_LCLCTRL_GPIO_OE0 |
   2.550 +			      GRC_LCLCTRL_GPIO_OE1 |
   2.551 +			      GRC_LCLCTRL_GPIO_OE2 |
   2.552 +			      GRC_LCLCTRL_GPIO_OUTPUT0 |
   2.553 +			      GRC_LCLCTRL_GPIO_OUTPUT1 |
   2.554 +			      GRC_LCLCTRL_GPIO_OUTPUT2));
   2.555 +			tr32(GRC_LOCAL_CTRL);
   2.556 +			udelay(100);
   2.557 +
   2.558 +			tw32(GRC_LOCAL_CTRL,
   2.559 +			     (GRC_LCLCTRL_GPIO_OE0 |
   2.560 +			      GRC_LCLCTRL_GPIO_OE1 |
   2.561 +			      GRC_LCLCTRL_GPIO_OE2 |
   2.562 +			      GRC_LCLCTRL_GPIO_OUTPUT0 |
   2.563 +			      GRC_LCLCTRL_GPIO_OUTPUT1));
   2.564 +			tr32(GRC_LOCAL_CTRL);
   2.565 +			udelay(100);
   2.566 +		}
   2.567 +	}
   2.568 +
   2.569 +	/* Finally, set the new power state. */
   2.570 +	pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
   2.571 +
   2.572 +	return 0;
   2.573 +}
   2.574 +
   2.575 +static void tg3_link_report(struct tg3 *tp)
   2.576 +{
   2.577 +	if (!netif_carrier_ok(tp->dev)) {
   2.578 +		printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
   2.579 +	} else {
   2.580 +		printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
   2.581 +		       tp->dev->name,
   2.582 +		       (tp->link_config.active_speed == SPEED_1000 ?
   2.583 +			1000 :
   2.584 +			(tp->link_config.active_speed == SPEED_100 ?
   2.585 +			 100 : 10)),
   2.586 +		       (tp->link_config.active_duplex == DUPLEX_FULL ?
   2.587 +			"full" : "half"));
   2.588 +
   2.589 +		printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
   2.590 +		       "%s for RX.\n",
   2.591 +		       tp->dev->name,
   2.592 +		       (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
   2.593 +		       (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
   2.594 +	}
   2.595 +}
   2.596 +
   2.597 +static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
   2.598 +{
   2.599 +	u32 new_tg3_flags = 0;
   2.600 +
   2.601 +	if (local_adv & ADVERTISE_PAUSE_CAP) {
   2.602 +		if (local_adv & ADVERTISE_PAUSE_ASYM) {
   2.603 +			if (remote_adv & LPA_PAUSE_CAP)
   2.604 +				new_tg3_flags |=
   2.605 +					(TG3_FLAG_RX_PAUSE |
   2.606 +					 TG3_FLAG_TX_PAUSE);
   2.607 +			else if (remote_adv & LPA_PAUSE_ASYM)
   2.608 +				new_tg3_flags |=
   2.609 +					(TG3_FLAG_RX_PAUSE);
   2.610 +		} else {
   2.611 +			if (remote_adv & LPA_PAUSE_CAP)
   2.612 +				new_tg3_flags |=
   2.613 +					(TG3_FLAG_RX_PAUSE |
   2.614 +					 TG3_FLAG_TX_PAUSE);
   2.615 +		}
   2.616 +	} else if (local_adv & ADVERTISE_PAUSE_ASYM) {
   2.617 +		if ((remote_adv & LPA_PAUSE_CAP) &&
   2.618 +		    (remote_adv & LPA_PAUSE_ASYM))
   2.619 +			new_tg3_flags |= TG3_FLAG_TX_PAUSE;
   2.620 +	}
   2.621 +
   2.622 +	tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
   2.623 +	tp->tg3_flags |= new_tg3_flags;
   2.624 +
   2.625 +	if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
   2.626 +		tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
   2.627 +	else
   2.628 +		tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
   2.629 +
   2.630 +	if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
   2.631 +		tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
   2.632 +	else
   2.633 +		tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
   2.634 +}
   2.635 +
   2.636 +static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
   2.637 +{
   2.638 +	switch (val & MII_TG3_AUX_STAT_SPDMASK) {
   2.639 +	case MII_TG3_AUX_STAT_10HALF:
   2.640 +		*speed = SPEED_10;
   2.641 +		*duplex = DUPLEX_HALF;
   2.642 +		break;
   2.643 +
   2.644 +	case MII_TG3_AUX_STAT_10FULL:
   2.645 +		*speed = SPEED_10;
   2.646 +		*duplex = DUPLEX_FULL;
   2.647 +		break;
   2.648 +
   2.649 +	case MII_TG3_AUX_STAT_100HALF:
   2.650 +		*speed = SPEED_100;
   2.651 +		*duplex = DUPLEX_HALF;
   2.652 +		break;
   2.653 +
   2.654 +	case MII_TG3_AUX_STAT_100FULL:
   2.655 +		*speed = SPEED_100;
   2.656 +		*duplex = DUPLEX_FULL;
   2.657 +		break;
   2.658 +
   2.659 +	case MII_TG3_AUX_STAT_1000HALF:
   2.660 +		*speed = SPEED_1000;
   2.661 +		*duplex = DUPLEX_HALF;
   2.662 +		break;
   2.663 +
   2.664 +	case MII_TG3_AUX_STAT_1000FULL:
   2.665 +		*speed = SPEED_1000;
   2.666 +		*duplex = DUPLEX_FULL;
   2.667 +		break;
   2.668 +
   2.669 +	default:
   2.670 +		*speed = SPEED_INVALID;
   2.671 +		*duplex = DUPLEX_INVALID;
   2.672 +		break;
   2.673 +	};
   2.674 +}
   2.675 +
   2.676 +static int tg3_phy_copper_begin(struct tg3 *tp, int wait_for_link)
   2.677 +{
   2.678 +	u32 new_adv;
   2.679 +	int i;
   2.680 +
   2.681 +	if (tp->link_config.phy_is_low_power) {
   2.682 +		/* Entering low power mode.  Disable gigabit and
   2.683 +		 * 100baseT advertisements.
   2.684 +		 */
   2.685 +		tg3_writephy(tp, MII_TG3_CTRL, 0);
   2.686 +
   2.687 +		new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
   2.688 +			   ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
   2.689 +		if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
   2.690 +			new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
   2.691 +
   2.692 +		tg3_writephy(tp, MII_ADVERTISE, new_adv);
   2.693 +	} else if (tp->link_config.speed == SPEED_INVALID) {
   2.694 +		tp->link_config.advertising =
   2.695 +			(ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
   2.696 +			 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
   2.697 +			 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
   2.698 +			 ADVERTISED_Autoneg | ADVERTISED_MII);
   2.699 +
   2.700 +		if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
   2.701 +			tp->link_config.advertising &=
   2.702 +				~(ADVERTISED_1000baseT_Half |
   2.703 +				  ADVERTISED_1000baseT_Full);
   2.704 +
   2.705 +		new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
   2.706 +		if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
   2.707 +			new_adv |= ADVERTISE_10HALF;
   2.708 +		if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
   2.709 +			new_adv |= ADVERTISE_10FULL;
   2.710 +		if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
   2.711 +			new_adv |= ADVERTISE_100HALF;
   2.712 +		if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
   2.713 +			new_adv |= ADVERTISE_100FULL;
   2.714 +		tg3_writephy(tp, MII_ADVERTISE, new_adv);
   2.715 +
   2.716 +		if (tp->link_config.advertising &
   2.717 +		    (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
   2.718 +			new_adv = 0;
   2.719 +			if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
   2.720 +				new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
   2.721 +			if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
   2.722 +				new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
   2.723 +			if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
   2.724 +			    (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
   2.725 +			     tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
   2.726 +				new_adv |= (MII_TG3_CTRL_AS_MASTER |
   2.727 +					    MII_TG3_CTRL_ENABLE_AS_MASTER);
   2.728 +			tg3_writephy(tp, MII_TG3_CTRL, new_adv);
   2.729 +		} else {
   2.730 +			tg3_writephy(tp, MII_TG3_CTRL, 0);
   2.731 +		}
   2.732 +	} else {
   2.733 +		/* Asking for a specific link mode. */
   2.734 +		if (tp->link_config.speed == SPEED_1000) {
   2.735 +			new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
   2.736 +			tg3_writephy(tp, MII_ADVERTISE, new_adv);
   2.737 +
   2.738 +			if (tp->link_config.duplex == DUPLEX_FULL)
   2.739 +				new_adv = MII_TG3_CTRL_ADV_1000_FULL;
   2.740 +			else
   2.741 +				new_adv = MII_TG3_CTRL_ADV_1000_HALF;
   2.742 +			if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
   2.743 +			    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
   2.744 +				new_adv |= (MII_TG3_CTRL_AS_MASTER |
   2.745 +					    MII_TG3_CTRL_ENABLE_AS_MASTER);
   2.746 +			tg3_writephy(tp, MII_TG3_CTRL, new_adv);
   2.747 +		} else {
   2.748 +			tg3_writephy(tp, MII_TG3_CTRL, 0);
   2.749 +
   2.750 +			new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
   2.751 +			if (tp->link_config.speed == SPEED_100) {
   2.752 +				if (tp->link_config.duplex == DUPLEX_FULL)
   2.753 +					new_adv |= ADVERTISE_100FULL;
   2.754 +				else
   2.755 +					new_adv |= ADVERTISE_100HALF;
   2.756 +			} else {
   2.757 +				if (tp->link_config.duplex == DUPLEX_FULL)
   2.758 +					new_adv |= ADVERTISE_10FULL;
   2.759 +				else
   2.760 +					new_adv |= ADVERTISE_10HALF;
   2.761 +			}
   2.762 +			tg3_writephy(tp, MII_ADVERTISE, new_adv);
   2.763 +		}
   2.764 +	}
   2.765 +
   2.766 +	if (tp->link_config.autoneg == AUTONEG_DISABLE &&
   2.767 +	    tp->link_config.speed != SPEED_INVALID) {
   2.768 +		u32 bmcr, orig_bmcr;
   2.769 +
   2.770 +		tp->link_config.active_speed = tp->link_config.speed;
   2.771 +		tp->link_config.active_duplex = tp->link_config.duplex;
   2.772 +
   2.773 +		bmcr = 0;
   2.774 +		switch (tp->link_config.speed) {
   2.775 +		default:
   2.776 +		case SPEED_10:
   2.777 +			break;
   2.778 +
   2.779 +		case SPEED_100:
   2.780 +			bmcr |= BMCR_SPEED100;
   2.781 +			break;
   2.782 +
   2.783 +		case SPEED_1000:
   2.784 +			bmcr |= TG3_BMCR_SPEED1000;
   2.785 +			break;
   2.786 +		};
   2.787 +
   2.788 +		if (tp->link_config.duplex == DUPLEX_FULL)
   2.789 +			bmcr |= BMCR_FULLDPLX;
   2.790 +
   2.791 +		tg3_readphy(tp, MII_BMCR, &orig_bmcr);
   2.792 +		if (bmcr != orig_bmcr) {
   2.793 +			tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
   2.794 +			for (i = 0; i < 15000; i++) {
   2.795 +				u32 tmp;
   2.796 +
   2.797 +				udelay(10);
   2.798 +				tg3_readphy(tp, MII_BMSR, &tmp);
   2.799 +				tg3_readphy(tp, MII_BMSR, &tmp);
   2.800 +				if (!(tmp & BMSR_LSTATUS)) {
   2.801 +					udelay(40);
   2.802 +					break;
   2.803 +				}
   2.804 +			}
   2.805 +			tg3_writephy(tp, MII_BMCR, bmcr);
   2.806 +			udelay(40);
   2.807 +		}
   2.808 +	} else {
   2.809 +		tg3_writephy(tp, MII_BMCR,
   2.810 +			     BMCR_ANENABLE | BMCR_ANRESTART);
   2.811 +	}
   2.812 +
   2.813 +	if (wait_for_link) {
   2.814 +		tp->link_config.active_speed = SPEED_INVALID;
   2.815 +		tp->link_config.active_duplex = DUPLEX_INVALID;
   2.816 +		for (i = 0; i < 300000; i++) {
   2.817 +			u32 tmp;
   2.818 +
   2.819 +			udelay(10);
   2.820 +			tg3_readphy(tp, MII_BMSR, &tmp);
   2.821 +			tg3_readphy(tp, MII_BMSR, &tmp);
   2.822 +			if (!(tmp & BMSR_LSTATUS))
   2.823 +				continue;
   2.824 +
   2.825 +			tg3_readphy(tp, MII_TG3_AUX_STAT, &tmp);
   2.826 +			tg3_aux_stat_to_speed_duplex(tp, tmp,
   2.827 +						     &tp->link_config.active_speed,
   2.828 +						     &tp->link_config.active_duplex);
   2.829 +		}
   2.830 +		if (tp->link_config.active_speed == SPEED_INVALID)
   2.831 +			return -EINVAL;
   2.832 +	}
   2.833 +
   2.834 +	return 0;
   2.835 +}
   2.836 +
   2.837 +static int tg3_init_5401phy_dsp(struct tg3 *tp)
   2.838 +{
   2.839 +	int err;
   2.840 +
   2.841 +	/* Turn off tap power management. */
   2.842 +	err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c20);
   2.843 +
   2.844 +	err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
   2.845 +	err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
   2.846 +
   2.847 +	err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
   2.848 +	err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
   2.849 +
   2.850 +	err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
   2.851 +	err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
   2.852 +
   2.853 +	err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
   2.854 +	err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
   2.855 +
   2.856 +	err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
   2.857 +	err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
   2.858 +
   2.859 +	udelay(40);
   2.860 +
   2.861 +	return err;
   2.862 +}
   2.863 +
   2.864 +static int tg3_setup_copper_phy(struct tg3 *tp)
   2.865 +{
   2.866 +	int current_link_up;
   2.867 +	u32 bmsr, dummy;
   2.868 +	u16 current_speed;
   2.869 +	u8 current_duplex;
   2.870 +	int i, err;
   2.871 +
   2.872 +	tw32(MAC_STATUS,
   2.873 +	     (MAC_STATUS_SYNC_CHANGED |
   2.874 +	      MAC_STATUS_CFG_CHANGED));
   2.875 +	tr32(MAC_STATUS);
   2.876 +	udelay(40);
   2.877 +
   2.878 +	tp->mi_mode = MAC_MI_MODE_BASE;
   2.879 +	tw32(MAC_MI_MODE, tp->mi_mode);
   2.880 +	tr32(MAC_MI_MODE);
   2.881 +	udelay(40);
   2.882 +
   2.883 +	tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
   2.884 +
   2.885 +	if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
   2.886 +		tg3_readphy(tp, MII_BMSR, &bmsr);
   2.887 +		tg3_readphy(tp, MII_BMSR, &bmsr);
   2.888 +
   2.889 +		if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
   2.890 +			bmsr = 0;
   2.891 +
   2.892 +		if (!(bmsr & BMSR_LSTATUS)) {
   2.893 +			err = tg3_init_5401phy_dsp(tp);
   2.894 +			if (err)
   2.895 +				return err;
   2.896 +
   2.897 +			tg3_readphy(tp, MII_BMSR, &bmsr);
   2.898 +			for (i = 0; i < 1000; i++) {
   2.899 +				udelay(10);
   2.900 +				tg3_readphy(tp, MII_BMSR, &bmsr);
   2.901 +				if (bmsr & BMSR_LSTATUS) {
   2.902 +					udelay(40);
   2.903 +					break;
   2.904 +				}
   2.905 +			}
   2.906 +
   2.907 +			if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
   2.908 +			    !(bmsr & BMSR_LSTATUS) &&
   2.909 +			    tp->link_config.active_speed == SPEED_1000) {
   2.910 +				err = tg3_phy_reset(tp, 1);
   2.911 +				if (!err)
   2.912 +					err = tg3_init_5401phy_dsp(tp);
   2.913 +				if (err)
   2.914 +					return err;
   2.915 +			}
   2.916 +		}
   2.917 +	} else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
   2.918 +		   tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
   2.919 +		/* 5701 {A0,B0} CRC bug workaround */
   2.920 +		tg3_writephy(tp, 0x15, 0x0a75);
   2.921 +		tg3_writephy(tp, 0x1c, 0x8c68);
   2.922 +		tg3_writephy(tp, 0x1c, 0x8d68);
   2.923 +		tg3_writephy(tp, 0x1c, 0x8c68);
   2.924 +	}
   2.925 +
   2.926 +	/* Clear pending interrupts... */
   2.927 +	tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
   2.928 +	tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
   2.929 +
   2.930 +	if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
   2.931 +		tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
   2.932 +	else
   2.933 +		tg3_writephy(tp, MII_TG3_IMASK, ~0);
   2.934 +
   2.935 +	if (tp->led_mode == led_mode_three_link)
   2.936 +		tg3_writephy(tp, MII_TG3_EXT_CTRL,
   2.937 +			     MII_TG3_EXT_CTRL_LNK3_LED_MODE);
   2.938 +	else
   2.939 +		tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
   2.940 +
   2.941 +	current_link_up = 0;
   2.942 +	current_speed = SPEED_INVALID;
   2.943 +	current_duplex = DUPLEX_INVALID;
   2.944 +
   2.945 +	tg3_readphy(tp, MII_BMSR, &bmsr);
   2.946 +	tg3_readphy(tp, MII_BMSR, &bmsr);
   2.947 +
   2.948 +	if (bmsr & BMSR_LSTATUS) {
   2.949 +		u32 aux_stat, bmcr;
   2.950 +
   2.951 +		tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
   2.952 +		for (i = 0; i < 2000; i++) {
   2.953 +			udelay(10);
   2.954 +			tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
   2.955 +			if (aux_stat)
   2.956 +				break;
   2.957 +		}
   2.958 +
   2.959 +		tg3_aux_stat_to_speed_duplex(tp, aux_stat,
   2.960 +					     &current_speed,
   2.961 +					     &current_duplex);
   2.962 +		tg3_readphy(tp, MII_BMCR, &bmcr);
   2.963 +		tg3_readphy(tp, MII_BMCR, &bmcr);
   2.964 +		if (tp->link_config.autoneg == AUTONEG_ENABLE) {
   2.965 +			if (bmcr & BMCR_ANENABLE) {
   2.966 +				u32 gig_ctrl;
   2.967 +
   2.968 +				current_link_up = 1;
   2.969 +
   2.970 +				/* Force autoneg restart if we are exiting
   2.971 +				 * low power mode.
   2.972 +				 */
   2.973 +				tg3_readphy(tp, MII_TG3_CTRL, &gig_ctrl);
   2.974 +				if (!(gig_ctrl & (MII_TG3_CTRL_ADV_1000_HALF |
   2.975 +						  MII_TG3_CTRL_ADV_1000_FULL))) {
   2.976 +					current_link_up = 0;
   2.977 +				}
   2.978 +			} else {
   2.979 +				current_link_up = 0;
   2.980 +			}
   2.981 +		} else {
   2.982 +			if (!(bmcr & BMCR_ANENABLE) &&
   2.983 +			    tp->link_config.speed == current_speed &&
   2.984 +			    tp->link_config.duplex == current_duplex) {
   2.985 +				current_link_up = 1;
   2.986 +			} else {
   2.987 +				current_link_up = 0;
   2.988 +			}
   2.989 +		}
   2.990 +
   2.991 +		tp->link_config.active_speed = current_speed;
   2.992 +		tp->link_config.active_duplex = current_duplex;
   2.993 +	}
   2.994 +
   2.995 +	if (current_link_up == 1 &&
   2.996 +	    (tp->link_config.active_duplex == DUPLEX_FULL) &&
   2.997 +	    (tp->link_config.autoneg == AUTONEG_ENABLE)) {
   2.998 +		u32 local_adv, remote_adv;
   2.999 +
  2.1000 +		tg3_readphy(tp, MII_ADVERTISE, &local_adv);
  2.1001 +		local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  2.1002 +
  2.1003 +		tg3_readphy(tp, MII_LPA, &remote_adv);
  2.1004 +		remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
  2.1005 +
  2.1006 +		/* If we are not advertising full pause capability,
  2.1007 +		 * something is wrong.  Bring the link down and reconfigure.
  2.1008 +		 */
  2.1009 +		if (local_adv != ADVERTISE_PAUSE_CAP) {
  2.1010 +			current_link_up = 0;
  2.1011 +		} else {
  2.1012 +			tg3_setup_flow_control(tp, local_adv, remote_adv);
  2.1013 +		}
  2.1014 +	}
  2.1015 +
  2.1016 +	if (current_link_up == 0) {
  2.1017 +		u32 tmp;
  2.1018 +
  2.1019 +		tg3_phy_copper_begin(tp, 0);
  2.1020 +
  2.1021 +		tg3_readphy(tp, MII_BMSR, &tmp);
  2.1022 +		tg3_readphy(tp, MII_BMSR, &tmp);
  2.1023 +		if (tmp & BMSR_LSTATUS)
  2.1024 +			current_link_up = 1;
  2.1025 +	}
  2.1026 +
  2.1027 +	tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  2.1028 +	if (current_link_up == 1) {
  2.1029 +		if (tp->link_config.active_speed == SPEED_100 ||
  2.1030 +		    tp->link_config.active_speed == SPEED_10)
  2.1031 +			tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  2.1032 +		else
  2.1033 +			tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2.1034 +	} else
  2.1035 +		tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2.1036 +
  2.1037 +	tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  2.1038 +	if (tp->link_config.active_duplex == DUPLEX_HALF)
  2.1039 +		tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  2.1040 +
  2.1041 +	tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  2.1042 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  2.1043 +		if ((tp->led_mode == led_mode_link10) ||
  2.1044 +		    (current_link_up == 1 &&
  2.1045 +		     tp->link_config.active_speed == SPEED_10))
  2.1046 +			tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  2.1047 +	} else {
  2.1048 +		if (current_link_up == 1)
  2.1049 +			tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  2.1050 +		tw32(MAC_LED_CTRL, LED_CTRL_PHY_MODE_1);
  2.1051 +	}
  2.1052 +
  2.1053 +	/* ??? Without this setting Netgear GA302T PHY does not
  2.1054 +	 * ??? send/receive packets...
  2.1055 +	 */
  2.1056 +	if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
  2.1057 +	    tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
  2.1058 +		tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
  2.1059 +		tw32(MAC_MI_MODE, tp->mi_mode);
  2.1060 +		tr32(MAC_MI_MODE);
  2.1061 +		udelay(40);
  2.1062 +	}
  2.1063 +
  2.1064 +	tw32(MAC_MODE, tp->mac_mode);
  2.1065 +	tr32(MAC_MODE);
  2.1066 +	udelay(40);
  2.1067 +
  2.1068 +	if (tp->tg3_flags &
  2.1069 +	    (TG3_FLAG_USE_LINKCHG_REG |
  2.1070 +	     TG3_FLAG_POLL_SERDES)) {
  2.1071 +		/* Polled via timer. */
  2.1072 +		tw32(MAC_EVENT, 0);
  2.1073 +	} else {
  2.1074 +		tw32(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2.1075 +	}
  2.1076 +	tr32(MAC_EVENT);
  2.1077 +	udelay(40);
  2.1078 +
  2.1079 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
  2.1080 +	    current_link_up == 1 &&
  2.1081 +	    tp->link_config.active_speed == SPEED_1000 &&
  2.1082 +	    ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
  2.1083 +	     (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
  2.1084 +		udelay(120);
  2.1085 +		tw32(MAC_STATUS,
  2.1086 +		     (MAC_STATUS_SYNC_CHANGED |
  2.1087 +		      MAC_STATUS_CFG_CHANGED));
  2.1088 +		tr32(MAC_STATUS);
  2.1089 +		udelay(40);
  2.1090 +		tg3_write_mem(tp,
  2.1091 +			      NIC_SRAM_FIRMWARE_MBOX,
  2.1092 +			      NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
  2.1093 +	}
  2.1094 +
  2.1095 +	if (current_link_up != netif_carrier_ok(tp->dev)) {
  2.1096 +		if (current_link_up)
  2.1097 +			netif_carrier_on(tp->dev);
  2.1098 +		else
  2.1099 +			netif_carrier_off(tp->dev);
  2.1100 +		tg3_link_report(tp);
  2.1101 +	}
  2.1102 +
  2.1103 +	return 0;
  2.1104 +}
  2.1105 +
  2.1106 +struct tg3_fiber_aneginfo {
  2.1107 +	int state;
  2.1108 +#define ANEG_STATE_UNKNOWN		0
  2.1109 +#define ANEG_STATE_AN_ENABLE		1
  2.1110 +#define ANEG_STATE_RESTART_INIT		2
  2.1111 +#define ANEG_STATE_RESTART		3
  2.1112 +#define ANEG_STATE_DISABLE_LINK_OK	4
  2.1113 +#define ANEG_STATE_ABILITY_DETECT_INIT	5
  2.1114 +#define ANEG_STATE_ABILITY_DETECT	6
  2.1115 +#define ANEG_STATE_ACK_DETECT_INIT	7
  2.1116 +#define ANEG_STATE_ACK_DETECT		8
  2.1117 +#define ANEG_STATE_COMPLETE_ACK_INIT	9
  2.1118 +#define ANEG_STATE_COMPLETE_ACK		10
  2.1119 +#define ANEG_STATE_IDLE_DETECT_INIT	11
  2.1120 +#define ANEG_STATE_IDLE_DETECT		12
  2.1121 +#define ANEG_STATE_LINK_OK		13
  2.1122 +#define ANEG_STATE_NEXT_PAGE_WAIT_INIT	14
  2.1123 +#define ANEG_STATE_NEXT_PAGE_WAIT	15
  2.1124 +
  2.1125 +	u32 flags;
  2.1126 +#define MR_AN_ENABLE		0x00000001
  2.1127 +#define MR_RESTART_AN		0x00000002
  2.1128 +#define MR_AN_COMPLETE		0x00000004
  2.1129 +#define MR_PAGE_RX		0x00000008
  2.1130 +#define MR_NP_LOADED		0x00000010
  2.1131 +#define MR_TOGGLE_TX		0x00000020
  2.1132 +#define MR_LP_ADV_FULL_DUPLEX	0x00000040
  2.1133 +#define MR_LP_ADV_HALF_DUPLEX	0x00000080
  2.1134 +#define MR_LP_ADV_SYM_PAUSE	0x00000100
  2.1135 +#define MR_LP_ADV_ASYM_PAUSE	0x00000200
  2.1136 +#define MR_LP_ADV_REMOTE_FAULT1	0x00000400
  2.1137 +#define MR_LP_ADV_REMOTE_FAULT2	0x00000800
  2.1138 +#define MR_LP_ADV_NEXT_PAGE	0x00001000
  2.1139 +#define MR_TOGGLE_RX		0x00002000
  2.1140 +#define MR_NP_RX		0x00004000
  2.1141 +
  2.1142 +#define MR_LINK_OK		0x80000000
  2.1143 +
  2.1144 +	unsigned long link_time, cur_time;
  2.1145 +
  2.1146 +	u32 ability_match_cfg;
  2.1147 +	int ability_match_count;
  2.1148 +
  2.1149 +	char ability_match, idle_match, ack_match;
  2.1150 +
  2.1151 +	u32 txconfig, rxconfig;
  2.1152 +#define ANEG_CFG_NP		0x00000080
  2.1153 +#define ANEG_CFG_ACK		0x00000040
  2.1154 +#define ANEG_CFG_RF2		0x00000020
  2.1155 +#define ANEG_CFG_RF1		0x00000010
  2.1156 +#define ANEG_CFG_PS2		0x00000001
  2.1157 +#define ANEG_CFG_PS1		0x00008000
  2.1158 +#define ANEG_CFG_HD		0x00004000
  2.1159 +#define ANEG_CFG_FD		0x00002000
  2.1160 +#define ANEG_CFG_INVAL		0x00001f06
  2.1161 +
  2.1162 +};
  2.1163 +#define ANEG_OK		0
  2.1164 +#define ANEG_DONE	1
  2.1165 +#define ANEG_TIMER_ENAB	2
  2.1166 +#define ANEG_FAILED	-1
  2.1167 +
  2.1168 +#define ANEG_STATE_SETTLE_TIME	10000
  2.1169 +
  2.1170 +static int tg3_fiber_aneg_smachine(struct tg3 *tp,
  2.1171 +				   struct tg3_fiber_aneginfo *ap)
  2.1172 +{
  2.1173 +	unsigned long delta;
  2.1174 +	u32 rx_cfg_reg;
  2.1175 +	int ret;
  2.1176 +
  2.1177 +	if (ap->state == ANEG_STATE_UNKNOWN) {
  2.1178 +		ap->rxconfig = 0;
  2.1179 +		ap->link_time = 0;
  2.1180 +		ap->cur_time = 0;
  2.1181 +		ap->ability_match_cfg = 0;
  2.1182 +		ap->ability_match_count = 0;
  2.1183 +		ap->ability_match = 0;
  2.1184 +		ap->idle_match = 0;
  2.1185 +		ap->ack_match = 0;
  2.1186 +	}
  2.1187 +	ap->cur_time++;
  2.1188 +
  2.1189 +	if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
  2.1190 +		rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
  2.1191 +
  2.1192 +		if (rx_cfg_reg != ap->ability_match_cfg) {
  2.1193 +			ap->ability_match_cfg = rx_cfg_reg;
  2.1194 +			ap->ability_match = 0;
  2.1195 +			ap->ability_match_count = 0;
  2.1196 +		} else {
  2.1197 +			if (++ap->ability_match_count > 1) {
  2.1198 +				ap->ability_match = 1;
  2.1199 +				ap->ability_match_cfg = rx_cfg_reg;
  2.1200 +			}
  2.1201 +		}
  2.1202 +		if (rx_cfg_reg & ANEG_CFG_ACK)
  2.1203 +			ap->ack_match = 1;
  2.1204 +		else
  2.1205 +			ap->ack_match = 0;
  2.1206 +
  2.1207 +		ap->idle_match = 0;
  2.1208 +	} else {
  2.1209 +		ap->idle_match = 1;
  2.1210 +		ap->ability_match_cfg = 0;
  2.1211 +		ap->ability_match_count = 0;
  2.1212 +		ap->ability_match = 0;
  2.1213 +		ap->ack_match = 0;
  2.1214 +
  2.1215 +		rx_cfg_reg = 0;
  2.1216 +	}
  2.1217 +
  2.1218 +	ap->rxconfig = rx_cfg_reg;
  2.1219 +	ret = ANEG_OK;
  2.1220 +
  2.1221 +	switch(ap->state) {
  2.1222 +	case ANEG_STATE_UNKNOWN:
  2.1223 +		if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
  2.1224 +			ap->state = ANEG_STATE_AN_ENABLE;
  2.1225 +
  2.1226 +		/* fallthru */
  2.1227 +	case ANEG_STATE_AN_ENABLE:
  2.1228 +		ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
  2.1229 +		if (ap->flags & MR_AN_ENABLE) {
  2.1230 +			ap->link_time = 0;
  2.1231 +			ap->cur_time = 0;
  2.1232 +			ap->ability_match_cfg = 0;
  2.1233 +			ap->ability_match_count = 0;
  2.1234 +			ap->ability_match = 0;
  2.1235 +			ap->idle_match = 0;
  2.1236 +			ap->ack_match = 0;
  2.1237 +
  2.1238 +			ap->state = ANEG_STATE_RESTART_INIT;
  2.1239 +		} else {
  2.1240 +			ap->state = ANEG_STATE_DISABLE_LINK_OK;
  2.1241 +		}
  2.1242 +		break;
  2.1243 +
  2.1244 +	case ANEG_STATE_RESTART_INIT:
  2.1245 +		ap->link_time = ap->cur_time;
  2.1246 +		ap->flags &= ~(MR_NP_LOADED);
  2.1247 +		ap->txconfig = 0;
  2.1248 +		tw32(MAC_TX_AUTO_NEG, 0);
  2.1249 +		tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2.1250 +		tw32(MAC_MODE, tp->mac_mode);
  2.1251 +		tr32(MAC_MODE);
  2.1252 +		udelay(40);
  2.1253 +
  2.1254 +		ret = ANEG_TIMER_ENAB;
  2.1255 +		ap->state = ANEG_STATE_RESTART;
  2.1256 +
  2.1257 +		/* fallthru */
  2.1258 +	case ANEG_STATE_RESTART:
  2.1259 +		delta = ap->cur_time - ap->link_time;
  2.1260 +		if (delta > ANEG_STATE_SETTLE_TIME) {
  2.1261 +			ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
  2.1262 +		} else {
  2.1263 +			ret = ANEG_TIMER_ENAB;
  2.1264 +		}
  2.1265 +		break;
  2.1266 +
  2.1267 +	case ANEG_STATE_DISABLE_LINK_OK:
  2.1268 +		ret = ANEG_DONE;
  2.1269 +		break;
  2.1270 +
  2.1271 +	case ANEG_STATE_ABILITY_DETECT_INIT:
  2.1272 +		ap->flags &= ~(MR_TOGGLE_TX);
  2.1273 +		ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
  2.1274 +		tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  2.1275 +		tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2.1276 +		tw32(MAC_MODE, tp->mac_mode);
  2.1277 +		tr32(MAC_MODE);
  2.1278 +		udelay(40);
  2.1279 +
  2.1280 +		ap->state = ANEG_STATE_ABILITY_DETECT;
  2.1281 +		break;
  2.1282 +
  2.1283 +	case ANEG_STATE_ABILITY_DETECT:
  2.1284 +		if (ap->ability_match != 0 && ap->rxconfig != 0) {
  2.1285 +			ap->state = ANEG_STATE_ACK_DETECT_INIT;
  2.1286 +		}
  2.1287 +		break;
  2.1288 +
  2.1289 +	case ANEG_STATE_ACK_DETECT_INIT:
  2.1290 +		ap->txconfig |= ANEG_CFG_ACK;
  2.1291 +		tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  2.1292 +		tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2.1293 +		tw32(MAC_MODE, tp->mac_mode);
  2.1294 +		tr32(MAC_MODE);
  2.1295 +		udelay(40);
  2.1296 +
  2.1297 +		ap->state = ANEG_STATE_ACK_DETECT;
  2.1298 +
  2.1299 +		/* fallthru */
  2.1300 +	case ANEG_STATE_ACK_DETECT:
  2.1301 +		if (ap->ack_match != 0) {
  2.1302 +			if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
  2.1303 +			    (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
  2.1304 +				ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
  2.1305 +			} else {
  2.1306 +				ap->state = ANEG_STATE_AN_ENABLE;
  2.1307 +			}
  2.1308 +		} else if (ap->ability_match != 0 &&
  2.1309 +			   ap->rxconfig == 0) {
  2.1310 +			ap->state = ANEG_STATE_AN_ENABLE;
  2.1311 +		}
  2.1312 +		break;
  2.1313 +
  2.1314 +	case ANEG_STATE_COMPLETE_ACK_INIT:
  2.1315 +		if (ap->rxconfig & ANEG_CFG_INVAL) {
  2.1316 +			ret = ANEG_FAILED;
  2.1317 +			break;
  2.1318 +		}
  2.1319 +		ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
  2.1320 +			       MR_LP_ADV_HALF_DUPLEX |
  2.1321 +			       MR_LP_ADV_SYM_PAUSE |
  2.1322 +			       MR_LP_ADV_ASYM_PAUSE |
  2.1323 +			       MR_LP_ADV_REMOTE_FAULT1 |
  2.1324 +			       MR_LP_ADV_REMOTE_FAULT2 |
  2.1325 +			       MR_LP_ADV_NEXT_PAGE |
  2.1326 +			       MR_TOGGLE_RX |
  2.1327 +			       MR_NP_RX);
  2.1328 +		if (ap->rxconfig & ANEG_CFG_FD)
  2.1329 +			ap->flags |= MR_LP_ADV_FULL_DUPLEX;
  2.1330 +		if (ap->rxconfig & ANEG_CFG_HD)
  2.1331 +			ap->flags |= MR_LP_ADV_HALF_DUPLEX;
  2.1332 +		if (ap->rxconfig & ANEG_CFG_PS1)
  2.1333 +			ap->flags |= MR_LP_ADV_SYM_PAUSE;
  2.1334 +		if (ap->rxconfig & ANEG_CFG_PS2)
  2.1335 +			ap->flags |= MR_LP_ADV_ASYM_PAUSE;
  2.1336 +		if (ap->rxconfig & ANEG_CFG_RF1)
  2.1337 +			ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
  2.1338 +		if (ap->rxconfig & ANEG_CFG_RF2)
  2.1339 +			ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
  2.1340 +		if (ap->rxconfig & ANEG_CFG_NP)
  2.1341 +			ap->flags |= MR_LP_ADV_NEXT_PAGE;
  2.1342 +
  2.1343 +		ap->link_time = ap->cur_time;
  2.1344 +
  2.1345 +		ap->flags ^= (MR_TOGGLE_TX);
  2.1346 +		if (ap->rxconfig & 0x0008)
  2.1347 +			ap->flags |= MR_TOGGLE_RX;
  2.1348 +		if (ap->rxconfig & ANEG_CFG_NP)
  2.1349 +			ap->flags |= MR_NP_RX;
  2.1350 +		ap->flags |= MR_PAGE_RX;
  2.1351 +
  2.1352 +		ap->state = ANEG_STATE_COMPLETE_ACK;
  2.1353 +		ret = ANEG_TIMER_ENAB;
  2.1354 +		break;
  2.1355 +
  2.1356 +	case ANEG_STATE_COMPLETE_ACK:
  2.1357 +		if (ap->ability_match != 0 &&
  2.1358 +		    ap->rxconfig == 0) {
  2.1359 +			ap->state = ANEG_STATE_AN_ENABLE;
  2.1360 +			break;
  2.1361 +		}
  2.1362 +		delta = ap->cur_time - ap->link_time;
  2.1363 +		if (delta > ANEG_STATE_SETTLE_TIME) {
  2.1364 +			if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
  2.1365 +				ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  2.1366 +			} else {
  2.1367 +				if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
  2.1368 +				    !(ap->flags & MR_NP_RX)) {
  2.1369 +					ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  2.1370 +				} else {
  2.1371 +					ret = ANEG_FAILED;
  2.1372 +				}
  2.1373 +			}
  2.1374 +		}
  2.1375 +		break;
  2.1376 +
  2.1377 +	case ANEG_STATE_IDLE_DETECT_INIT:
  2.1378 +		ap->link_time = ap->cur_time;
  2.1379 +		tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  2.1380 +		tw32(MAC_MODE, tp->mac_mode);
  2.1381 +		tr32(MAC_MODE);
  2.1382 +		udelay(40);
  2.1383 +
  2.1384 +		ap->state = ANEG_STATE_IDLE_DETECT;
  2.1385 +		ret = ANEG_TIMER_ENAB;
  2.1386 +		break;
  2.1387 +
  2.1388 +	case ANEG_STATE_IDLE_DETECT:
  2.1389 +		if (ap->ability_match != 0 &&
  2.1390 +		    ap->rxconfig == 0) {
  2.1391 +			ap->state = ANEG_STATE_AN_ENABLE;
  2.1392 +			break;
  2.1393 +		}
  2.1394 +		delta = ap->cur_time - ap->link_time;
  2.1395 +		if (delta > ANEG_STATE_SETTLE_TIME) {
  2.1396 +			/* XXX another gem from the Broadcom driver :( */
  2.1397 +			ap->state = ANEG_STATE_LINK_OK;
  2.1398 +		}
  2.1399 +		break;
  2.1400 +
  2.1401 +	case ANEG_STATE_LINK_OK:
  2.1402 +		ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
  2.1403 +		ret = ANEG_DONE;
  2.1404 +		break;
  2.1405 +
  2.1406 +	case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
  2.1407 +		/* ??? unimplemented */
  2.1408 +		break;
  2.1409 +
  2.1410 +	case ANEG_STATE_NEXT_PAGE_WAIT:
  2.1411 +		/* ??? unimplemented */
  2.1412 +		break;
  2.1413 +
  2.1414 +	default:
  2.1415 +		ret = ANEG_FAILED;
  2.1416 +		break;
  2.1417 +	};
  2.1418 +
  2.1419 +	return ret;
  2.1420 +}
  2.1421 +
  2.1422 +static int tg3_setup_fiber_phy(struct tg3 *tp)
  2.1423 +{
  2.1424 +	u32 orig_pause_cfg;
  2.1425 +	u16 orig_active_speed;
  2.1426 +	u8 orig_active_duplex;
  2.1427 +	int current_link_up;
  2.1428 +	int i;
  2.1429 +
  2.1430 +	orig_pause_cfg =
  2.1431 +		(tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
  2.1432 +				  TG3_FLAG_TX_PAUSE));
  2.1433 +	orig_active_speed = tp->link_config.active_speed;
  2.1434 +	orig_active_duplex = tp->link_config.active_duplex;
  2.1435 +
  2.1436 +	tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  2.1437 +	tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
  2.1438 +	tw32(MAC_MODE, tp->mac_mode);
  2.1439 +	tr32(MAC_MODE);
  2.1440 +	udelay(40);
  2.1441 +
  2.1442 +	/* Reset when initting first time or we have a link. */
  2.1443 +	if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
  2.1444 +	    (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
  2.1445 +		/* Set PLL lock range. */
  2.1446 +		tg3_writephy(tp, 0x16, 0x8007);
  2.1447 +
  2.1448 +		/* SW reset */
  2.1449 +		tg3_writephy(tp, MII_BMCR, BMCR_RESET);
  2.1450 +
  2.1451 +		/* Wait for reset to complete. */
  2.1452 +		/* XXX schedule_timeout() ... */
  2.1453 +		for (i = 0; i < 500; i++)
  2.1454 +			udelay(10);
  2.1455 +
  2.1456 +		/* Config mode; select PMA/Ch 1 regs. */
  2.1457 +		tg3_writephy(tp, 0x10, 0x8411);
  2.1458 +
  2.1459 +		/* Enable auto-lock and comdet, select txclk for tx. */
  2.1460 +		tg3_writephy(tp, 0x11, 0x0a10);
  2.1461 +
  2.1462 +		tg3_writephy(tp, 0x18, 0x00a0);
  2.1463 +		tg3_writephy(tp, 0x16, 0x41ff);
  2.1464 +
  2.1465 +		/* Assert and deassert POR. */
  2.1466 +		tg3_writephy(tp, 0x13, 0x0400);
  2.1467 +		udelay(40);
  2.1468 +		tg3_writephy(tp, 0x13, 0x0000);
  2.1469 +
  2.1470 +		tg3_writephy(tp, 0x11, 0x0a50);
  2.1471 +		udelay(40);
  2.1472 +		tg3_writephy(tp, 0x11, 0x0a10);
  2.1473 +
  2.1474 +		/* Wait for signal to stabilize */
  2.1475 +		/* XXX schedule_timeout() ... */
  2.1476 +		for (i = 0; i < 15000; i++)
  2.1477 +			udelay(10);
  2.1478 +
  2.1479 +		/* Deselect the channel register so we can read the PHYID
  2.1480 +		 * later.
  2.1481 +		 */
  2.1482 +		tg3_writephy(tp, 0x10, 0x8011);
  2.1483 +	}
  2.1484 +
  2.1485 +	/* Enable link change interrupt unless serdes polling.  */
  2.1486 +	if (!(tp->tg3_flags & TG3_FLAG_POLL_SERDES))
  2.1487 +		tw32(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2.1488 +	else
  2.1489 +		tw32(MAC_EVENT, 0);
  2.1490 +	tr32(MAC_EVENT);
  2.1491 +	udelay(40);
  2.1492 +
  2.1493 +	current_link_up = 0;
  2.1494 +	if (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) {
  2.1495 +		if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  2.1496 +		    !(tp->tg3_flags & TG3_FLAG_GOT_SERDES_FLOWCTL)) {
  2.1497 +			struct tg3_fiber_aneginfo aninfo;
  2.1498 +			int status = ANEG_FAILED;
  2.1499 +			unsigned int tick;
  2.1500 +			u32 tmp;
  2.1501 +
  2.1502 +			memset(&aninfo, 0, sizeof(aninfo));
  2.1503 +			aninfo.flags |= (MR_AN_ENABLE);
  2.1504 +
  2.1505 +			tw32(MAC_TX_AUTO_NEG, 0);
  2.1506 +
  2.1507 +			tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  2.1508 +			tw32(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
  2.1509 +			tr32(MAC_MODE);
  2.1510 +			udelay(40);
  2.1511 +
  2.1512 +			tw32(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
  2.1513 +			tr32(MAC_MODE);
  2.1514 +			udelay(40);
  2.1515 +
  2.1516 +			aninfo.state = ANEG_STATE_UNKNOWN;
  2.1517 +			aninfo.cur_time = 0;
  2.1518 +			tick = 0;
  2.1519 +			while (++tick < 195000) {
  2.1520 +				status = tg3_fiber_aneg_smachine(tp, &aninfo);
  2.1521 +				if (status == ANEG_DONE ||
  2.1522 +				    status == ANEG_FAILED)
  2.1523 +					break;
  2.1524 +
  2.1525 +				udelay(1);
  2.1526 +			}
  2.1527 +
  2.1528 +			tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  2.1529 +			tw32(MAC_MODE, tp->mac_mode);
  2.1530 +			tr32(MAC_MODE);
  2.1531 +			udelay(40);
  2.1532 +
  2.1533 +			if (status == ANEG_DONE &&
  2.1534 +			    (aninfo.flags &
  2.1535 +			     (MR_AN_COMPLETE | MR_LINK_OK |
  2.1536 +			      MR_LP_ADV_FULL_DUPLEX))) {
  2.1537 +				u32 local_adv, remote_adv;
  2.1538 +
  2.1539 +				local_adv = ADVERTISE_PAUSE_CAP;
  2.1540 +				remote_adv = 0;
  2.1541 +				if (aninfo.flags & MR_LP_ADV_SYM_PAUSE)
  2.1542 +					remote_adv |= LPA_PAUSE_CAP;
  2.1543 +				if (aninfo.flags & MR_LP_ADV_ASYM_PAUSE)
  2.1544 +					remote_adv |= LPA_PAUSE_ASYM;
  2.1545 +
  2.1546 +				tg3_setup_flow_control(tp, local_adv, remote_adv);
  2.1547 +
  2.1548 +				tp->tg3_flags |=
  2.1549 +					TG3_FLAG_GOT_SERDES_FLOWCTL;
  2.1550 +				current_link_up = 1;
  2.1551 +			}
  2.1552 +			for (i = 0; i < 60; i++) {
  2.1553 +				udelay(20);
  2.1554 +				tw32(MAC_STATUS,
  2.1555 +				     (MAC_STATUS_SYNC_CHANGED |
  2.1556 +				      MAC_STATUS_CFG_CHANGED));
  2.1557 +				tr32(MAC_STATUS);
  2.1558 +				udelay(40);
  2.1559 +				if ((tr32(MAC_STATUS) &
  2.1560 +				     (MAC_STATUS_SYNC_CHANGED |
  2.1561 +				      MAC_STATUS_CFG_CHANGED)) == 0)
  2.1562 +					break;
  2.1563 +			}
  2.1564 +			if (current_link_up == 0 &&
  2.1565 +			    (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
  2.1566 +				current_link_up = 1;
  2.1567 +			}
  2.1568 +		} else {
  2.1569 +			/* Forcing 1000FD link up. */
  2.1570 +			current_link_up = 1;
  2.1571 +		}
  2.1572 +	}
  2.1573 +
  2.1574 +	tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  2.1575 +	tw32(MAC_MODE, tp->mac_mode);
  2.1576 +	tr32(MAC_MODE);
  2.1577 +	udelay(40);
  2.1578 +
  2.1579 +	tp->hw_status->status =
  2.1580 +		(SD_STATUS_UPDATED |
  2.1581 +		 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
  2.1582 +
  2.1583 +	for (i = 0; i < 100; i++) {
  2.1584 +		udelay(20);
  2.1585 +		tw32(MAC_STATUS,
  2.1586 +		     (MAC_STATUS_SYNC_CHANGED |
  2.1587 +		      MAC_STATUS_CFG_CHANGED));
  2.1588 +		tr32(MAC_STATUS);
  2.1589 +		udelay(40);
  2.1590 +		if ((tr32(MAC_STATUS) &
  2.1591 +		     (MAC_STATUS_SYNC_CHANGED |
  2.1592 +		      MAC_STATUS_CFG_CHANGED)) == 0)
  2.1593 +			break;
  2.1594 +	}
  2.1595 +
  2.1596 +	if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0)
  2.1597 +		current_link_up = 0;
  2.1598 +
  2.1599 +	if (current_link_up == 1) {
  2.1600 +		tp->link_config.active_speed = SPEED_1000;
  2.1601 +		tp->link_config.active_duplex = DUPLEX_FULL;
  2.1602 +	} else {
  2.1603 +		tp->link_config.active_speed = SPEED_INVALID;
  2.1604 +		tp->link_config.active_duplex = DUPLEX_INVALID;
  2.1605 +	}
  2.1606 +
  2.1607 +	if (current_link_up != netif_carrier_ok(tp->dev)) {
  2.1608 +		if (current_link_up)
  2.1609 +			netif_carrier_on(tp->dev);
  2.1610 +		else
  2.1611 +			netif_carrier_off(tp->dev);
  2.1612 +		tg3_link_report(tp);
  2.1613 +	} else {
  2.1614 +		u32 now_pause_cfg =
  2.1615 +			tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
  2.1616 +					 TG3_FLAG_TX_PAUSE);
  2.1617 +		if (orig_pause_cfg != now_pause_cfg ||
  2.1618 +		    orig_active_speed != tp->link_config.active_speed ||
  2.1619 +		    orig_active_duplex != tp->link_config.active_duplex)
  2.1620 +			tg3_link_report(tp);
  2.1621 +	}
  2.1622 +
  2.1623 +	if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) {
  2.1624 +		tw32(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY);
  2.1625 +		tr32(MAC_MODE);
  2.1626 +		udelay(40);
  2.1627 +		if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
  2.1628 +			tw32(MAC_MODE, tp->mac_mode);
  2.1629 +			tr32(MAC_MODE);
  2.1630 +			udelay(40);
  2.1631 +		}
  2.1632 +	}
  2.1633 +
  2.1634 +	return 0;
  2.1635 +}
  2.1636 +
  2.1637 +static int tg3_setup_phy(struct tg3 *tp)
  2.1638 +{
  2.1639 +	int err;
  2.1640 +
  2.1641 +	if (tp->phy_id == PHY_ID_SERDES) {
  2.1642 +		err = tg3_setup_fiber_phy(tp);
  2.1643 +	} else {
  2.1644 +		err = tg3_setup_copper_phy(tp);
  2.1645 +	}
  2.1646 +
  2.1647 +	if (tp->link_config.active_speed == SPEED_1000 &&
  2.1648 +	    tp->link_config.active_duplex == DUPLEX_HALF)
  2.1649 +		tw32(MAC_TX_LENGTHS,
  2.1650 +		     ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  2.1651 +		      (6 << TX_LENGTHS_IPG_SHIFT) |
  2.1652 +		      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  2.1653 +	else
  2.1654 +		tw32(MAC_TX_LENGTHS,
  2.1655 +		     ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  2.1656 +		      (6 << TX_LENGTHS_IPG_SHIFT) |
  2.1657 +		      (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  2.1658 +
  2.1659 +	return err;
  2.1660 +}
  2.1661 +
  2.1662 +/* Tigon3 never reports partial packet sends.  So we do not
  2.1663 + * need special logic to handle SKBs that have not had all
  2.1664 + * of their frags sent yet, like SunGEM does.
  2.1665 + */
  2.1666 +static void tg3_tx(struct tg3 *tp)
  2.1667 +{
  2.1668 +	u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
  2.1669 +	u32 sw_idx = tp->tx_cons;
  2.1670 +
  2.1671 +	while (sw_idx != hw_idx) {
  2.1672 +		struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
  2.1673 +		struct sk_buff *skb = ri->skb;
  2.1674 +		int i;
  2.1675 +
  2.1676 +		if (unlikely(skb == NULL))
  2.1677 +			BUG();
  2.1678 +
  2.1679 +		pci_unmap_single(tp->pdev,
  2.1680 +				 pci_unmap_addr(ri, mapping),
  2.1681 +				 (skb->len - skb->data_len),
  2.1682 +				 PCI_DMA_TODEVICE);
  2.1683 +
  2.1684 +		ri->skb = NULL;
  2.1685 +
  2.1686 +		sw_idx = NEXT_TX(sw_idx);
  2.1687 +
  2.1688 +		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2.1689 +			if (unlikely(sw_idx == hw_idx))
  2.1690 +				BUG();
  2.1691 +
  2.1692 +			ri = &tp->tx_buffers[sw_idx];
  2.1693 +			if (unlikely(ri->skb != NULL))
  2.1694 +				BUG();
  2.1695 +
  2.1696 +			pci_unmap_page(tp->pdev,
  2.1697 +				       pci_unmap_addr(ri, mapping),
  2.1698 +				       skb_shinfo(skb)->frags[i].size,
  2.1699 +				       PCI_DMA_TODEVICE);
  2.1700 +
  2.1701 +			sw_idx = NEXT_TX(sw_idx);
  2.1702 +		}
  2.1703 +
  2.1704 +		dev_kfree_skb_irq(skb);
  2.1705 +	}
  2.1706 +
  2.1707 +	tp->tx_cons = sw_idx;
  2.1708 +
  2.1709 +	if (netif_queue_stopped(tp->dev) &&
  2.1710 +	    (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
  2.1711 +		netif_wake_queue(tp->dev);
  2.1712 +}
  2.1713 +
  2.1714 +/* Returns size of skb allocated or < 0 on error.
  2.1715 + *
  2.1716 + * We only need to fill in the address because the other members
  2.1717 + * of the RX descriptor are invariant, see tg3_init_rings.
  2.1718 + *
  2.1719 + * Note the purposeful assymetry of cpu vs. chip accesses.  For
  2.1720 + * posting buffers we only dirty the first cache line of the RX
  2.1721 + * descriptor (containing the address).  Whereas for the RX status
  2.1722 + * buffers the cpu only reads the last cacheline of the RX descriptor
  2.1723 + * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
  2.1724 + */
  2.1725 +static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
  2.1726 +			    int src_idx, u32 dest_idx_unmasked)
  2.1727 +{
  2.1728 +	struct tg3_rx_buffer_desc *desc;
  2.1729 +	struct ring_info *map, *src_map;
  2.1730 +	struct sk_buff *skb;
  2.1731 +	dma_addr_t mapping;
  2.1732 +	int skb_size, dest_idx;
  2.1733 +
  2.1734 +	src_map = NULL;
  2.1735 +	switch (opaque_key) {
  2.1736 +	case RXD_OPAQUE_RING_STD:
  2.1737 +		dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  2.1738 +		desc = &tp->rx_std[dest_idx];
  2.1739 +		map = &tp->rx_std_buffers[dest_idx];
  2.1740 +		if (src_idx >= 0)
  2.1741 +			src_map = &tp->rx_std_buffers[src_idx];
  2.1742 +		skb_size = RX_PKT_BUF_SZ;
  2.1743 +		break;
  2.1744 +
  2.1745 +	case RXD_OPAQUE_RING_JUMBO:
  2.1746 +		dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  2.1747 +		desc = &tp->rx_jumbo[dest_idx];
  2.1748 +		map = &tp->rx_jumbo_buffers[dest_idx];
  2.1749 +		if (src_idx >= 0)
  2.1750 +			src_map = &tp->rx_jumbo_buffers[src_idx];
  2.1751 +		skb_size = RX_JUMBO_PKT_BUF_SZ;
  2.1752 +		break;
  2.1753 +
  2.1754 +	default:
  2.1755 +		return -EINVAL;
  2.1756 +	};
  2.1757 +
  2.1758 +	/* Do not overwrite any of the map or rp information
  2.1759 +	 * until we are sure we can commit to a new buffer.
  2.1760 +	 *
  2.1761 +	 * Callers depend upon this behavior and assume that
  2.1762 +	 * we leave everything unchanged if we fail.
  2.1763 +	 */
  2.1764 +	skb = dev_alloc_skb(skb_size);
  2.1765 +	if (skb == NULL)
  2.1766 +		return -ENOMEM;
  2.1767 +
  2.1768 +	skb->dev = tp->dev;
  2.1769 +	skb_reserve(skb, tp->rx_offset);
  2.1770 +
  2.1771 +	mapping = pci_map_single(tp->pdev, skb->data,
  2.1772 +				 skb_size - tp->rx_offset,
  2.1773 +				 PCI_DMA_FROMDEVICE);
  2.1774 +
  2.1775 +	map->skb = skb;
  2.1776 +	pci_unmap_addr_set(map, mapping, mapping);
  2.1777 +
  2.1778 +	if (src_map != NULL)
  2.1779 +		src_map->skb = NULL;
  2.1780 +
  2.1781 +	desc->addr_hi = ((u64)mapping >> 32);
  2.1782 +	desc->addr_lo = ((u64)mapping & 0xffffffff);
  2.1783 +
  2.1784 +	return skb_size;
  2.1785 +}
  2.1786 +
  2.1787 +/* We only need to move over in the address because the other
  2.1788 + * members of the RX descriptor are invariant.  See notes above
  2.1789 + * tg3_alloc_rx_skb for full details.
  2.1790 + */
  2.1791 +static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
  2.1792 +			   int src_idx, u32 dest_idx_unmasked)
  2.1793 +{
  2.1794 +	struct tg3_rx_buffer_desc *src_desc, *dest_desc;
  2.1795 +	struct ring_info *src_map, *dest_map;
  2.1796 +	int dest_idx;
  2.1797 +
  2.1798 +	switch (opaque_key) {
  2.1799 +	case RXD_OPAQUE_RING_STD:
  2.1800 +		dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  2.1801 +		dest_desc = &tp->rx_std[dest_idx];
  2.1802 +		dest_map = &tp->rx_std_buffers[dest_idx];
  2.1803 +		src_desc = &tp->rx_std[src_idx];
  2.1804 +		src_map = &tp->rx_std_buffers[src_idx];
  2.1805 +		break;
  2.1806 +
  2.1807 +	case RXD_OPAQUE_RING_JUMBO:
  2.1808 +		dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  2.1809 +		dest_desc = &tp->rx_jumbo[dest_idx];
  2.1810 +		dest_map = &tp->rx_jumbo_buffers[dest_idx];
  2.1811 +		src_desc = &tp->rx_jumbo[src_idx];
  2.1812 +		src_map = &tp->rx_jumbo_buffers[src_idx];
  2.1813 +		break;
  2.1814 +
  2.1815 +	default:
  2.1816 +		return;
  2.1817 +	};
  2.1818 +
  2.1819 +	dest_map->skb = src_map->skb;
  2.1820 +	pci_unmap_addr_set(dest_map, mapping,
  2.1821 +			   pci_unmap_addr(src_map, mapping));
  2.1822 +	dest_desc->addr_hi = src_desc->addr_hi;
  2.1823 +	dest_desc->addr_lo = src_desc->addr_lo;
  2.1824 +
  2.1825 +	src_map->skb = NULL;
  2.1826 +}
  2.1827 +
  2.1828 +#if TG3_VLAN_TAG_USED
  2.1829 +static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
  2.1830 +{
  2.1831 +	return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
  2.1832 +}
  2.1833 +#endif
  2.1834 +
  2.1835 +/* The RX ring scheme is composed of multiple rings which post fresh
  2.1836 + * buffers to the chip, and one special ring the chip uses to report
  2.1837 + * status back to the host.
  2.1838 + *
  2.1839 + * The special ring reports the status of received packets to the
  2.1840 + * host.  The chip does not write into the original descriptor the
  2.1841 + * RX buffer was obtained from.  The chip simply takes the original
  2.1842 + * descriptor as provided by the host, updates the status and length
  2.1843 + * field, then writes this into the next status ring entry.
  2.1844 + *
  2.1845 + * Each ring the host uses to post buffers to the chip is described
  2.1846 + * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
  2.1847 + * it is first placed into the on-chip ram.  When the packet's length
  2.1848 + * is known, it walks down the TG3_BDINFO entries to select the ring.
  2.1849 + * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
  2.1850 + * which is within the range of the new packet's length is chosen.
  2.1851 + *
  2.1852 + * The "seperate ring for rx status" scheme may sound queer, but it makes
  2.1853 + * sense from a cache coherency perspective.  If only the host writes
  2.1854 + * to the buffer post rings, and only the chip writes to the rx status
  2.1855 + * rings, then cache lines never move beyond shared-modified state.
  2.1856 + * If both the host and chip were to write into the same ring, cache line
  2.1857 + * eviction could occur since both entities want it in an exclusive state.
  2.1858 + */
  2.1859 +static int tg3_rx(struct tg3 *tp, int budget)
  2.1860 +{
  2.1861 +	u32 work_mask;
  2.1862 +	u32 rx_rcb_ptr = tp->rx_rcb_ptr;
  2.1863 +	u16 hw_idx, sw_idx;
  2.1864 +	int received;
  2.1865 +
  2.1866 +	hw_idx = tp->hw_status->idx[0].rx_producer;
  2.1867 +	sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE;
  2.1868 +	work_mask = 0;
  2.1869 +	received = 0;
  2.1870 +	while (sw_idx != hw_idx && budget > 0) {
  2.1871 +		struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
  2.1872 +		unsigned int len;
  2.1873 +		struct sk_buff *skb;
  2.1874 +		dma_addr_t dma_addr;
  2.1875 +		u32 opaque_key, desc_idx, *post_ptr;
  2.1876 +
  2.1877 +		desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  2.1878 +		opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  2.1879 +		if (opaque_key == RXD_OPAQUE_RING_STD) {
  2.1880 +			dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
  2.1881 +						  mapping);
  2.1882 +			skb = tp->rx_std_buffers[desc_idx].skb;
  2.1883 +			post_ptr = &tp->rx_std_ptr;
  2.1884 +		} else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  2.1885 +			dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
  2.1886 +						  mapping);
  2.1887 +			skb = tp->rx_jumbo_buffers[desc_idx].skb;
  2.1888 +			post_ptr = &tp->rx_jumbo_ptr;
  2.1889 +		}
  2.1890 +		else {
  2.1891 +			goto next_pkt_nopost;
  2.1892 +		}
  2.1893 +
  2.1894 +		work_mask |= opaque_key;
  2.1895 +
  2.1896 +		if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  2.1897 +		    (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
  2.1898 +		drop_it:
  2.1899 +			tg3_recycle_rx(tp, opaque_key,
  2.1900 +				       desc_idx, *post_ptr);
  2.1901 +		drop_it_no_recycle:
  2.1902 +			/* Other statistics kept track of by card. */
  2.1903 +			tp->net_stats.rx_dropped++;
  2.1904 +			goto next_pkt;
  2.1905 +		}
  2.1906 +
  2.1907 +		len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
  2.1908 +
  2.1909 +		if (len > RX_COPY_THRESHOLD) {
  2.1910 +			int skb_size;
  2.1911 +
  2.1912 +			skb_size = tg3_alloc_rx_skb(tp, opaque_key,
  2.1913 +						    desc_idx, *post_ptr);
  2.1914 +			if (skb_size < 0)
  2.1915 +				goto drop_it;
  2.1916 +
  2.1917 +			pci_unmap_single(tp->pdev, dma_addr,
  2.1918 +					 skb_size - tp->rx_offset,
  2.1919 +					 PCI_DMA_FROMDEVICE);
  2.1920 +
  2.1921 +			skb_put(skb, len);
  2.1922 +		} else {
  2.1923 +			struct sk_buff *copy_skb;
  2.1924 +
  2.1925 +			tg3_recycle_rx(tp, opaque_key,
  2.1926 +				       desc_idx, *post_ptr);
  2.1927 +
  2.1928 +			copy_skb = dev_alloc_skb(len + 2);
  2.1929 +			if (copy_skb == NULL)
  2.1930 +				goto drop_it_no_recycle;
  2.1931 +
  2.1932 +			copy_skb->dev = tp->dev;
  2.1933 +			skb_reserve(copy_skb, 2);
  2.1934 +			skb_put(copy_skb, len);
  2.1935 +			pci_dma_sync_single(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  2.1936 +			memcpy(copy_skb->data, skb->data, len);
  2.1937 +
  2.1938 +			/* We'll reuse the original ring buffer. */
  2.1939 +			skb = copy_skb;
  2.1940 +		}
  2.1941 +
  2.1942 +		if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
  2.1943 +		    (desc->type_flags & RXD_FLAG_TCPUDP_CSUM)) {
  2.1944 +			skb->csum = htons((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  2.1945 +					  >> RXD_TCPCSUM_SHIFT);
  2.1946 +			skb->ip_summed = CHECKSUM_HW;
  2.1947 +		} else {
  2.1948 +			skb->ip_summed = CHECKSUM_NONE;
  2.1949 +		}
  2.1950 +
  2.1951 +		skb->protocol = eth_type_trans(skb, tp->dev);
  2.1952 +#if TG3_VLAN_TAG_USED
  2.1953 +		if (tp->vlgrp != NULL &&
  2.1954 +		    desc->type_flags & RXD_FLAG_VLAN) {
  2.1955 +			tg3_vlan_rx(tp, skb,
  2.1956 +				    desc->err_vlan & RXD_VLAN_MASK);
  2.1957 +		} else
  2.1958 +#endif
  2.1959 +
  2.1960 +#ifdef NAPI
  2.1961 +			netif_receive_skb(skb);
  2.1962 +#else
  2.1963 +		        netif_rx(skb);
  2.1964 +#endif
  2.1965 +		tp->dev->last_rx = jiffies;
  2.1966 +		received++;
  2.1967 +		budget--;
  2.1968 +
  2.1969 +next_pkt:
  2.1970 +		(*post_ptr)++;
  2.1971 +next_pkt_nopost:
  2.1972 +		rx_rcb_ptr++;
  2.1973 +		sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE;
  2.1974 +	}
  2.1975 +
  2.1976 +	/* ACK the status ring. */
  2.1977 +	tp->rx_rcb_ptr = rx_rcb_ptr;
  2.1978 +	tw32_mailbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW,
  2.1979 +		     (rx_rcb_ptr % TG3_RX_RCB_RING_SIZE));
  2.1980 +	if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.1981 +		tr32(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW);
  2.1982 +
  2.1983 +	/* Refill RX ring(s). */
  2.1984 +	if (work_mask & RXD_OPAQUE_RING_STD) {
  2.1985 +		sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
  2.1986 +		tw32_mailbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
  2.1987 +			     sw_idx);
  2.1988 +		if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.1989 +			tr32(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW);
  2.1990 +	}
  2.1991 +	if (work_mask & RXD_OPAQUE_RING_JUMBO) {
  2.1992 +		sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
  2.1993 +		tw32_mailbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
  2.1994 +			     sw_idx);
  2.1995 +		if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.1996 +			tr32(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW);
  2.1997 +	}
  2.1998 +
  2.1999 +	return received;
  2.2000 +}
  2.2001 +
  2.2002 +static int tg3_poll(struct net_device *netdev, int *budget)
  2.2003 +{
  2.2004 +	struct tg3 *tp = netdev->priv;
  2.2005 +	struct tg3_hw_status *sblk = tp->hw_status;
  2.2006 +	unsigned long flags;
  2.2007 +	int done;
  2.2008 +#ifdef NAPI
  2.2009 +	spin_lock_irqsave(&tp->lock, flags);
  2.2010 +#endif
  2.2011 +	if (!(tp->tg3_flags &
  2.2012 +	      (TG3_FLAG_USE_LINKCHG_REG |
  2.2013 +	       TG3_FLAG_POLL_SERDES))) {
  2.2014 +		if (sblk->status & SD_STATUS_LINK_CHG) {
  2.2015 +			sblk->status = SD_STATUS_UPDATED |
  2.2016 +				(sblk->status & ~SD_STATUS_LINK_CHG);
  2.2017 +			tg3_setup_phy(tp);
  2.2018 +		}
  2.2019 +	}
  2.2020 +
  2.2021 +	if (sblk->idx[0].tx_consumer != tp->tx_cons) {
  2.2022 +		spin_lock(&tp->tx_lock);
  2.2023 +		tg3_tx(tp);
  2.2024 +		spin_unlock(&tp->tx_lock);
  2.2025 +	}
  2.2026 +
  2.2027 +	done = 1;
  2.2028 +	if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
  2.2029 +		int orig_budget = *budget;
  2.2030 +		int work_done;
  2.2031 +
  2.2032 +#ifdef NAPI
  2.2033 +		if (orig_budget > netdev->quota)
  2.2034 +			orig_budget = netdev->quota;
  2.2035 +
  2.2036 +		work_done = tg3_rx(tp, orig_budget);
  2.2037 +		
  2.2038 +		*budget -= work_done;
  2.2039 +		netdev->quota -= work_done;
  2.2040 +
  2.2041 +
  2.2042 +		if (work_done >= orig_budget)
  2.2043 +			done = 0;
  2.2044 +#else
  2.2045 +		work_done = tg3_rx(tp, 1000);
  2.2046 +#endif
  2.2047 +	}
  2.2048 +#ifdef NAPI
  2.2049 +	if (done) {
  2.2050 +		netif_rx_complete(netdev);
  2.2051 +		tg3_enable_ints(tp);
  2.2052 +	}
  2.2053 +
  2.2054 +	spin_unlock_irqrestore(&tp->lock, flags);
  2.2055 +#endif
  2.2056 +	return (done ? 0 : 1);
  2.2057 +}
  2.2058 +
  2.2059 +static inline unsigned int tg3_has_work(struct net_device *dev, struct tg3 *tp)
  2.2060 +{
  2.2061 +	struct tg3_hw_status *sblk = tp->hw_status;
  2.2062 +	unsigned int work_exists = 0;
  2.2063 +
  2.2064 +	if (!(tp->tg3_flags &
  2.2065 +	      (TG3_FLAG_USE_LINKCHG_REG |
  2.2066 +	       TG3_FLAG_POLL_SERDES))) {
  2.2067 +		if (sblk->status & SD_STATUS_LINK_CHG)
  2.2068 +			work_exists = 1;
  2.2069 +	}
  2.2070 +	if (sblk->idx[0].tx_consumer != tp->tx_cons ||
  2.2071 +	    sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
  2.2072 +		work_exists = 1;
  2.2073 +
  2.2074 +	return work_exists;
  2.2075 +}
  2.2076 +
  2.2077 +static void tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  2.2078 +{
  2.2079 +	struct net_device *dev = dev_id;
  2.2080 +	struct tg3 *tp = dev->priv;
  2.2081 +	struct tg3_hw_status *sblk = tp->hw_status;
  2.2082 +	unsigned long flags;
  2.2083 +
  2.2084 +	spin_lock_irqsave(&tp->lock, flags);
  2.2085 +#if NAPI
  2.2086 +	if (sblk->status & SD_STATUS_UPDATED) {
  2.2087 +		tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  2.2088 +			     0x00000001);
  2.2089 +		tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
  2.2090 +		sblk->status &= ~SD_STATUS_UPDATED;
  2.2091 +
  2.2092 +		if (likely(tg3_has_work(dev, tp)))
  2.2093 +			netif_rx_schedule(dev);
  2.2094 +		else {
  2.2095 +			tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  2.2096 +			     	0x00000000);
  2.2097 +			tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
  2.2098 +		}
  2.2099 +	}
  2.2100 +#else
  2.2101 +	{
  2.2102 +	  int budget = 1000;
  2.2103 +	  tg3_poll( dev, &budget );
  2.2104 +	}
  2.2105 +#endif
  2.2106 +
  2.2107 +	spin_unlock_irqrestore(&tp->lock, flags);
  2.2108 +}
  2.2109 +
  2.2110 +static void tg3_init_rings(struct tg3 *);
  2.2111 +static int tg3_init_hw(struct tg3 *);
  2.2112 +
  2.2113 +static void tg3_tx_timeout(struct net_device *dev)
  2.2114 +{
  2.2115 +	struct tg3 *tp = dev->priv;
  2.2116 +
  2.2117 +	printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
  2.2118 +	       dev->name);
  2.2119 +
  2.2120 +	spin_lock_irq(&tp->lock);
  2.2121 +	spin_lock(&tp->tx_lock);
  2.2122 +
  2.2123 +	tg3_halt(tp);
  2.2124 +	tg3_init_rings(tp);
  2.2125 +	tg3_init_hw(tp);
  2.2126 +
  2.2127 +	spin_unlock(&tp->tx_lock);
  2.2128 +	spin_unlock_irq(&tp->lock);
  2.2129 +
  2.2130 +	netif_wake_queue(dev);
  2.2131 +}
  2.2132 +
  2.2133 +#if !PCI_DMA_BUS_IS_PHYS
  2.2134 +static void tg3_set_txd_addr(struct tg3 *tp, int entry, dma_addr_t mapping)
  2.2135 +{
  2.2136 +	if (tp->tg3_flags & TG3_FLAG_HOST_TXDS) {
  2.2137 +		struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
  2.2138 +
  2.2139 +		txd->addr_hi = ((u64) mapping >> 32);
  2.2140 +		txd->addr_lo = ((u64) mapping & 0xffffffff);
  2.2141 +	} else {
  2.2142 +		unsigned long txd;
  2.2143 +
  2.2144 +		txd = (tp->regs +
  2.2145 +		       NIC_SRAM_WIN_BASE +
  2.2146 +		       NIC_SRAM_TX_BUFFER_DESC);
  2.2147 +		txd += (entry * TXD_SIZE);
  2.2148 +
  2.2149 +		if (sizeof(dma_addr_t) != sizeof(u32))
  2.2150 +			writel(((u64) mapping >> 32),
  2.2151 +			       txd + TXD_ADDR + TG3_64BIT_REG_HIGH);
  2.2152 +
  2.2153 +		writel(((u64) mapping & 0xffffffff),
  2.2154 +		       txd + TXD_ADDR + TG3_64BIT_REG_LOW);
  2.2155 +	}
  2.2156 +}
  2.2157 +#endif
  2.2158 +
  2.2159 +static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
  2.2160 +
  2.2161 +static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
  2.2162 +				       u32 guilty_entry, int guilty_len,
  2.2163 +				       u32 last_plus_one, u32 *start, u32 mss)
  2.2164 +{
  2.2165 +	dma_addr_t new_addr;
  2.2166 +	u32 entry = *start;
  2.2167 +	int i;
  2.2168 +
  2.2169 +#if !PCI_DMA_BUS_IS_PHYS
  2.2170 +	/* IOMMU, just map the guilty area again which is guarenteed to
  2.2171 +	 * use different addresses.
  2.2172 +	 */
  2.2173 +
  2.2174 +	i = 0;
  2.2175 +	while (entry != guilty_entry) {
  2.2176 +		entry = NEXT_TX(entry);
  2.2177 +		i++;
  2.2178 +	}
  2.2179 +	if (i == 0) {
  2.2180 +		new_addr = pci_map_single(tp->pdev, skb->data, guilty_len,
  2.2181 +					  PCI_DMA_TODEVICE);
  2.2182 +	} else {
  2.2183 +		skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
  2.2184 +
  2.2185 +		new_addr = pci_map_page(tp->pdev,
  2.2186 +					frag->page, frag->page_offset,
  2.2187 +					guilty_len, PCI_DMA_TODEVICE);
  2.2188 +	}
  2.2189 +	pci_unmap_single(tp->pdev, pci_unmap_addr(&tp->tx_buffers[guilty_entry],
  2.2190 +						  mapping),
  2.2191 +			 guilty_len, PCI_DMA_TODEVICE);
  2.2192 +	tg3_set_txd_addr(tp, guilty_entry, new_addr);
  2.2193 +	pci_unmap_addr_set(&tp->tx_buffers[guilty_entry], mapping,
  2.2194 +			   new_addr);
  2.2195 +	*start = last_plus_one;
  2.2196 +#else
  2.2197 +	/* Oh well, no IOMMU, have to allocate a whole new SKB. */
  2.2198 +	struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
  2.2199 +
  2.2200 +	if (!new_skb) {
  2.2201 +		dev_kfree_skb(skb);
  2.2202 +		return -1;
  2.2203 +	}
  2.2204 +
  2.2205 +	/* NOTE: Broadcom's driver botches this case up really bad.
  2.2206 +	 *       This is especially true if any of the frag pages
  2.2207 +	 *       are in highmem.  It will instantly oops in that case.
  2.2208 +	 */
  2.2209 +
  2.2210 +	/* New SKB is guarenteed to be linear. */
  2.2211 +	entry = *start;
  2.2212 +	new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
  2.2213 +				  PCI_DMA_TODEVICE);
  2.2214 +	tg3_set_txd(tp, entry, new_addr, new_skb->len,
  2.2215 +		    (skb->ip_summed == CHECKSUM_HW) ?
  2.2216 +		    TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
  2.2217 +	*start = NEXT_TX(entry);
  2.2218 +
  2.2219 +	/* Now clean up the sw ring entries. */
  2.2220 +	i = 0;
  2.2221 +	while (entry != last_plus_one) {
  2.2222 +		int len;
  2.2223 +
  2.2224 +		if (i == 0)
  2.2225 +			len = skb->len - skb->data_len;
  2.2226 +		else
  2.2227 +			len = skb_shinfo(skb)->frags[i-1].size;
  2.2228 +		pci_unmap_single(tp->pdev,
  2.2229 +				 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
  2.2230 +				 len, PCI_DMA_TODEVICE);
  2.2231 +		if (i == 0) {
  2.2232 +			tp->tx_buffers[entry].skb = new_skb;
  2.2233 +			pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
  2.2234 +		} else {
  2.2235 +			tp->tx_buffers[entry].skb = NULL;
  2.2236 +		}
  2.2237 +		entry = NEXT_TX(entry);
  2.2238 +	}
  2.2239 +
  2.2240 +	dev_kfree_skb(skb);
  2.2241 +#endif
  2.2242 +
  2.2243 +	return 0;
  2.2244 +}
  2.2245 +
  2.2246 +static void tg3_set_txd(struct tg3 *tp, int entry,
  2.2247 +			dma_addr_t mapping, int len, u32 flags,
  2.2248 +			u32 mss_and_is_end)
  2.2249 +{
  2.2250 +	int is_end = (mss_and_is_end & 0x1);
  2.2251 +	u32 mss = (mss_and_is_end >> 1);
  2.2252 +	u32 vlan_tag = 0;
  2.2253 +
  2.2254 +	if (is_end)
  2.2255 +		flags |= TXD_FLAG_END;
  2.2256 +	if (flags & TXD_FLAG_VLAN) {
  2.2257 +		vlan_tag = flags >> 16;
  2.2258 +		flags &= 0xffff;
  2.2259 +	}
  2.2260 +	vlan_tag |= (mss << TXD_MSS_SHIFT);
  2.2261 +	if (tp->tg3_flags & TG3_FLAG_HOST_TXDS) {
  2.2262 +		struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
  2.2263 +
  2.2264 +		txd->addr_hi = ((u64) mapping >> 32);
  2.2265 +		txd->addr_lo = ((u64) mapping & 0xffffffff);
  2.2266 +		txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
  2.2267 +		txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
  2.2268 +	} else {
  2.2269 +		struct tx_ring_info *txr = &tp->tx_buffers[entry];
  2.2270 +		unsigned long txd;
  2.2271 +
  2.2272 +		txd = (tp->regs +
  2.2273 +		       NIC_SRAM_WIN_BASE +
  2.2274 +		       NIC_SRAM_TX_BUFFER_DESC);
  2.2275 +		txd += (entry * TXD_SIZE);
  2.2276 +
  2.2277 +		/* Save some PIOs */
  2.2278 +		if (sizeof(dma_addr_t) != sizeof(u32))
  2.2279 +			writel(((u64) mapping >> 32),
  2.2280 +			       txd + TXD_ADDR + TG3_64BIT_REG_HIGH);
  2.2281 +
  2.2282 +		writel(((u64) mapping & 0xffffffff),
  2.2283 +		       txd + TXD_ADDR + TG3_64BIT_REG_LOW);
  2.2284 +		writel(len << TXD_LEN_SHIFT | flags, txd + TXD_LEN_FLAGS);
  2.2285 +		if (txr->prev_vlan_tag != vlan_tag) {
  2.2286 +			writel(vlan_tag << TXD_VLAN_TAG_SHIFT, txd + TXD_VLAN_TAG);
  2.2287 +			txr->prev_vlan_tag = vlan_tag;
  2.2288 +		}
  2.2289 +	}
  2.2290 +}
  2.2291 +
  2.2292 +static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
  2.2293 +{
  2.2294 +	u32 base = (u32) mapping & 0xffffffff;
  2.2295 +
  2.2296 +	return ((base > 0xffffdcc0) &&
  2.2297 +		((u64) mapping >> 32) == 0 &&
  2.2298 +		(base + len + 8 < base));
  2.2299 +}
  2.2300 +
  2.2301 +static int tg3_start_xmit_4gbug(struct sk_buff *skb, struct net_device *dev)
  2.2302 +{
  2.2303 +	struct tg3 *tp = dev->priv;
  2.2304 +	dma_addr_t mapping;
  2.2305 +	unsigned int i;
  2.2306 +	u32 len, entry, base_flags, mss;
  2.2307 +	int would_hit_hwbug;
  2.2308 +	unsigned long flags;
  2.2309 +
  2.2310 +	len = (skb->len - skb->data_len);
  2.2311 +
  2.2312 +	/* No BH disabling for tx_lock here.  We are running in BH disabled
  2.2313 +	 * context and TX reclaim runs via tp->poll inside of a software
  2.2314 +	 * interrupt.  Rejoice!
  2.2315 +	 *
  2.2316 +	 * Actually, things are not so simple.  If we are to take a hw
  2.2317 +	 * IRQ here, we can deadlock, consider:
  2.2318 +	 *
  2.2319 +	 *       CPU1		CPU2
  2.2320 +	 *   tg3_start_xmit
  2.2321 +	 *   take tp->tx_lock
  2.2322 +	 *			tg3_timer
  2.2323 +	 *			take tp->lock
  2.2324 +	 *   tg3_interrupt
  2.2325 +	 *   spin on tp->lock
  2.2326 +	 *			spin on tp->tx_lock
  2.2327 +	 *
  2.2328 +	 * So we really do need to disable interrupts when taking
  2.2329 +	 * tx_lock here.
  2.2330 +	 */
  2.2331 +	spin_lock_irqsave(&tp->tx_lock, flags);
  2.2332 +
  2.2333 +	/* This is a hard error, log it. */
  2.2334 +	if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
  2.2335 +		netif_stop_queue(dev);
  2.2336 +		spin_unlock_irqrestore(&tp->tx_lock, flags);
  2.2337 +		printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
  2.2338 +		       dev->name);
  2.2339 +		return 1;
  2.2340 +	}
  2.2341 +
  2.2342 +	entry = tp->tx_prod;
  2.2343 +	base_flags = 0;
  2.2344 +	if (skb->ip_summed == CHECKSUM_HW)
  2.2345 +		base_flags |= TXD_FLAG_TCPUDP_CSUM;
  2.2346 +#if TG3_DO_TSO != 0
  2.2347 +	if ((mss = skb_shinfo(skb)->tso_size) != 0)
  2.2348 +		base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  2.2349 +			       TXD_FLAG_CPU_POST_DMA);
  2.2350 +#else
  2.2351 +	mss = 0;
  2.2352 +#endif
  2.2353 +#if TG3_VLAN_TAG_USED
  2.2354 +	if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  2.2355 +		base_flags |= (TXD_FLAG_VLAN |
  2.2356 +			       (vlan_tx_tag_get(skb) << 16));
  2.2357 +#endif
  2.2358 +
  2.2359 +	/* Queue skb data, a.k.a. the main skb fragment. */
  2.2360 +	mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  2.2361 +
  2.2362 +	tp->tx_buffers[entry].skb = skb;
  2.2363 +	pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  2.2364 +
  2.2365 +	would_hit_hwbug = 0;
  2.2366 +
  2.2367 +	if (tg3_4g_overflow_test(mapping, len))
  2.2368 +		would_hit_hwbug = entry + 1;
  2.2369 +
  2.2370 +	tg3_set_txd(tp, entry, mapping, len, base_flags,
  2.2371 +		    (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  2.2372 +
  2.2373 +	entry = NEXT_TX(entry);
  2.2374 +
  2.2375 +	/* Now loop through additional data fragments, and queue them. */
  2.2376 +	if (skb_shinfo(skb)->nr_frags > 0) {
  2.2377 +		unsigned int i, last;
  2.2378 +
  2.2379 +		last = skb_shinfo(skb)->nr_frags - 1;
  2.2380 +		for (i = 0; i <= last; i++) {
  2.2381 +			skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2.2382 +
  2.2383 +			len = frag->size;
  2.2384 +			mapping = pci_map_page(tp->pdev,
  2.2385 +					       frag->page,
  2.2386 +					       frag->page_offset,
  2.2387 +					       len, PCI_DMA_TODEVICE);
  2.2388 +
  2.2389 +			tp->tx_buffers[entry].skb = NULL;
  2.2390 +			pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  2.2391 +
  2.2392 +			if (tg3_4g_overflow_test(mapping, len)) {
  2.2393 +				/* Only one should match. */
  2.2394 +				if (would_hit_hwbug)
  2.2395 +					BUG();
  2.2396 +				would_hit_hwbug = entry + 1;
  2.2397 +			}
  2.2398 +
  2.2399 +			tg3_set_txd(tp, entry, mapping, len,
  2.2400 +				    base_flags, (i == last) | (mss << 1));
  2.2401 +
  2.2402 +			entry = NEXT_TX(entry);
  2.2403 +		}
  2.2404 +	}
  2.2405 +
  2.2406 +	if (would_hit_hwbug) {
  2.2407 +		u32 last_plus_one = entry;
  2.2408 +		u32 start;
  2.2409 +		unsigned int len = 0;
  2.2410 +
  2.2411 +		would_hit_hwbug -= 1;
  2.2412 +		entry = entry - 1 - skb_shinfo(skb)->nr_frags;
  2.2413 +		entry &= (TG3_TX_RING_SIZE - 1);
  2.2414 +		start = entry;
  2.2415 +		i = 0;
  2.2416 +		while (entry != last_plus_one) {
  2.2417 +			if (i == 0)
  2.2418 +				len = skb->len - skb->data_len;
  2.2419 +			else
  2.2420 +				len = skb_shinfo(skb)->frags[i-1].size;
  2.2421 +
  2.2422 +			if (entry == would_hit_hwbug)
  2.2423 +				break;
  2.2424 +
  2.2425 +			i++;
  2.2426 +			entry = NEXT_TX(entry);
  2.2427 +
  2.2428 +		}
  2.2429 +
  2.2430 +		/* If the workaround fails due to memory/mapping
  2.2431 +		 * failure, silently drop this packet.
  2.2432 +		 */
  2.2433 +		if (tigon3_4gb_hwbug_workaround(tp, skb,
  2.2434 +						entry, len,
  2.2435 +						last_plus_one,
  2.2436 +						&start, mss))
  2.2437 +			goto out_unlock;
  2.2438 +
  2.2439 +		entry = start;
  2.2440 +	}
  2.2441 +
  2.2442 +	/* Packets are ready, update Tx producer idx local and on card. */
  2.2443 +	if (tp->tg3_flags & TG3_FLAG_HOST_TXDS) {
  2.2444 +		tw32_mailbox((MAILBOX_SNDHOST_PROD_IDX_0 +
  2.2445 +			      TG3_64BIT_REG_LOW), entry);
  2.2446 +		if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
  2.2447 +			tw32_mailbox((MAILBOX_SNDHOST_PROD_IDX_0 +
  2.2448 +				      TG3_64BIT_REG_LOW), entry);
  2.2449 +		if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.2450 +			tr32(MAILBOX_SNDHOST_PROD_IDX_0 +
  2.2451 +			     TG3_64BIT_REG_LOW);
  2.2452 +	} else {
  2.2453 +		/* First, make sure tg3 sees last descriptor fully
  2.2454 +		 * in SRAM.
  2.2455 +		 */
  2.2456 +		if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.2457 +			tr32(MAILBOX_SNDNIC_PROD_IDX_0 +
  2.2458 +			     TG3_64BIT_REG_LOW);
  2.2459 +
  2.2460 +		tw32_mailbox((MAILBOX_SNDNIC_PROD_IDX_0 +
  2.2461 +			      TG3_64BIT_REG_LOW), entry);
  2.2462 +		if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
  2.2463 +			tw32_mailbox((MAILBOX_SNDNIC_PROD_IDX_0 +
  2.2464 +				      TG3_64BIT_REG_LOW), entry);
  2.2465 +
  2.2466 +		/* Now post the mailbox write itself.  */
  2.2467 +		if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.2468 +			tr32(MAILBOX_SNDNIC_PROD_IDX_0 +
  2.2469 +			     TG3_64BIT_REG_LOW);
  2.2470 +	}
  2.2471 +
  2.2472 +	tp->tx_prod = entry;
  2.2473 +	if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
  2.2474 +		netif_stop_queue(dev);
  2.2475 +
  2.2476 +out_unlock:
  2.2477 +	spin_unlock_irqrestore(&tp->tx_lock, flags);
  2.2478 +
  2.2479 +	dev->trans_start = jiffies;
  2.2480 +
  2.2481 +	return 0;
  2.2482 +}
  2.2483 +
  2.2484 +static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
  2.2485 +{
  2.2486 +	struct tg3 *tp = dev->priv;
  2.2487 +	dma_addr_t mapping;
  2.2488 +	u32 len, entry, base_flags, mss;
  2.2489 +	unsigned long flags;
  2.2490 +
  2.2491 +	len = (skb->len - skb->data_len);
  2.2492 +
  2.2493 +	/* No BH disabling for tx_lock here.  We are running in BH disabled
  2.2494 +	 * context and TX reclaim runs via tp->poll inside of a software
  2.2495 +	 * interrupt.  Rejoice!
  2.2496 +	 *
  2.2497 +	 * Actually, things are not so simple.  If we are to take a hw
  2.2498 +	 * IRQ here, we can deadlock, consider:
  2.2499 +	 *
  2.2500 +	 *       CPU1		CPU2
  2.2501 +	 *   tg3_start_xmit
  2.2502 +	 *   take tp->tx_lock
  2.2503 +	 *			tg3_timer
  2.2504 +	 *			take tp->lock
  2.2505 +	 *   tg3_interrupt
  2.2506 +	 *   spin on tp->lock
  2.2507 +	 *			spin on tp->tx_lock
  2.2508 +	 *
  2.2509 +	 * So we really do need to disable interrupts when taking
  2.2510 +	 * tx_lock here.
  2.2511 +	 */
  2.2512 +	spin_lock_irqsave(&tp->tx_lock, flags);
  2.2513 +
  2.2514 +	/* This is a hard error, log it. */
  2.2515 +	if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
  2.2516 +		netif_stop_queue(dev);
  2.2517 +		spin_unlock_irqrestore(&tp->tx_lock, flags);
  2.2518 +		printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
  2.2519 +		       dev->name);
  2.2520 +		return 1;
  2.2521 +	}
  2.2522 +
  2.2523 +	entry = tp->tx_prod;
  2.2524 +	base_flags = 0;
  2.2525 +	if (skb->ip_summed == CHECKSUM_HW)
  2.2526 +		base_flags |= TXD_FLAG_TCPUDP_CSUM;
  2.2527 +#if TG3_DO_TSO != 0
  2.2528 +	if ((mss = skb_shinfo(skb)->tso_size) != 0)
  2.2529 +		base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  2.2530 +			       TXD_FLAG_CPU_POST_DMA);
  2.2531 +#else
  2.2532 +	mss = 0;
  2.2533 +#endif
  2.2534 +#if TG3_VLAN_TAG_USED
  2.2535 +	if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  2.2536 +		base_flags |= (TXD_FLAG_VLAN |
  2.2537 +			       (vlan_tx_tag_get(skb) << 16));
  2.2538 +#endif
  2.2539 +
  2.2540 +	/* Queue skb data, a.k.a. the main skb fragment. */
  2.2541 +	mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  2.2542 +
  2.2543 +	tp->tx_buffers[entry].skb = skb;
  2.2544 +	pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  2.2545 +
  2.2546 +	tg3_set_txd(tp, entry, mapping, len, base_flags,
  2.2547 +		    (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  2.2548 +
  2.2549 +	entry = NEXT_TX(entry);
  2.2550 +
  2.2551 +	/* Now loop through additional data fragments, and queue them. */
  2.2552 +	if (skb_shinfo(skb)->nr_frags > 0) {
  2.2553 +		unsigned int i, last;
  2.2554 +
  2.2555 +		last = skb_shinfo(skb)->nr_frags - 1;
  2.2556 +		for (i = 0; i <= last; i++) {
  2.2557 +			skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2.2558 +
  2.2559 +
  2.2560 +			len = frag->size;
  2.2561 +			mapping = pci_map_page(tp->pdev,
  2.2562 +					       frag->page,
  2.2563 +					       frag->page_offset,
  2.2564 +					       len, PCI_DMA_TODEVICE);
  2.2565 +
  2.2566 +			tp->tx_buffers[entry].skb = NULL;
  2.2567 +			pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  2.2568 +
  2.2569 +			tg3_set_txd(tp, entry, mapping, len,
  2.2570 +				    base_flags, (i == last) | (mss << 1));
  2.2571 +
  2.2572 +			entry = NEXT_TX(entry);
  2.2573 +		}
  2.2574 +	}
  2.2575 +
  2.2576 +	/* Packets are ready, update Tx producer idx local and on card.
  2.2577 +	 * We know this is not a 5700 (by virtue of not being a chip
  2.2578 +	 * requiring the 4GB overflow workaround) so we can safely omit
  2.2579 +	 * the double-write bug tests.
  2.2580 +	 */
  2.2581 +	if (tp->tg3_flags & TG3_FLAG_HOST_TXDS) {
  2.2582 +		tw32_mailbox((MAILBOX_SNDHOST_PROD_IDX_0 +
  2.2583 +			      TG3_64BIT_REG_LOW), entry);
  2.2584 +		if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.2585 +			tr32(MAILBOX_SNDHOST_PROD_IDX_0 +
  2.2586 +			     TG3_64BIT_REG_LOW);
  2.2587 +	} else {
  2.2588 +		/* First, make sure tg3 sees last descriptor fully
  2.2589 +		 * in SRAM.
  2.2590 +		 */
  2.2591 +		if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.2592 +			tr32(MAILBOX_SNDNIC_PROD_IDX_0 +
  2.2593 +			     TG3_64BIT_REG_LOW);
  2.2594 +
  2.2595 +		tw32_mailbox((MAILBOX_SNDNIC_PROD_IDX_0 +
  2.2596 +			      TG3_64BIT_REG_LOW), entry);
  2.2597 +
  2.2598 +		/* Now post the mailbox write itself.  */
  2.2599 +		if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.2600 +			tr32(MAILBOX_SNDNIC_PROD_IDX_0 +
  2.2601 +			     TG3_64BIT_REG_LOW);
  2.2602 +	}
  2.2603 +
  2.2604 +	tp->tx_prod = entry;
  2.2605 +	if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
  2.2606 +		netif_stop_queue(dev);
  2.2607 +
  2.2608 +	spin_unlock_irqrestore(&tp->tx_lock, flags);
  2.2609 +
  2.2610 +	dev->trans_start = jiffies;
  2.2611 +
  2.2612 +	return 0;
  2.2613 +}
  2.2614 +
  2.2615 +static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
  2.2616 +			       int new_mtu)
  2.2617 +{
  2.2618 +	dev->mtu = new_mtu;
  2.2619 +
  2.2620 +	if (new_mtu > ETH_DATA_LEN)
  2.2621 +		tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
  2.2622 +	else
  2.2623 +		tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE;
  2.2624 +}
  2.2625 +
  2.2626 +static int tg3_change_mtu(struct net_device *dev, int new_mtu)
  2.2627 +{
  2.2628 +	struct tg3 *tp = dev->priv;
  2.2629 +
  2.2630 +	if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU)
  2.2631 +		return -EINVAL;
  2.2632 +
  2.2633 +	if (!netif_running(dev)) {
  2.2634 +		/* We'll just catch it later when the
  2.2635 +		 * device is up'd.
  2.2636 +		 */
  2.2637 +		tg3_set_mtu(dev, tp, new_mtu);
  2.2638 +		return 0;
  2.2639 +	}
  2.2640 +
  2.2641 +	spin_lock_irq(&tp->lock);
  2.2642 +	spin_lock(&tp->tx_lock);
  2.2643 +
  2.2644 +	tg3_halt(tp);
  2.2645 +
  2.2646 +	tg3_set_mtu(dev, tp, new_mtu);
  2.2647 +
  2.2648 +	tg3_init_rings(tp);
  2.2649 +	tg3_init_hw(tp);
  2.2650 +
  2.2651 +	spin_unlock(&tp->tx_lock);
  2.2652 +	spin_unlock_irq(&tp->lock);
  2.2653 +
  2.2654 +	return 0;
  2.2655 +}
  2.2656 +
  2.2657 +/* Free up pending packets in all rx/tx rings.
  2.2658 + *
  2.2659 + * The chip has been shut down and the driver detached from
  2.2660 + * the networking, so no interrupts or new tx packets will
  2.2661 + * end up in the driver.  tp->{tx,}lock is not held and we are not
  2.2662 + * in an interrupt context and thus may sleep.
  2.2663 + */
  2.2664 +static void tg3_free_rings(struct tg3 *tp)
  2.2665 +{
  2.2666 +	struct ring_info *rxp;
  2.2667 +	int i;
  2.2668 +
  2.2669 +	for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  2.2670 +		rxp = &tp->rx_std_buffers[i];
  2.2671 +
  2.2672 +		if (rxp->skb == NULL)
  2.2673 +			continue;
  2.2674 +		pci_unmap_single(tp->pdev,
  2.2675 +				 pci_unmap_addr(rxp, mapping),
  2.2676 +				 RX_PKT_BUF_SZ - tp->rx_offset,
  2.2677 +				 PCI_DMA_FROMDEVICE);
  2.2678 +		dev_kfree_skb_any(rxp->skb);
  2.2679 +		rxp->skb = NULL;
  2.2680 +	}
  2.2681 +
  2.2682 +	for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  2.2683 +		rxp = &tp->rx_jumbo_buffers[i];
  2.2684 +
  2.2685 +		if (rxp->skb == NULL)
  2.2686 +			continue;
  2.2687 +		pci_unmap_single(tp->pdev,
  2.2688 +				 pci_unmap_addr(rxp, mapping),
  2.2689 +				 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
  2.2690 +				 PCI_DMA_FROMDEVICE);
  2.2691 +		dev_kfree_skb_any(rxp->skb);
  2.2692 +		rxp->skb = NULL;
  2.2693 +	}
  2.2694 +
  2.2695 +	for (i = 0; i < TG3_TX_RING_SIZE; ) {
  2.2696 +		struct tx_ring_info *txp;
  2.2697 +		struct sk_buff *skb;
  2.2698 +		int j;
  2.2699 +
  2.2700 +		txp = &tp->tx_buffers[i];
  2.2701 +		skb = txp->skb;
  2.2702 +
  2.2703 +		if (skb == NULL) {
  2.2704 +			i++;
  2.2705 +			continue;
  2.2706 +		}
  2.2707 +
  2.2708 +		pci_unmap_single(tp->pdev,
  2.2709 +				 pci_unmap_addr(txp, mapping),
  2.2710 +				 (skb->len - skb->data_len),
  2.2711 +				 PCI_DMA_TODEVICE);
  2.2712 +		txp->skb = NULL;
  2.2713 +
  2.2714 +		i++;
  2.2715 +
  2.2716 +		for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
  2.2717 +			txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
  2.2718 +			pci_unmap_page(tp->pdev,
  2.2719 +				       pci_unmap_addr(txp, mapping),
  2.2720 +				       skb_shinfo(skb)->frags[j].size,
  2.2721 +				       PCI_DMA_TODEVICE);
  2.2722 +			i++;
  2.2723 +		}
  2.2724 +
  2.2725 +		dev_kfree_skb_any(skb);
  2.2726 +	}
  2.2727 +}
  2.2728 +
  2.2729 +/* Initialize tx/rx rings for packet processing.
  2.2730 + *
  2.2731 + * The chip has been shut down and the driver detached from
  2.2732 + * the networking, so no interrupts or new tx packets will
  2.2733 + * end up in the driver.  tp->{tx,}lock is not held and we are not
  2.2734 + * in an interrupt context and thus may sleep.
  2.2735 + */
  2.2736 +static void tg3_init_rings(struct tg3 *tp)
  2.2737 +{
  2.2738 +	unsigned long start, end;
  2.2739 +	u32 i;
  2.2740 +
  2.2741 +	/* Free up all the SKBs. */
  2.2742 +	tg3_free_rings(tp);
  2.2743 +
  2.2744 +	/* Zero out all descriptors. */
  2.2745 +	memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
  2.2746 +	memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
  2.2747 +	memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES);
  2.2748 +
  2.2749 +	if (tp->tg3_flags & TG3_FLAG_HOST_TXDS) {
  2.2750 +		memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
  2.2751 +	} else {
  2.2752 +		start = (tp->regs +
  2.2753 +			 NIC_SRAM_WIN_BASE +
  2.2754 +			 NIC_SRAM_TX_BUFFER_DESC);
  2.2755 +		end = start + TG3_TX_RING_BYTES;
  2.2756 +		while (start < end) {
  2.2757 +			writel(0, start);
  2.2758 +			start += 4;
  2.2759 +		}
  2.2760 +		for (i = 0; i < TG3_TX_RING_SIZE; i++)
  2.2761 +			tp->tx_buffers[i].prev_vlan_tag = 0;
  2.2762 +	}
  2.2763 +
  2.2764 +	/* Initialize invariants of the rings, we only set this
  2.2765 +	 * stuff once.  This works because the card does not
  2.2766 +	 * write into the rx buffer posting rings.
  2.2767 +	 */
  2.2768 +	for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  2.2769 +		struct tg3_rx_buffer_desc *rxd;
  2.2770 +
  2.2771 +		rxd = &tp->rx_std[i];
  2.2772 +		rxd->idx_len = (RX_PKT_BUF_SZ - tp->rx_offset - 64)
  2.2773 +			<< RXD_LEN_SHIFT;
  2.2774 +		rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
  2.2775 +		rxd->opaque = (RXD_OPAQUE_RING_STD |
  2.2776 +			       (i << RXD_OPAQUE_INDEX_SHIFT));
  2.2777 +	}
  2.2778 +
  2.2779 +	if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
  2.2780 +		for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  2.2781 +			struct tg3_rx_buffer_desc *rxd;
  2.2782 +
  2.2783 +			rxd = &tp->rx_jumbo[i];
  2.2784 +			rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
  2.2785 +				<< RXD_LEN_SHIFT;
  2.2786 +			rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
  2.2787 +				RXD_FLAG_JUMBO;
  2.2788 +			rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
  2.2789 +			       (i << RXD_OPAQUE_INDEX_SHIFT));
  2.2790 +		}
  2.2791 +	}
  2.2792 +
  2.2793 +	/* Now allocate fresh SKBs for each rx ring. */
  2.2794 +	for (i = 0; i < tp->rx_pending; i++) {
  2.2795 +		if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
  2.2796 +				     -1, i) < 0)
  2.2797 +			break;
  2.2798 +	}
  2.2799 +
  2.2800 +	if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
  2.2801 +		for (i = 0; i < tp->rx_jumbo_pending; i++) {
  2.2802 +			if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
  2.2803 +					     -1, i) < 0)
  2.2804 +				break;
  2.2805 +		}
  2.2806 +	}
  2.2807 +}
  2.2808 +
  2.2809 +/*
  2.2810 + * Must not be invoked with interrupt sources disabled and
  2.2811 + * the hardware shutdown down.
  2.2812 + */
  2.2813 +static void tg3_free_consistent(struct tg3 *tp)
  2.2814 +{
  2.2815 +	if (tp->rx_std_buffers) {
  2.2816 +		kfree(tp->rx_std_buffers);
  2.2817 +		tp->rx_std_buffers = NULL;
  2.2818 +	}
  2.2819 +	if (tp->rx_std) {
  2.2820 +		pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
  2.2821 +				    tp->rx_std, tp->rx_std_mapping);
  2.2822 +		tp->rx_std = NULL;
  2.2823 +	}
  2.2824 +	if (tp->rx_jumbo) {
  2.2825 +		pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  2.2826 +				    tp->rx_jumbo, tp->rx_jumbo_mapping);
  2.2827 +		tp->rx_jumbo = NULL;
  2.2828 +	}
  2.2829 +	if (tp->rx_rcb) {
  2.2830 +		pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES,
  2.2831 +				    tp->rx_rcb, tp->rx_rcb_mapping);
  2.2832 +		tp->rx_rcb = NULL;
  2.2833 +	}
  2.2834 +	if (tp->tx_ring) {
  2.2835 +		pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
  2.2836 +			tp->tx_ring, tp->tx_desc_mapping);
  2.2837 +		tp->tx_ring = NULL;
  2.2838 +	}
  2.2839 +	if (tp->hw_status) {
  2.2840 +		pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
  2.2841 +				    tp->hw_status, tp->status_mapping);
  2.2842 +		tp->hw_status = NULL;
  2.2843 +	}
  2.2844 +	if (tp->hw_stats) {
  2.2845 +		pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
  2.2846 +				    tp->hw_stats, tp->stats_mapping);
  2.2847 +		tp->hw_stats = NULL;
  2.2848 +	}
  2.2849 +}
  2.2850 +
  2.2851 +/*
  2.2852 + * Must not be invoked with interrupt sources disabled and
  2.2853 + * the hardware shutdown down.  Can sleep.
  2.2854 + */
  2.2855 +static int tg3_alloc_consistent(struct tg3 *tp)
  2.2856 +{
  2.2857 +	tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
  2.2858 +				      (TG3_RX_RING_SIZE +
  2.2859 +				       TG3_RX_JUMBO_RING_SIZE)) +
  2.2860 +				     (sizeof(struct tx_ring_info) *
  2.2861 +				      TG3_TX_RING_SIZE),
  2.2862 +				     GFP_KERNEL);
  2.2863 +	if (!tp->rx_std_buffers)
  2.2864 +		return -ENOMEM;
  2.2865 +
  2.2866 +	memset(tp->rx_std_buffers, 0,
  2.2867 +	       (sizeof(struct ring_info) *
  2.2868 +		(TG3_RX_RING_SIZE +
  2.2869 +		 TG3_RX_JUMBO_RING_SIZE)) +
  2.2870 +	       (sizeof(struct tx_ring_info) *
  2.2871 +		TG3_TX_RING_SIZE));
  2.2872 +
  2.2873 +	tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
  2.2874 +	tp->tx_buffers = (struct tx_ring_info *)
  2.2875 +		&tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
  2.2876 +
  2.2877 +	tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
  2.2878 +					  &tp->rx_std_mapping);
  2.2879 +	if (!tp->rx_std)
  2.2880 +		goto err_out;
  2.2881 +
  2.2882 +	tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  2.2883 +					    &tp->rx_jumbo_mapping);
  2.2884 +
  2.2885 +	if (!tp->rx_jumbo)
  2.2886 +		goto err_out;
  2.2887 +
  2.2888 +	tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES,
  2.2889 +					  &tp->rx_rcb_mapping);
  2.2890 +	if (!tp->rx_rcb)
  2.2891 +		goto err_out;
  2.2892 +
  2.2893 +	if (tp->tg3_flags & TG3_FLAG_HOST_TXDS) {
  2.2894 +		tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
  2.2895 +						   &tp->tx_desc_mapping);
  2.2896 +		if (!tp->tx_ring)
  2.2897 +			goto err_out;
  2.2898 +	} else {
  2.2899 +		tp->tx_ring = NULL;
  2.2900 +		tp->tx_desc_mapping = 0;
  2.2901 +	}
  2.2902 +
  2.2903 +	tp->hw_status = pci_alloc_consistent(tp->pdev,
  2.2904 +					     TG3_HW_STATUS_SIZE,
  2.2905 +					     &tp->status_mapping);
  2.2906 +	if (!tp->hw_status)
  2.2907 +		goto err_out;
  2.2908 +
  2.2909 +	tp->hw_stats = pci_alloc_consistent(tp->pdev,
  2.2910 +					    sizeof(struct tg3_hw_stats),
  2.2911 +					    &tp->stats_mapping);
  2.2912 +	if (!tp->hw_stats)
  2.2913 +		goto err_out;
  2.2914 +
  2.2915 +	memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  2.2916 +	memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  2.2917 +
  2.2918 +	return 0;
  2.2919 +
  2.2920 +err_out:
  2.2921 +	tg3_free_consistent(tp);
  2.2922 +	return -ENOMEM;
  2.2923 +}
  2.2924 +
  2.2925 +#define MAX_WAIT_CNT 1000
  2.2926 +
  2.2927 +/* To stop a block, clear the enable bit and poll till it
  2.2928 + * clears.  tp->lock is held.
  2.2929 + */
  2.2930 +static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit)
  2.2931 +{
  2.2932 +	unsigned int i;
  2.2933 +	u32 val;
  2.2934 +
  2.2935 +	val = tr32(ofs);
  2.2936 +	val &= ~enable_bit;
  2.2937 +	tw32(ofs, val);
  2.2938 +	tr32(ofs);
  2.2939 +
  2.2940 +	for (i = 0; i < MAX_WAIT_CNT; i++) {
  2.2941 +		udelay(100);
  2.2942 +		val = tr32(ofs);
  2.2943 +		if ((val & enable_bit) == 0)
  2.2944 +			break;
  2.2945 +	}
  2.2946 +
  2.2947 +	if (i == MAX_WAIT_CNT) {
  2.2948 +		printk(KERN_ERR PFX "tg3_stop_block timed out, "
  2.2949 +		       "ofs=%lx enable_bit=%x\n",
  2.2950 +		       ofs, enable_bit);
  2.2951 +		return -ENODEV;
  2.2952 +	}
  2.2953 +
  2.2954 +	return 0;
  2.2955 +}
  2.2956 +
  2.2957 +/* tp->lock is held. */
  2.2958 +static int tg3_abort_hw(struct tg3 *tp)
  2.2959 +{
  2.2960 +	int i, err;
  2.2961 +
  2.2962 +	tg3_disable_ints(tp);
  2.2963 +
  2.2964 +	tp->rx_mode &= ~RX_MODE_ENABLE;
  2.2965 +	tw32(MAC_RX_MODE, tp->rx_mode);
  2.2966 +	tr32(MAC_RX_MODE);
  2.2967 +	udelay(10);
  2.2968 +
  2.2969 +	err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE);
  2.2970 +	err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  2.2971 +	err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE);
  2.2972 +	err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE);
  2.2973 +	err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE);
  2.2974 +	err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE);
  2.2975 +
  2.2976 +	err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE);
  2.2977 +	err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE);
  2.2978 +	err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  2.2979 +	err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE);
  2.2980 +	err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  2.2981 +	err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE);
  2.2982 +	if (err)
  2.2983 +		goto out;
  2.2984 +
  2.2985 +	tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  2.2986 +	tw32(MAC_MODE, tp->mac_mode);
  2.2987 +	tr32(MAC_MODE);
  2.2988 +	udelay(40);
  2.2989 +
  2.2990 +	tp->tx_mode &= ~TX_MODE_ENABLE;
  2.2991 +	tw32(MAC_TX_MODE, tp->tx_mode);
  2.2992 +	tr32(MAC_TX_MODE);
  2.2993 +
  2.2994 +	for (i = 0; i < MAX_WAIT_CNT; i++) {
  2.2995 +		udelay(100);
  2.2996 +		if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
  2.2997 +			break;
  2.2998 +	}
  2.2999 +	if (i >= MAX_WAIT_CNT) {
  2.3000 +		printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
  2.3001 +		       "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
  2.3002 +		       tp->dev->name, tr32(MAC_TX_MODE));
  2.3003 +		return -ENODEV;
  2.3004 +	}
  2.3005 +
  2.3006 +	err  = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
  2.3007 +	err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE);
  2.3008 +	err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
  2.3009 +
  2.3010 +	tw32(FTQ_RESET, 0xffffffff);
  2.3011 +	tw32(FTQ_RESET, 0x00000000);
  2.3012 +
  2.3013 +	err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
  2.3014 +	err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
  2.3015 +	if (err)
  2.3016 +		goto out;
  2.3017 +
  2.3018 +	memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  2.3019 +
  2.3020 +out:
  2.3021 +	return err;
  2.3022 +}
  2.3023 +
  2.3024 +/* tp->lock is held. */
  2.3025 +static void tg3_chip_reset(struct tg3 *tp)
  2.3026 +{
  2.3027 +	u32 val;
  2.3028 +
  2.3029 +	/* Force NVRAM to settle.
  2.3030 +	 * This deals with a chip bug which can result in EEPROM
  2.3031 +	 * corruption.
  2.3032 +	 */
  2.3033 +	if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  2.3034 +		int i;
  2.3035 +
  2.3036 +		tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  2.3037 +		for (i = 0; i < 100000; i++) {
  2.3038 +			if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  2.3039 +				break;
  2.3040 +			udelay(10);
  2.3041 +		}
  2.3042 +	}
  2.3043 +
  2.3044 +	tw32(GRC_MISC_CFG, GRC_MISC_CFG_CORECLK_RESET);
  2.3045 +
  2.3046 +	/* Flush PCI posted writes.  The normal MMIO registers
  2.3047 +	 * are inaccessible at this time so this is the only
  2.3048 +	 * way to make this reliably.  I tried to use indirect
  2.3049 +	 * register read/write but this upset some 5701 variants.
  2.3050 +	 */
  2.3051 +	pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
  2.3052 +
  2.3053 +	udelay(40);
  2.3054 +	udelay(40);
  2.3055 +	udelay(40);
  2.3056 +
  2.3057 +	/* Re-enable indirect register accesses. */
  2.3058 +	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  2.3059 +			       tp->misc_host_ctrl);
  2.3060 +
  2.3061 +	/* Set MAX PCI retry to zero. */
  2.3062 +	val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
  2.3063 +	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  2.3064 +	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
  2.3065 +		val |= PCISTATE_RETRY_SAME_DMA;
  2.3066 +	pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
  2.3067 +
  2.3068 +	pci_restore_state(tp->pdev, tp->pci_cfg_state);
  2.3069 +
  2.3070 +	/* Make sure PCI-X relaxed ordering bit is clear. */
  2.3071 +	pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
  2.3072 +	val &= ~PCIX_CAPS_RELAXED_ORDERING;
  2.3073 +	pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
  2.3074 +
  2.3075 +	tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  2.3076 +
  2.3077 +	tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
  2.3078 +}
  2.3079 +
  2.3080 +/* tp->lock is held. */
  2.3081 +static void tg3_stop_fw(struct tg3 *tp)
  2.3082 +{
  2.3083 +	if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  2.3084 +		u32 val;
  2.3085 +		int i;
  2.3086 +
  2.3087 +		tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
  2.3088 +		val = tr32(GRC_RX_CPU_EVENT);
  2.3089 +		val |= (1 << 14);
  2.3090 +		tw32(GRC_RX_CPU_EVENT, val);
  2.3091 +
  2.3092 +		/* Wait for RX cpu to ACK the event.  */
  2.3093 +		for (i = 0; i < 100; i++) {
  2.3094 +			if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
  2.3095 +				break;
  2.3096 +			udelay(1);
  2.3097 +		}
  2.3098 +	}
  2.3099 +}
  2.3100 +
  2.3101 +/* tp->lock is held. */
  2.3102 +static int tg3_halt(struct tg3 *tp)
  2.3103 +{
  2.3104 +	u32 val;
  2.3105 +	int i;
  2.3106 +
  2.3107 +	tg3_stop_fw(tp);
  2.3108 +	tg3_abort_hw(tp);
  2.3109 +	tg3_chip_reset(tp);
  2.3110 +	tg3_write_mem(tp,
  2.3111 +		      NIC_SRAM_FIRMWARE_MBOX,
  2.3112 +		      NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  2.3113 +	for (i = 0; i < 100000; i++) {
  2.3114 +		tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  2.3115 +		if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  2.3116 +			break;
  2.3117 +		udelay(10);
  2.3118 +	}
  2.3119 +
  2.3120 +	if (i >= 100000) {
  2.3121 +		printk(KERN_ERR PFX "tg3_halt timed out for %s, "
  2.3122 +		       "firmware will not restart magic=%08x\n",
  2.3123 +		       tp->dev->name, val);
  2.3124 +		return -ENODEV;
  2.3125 +	}
  2.3126 +
  2.3127 +	if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  2.3128 +		if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
  2.3129 +			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  2.3130 +				      DRV_STATE_WOL);
  2.3131 +		else
  2.3132 +			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  2.3133 +				      DRV_STATE_UNLOAD);
  2.3134 +	} else
  2.3135 +		tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  2.3136 +			      DRV_STATE_SUSPEND);
  2.3137 +
  2.3138 +	return 0;
  2.3139 +}
  2.3140 +
  2.3141 +#define TG3_FW_RELEASE_MAJOR	0x0
  2.3142 +#define TG3_FW_RELASE_MINOR	0x0
  2.3143 +#define TG3_FW_RELEASE_FIX	0x0
  2.3144 +#define TG3_FW_START_ADDR	0x08000000
  2.3145 +#define TG3_FW_TEXT_ADDR	0x08000000
  2.3146 +#define TG3_FW_TEXT_LEN		0x9c0
  2.3147 +#define TG3_FW_RODATA_ADDR	0x080009c0
  2.3148 +#define TG3_FW_RODATA_LEN	0x60
  2.3149 +#define TG3_FW_DATA_ADDR	0x08000a40
  2.3150 +#define TG3_FW_DATA_LEN		0x20
  2.3151 +#define TG3_FW_SBSS_ADDR	0x08000a60
  2.3152 +#define TG3_FW_SBSS_LEN		0xc
  2.3153 +#define TG3_FW_BSS_ADDR		0x08000a70
  2.3154 +#define TG3_FW_BSS_LEN		0x10
  2.3155 +
  2.3156 +static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
  2.3157 +	0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
  2.3158 +	0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
  2.3159 +	0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
  2.3160 +	0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
  2.3161 +	0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
  2.3162 +	0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
  2.3163 +	0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
  2.3164 +	0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
  2.3165 +	0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
  2.3166 +	0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
  2.3167 +	0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
  2.3168 +	0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
  2.3169 +	0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
  2.3170 +	0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
  2.3171 +	0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
  2.3172 +	0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  2.3173 +	0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
  2.3174 +	0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
  2.3175 +	0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
  2.3176 +	0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  2.3177 +	0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
  2.3178 +	0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
  2.3179 +	0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  2.3180 +	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2.3181 +	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2.3182 +	0, 0, 0, 0, 0, 0,
  2.3183 +	0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
  2.3184 +	0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  2.3185 +	0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  2.3186 +	0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  2.3187 +	0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
  2.3188 +	0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
  2.3189 +	0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
  2.3190 +	0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
  2.3191 +	0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  2.3192 +	0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  2.3193 +	0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
  2.3194 +	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2.3195 +	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2.3196 +	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2.3197 +	0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
  2.3198 +	0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
  2.3199 +	0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
  2.3200 +	0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
  2.3201 +	0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
  2.3202 +	0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
  2.3203 +	0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
  2.3204 +	0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
  2.3205 +	0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
  2.3206 +	0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
  2.3207 +	0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
  2.3208 +	0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
  2.3209 +	0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
  2.3210 +	0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
  2.3211 +	0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
  2.3212 +	0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
  2.3213 +	0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
  2.3214 +	0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
  2.3215 +	0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
  2.3216 +	0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
  2.3217 +	0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
  2.3218 +	0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
  2.3219 +	0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
  2.3220 +	0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
  2.3221 +	0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
  2.3222 +	0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
  2.3223 +	0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
  2.3224 +	0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
  2.3225 +	0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
  2.3226 +	0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
  2.3227 +	0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
  2.3228 +	0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
  2.3229 +	0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
  2.3230 +	0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
  2.3231 +	0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
  2.3232 +	0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
  2.3233 +	0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
  2.3234 +	0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
  2.3235 +	0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
  2.3236 +	0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
  2.3237 +	0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
  2.3238 +	0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
  2.3239 +	0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
  2.3240 +	0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
  2.3241 +	0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
  2.3242 +	0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
  2.3243 +	0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
  2.3244 +	0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
  2.3245 +	0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
  2.3246 +	0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
  2.3247 +	0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
  2.3248 +};
  2.3249 +
  2.3250 +static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
  2.3251 +	0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
  2.3252 +	0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
  2.3253 +	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
  2.3254 +	0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
  2.3255 +	0x00000000
  2.3256 +};
  2.3257 +
  2.3258 +#if 0 /* All zeros, dont eat up space with it. */
  2.3259 +u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
  2.3260 +	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  2.3261 +	0x00000000, 0x00000000, 0x00000000, 0x00000000
  2.3262 +};
  2.3263 +#endif
  2.3264 +
  2.3265 +#define RX_CPU_SCRATCH_BASE	0x30000
  2.3266 +#define RX_CPU_SCRATCH_SIZE	0x04000
  2.3267 +#define TX_CPU_SCRATCH_BASE	0x34000
  2.3268 +#define TX_CPU_SCRATCH_SIZE	0x04000
  2.3269 +
  2.3270 +/* tp->lock is held. */
  2.3271 +static int tg3_reset_cpu(struct tg3 *tp, u32 offset)
  2.3272 +{
  2.3273 +	int i;
  2.3274 +
  2.3275 +	tw32(offset + CPU_STATE, 0xffffffff);
  2.3276 +	tw32(offset + CPU_MODE,  CPU_MODE_RESET);
  2.3277 +	if (offset == RX_CPU_BASE) {
  2.3278 +		for (i = 0; i < 10000; i++)
  2.3279 +			if (!(tr32(offset + CPU_MODE) & CPU_MODE_RESET))
  2.3280 +				break;
  2.3281 +		tw32(offset + CPU_STATE, 0xffffffff);
  2.3282 +		tw32(offset + CPU_MODE,  CPU_MODE_RESET);
  2.3283 +		tr32(offset + CPU_MODE);
  2.3284 +		udelay(10);
  2.3285 +	} else {
  2.3286 +		for (i = 0; i < 10000; i++) {
  2.3287 +			if (!(tr32(offset + CPU_MODE) & CPU_MODE_RESET))
  2.3288 +				break;
  2.3289 +			tw32(offset + CPU_STATE, 0xffffffff);
  2.3290 +			tw32(offset + CPU_MODE,  CPU_MODE_RESET);
  2.3291 +			tr32(offset + CPU_MODE);
  2.3292 +			udelay(10);
  2.3293 +		}
  2.3294 +	}
  2.3295 +
  2.3296 +	if (i >= 10000) {
  2.3297 +		printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
  2.3298 +		       "and %s CPU\n",
  2.3299 +		       tp->dev->name,
  2.3300 +		       (offset == RX_CPU_BASE ? "RX" : "TX"));
  2.3301 +		return -ENODEV;
  2.3302 +	}
  2.3303 +	return 0;
  2.3304 +}
  2.3305 +
  2.3306 +struct fw_info {
  2.3307 +	unsigned int text_base;
  2.3308 +	unsigned int text_len;
  2.3309 +	u32 *text_data;
  2.3310 +	unsigned int rodata_base;
  2.3311 +	unsigned int rodata_len;
  2.3312 +	u32 *rodata_data;
  2.3313 +	unsigned int data_base;
  2.3314 +	unsigned int data_len;
  2.3315 +	u32 *data_data;
  2.3316 +};
  2.3317 +
  2.3318 +/* tp->lock is held. */
  2.3319 +static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
  2.3320 +				 int cpu_scratch_size, struct fw_info *info)
  2.3321 +{
  2.3322 +	int err, i;
  2.3323 +	u32 orig_tg3_flags = tp->tg3_flags;
  2.3324 +
  2.3325 +	/* Force use of PCI config space for indirect register
  2.3326 +	 * write calls.
  2.3327 +	 */
  2.3328 +	tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  2.3329 +
  2.3330 +	err = tg3_reset_cpu(tp, cpu_base);
  2.3331 +	if (err)
  2.3332 +		goto out;
  2.3333 +
  2.3334 +	for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  2.3335 +		tg3_write_indirect_reg32(tp, cpu_scratch_base + i, 0);
  2.3336 +	tw32(cpu_base + CPU_STATE, 0xffffffff);
  2.3337 +	tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
  2.3338 +	for (i = 0; i < (info->text_len / sizeof(u32)); i++)
  2.3339 +		tg3_write_indirect_reg32(tp, (cpu_scratch_base +
  2.3340 +					      (info->text_base & 0xffff) +
  2.3341 +					      (i * sizeof(u32))),
  2.3342 +					 (info->text_data ?
  2.3343 +					  info->text_data[i] : 0));
  2.3344 +	for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
  2.3345 +		tg3_write_indirect_reg32(tp, (cpu_scratch_base +
  2.3346 +					      (info->rodata_base & 0xffff) +
  2.3347 +					      (i * sizeof(u32))),
  2.3348 +					 (info->rodata_data ?
  2.3349 +					  info->rodata_data[i] : 0));
  2.3350 +	for (i = 0; i < (info->data_len / sizeof(u32)); i++)
  2.3351 +		tg3_write_indirect_reg32(tp, (cpu_scratch_base +
  2.3352 +					      (info->data_base & 0xffff) +
  2.3353 +					      (i * sizeof(u32))),
  2.3354 +					 (info->data_data ?
  2.3355 +					  info->data_data[i] : 0));
  2.3356 +
  2.3357 +	err = 0;
  2.3358 +
  2.3359 +out:
  2.3360 +	tp->tg3_flags = orig_tg3_flags;
  2.3361 +	return err;
  2.3362 +}
  2.3363 +
  2.3364 +/* tp->lock is held. */
  2.3365 +static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
  2.3366 +{
  2.3367 +	struct fw_info info;
  2.3368 +	int err, i;
  2.3369 +
  2.3370 +	info.text_base = TG3_FW_TEXT_ADDR;
  2.3371 +	info.text_len = TG3_FW_TEXT_LEN;
  2.3372 +	info.text_data = &tg3FwText[0];
  2.3373 +	info.rodata_base = TG3_FW_RODATA_ADDR;
  2.3374 +	info.rodata_len = TG3_FW_RODATA_LEN;
  2.3375 +	info.rodata_data = &tg3FwRodata[0];
  2.3376 +	info.data_base = TG3_FW_DATA_ADDR;
  2.3377 +	info.data_len = TG3_FW_DATA_LEN;
  2.3378 +	info.data_data = NULL;
  2.3379 +
  2.3380 +	err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
  2.3381 +				    RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
  2.3382 +				    &info);
  2.3383 +	if (err)
  2.3384 +		return err;
  2.3385 +
  2.3386 +	err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  2.3387 +				    TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  2.3388 +				    &info);
  2.3389 +	if (err)
  2.3390 +		return err;
  2.3391 +
  2.3392 +	/* Now startup only the RX cpu. */
  2.3393 +	tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  2.3394 +	tw32(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
  2.3395 +
  2.3396 +	/* Flush posted writes. */
  2.3397 +	tr32(RX_CPU_BASE + CPU_PC);
  2.3398 +	for (i = 0; i < 5; i++) {
  2.3399 +		if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
  2.3400 +			break;
  2.3401 +		tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  2.3402 +		tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
  2.3403 +		tw32(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
  2.3404 +
  2.3405 +		/* Flush posted writes. */
  2.3406 +		tr32(RX_CPU_BASE + CPU_PC);
  2.3407 +
  2.3408 +		udelay(1000);
  2.3409 +	}
  2.3410 +	if (i >= 5) {
  2.3411 +		printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
  2.3412 +		       "to set RX CPU PC, is %08x should be %08x\n",
  2.3413 +		       tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
  2.3414 +		       TG3_FW_TEXT_ADDR);
  2.3415 +		return -ENODEV;
  2.3416 +	}
  2.3417 +	tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  2.3418 +	tw32(RX_CPU_BASE + CPU_MODE,  0x00000000);
  2.3419 +
  2.3420 +	/* Flush posted writes. */
  2.3421 +	tr32(RX_CPU_BASE + CPU_MODE);
  2.3422 +
  2.3423 +	return 0;
  2.3424 +}
  2.3425 +
  2.3426 +#if TG3_DO_TSO != 0
  2.3427 +
  2.3428 +#define TG3_TSO_FW_RELEASE_MAJOR	0x1
  2.3429 +#define TG3_TSO_FW_RELASE_MINOR		0x8
  2.3430 +#define TG3_TSO_FW_RELEASE_FIX		0x0
  2.3431 +#define TG3_TSO_FW_START_ADDR		0x08000000
  2.3432 +#define TG3_TSO_FW_TEXT_ADDR		0x08000000
  2.3433 +#define TG3_TSO_FW_TEXT_LEN		0x1650
  2.3434 +#define TG3_TSO_FW_RODATA_ADDR		0x08001650
  2.3435 +#define TG3_TSO_FW_RODATA_LEN		0x30
  2.3436 +#define TG3_TSO_FW_DATA_ADDR		0x080016a0
  2.3437 +#define TG3_TSO_FW_DATA_LEN		0x20
  2.3438 +#define TG3_TSO_FW_SBSS_ADDR		0x080016c0
  2.3439 +#define TG3_TSO_FW_SBSS_LEN		0x14
  2.3440 +#define TG3_TSO_FW_BSS_ADDR		0x080016e0
  2.3441 +#define TG3_TSO_FW_BSS_LEN		0x8fc
  2.3442 +
  2.3443 +static u32 tg3TsoFwText[] = {
  2.3444 +	0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
  2.3445 +	0x37bd4000, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000010, 0x00000000,
  2.3446 +	0x0000000d, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0x3c1bc000,
  2.3447 +	0xafbf0018, 0x0e000058, 0xaf60680c, 0x3c040800, 0x24841650, 0x03602821,
  2.3448 +	0x24060001, 0x24070004, 0xafa00010, 0x0e00006c, 0xafa00014, 0x8f625c50,
  2.3449 +	0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001, 0xaf625c90, 0x2402ffff,
  2.3450 +	0x0e000098, 0xaf625404, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
  2.3451 +	0x00000000, 0x00000000, 0x24030b60, 0x24050fff, 0xac000b50, 0x00002021,
  2.3452 +	0xac640000, 0x24630004, 0x0065102b, 0x1440fffc, 0x24840001, 0x24030b60,
  2.3453 +	0x0065102b, 0x10400011, 0x00002021, 0x24090b54, 0x3c06dead, 0x34c6beef,
  2.3454 +	0x24080b58, 0x24070b5c, 0x8c620000, 0x50440006, 0x24630004, 0xad260000,
  2.3455 +	0x8c620000, 0xace40000, 0xad020000, 0x24630004, 0x0065102b, 0x1440fff6,
  2.3456 +	0x24840001, 0x03e00008, 0x00000000, 0x27bdfff8, 0x18800009, 0x00002821,
  2.3457 +	0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000, 0x24a50001, 0x00a4102a,
  2.3458 +	0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008, 0x3c020800, 0x34423000,
  2.3459 +	0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac2216c4,
  2.3460 +	0x24020040, 0x3c010800, 0xac2216c8, 0x3c010800, 0xac2016c0, 0xac600000,
  2.3461 +	0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  2.3462 +	0x00804821, 0x8faa0010, 0x3c020800, 0x8c4216c0, 0x3c040800, 0x8c8416c8,
  2.3463 +	0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac2316c0, 0x14400003,
  2.3464 +	0x00004021, 0x3c010800, 0xac2016c0, 0x3c020800, 0x8c4216c0, 0x3c030800,
  2.3465 +	0x8c6316c4, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  2.3466 +	0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c4216c0,
  2.3467 +	0x3c030800, 0x8c6316c4, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
  2.3468 +	0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  2.3469 +	0x00000000, 0x00000000, 0x27bdffe0, 0xafbf0018, 0xafb10014, 0x0e0000b6,
  2.3470 +	0xafb00010, 0x24110001, 0x8f706820, 0x32020100, 0x10400003, 0x00000000,
  2.3471 +	0x0e000127, 0x00000000, 0x8f706820, 0x32022000, 0x10400004, 0x32020001,
  2.3472 +	0x0e00025a, 0x24040001, 0x32020001, 0x10400003, 0x00000000, 0x0e0000e6,
  2.3473 +	0x00000000, 0x0a00009e, 0xaf715028, 0x8fbf0018, 0x8fb10014, 0x8fb00010,
  2.3474 +	0x03e00008, 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841660, 0x00002821,
  2.3475 +	0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00006c, 0xafa00014,
  2.3476 +	0x3c010800, 0xa4201fb8, 0x3c010800, 0xa02016f8, 0x3c010800, 0xac2016fc,
  2.3477 +	0x3c010800, 0xac201700, 0x3c010800, 0xac201704, 0x3c010800, 0xac20170c,
  2.3478 +	0x3c010800, 0xac201718, 0x3c010800, 0xac20171c, 0x8f624434, 0x3c010800,
  2.3479 +	0xac2216e8, 0x8f624438, 0x3c010800, 0xac2216ec, 0x8f624410, 0x3c010800,
  2.3480 +	0xac2016e0, 0x3c010800, 0xac2016e4, 0x3c010800, 0xac201fc0, 0x3c010800,
  2.3481 +	0xac201f68, 0x3c010800, 0xac201f6c, 0x3c010800, 0xac2216f0, 0x8fbf0018,
  2.3482 +	0x03e00008, 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x2484166c, 0x00002821,
  2.3483 +	0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00006c, 0xafa00014,
  2.3484 +	0x3c040800, 0x24841660, 0x00002821, 0x00003021, 0x00003821, 0xafa00010,
  2.3485 +	0x0e00006c, 0xafa00014, 0x3c010800, 0xa4201fb8, 0x3c010800, 0xa02016f8,
  2.3486 +	0x3c010800, 0xac2016fc, 0x3c010800, 0xac201700, 0x3c010800, 0xac201704,
  2.3487 +	0x3c010800, 0xac20170c, 0x3c010800, 0xac201718, 0x3c010800, 0xac20171c,
  2.3488 +	0x8f624434, 0x3c010800, 0xac2216e8, 0x8f624438, 0x3c010800, 0xac2216ec,
  2.3489 +	0x8f624410, 0x3c010800, 0xac2016e0, 0x3c010800, 0xac2016e4, 0x3c010800,
  2.3490 +	0xac201fc0, 0x3c010800, 0xac201f68, 0x3c010800, 0xac201f6c, 0x3c010800,
  2.3491 +	0xac2216f0, 0x0e000120, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  2.3492 +	0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
  2.3493 +	0xaf636820, 0x27bdffd0, 0x3c0300ff, 0xafbf002c, 0xafb60028, 0xafb50024,
  2.3494 +	0xafb40020, 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f665c5c,
  2.3495 +	0x3c040800, 0x2484171c, 0x8c820000, 0x3463fff8, 0x14460005, 0x00c38824,
  2.3496 +	0x3c020800, 0x904216f8, 0x14400115, 0x00000000, 0x00111902, 0x306300ff,
  2.3497 +	0x30c20003, 0x000211c0, 0x00623825, 0x00e02821, 0x00061602, 0xac860000,
  2.3498 +	0x3c030800, 0x906316f8, 0x3044000f, 0x1460002b, 0x00804021, 0x24020001,
  2.3499 +	0x3c010800, 0xa02216f8, 0x00071100, 0x00821025, 0x3c010800, 0xac2016fc,
  2.3500 +	0x3c010800, 0xac201700, 0x3c010800, 0xac201704, 0x3c010800, 0xac20170c,
  2.3501 +	0x3c010800, 0xac201718, 0x3c010800, 0xac201710, 0x3c010800, 0xac201714,
  2.3502 +	0x3c010800, 0xa4221fb8, 0x9623000c, 0x30628000, 0x10400008, 0x30627fff,
  2.3503 +	0x2442003e, 0x3c010800, 0xa42216f6, 0x24020001, 0x3c010800, 0x0a00016e,
  2.3504 +	0xac221fd4, 0x24620036, 0x3c010800, 0xa42216f6, 0x3c010800, 0xac201fd4,
  2.3505 +	0x3c010800, 0xac201fd0, 0x3c010800, 0x0a000176, 0xac201fd8, 0x9622000c,
  2.3506 +	0x3c010800, 0xa4221fcc, 0x3c040800, 0x248416fc, 0x8c820000, 0x00021100,
  2.3507 +	0x3c010800, 0x00220821, 0xac311728, 0x8c820000, 0x00021100, 0x3c010800,
  2.3508 +	0x00220821, 0xac26172c, 0x8c820000, 0x24a30001, 0x306701ff, 0x00021100,
  2.3509 +	0x3c010800, 0x00220821, 0xac271730, 0x8c820000, 0x00021100, 0x3c010800,
  2.3510 +	0x00220821, 0xac281734, 0x96230008, 0x3c020800, 0x8c42170c, 0x00432821,
  2.3511 +	0x3c010800, 0xac25170c, 0x9622000a, 0x30420004, 0x14400019, 0x00071100,
  2.3512 +	0x3c02c000, 0x00c21825, 0xaf635c5c, 0x8f625c50, 0x30420002, 0x1440fffc,
  2.3513 +	0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002, 0x1440001e, 0x00000000,
  2.3514 +	0x8f630c14, 0x3c020800, 0x8c4216b4, 0x3063000f, 0x24420001, 0x3c010800,
  2.3515 +	0xac2216b4, 0x2c620002, 0x1040fff7, 0x00000000, 0x0a0001c1, 0x00000000,
  2.3516 +	0x3c030800, 0x8c6316e0, 0x3c040800, 0x948416f4, 0x01021025, 0x3c010800,
  2.3517 +	0xa4221fba, 0x24020001, 0x3c010800, 0xac221718, 0x24630001, 0x0085202a,
  2.3518 +	0x3c010800, 0x10800003, 0xac2316e0, 0x3c010800, 0xa42516f4, 0x3c030800,
  2.3519 +	0x246316fc, 0x8c620000, 0x24420001, 0xac620000, 0x28420080, 0x14400005,
  2.3520 +	0x24020001, 0x0e0002df, 0x24040002, 0x0a000250, 0x00000000, 0x3c030800,
  2.3521 +	0x906316f8, 0x1462007c, 0x24020003, 0x3c160800, 0x96d616f6, 0x3c050800,
  2.3522 +	0x8ca5170c, 0x32c4ffff, 0x00a4102a, 0x14400078, 0x00000000, 0x3c020800,
  2.3523 +	0x8c421718, 0x10400005, 0x32c2ffff, 0x14a40003, 0x00000000, 0x3c010800,
  2.3524 +	0xac231fd0, 0x10400062, 0x00009021, 0x0040a021, 0x3c150800, 0x26b51700,
  2.3525 +	0x26b30010, 0x8ea20000, 0x00028100, 0x3c110800, 0x02308821, 0x0e0002e1,
  2.3526 +	0x8e311728, 0x00403021, 0x10c00059, 0x00000000, 0x9628000a, 0x31020040,
  2.3527 +	0x10400004, 0x2407180c, 0x8e22000c, 0x2407188c, 0xacc20018, 0x31021000,
  2.3528 +	0x10400004, 0x34e32000, 0x00081040, 0x3042c000, 0x00623825, 0x3c030800,
  2.3529 +	0x00701821, 0x8c631730, 0x3c020800, 0x00501021, 0x8c421734, 0x00031d00,
  2.3530 +	0x00021400, 0x00621825, 0xacc30014, 0x8ea30004, 0x96220008, 0x00432023,
  2.3531 +	0x3242ffff, 0x3083ffff, 0x00431021, 0x0282102a, 0x14400002, 0x02d22823,
  2.3532 +	0x00802821, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000, 0x8e220000,
  2.3533 +	0xacc20000, 0x8e220004, 0x8e63fff4, 0x00431021, 0xacc20004, 0xa4c5000e,
  2.3534 +	0x8e62fff4, 0x00441021, 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005,
  2.3535 +	0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0xae62fff0, 0xacc00008,
  2.3536 +	0x3242ffff, 0x14540008, 0x24020305, 0x31020080, 0x54400001, 0x34e70010,
  2.3537 +	0x24020905, 0xa4c2000c, 0x0a000233, 0x34e70020, 0xa4c2000c, 0x30e2ffff,
  2.3538 +	0xacc20010, 0x3c020800, 0x8c421fd0, 0x10400003, 0x3c024b65, 0x0a00023d,
  2.3539 +	0x34427654, 0x3c02b49a, 0x344289ab, 0xacc2001c, 0x0e000560, 0x00c02021,
  2.3540 +	0x3242ffff, 0x0054102b, 0x1440ffa4, 0x00000000, 0x24020002, 0x3c010800,
  2.3541 +	0x0a000250, 0xa02216f8, 0x8ea208bc, 0x24420001, 0x0a000250, 0xaea208bc,
  2.3542 +	0x14620003, 0x00000000, 0x0e000450, 0x00000000, 0x8fbf002c, 0x8fb60028,
  2.3543 +	0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010,
  2.3544 +	0x03e00008, 0x27bd0030, 0x27bdffd8, 0xafb3001c, 0x00809821, 0xafbf0020,
  2.3545 +	0xafb20018, 0xafb10014, 0xafb00010, 0x8f725c9c, 0x3c0200ff, 0x3442fff8,
  2.3546 +	0x3c040800, 0x24841714, 0x02428824, 0x9623000e, 0x8c820000, 0x00431021,
  2.3547 +	0xac820000, 0x8e220010, 0x30420020, 0x14400011, 0x00000000, 0x0e0002f7,
  2.3548 +	0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
  2.3549 +	0x10400061, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x1040005c,
  2.3550 +	0x00000000, 0x0a000278, 0x00000000, 0x8e220008, 0x00021c02, 0x000321c0,
  2.3551 +	0x3042ffff, 0x3c030800, 0x906316f8, 0x000229c0, 0x24020002, 0x14620003,
  2.3552 +	0x3c034b65, 0x0a000290, 0x00008021, 0x8e22001c, 0x34637654, 0x10430002,
  2.3553 +	0x24100002, 0x24100001, 0x0e000300, 0x02003021, 0x24020003, 0x3c010800,
  2.3554 +	0xa02216f8, 0x24020002, 0x1202000a, 0x24020001, 0x3c030800, 0x8c631fd0,
  2.3555 +	0x10620006, 0x00000000, 0x3c020800, 0x94421fb8, 0x00021400, 0x0a0002cd,
  2.3556 +	0xae220014, 0x3c040800, 0x24841fba, 0x94820000, 0x00021400, 0xae220014,
  2.3557 +	0x3c020800, 0x8c42171c, 0x3c03c000, 0x3c010800, 0xa02016f8, 0x00431025,
  2.3558 +	0xaf625c5c, 0x8f625c50, 0x30420002, 0x10400009, 0x00000000, 0x2484f762,
  2.3559 +	0x8c820000, 0x00431025, 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa,
  2.3560 +	0x00000000, 0x3c020800, 0x244216e4, 0x8c430000, 0x24630001, 0xac430000,
  2.3561 +	0x8f630c14, 0x3063000f, 0x2c620002, 0x1440000b, 0x00009821, 0x8f630c14,
  2.3562 +	0x3c020800, 0x8c4216b4, 0x3063000f, 0x24420001, 0x3c010800, 0xac2216b4,
  2.3563 +	0x2c620002, 0x1040fff7, 0x00009821, 0x3c024000, 0x02421825, 0xaf635c9c,
  2.3564 +	0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x12600003, 0x00000000,
  2.3565 +	0x0e000450, 0x00000000, 0x8fbf0020, 0x8fb3001c, 0x8fb20018, 0x8fb10014,
  2.3566 +	0x8fb00010, 0x03e00008, 0x27bd0028, 0x0a0002df, 0x00000000, 0x8f634450,
  2.3567 +	0x3c040800, 0x248416e8, 0x8c820000, 0x00031c02, 0x0043102b, 0x14400007,
  2.3568 +	0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02, 0x0083102b, 0x1040fffc,
  2.3569 +	0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd, 0x00000000,
  2.3570 +	0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000, 0x00822025, 0xaf645c38,
  2.3571 +	0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000, 0x03e00008, 0x00000000,
  2.3572 +	0x27bdffe0, 0x00805021, 0x14c00017, 0x254c0008, 0x3c020800, 0x8c421fd4,
  2.3573 +	0x1040000a, 0x2402003e, 0x3c010800, 0xa4221fb0, 0x24020016, 0x3c010800,
  2.3574 +	0xa4221fb2, 0x2402002a, 0x3c010800, 0x0a00031a, 0xa4221fb4, 0x95420014,
  2.3575 +	0x3c010800, 0xa4221fb0, 0x8d430010, 0x00031402, 0x3c010800, 0xa4221fb2,
  2.3576 +	0x3c010800, 0xa4231fb4, 0x3c040800, 0x94841fb4, 0x3c030800, 0x94631fb2,
  2.3577 +	0x958d0006, 0x3c020800, 0x94421fb0, 0x00832023, 0x01a27023, 0x3065ffff,
  2.3578 +	0x24a20028, 0x01824021, 0x3082ffff, 0x14c0001a, 0x01025821, 0x9562000c,
  2.3579 +	0x3042003f, 0x3c010800, 0xa4221fb6, 0x95620004, 0x95630006, 0x3c010800,
  2.3580 +	0xac201fc4, 0x3c010800, 0xac201fc8, 0x00021400, 0x00431025, 0x3c010800,
  2.3581 +	0xac221720, 0x95020004, 0x3c010800, 0xa4221724, 0x95030002, 0x01a51023,
  2.3582 +	0x0043102a, 0x10400010, 0x24020001, 0x3c010800, 0x0a00034e, 0xac221fd8,
  2.3583 +	0x3c030800, 0x8c631fc8, 0x3c020800, 0x94421724, 0x00431021, 0xa5020004,
  2.3584 +	0x3c020800, 0x94421720, 0xa5620004, 0x3c020800, 0x8c421720, 0xa5620006,
  2.3585 +	0x3c020800, 0x8c421fd0, 0x3c070800, 0x8ce71fc4, 0x3c050800, 0x144000c7,
  2.3586 +	0x8ca51fc8, 0x3c020800, 0x94421724, 0x00451821, 0x3063ffff, 0x0062182b,
  2.3587 +	0x24020002, 0x10c2000d, 0x00a32823, 0x3c020800, 0x94421fb6, 0x30420009,
  2.3588 +	0x10400008, 0x00000000, 0x9562000c, 0x3042fff6, 0xa562000c, 0x3c020800,
  2.3589 +	0x94421fb6, 0x30420009, 0x00e23823, 0x3c020800, 0x8c421fd8, 0x1040004b,
  2.3590 +	0x24020002, 0x01003021, 0x3c020800, 0x94421fb2, 0x00003821, 0xa500000a,
  2.3591 +	0x01a21023, 0xa5020002, 0x3082ffff, 0x00021042, 0x18400008, 0x00002821,
  2.3592 +	0x00401821, 0x94c20000, 0x24e70001, 0x00a22821, 0x00e3102a, 0x1440fffb,
  2.3593 +	0x24c60002, 0x00051c02, 0x30a2ffff, 0x00622821, 0x00051402, 0x00a22821,
  2.3594 +	0x00a04821, 0x00051027, 0xa502000a, 0x00002821, 0x2506000c, 0x00003821,
  2.3595 +	0x94c20000, 0x24e70001, 0x00a22821, 0x2ce20004, 0x1440fffb, 0x24c60002,
  2.3596 +	0x95020002, 0x00003821, 0x91030009, 0x00442023, 0x01603021, 0x3082ffff,
  2.3597 +	0xa4c00010, 0x00621821, 0x00021042, 0x18400010, 0x00a32821, 0x00404021,
  2.3598 +	0x94c20000, 0x24c60002, 0x00a22821, 0x30c2007f, 0x14400006, 0x24e70001,
  2.3599 +	0x8d430000, 0x3c02007f, 0x3442ff80, 0x00625024, 0x25460008, 0x00e8102a,
  2.3600 +	0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00051c02, 0xa0c00001,
  2.3601 +	0x94c20000, 0x00a22821, 0x00051c02, 0x30a2ffff, 0x00622821, 0x00051402,
  2.3602 +	0x00a22821, 0x0a000415, 0x30a5ffff, 0x14c20063, 0x00000000, 0x3c090800,
  2.3603 +	0x95291fb2, 0x95030002, 0x01a91023, 0x1062005d, 0x01003021, 0x00003821,
  2.3604 +	0x00002821, 0x01a91023, 0xa5020002, 0x3082ffff, 0x00021042, 0x18400008,
  2.3605 +	0xa500000a, 0x00401821, 0x94c20000, 0x24e70001, 0x00a22821, 0x00e3102a,
  2.3606 +	0x1440fffb, 0x24c60002, 0x00051c02, 0x30a2ffff, 0x00622821, 0x00051402,
  2.3607 +	0x00a22821, 0x00a04821, 0x00051027, 0xa502000a, 0x00002821, 0x2506000c,
  2.3608 +	0x00003821, 0x94c20000, 0x24e70001, 0x00a22821, 0x2ce20004, 0x1440fffb,
  2.3609 +	0x24c60002, 0x95020002, 0x00003821, 0x91030009, 0x00442023, 0x01603021,
  2.3610 +	0x3082ffff, 0xa4c00010, 0x3c040800, 0x94841fb4, 0x00621821, 0x00a32821,
  2.3611 +	0x00051c02, 0x30a2ffff, 0x00622821, 0x00051c02, 0x3c020800, 0x94421fb0,
  2.3612 +	0x00a34021, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043, 0x18400010,
  2.3613 +	0x00002821, 0x00402021, 0x94c20000, 0x24c60002, 0x00a22821, 0x30c2007f,
  2.3614 +	0x14400006, 0x24e70001, 0x8d430000, 0x3c02007f, 0x3442ff80, 0x00625024,
  2.3615 +	0x25460008, 0x00e4102a, 0x1440fff3, 0x00000000, 0x3c020800, 0x94421fcc,
  2.3616 +	0x00a22821, 0x00051c02, 0x30a2ffff, 0x00622821, 0x00051402, 0x00a22821,
  2.3617 +	0x3102ffff, 0x00a22821, 0x00051c02, 0x30a2ffff, 0x00622821, 0x00051402,
  2.3618 +	0x00a22821, 0x00a02021, 0x00051027, 0xa5620010, 0xad800014, 0x0a000435,
  2.3619 +	0xad800000, 0x8d830010, 0x00602021, 0x10a00007, 0x00034c02, 0x01252821,
  2.3620 +	0x00051402, 0x30a3ffff, 0x00432821, 0x00051402, 0x00a24821, 0x00091027,
  2.3621 +	0xa502000a, 0x3c030800, 0x94631fb4, 0x3082ffff, 0x01a21021, 0x00432823,
  2.3622 +	0x00a72821, 0x00051c02, 0x30a2ffff, 0x00622821, 0x00051402, 0x00a22821,
  2.3623 +	0x00a02021, 0x00051027, 0xa5620010, 0x3082ffff, 0x00091c00, 0x00431025,
  2.3624 +	0xad820010, 0x3c020800, 0x8c421fd4, 0x10400002, 0x25a2fff2, 0xa5820034,
  2.3625 +	0x3c020800, 0x8c421fc8, 0x3c030800, 0x8c631720, 0x24420001, 0x3c010800,
  2.3626 +	0xac221fc8, 0x3c020800, 0x8c421fc4, 0x31c4ffff, 0x00641821, 0x3c010800,
  2.3627 +	0xac231720, 0x00441021, 0x3c010800, 0xac221fc4, 0x03e00008, 0x27bd0020,
  2.3628 +	0x27bdffc8, 0x3c040800, 0x248416f8, 0xafbf0034, 0xafbe0030, 0xafb7002c,
  2.3629 +	0xafb60028, 0xafb50024, 0xafb40020, 0xafb3001c, 0xafb20018, 0xafb10014,
  2.3630 +	0xafb00010, 0x90830000, 0x24020003, 0x146200f4, 0x00000000, 0x3c020800,
  2.3631 +	0x8c421710, 0x3c030800, 0x8c63170c, 0x3c1e0800, 0x97de16f6, 0x0043102a,
  2.3632 +	0x104000eb, 0x3c168000, 0x249708c4, 0x33d5ffff, 0x24920018, 0x3c020800,
  2.3633 +	0x8c421718, 0x104000e4, 0x00000000, 0x3c140800, 0x96941fb0, 0x3282ffff,
  2.3634 +	0x104000d6, 0x00008021, 0x00409821, 0x00008821, 0x8f634450, 0x3c020800,
  2.3635 +	0x8c4216e8, 0x00031c02, 0x0043102b, 0x14400008, 0x00000000, 0x3c040800,
  2.3636 +	0x8c8416ec, 0x8f624450, 0x00021c02, 0x0083102b, 0x1040fffc, 0x00000000,
  2.3637 +	0xaf764444, 0x8f624444, 0x00561024, 0x10400006, 0x00000000, 0x3c038000,
  2.3638 +	0x8f624444, 0x00431024, 0x1440fffd, 0x00000000, 0x8f624448, 0x3046ffff,
  2.3639 +	0x10c0005f, 0x00000000, 0x3c090800, 0x01314821, 0x8d291728, 0x9528000a,
  2.3640 +	0x31020040, 0x10400004, 0x2407180c, 0x8d22000c, 0x2407188c, 0xacc20018,
  2.3641 +	0x31021000, 0x10400004, 0x34e32000, 0x00081040, 0x3042c000, 0x00623825,
  2.3642 +	0x31020080, 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421730,
  2.3643 +	0x3c030800, 0x00711821, 0x8c631734, 0x00021500, 0x00031c00, 0x00431025,
  2.3644 +	0xacc20014, 0x95240008, 0x3202ffff, 0x00821021, 0x0262102a, 0x14400002,
  2.3645 +	0x02902823, 0x00802821, 0x8d220000, 0x02058021, 0xacc20000, 0x8d220004,
  2.3646 +	0x00c02021, 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e,
  2.3647 +	0xac820010, 0x24020305, 0x0e000560, 0xa482000c, 0x3202ffff, 0x0053102b,
  2.3648 +	0x1440ffaf, 0x3202ffff, 0x0a00054c, 0x00000000, 0x8e420000, 0x8e43fffc,
  2.3649 +	0x0043102a, 0x10400084, 0x00000000, 0x8e45fff0, 0x8f644450, 0x3c030800,
  2.3650 +	0x8c6316e8, 0x00051100, 0x3c090800, 0x01224821, 0x8d291728, 0x00041402,
  2.3651 +	0x0062182b, 0x14600008, 0x00000000, 0x3c030800, 0x8c6316ec, 0x8f624450,
  2.3652 +	0x00021402, 0x0062102b, 0x1040fffc, 0x00000000, 0xaf764444, 0x8f624444,
  2.3653 +	0x00561024, 0x10400006, 0x00000000, 0x3c038000, 0x8f624444, 0x00431024,
  2.3654 +	0x1440fffd, 0x00000000, 0x8f624448, 0x3046ffff, 0x14c00005, 0x00000000,
  2.3655 +	0x8ee20000, 0x24420001, 0x0a000554, 0xaee20000, 0x9528000a, 0x31020040,
  2.3656 +	0x10400004, 0x2407180c, 0x8d22000c, 0x2407188c, 0xacc20018, 0x31021000,
  2.3657 +	0x10400004, 0x34e32000, 0x00081040, 0x3042c000, 0x00623825, 0x00051900,
  2.3658 +	0x3c020800, 0x00431021, 0x8c421730, 0x3c010800, 0x00230821, 0x8c231734,
  2.3659 +	0x00021500, 0x00031c00, 0x00431025, 0xacc20014, 0x3c030800, 0x8c631704,
  2.3660 +	0x95220008, 0x00432023, 0x3202ffff, 0x3083ffff, 0x00431021, 0x02a2102a,
  2.3661 +	0x14400002, 0x03d02823, 0x00802821, 0x8e420000, 0x30a4ffff, 0x00441021,
  2.3662 +	0xae420000, 0xa4c5000e, 0x8d220000, 0xacc20000, 0x8d220004, 0x8e43fff4,
  2.3663 +	0x00431021, 0xacc20004, 0x8e43fff4, 0x95220008, 0x00641821, 0x0062102a,
  2.3664 +	0x14400006, 0x02058021, 0x8e42fff0, 0xae40fff4, 0x24420001, 0x0a000530,
  2.3665 +	0xae42fff0, 0xae43fff4, 0xacc00008, 0x3202ffff, 0x10550003, 0x31020004,
  2.3666 +	0x10400006, 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020,
  2.3667 +	0x24020905, 0xa4c2000c, 0x30e2ffff, 0xacc20010, 0x3c030800, 0x8c63170c,
  2.3668 +	0x3c020800, 0x8c421710, 0x54620004, 0x3c02b49a, 0x3c024b65, 0x0a000548,
  2.3669 +	0x34427654, 0x344289ab, 0xacc2001c, 0x0e000560, 0x00c02021, 0x3202ffff,
  2.3670 +	0x0055102b, 0x1440ff7e, 0x00000000, 0x8e420000, 0x8e43fffc, 0x0043102a,
  2.3671 +	0x1440ff1a, 0x00000000, 0x8fbf0034, 0x8fbe0030, 0x8fb7002c, 0x8fb60028,
  2.3672 +	0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010,
  2.3673 +	0x03e00008, 0x27bd0038, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
  2.3674 +	0x8f634410, 0x0a00056f, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
  2.3675 +	0x00000000, 0x0e00025a, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
  2.3676 +	0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
  2.3677 +	0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c4216b4, 0x3063000f,
  2.3678 +	0x24420001, 0x3c010800, 0xac2216b4, 0x2c620002, 0x1040fff7, 0x00000000,
  2.3679 +	0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
  2.3680 +	0x30422000, 0x1040fff8, 0x00000000, 0x0e00025a, 0x00002021, 0x0a000582,
  2.3681 +	0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
  2.3682 +	0x00000000
  2.3683 +};
  2.3684 +
  2.3685 +u32 tg3TsoFwRodata[] = {
  2.3686 +	0x4d61696e, 0x43707542, 0x00000000, 0x00000000, 0x74637073, 0x6567496e,
  2.3687 +	0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000, 0x00000000,
  2.3688 +	0x00000000
  2.3689 +};
  2.3690 +
  2.3691 +#if 0 /* All zeros, dont eat up space with it. */
  2.3692 +u32 tg3TsoFwData[] = {
  2.3693 +	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  2.3694 +	0x00000000, 0x00000000, 0x00000000
  2.3695 +};
  2.3696 +#endif
  2.3697 +
  2.3698 +/* tp->lock is held. */
  2.3699 +static int tg3_load_tso_firmware(struct tg3 *tp)
  2.3700 +{
  2.3701 +	struct fw_info info;
  2.3702 +	int err, i;
  2.3703 +
  2.3704 +	info.text_base = TG3_TSO_FW_TEXT_ADDR;
  2.3705 +	info.text_len = TG3_TSO_FW_TEXT_LEN;
  2.3706 +	info.text_data = &tg3TsoFwText[0];
  2.3707 +	info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
  2.3708 +	info.rodata_len = TG3_TSO_FW_RODATA_LEN;
  2.3709 +	info.rodata_data = &tg3TsoFwRodata[0];
  2.3710 +	info.data_base = TG3_TSO_FW_DATA_ADDR;
  2.3711 +	info.data_len = TG3_TSO_FW_DATA_LEN;
  2.3712 +	info.data_data = NULL;
  2.3713 +
  2.3714 +	err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  2.3715 +				    TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  2.3716 +				    &info);
  2.3717 +	if (err)
  2.3718 +		return err;
  2.3719 +
  2.3720 +	/* Now startup only the TX cpu. */
  2.3721 +	tw32(TX_CPU_BASE + CPU_STATE, 0xffffffff);
  2.3722 +	tw32(TX_CPU_BASE + CPU_PC,    TG3_TSO_FW_TEXT_ADDR);
  2.3723 +
  2.3724 +	/* Flush posted writes. */
  2.3725 +	tr32(TX_CPU_BASE + CPU_PC);
  2.3726 +	for (i = 0; i < 5; i++) {
  2.3727 +		if (tr32(TX_CPU_BASE + CPU_PC) == TG3_TSO_FW_TEXT_ADDR)
  2.3728 +			break;
  2.3729 +		tw32(TX_CPU_BASE + CPU_STATE, 0xffffffff);
  2.3730 +		tw32(TX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
  2.3731 +		tw32(TX_CPU_BASE + CPU_PC,    TG3_TSO_FW_TEXT_ADDR);
  2.3732 +
  2.3733 +		/* Flush posted writes. */
  2.3734 +		tr32(TX_CPU_BASE + CPU_PC);
  2.3735 +
  2.3736 +		udelay(1000);
  2.3737 +	}
  2.3738 +	if (i >= 5) {
  2.3739 +		printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
  2.3740 +		       "to set TX CPU PC, is %08x should be %08x\n",
  2.3741 +		       tp->dev->name, tr32(TX_CPU_BASE + CPU_PC),
  2.3742 +		       TG3_TSO_FW_TEXT_ADDR);
  2.3743 +		return -ENODEV;
  2.3744 +	}
  2.3745 +	tw32(TX_CPU_BASE + CPU_STATE, 0xffffffff);
  2.3746 +	tw32(TX_CPU_BASE + CPU_MODE,  0x00000000);
  2.3747 +
  2.3748 +	/* Flush posted writes. */
  2.3749 +	tr32(TX_CPU_BASE + CPU_MODE);
  2.3750 +
  2.3751 +	return 0;
  2.3752 +}
  2.3753 +
  2.3754 +#endif /* TG3_DO_TSO != 0 */
  2.3755 +
  2.3756 +/* tp->lock is held. */
  2.3757 +static void __tg3_set_mac_addr(struct tg3 *tp)
  2.3758 +{
  2.3759 +	u32 addr_high, addr_low;
  2.3760 +	int i;
  2.3761 +
  2.3762 +	addr_high = ((tp->dev->dev_addr[0] << 8) |
  2.3763 +		     tp->dev->dev_addr[1]);
  2.3764 +	addr_low = ((tp->dev->dev_addr[2] << 24) |
  2.3765 +		    (tp->dev->dev_addr[3] << 16) |
  2.3766 +		    (tp->dev->dev_addr[4] <<  8) |
  2.3767 +		    (tp->dev->dev_addr[5] <<  0));
  2.3768 +	for (i = 0; i < 4; i++) {
  2.3769 +		tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
  2.3770 +		tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  2.3771 +	}
  2.3772 +
  2.3773 +	addr_high = (tp->dev->dev_addr[0] +
  2.3774 +		     tp->dev->dev_addr[1] +
  2.3775 +		     tp->dev->dev_addr[2] +
  2.3776 +		     tp->dev->dev_addr[3] +
  2.3777 +		     tp->dev->dev_addr[4] +
  2.3778 +		     tp->dev->dev_addr[5]) &
  2.3779 +		TX_BACKOFF_SEED_MASK;
  2.3780 +	tw32(MAC_TX_BACKOFF_SEED, addr_high);
  2.3781 +}
  2.3782 +
  2.3783 +static int tg3_set_mac_addr(struct net_device *dev, void *p)
  2.3784 +{
  2.3785 +	struct tg3 *tp = dev->priv;
  2.3786 +	struct sockaddr *addr = p;
  2.3787 +
  2.3788 +	if (netif_running(dev))
  2.3789 +		return -EBUSY;
  2.3790 +
  2.3791 +	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  2.3792 +
  2.3793 +	spin_lock_irq(&tp->lock);
  2.3794 +	__tg3_set_mac_addr(tp);
  2.3795 +	spin_unlock_irq(&tp->lock);
  2.3796 +
  2.3797 +	return 0;
  2.3798 +}
  2.3799 +
  2.3800 +/* tp->lock is held. */
  2.3801 +static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
  2.3802 +			   dma_addr_t mapping, u32 maxlen_flags,
  2.3803 +			   u32 nic_addr)
  2.3804 +{
  2.3805 +	tg3_write_mem(tp,
  2.3806 +		      (bdinfo_addr +
  2.3807 +		       TG3_BDINFO_HOST_ADDR +
  2.3808 +		       TG3_64BIT_REG_HIGH),
  2.3809 +		      ((u64) mapping >> 32));
  2.3810 +	tg3_write_mem(tp,
  2.3811 +		      (bdinfo_addr +
  2.3812 +		       TG3_BDINFO_HOST_ADDR +
  2.3813 +		       TG3_64BIT_REG_LOW),
  2.3814 +		      ((u64) mapping & 0xffffffff));
  2.3815 +	tg3_write_mem(tp,
  2.3816 +		      (bdinfo_addr +
  2.3817 +		       TG3_BDINFO_MAXLEN_FLAGS),
  2.3818 +		       maxlen_flags);
  2.3819 +	tg3_write_mem(tp,
  2.3820 +		      (bdinfo_addr +
  2.3821 +		       TG3_BDINFO_NIC_ADDR),
  2.3822 +		      nic_addr);
  2.3823 +}
  2.3824 +
  2.3825 +static void __tg3_set_rx_mode(struct net_device *);
  2.3826 +
  2.3827 +/* tp->lock is held. */
  2.3828 +static int tg3_reset_hw(struct tg3 *tp)
  2.3829 +{
  2.3830 +	u32 val;
  2.3831 +	int i, err;
  2.3832 +
  2.3833 +	tg3_disable_ints(tp);
  2.3834 +
  2.3835 +	tg3_stop_fw(tp);
  2.3836 +
  2.3837 +	if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
  2.3838 +		err = tg3_abort_hw(tp);
  2.3839 +		if (err)
  2.3840 +			return err;
  2.3841 +	}
  2.3842 +
  2.3843 +	tg3_chip_reset(tp);
  2.3844 +
  2.3845 +	tw32(GRC_MODE, tp->grc_mode);
  2.3846 +	tg3_write_mem(tp,
  2.3847 +		      NIC_SRAM_FIRMWARE_MBOX,
  2.3848 +		      NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  2.3849 +	if (tp->phy_id == PHY_ID_SERDES) {
  2.3850 +		tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
  2.3851 +		tw32(MAC_MODE, tp->mac_mode);
  2.3852 +	} else
  2.3853 +		tw32(MAC_MODE, 0);
  2.3854 +	tr32(MAC_MODE);
  2.3855 +	udelay(40);
  2.3856 +
  2.3857 +	/* Wait for firmware initialization to complete. */
  2.3858 +	for (i = 0; i < 100000; i++) {
  2.3859 +		tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  2.3860 +		if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  2.3861 +			break;
  2.3862 +		udelay(10);
  2.3863 +	}
  2.3864 +	if (i >= 100000) {
  2.3865 +		printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
  2.3866 +		       "firmware will not restart magic=%08x\n",
  2.3867 +		       tp->dev->name, val);
  2.3868 +		return -ENODEV;
  2.3869 +	}
  2.3870 +
  2.3871 +	if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
  2.3872 +		tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  2.3873 +			      DRV_STATE_START);
  2.3874 +	else
  2.3875 +		tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  2.3876 +			      DRV_STATE_SUSPEND);
  2.3877 +
  2.3878 +	/* This works around an issue with Athlon chipsets on
  2.3879 +	 * B3 tigon3 silicon.  This bit has no effect on any
  2.3880 +	 * other revision.
  2.3881 +	 */
  2.3882 +	val = tr32(TG3PCI_CLOCK_CTRL);
  2.3883 +	val |= CLOCK_CTRL_DELAY_PCI_GRANT;
  2.3884 +	tw32(TG3PCI_CLOCK_CTRL, val);
  2.3885 +	tr32(TG3PCI_CLOCK_CTRL);
  2.3886 +
  2.3887 +	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  2.3888 +	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  2.3889 +		val = tr32(TG3PCI_PCISTATE);
  2.3890 +		val |= PCISTATE_RETRY_SAME_DMA;
  2.3891 +		tw32(TG3PCI_PCISTATE, val);
  2.3892 +	}
  2.3893 +
  2.3894 +	/* Clear statistics/status block in chip, and status block in ram. */
  2.3895 +	for (i = NIC_SRAM_STATS_BLK;
  2.3896 +	     i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  2.3897 +	     i += sizeof(u32)) {
  2.3898 +		tg3_write_mem(tp, i, 0);
  2.3899 +		udelay(40);
  2.3900 +	}
  2.3901 +	memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  2.3902 +
  2.3903 +	/* This value is determined during the probe time DMA
  2.3904 +	 * engine test, tg3_test_dma.
  2.3905 +	 */
  2.3906 +	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  2.3907 +
  2.3908 +	tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
  2.3909 +			  GRC_MODE_4X_NIC_SEND_RINGS |
  2.3910 +			  GRC_MODE_NO_TX_PHDR_CSUM |
  2.3911 +			  GRC_MODE_NO_RX_PHDR_CSUM);
  2.3912 +	if (tp->tg3_flags & TG3_FLAG_HOST_TXDS)
  2.3913 +		tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
  2.3914 +	else
  2.3915 +		tp->grc_mode |= GRC_MODE_4X_NIC_SEND_RINGS;
  2.3916 +	if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
  2.3917 +		tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
  2.3918 +	if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
  2.3919 +		tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
  2.3920 +
  2.3921 +	tw32(GRC_MODE,
  2.3922 +	     tp->grc_mode |
  2.3923 +	     (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
  2.3924 +
  2.3925 +	/* Setup the timer prescalar register.  Clock is always 66Mhz. */
  2.3926 +	tw32(GRC_MISC_CFG,
  2.3927 +	     (65 << GRC_MISC_CFG_PRESCALAR_SHIFT));
  2.3928 +
  2.3929 +	/* Initialize MBUF/DESC pool. */
  2.3930 +	tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  2.3931 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  2.3932 +		tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  2.3933 +	else
  2.3934 +		tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  2.3935 +	tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  2.3936 +	tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  2.3937 +
  2.3938 +	if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
  2.3939 +		tw32(BUFMGR_MB_RDMA_LOW_WATER,
  2.3940 +		     tp->bufmgr_config.mbuf_read_dma_low_water);
  2.3941 +		tw32(BUFMGR_MB_MACRX_LOW_WATER,
  2.3942 +		     tp->bufmgr_config.mbuf_mac_rx_low_water);
  2.3943 +		tw32(BUFMGR_MB_HIGH_WATER,
  2.3944 +		     tp->bufmgr_config.mbuf_high_water);
  2.3945 +	} else {
  2.3946 +		tw32(BUFMGR_MB_RDMA_LOW_WATER,
  2.3947 +		     tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
  2.3948 +		tw32(BUFMGR_MB_MACRX_LOW_WATER,
  2.3949 +		     tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
  2.3950 +		tw32(BUFMGR_MB_HIGH_WATER,
  2.3951 +		     tp->bufmgr_config.mbuf_high_water_jumbo);
  2.3952 +	}
  2.3953 +	tw32(BUFMGR_DMA_LOW_WATER,
  2.3954 +	     tp->bufmgr_config.dma_low_water);
  2.3955 +	tw32(BUFMGR_DMA_HIGH_WATER,
  2.3956 +	     tp->bufmgr_config.dma_high_water);
  2.3957 +
  2.3958 +	tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
  2.3959 +	for (i = 0; i < 2000; i++) {
  2.3960 +		if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
  2.3961 +			break;
  2.3962 +		udelay(10);
  2.3963 +	}
  2.3964 +	if (i >= 2000) {
  2.3965 +		printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
  2.3966 +		       tp->dev->name);
  2.3967 +		return -ENODEV;
  2.3968 +	}
  2.3969 +
  2.3970 +	tw32(FTQ_RESET, 0xffffffff);
  2.3971 +	tw32(FTQ_RESET, 0x00000000);
  2.3972 +	for (i = 0; i < 2000; i++) {
  2.3973 +		if (tr32(FTQ_RESET) == 0x00000000)
  2.3974 +			break;
  2.3975 +		udelay(10);
  2.3976 +	}
  2.3977 +	if (i >= 2000) {
  2.3978 +		printk(KERN_ERR PFX "tg3_reset_hw cannot reset FTQ for %s.\n",
  2.3979 +		       tp->dev->name);
  2.3980 +		return -ENODEV;
  2.3981 +	}
  2.3982 +
  2.3983 +	/* Initialize TG3_BDINFO's at:
  2.3984 +	 *  RCVDBDI_STD_BD:	standard eth size rx ring
  2.3985 +	 *  RCVDBDI_JUMBO_BD:	jumbo frame rx ring
  2.3986 +	 *  RCVDBDI_MINI_BD:	small frame rx ring (??? does not work)
  2.3987 +	 *
  2.3988 +	 * like so:
  2.3989 +	 *  TG3_BDINFO_HOST_ADDR:	high/low parts of DMA address of ring
  2.3990 +	 *  TG3_BDINFO_MAXLEN_FLAGS:	(rx max buffer size << 16) |
  2.3991 +	 *                              ring attribute flags
  2.3992 +	 *  TG3_BDINFO_NIC_ADDR:	location of descriptors in nic SRAM
  2.3993 +	 *
  2.3994 +	 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
  2.3995 +	 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
  2.3996 +	 *
  2.3997 +	 * The size of each ring is fixed in the firmware, but the location is
  2.3998 +	 * configurable.
  2.3999 +	 */
  2.4000 +	tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  2.4001 +	     ((u64) tp->rx_std_mapping >> 32));
  2.4002 +	tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  2.4003 +	     ((u64) tp->rx_std_mapping & 0xffffffff));
  2.4004 +	tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.4005 +	     RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  2.4006 +	tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  2.4007 +	     NIC_SRAM_RX_BUFFER_DESC);
  2.4008 +
  2.4009 +	tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.4010 +	     BDINFO_FLAGS_DISABLED);
  2.4011 +
  2.4012 +	if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
  2.4013 +		tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  2.4014 +		     ((u64) tp->rx_jumbo_mapping >> 32));
  2.4015 +		tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  2.4016 +		     ((u64) tp->rx_jumbo_mapping & 0xffffffff));
  2.4017 +		tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.4018 +		     RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  2.4019 +		tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  2.4020 +		     NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  2.4021 +	} else {
  2.4022 +		tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.4023 +		     BDINFO_FLAGS_DISABLED);
  2.4024 +	}
  2.4025 +
  2.4026 +	/* Setup replenish thresholds. */
  2.4027 +	tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
  2.4028 +	tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
  2.4029 +
  2.4030 +	/* Clear out send RCB ring in SRAM. */
  2.4031 +	for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
  2.4032 +		tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED);
  2.4033 +
  2.4034 +	tp->tx_prod = 0;
  2.4035 +	tp->tx_cons = 0;
  2.4036 +	tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
  2.4037 +	tw32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
  2.4038 +	if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.4039 +		tr32(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW);
  2.4040 +
  2.4041 +	if (tp->tg3_flags & TG3_FLAG_HOST_TXDS) {
  2.4042 +		tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
  2.4043 +			       tp->tx_desc_mapping,
  2.4044 +			       (TG3_TX_RING_SIZE <<
  2.4045 +				BDINFO_FLAGS_MAXLEN_SHIFT),
  2.4046 +			       NIC_SRAM_TX_BUFFER_DESC);
  2.4047 +	} else {
  2.4048 +		tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
  2.4049 +			       0,
  2.4050 +			       BDINFO_FLAGS_DISABLED,
  2.4051 +			       NIC_SRAM_TX_BUFFER_DESC);
  2.4052 +	}
  2.4053 +
  2.4054 +	for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) {
  2.4055 +		tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  2.4056 +			      BDINFO_FLAGS_DISABLED);
  2.4057 +	}
  2.4058 +
  2.4059 +	tp->rx_rcb_ptr = 0;
  2.4060 +	tw32_mailbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
  2.4061 +	if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.4062 +		tr32(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW);
  2.4063 +
  2.4064 +	tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
  2.4065 +		       tp->rx_rcb_mapping,
  2.4066 +		       (TG3_RX_RCB_RING_SIZE <<
  2.4067 +			BDINFO_FLAGS_MAXLEN_SHIFT),
  2.4068 +		       0);
  2.4069 +
  2.4070 +	tp->rx_std_ptr = tp->rx_pending;
  2.4071 +	tw32_mailbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
  2.4072 +		     tp->rx_std_ptr);
  2.4073 +	if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.4074 +		tr32(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW);
  2.4075 +
  2.4076 +	if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)
  2.4077 +		tp->rx_jumbo_ptr = tp->rx_jumbo_pending;
  2.4078 +	else
  2.4079 +		tp->rx_jumbo_ptr = 0;
  2.4080 +	tw32_mailbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
  2.4081 +		     tp->rx_jumbo_ptr);
  2.4082 +	if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  2.4083 +		tr32(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW);
  2.4084 +
  2.4085 +	/* Initialize MAC address and backoff seed. */
  2.4086 +	__tg3_set_mac_addr(tp);
  2.4087 +
  2.4088 +	/* MTU + ethernet header + FCS + optional VLAN tag */
  2.4089 +	tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
  2.4090 +
  2.4091 +	/* The slot time is changed by tg3_setup_phy if we
  2.4092 +	 * run at gigabit with half duplex.
  2.4093 +	 */
  2.4094 +	tw32(MAC_TX_LENGTHS,
  2.4095 +	     (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  2.4096 +	     (6 << TX_LENGTHS_IPG_SHIFT) |
  2.4097 +	     (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
  2.4098 +
  2.4099 +	/* Receive rules. */
  2.4100 +	tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  2.4101 +	tw32(RCVLPC_CONFIG, 0x0181);
  2.4102 +
  2.4103 +	/* Receive/send statistics. */
  2.4104 +	tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  2.4105 +	tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  2.4106 +	tw32(SNDDATAI_STATSENAB, 0xffffff);
  2.4107 +	tw32(SNDDATAI_STATSCTRL,
  2.4108 +	     (SNDDATAI_SCTRL_ENABLE |
  2.4109 +	      SNDDATAI_SCTRL_FASTUPD));
  2.4110 +
  2.4111 +	/* Setup host coalescing engine. */
  2.4112 +	tw32(HOSTCC_MODE, 0);
  2.4113 +	for (i = 0; i < 2000; i++) {
  2.4114 +		if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
  2.4115 +			break;
  2.4116 +		udelay(10);
  2.4117 +	}
  2.4118 +
  2.4119 +	tw32(HOSTCC_RXCOL_TICKS, 0);
  2.4120 +	tw32(HOSTCC_RXMAX_FRAMES, 1);
  2.4121 +	tw32(HOSTCC_RXCOAL_TICK_INT, 0);
  2.4122 +	tw32(HOSTCC_RXCOAL_MAXF_INT, 1);
  2.4123 +	tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
  2.4124 +	tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
  2.4125 +	tw32(HOSTCC_TXCOAL_TICK_INT, 0);
  2.4126 +	tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
  2.4127 +	tw32(HOSTCC_STAT_COAL_TICKS,
  2.4128 +	     DEFAULT_STAT_COAL_TICKS);
  2.4129 +
  2.4130 +	/* Status/statistics block address. */
  2.4131 +	tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  2.4132 +	     ((u64) tp->stats_mapping >> 32));
  2.4133 +	tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  2.4134 +	     ((u64) tp->stats_mapping & 0xffffffff));
  2.4135 +	tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  2.4136 +	     ((u64) tp->status_mapping >> 32));
  2.4137 +	tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  2.4138 +	     ((u64) tp->status_mapping & 0xffffffff));
  2.4139 +	tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  2.4140 +	tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  2.4141 +
  2.4142 +	tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  2.4143 +
  2.4144 +	tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  2.4145 +	tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  2.4146 +	tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  2.4147 +
  2.4148 +	tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  2.4149 +		MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
  2.4150 +	tw32(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
  2.4151 +	tr32(MAC_MODE);
  2.4152 +	udelay(40);
  2.4153 +
  2.4154 +	tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
  2.4155 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  2.4156 +		tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  2.4157 +				       GRC_LCLCTRL_GPIO_OUTPUT1);
  2.4158 +	tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  2.4159 +	tr32(GRC_LOCAL_CTRL);
  2.4160 +	udelay(100);
  2.4161 +
  2.4162 +	tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
  2.4163 +	tr32(MAILBOX_INTERRUPT_0);
  2.4164 +
  2.4165 +	tw32(DMAC_MODE, DMAC_MODE_ENABLE);
  2.4166 +	tr32(DMAC_MODE);
  2.4167 +	udelay(40);
  2.4168 +
  2.4169 +	tw32(WDMAC_MODE, (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  2.4170 +			  WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  2.4171 +			  WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  2.4172 +			  WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  2.4173 +			  WDMAC_MODE_LNGREAD_ENAB));
  2.4174 +	tr32(WDMAC_MODE);
  2.4175 +	udelay(40);
  2.4176 +
  2.4177 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
  2.4178 +	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  2.4179 +		val = tr32(TG3PCI_X_CAPS);
  2.4180 +		val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
  2.4181 +		val |= (PCIX_CAPS_MAX_BURST_5704 << PCIX_CAPS_BURST_SHIFT);
  2.4182 +		if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
  2.4183 +			val |= (tp->split_mode_max_reqs <<
  2.4184 +				PCIX_CAPS_SPLIT_SHIFT);
  2.4185 +		tw32(TG3PCI_X_CAPS, val);
  2.4186 +	}
  2.4187 +
  2.4188 +	val = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  2.4189 +	       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  2.4190 +	       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  2.4191 +	       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  2.4192 +	       RDMAC_MODE_LNGREAD_ENAB);
  2.4193 +	if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
  2.4194 +		val |= RDMAC_MODE_SPLIT_ENABLE;
  2.4195 +	tw32(RDMAC_MODE, val);
  2.4196 +	tr32(RDMAC_MODE);
  2.4197 +	udelay(40);
  2.4198 +
  2.4199 +	tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  2.4200 +	tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  2.4201 +	tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  2.4202 +	tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  2.4203 +	tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  2.4204 +	tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
  2.4205 +	tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  2.4206 +	tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
  2.4207 +	tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
  2.4208 +
  2.4209 +	if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
  2.4210 +		err = tg3_load_5701_a0_firmware_fix(tp);
  2.4211 +		if (err)
  2.4212 +			return err;
  2.4213 +	}
  2.4214 +
  2.4215 +#if TG3_DO_TSO != 0
  2.4216 +	err = tg3_load_tso_firmware(tp);
  2.4217 +	if (err)
  2.4218 +		return err;
  2.4219 +#endif
  2.4220 +
  2.4221 +	tp->tx_mode = TX_MODE_ENABLE;
  2.4222 +	tw32(MAC_TX_MODE, tp->tx_mode);
  2.4223 +	tr32(MAC_TX_MODE);
  2.4224 +	udelay(100);
  2.4225 +
  2.4226 +	tp->rx_mode = RX_MODE_ENABLE;
  2.4227 +	tw32(MAC_RX_MODE, tp->rx_mode);
  2.4228 +	tr32(MAC_RX_MODE);
  2.4229 +	udelay(10);
  2.4230 +
  2.4231 +	if (tp->link_config.phy_is_low_power) {
  2.4232 +		tp->link_config.phy_is_low_power = 0;
  2.4233 +		tp->link_config.speed = tp->link_config.orig_speed;
  2.4234 +		tp->link_config.duplex = tp->link_config.orig_duplex;
  2.4235 +		tp->link_config.autoneg = tp->link_config.orig_autoneg;
  2.4236 +	}
  2.4237 +
  2.4238 +	tp->mi_mode = MAC_MI_MODE_BASE;
  2.4239 +	tw32(MAC_MI_MODE, tp->mi_mode);
  2.4240 +	tr32(MAC_MI_MODE);
  2.4241 +	udelay(40);
  2.4242 +
  2.4243 +	tw32(MAC_LED_CTRL, 0);
  2.4244 +	tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  2.4245 +	tw32(MAC_RX_MODE, RX_MODE_RESET);
  2.4246 +	tr32(MAC_RX_MODE);
  2.4247 +	udelay(10);
  2.4248 +	tw32(MAC_RX_MODE, tp->rx_mode);
  2.4249 +	tr32(MAC_RX_MODE);
  2.4250 +	udelay(10);
  2.4251 +
  2.4252 +	if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
  2.4253 +		tw32(MAC_SERDES_CFG, 0x616000);
  2.4254 +
  2.4255 +	err = tg3_setup_phy(tp);
  2.4256 +	if (err)
  2.4257 +		return err;
  2.4258 +
  2.4259 +	if (tp->phy_id != PHY_ID_SERDES) {
  2.4260 +		u32 tmp;
  2.4261 +
  2.4262 +		/* Clear CRC stats. */
  2.4263 +		tg3_readphy(tp, 0x1e, &tmp);
  2.4264 +		tg3_writephy(tp, 0x1e, tmp | 0x8000);
  2.4265 +		tg3_readphy(tp, 0x14, &tmp);
  2.4266 +	}
  2.4267 +
  2.4268 +	__tg3_set_rx_mode(tp->dev);
  2.4269 +
  2.4270 +	/* Initialize receive rules. */
  2.4271 +	tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
  2.4272 +	tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  2.4273 +	tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
  2.4274 +	tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  2.4275 +#if 0
  2.4276 +	tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0);
  2.4277 +	tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0);
  2.4278 +#endif
  2.4279 +	tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
  2.4280 +	tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
  2.4281 +	tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
  2.4282 +	tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
  2.4283 +	tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
  2.4284 +	tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
  2.4285 +	tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
  2.4286 +	tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
  2.4287 +	tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
  2.4288 +	tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
  2.4289 +	tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
  2.4290 +	tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
  2.4291 +
  2.4292 +	if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
  2.4293 +		tg3_enable_ints(tp);
  2.4294 +
  2.4295 +	return 0;
  2.4296 +}
  2.4297 +
  2.4298 +/* Called at device open time to get the chip ready for
  2.4299 + * packet processing.  Invoked with tp->lock held.
  2.4300 + */
  2.4301 +static int tg3_init_hw(struct tg3 *tp)
  2.4302 +{
  2.4303 +	int err;
  2.4304 +
  2.4305 +	/* Force the chip into D0. */
  2.4306 +	err = tg3_set_power_state(tp, 0);
  2.4307 +	if (err)
  2.4308 +		goto out;
  2.4309 +
  2.4310 +	tg3_switch_clocks(tp);
  2.4311 +
  2.4312 +	tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  2.4313 +
  2.4314 +	err = tg3_reset_hw(tp);
  2.4315 +
  2.4316 +out:
  2.4317 +	return err;
  2.4318 +}
  2.4319 +
  2.4320 +static void tg3_timer(unsigned long __opaque)
  2.4321 +{
  2.4322 +	struct tg3 *tp = (struct tg3 *) __opaque;
  2.4323 +	unsigned long flags;
  2.4324 +
  2.4325 +	spin_lock_irqsave(&tp->lock, flags);
  2.4326 +	spin_lock(&tp->tx_lock);
  2.4327 +
  2.4328 +	/* All of this garbage is because when using non-tagged
  2.4329 +	 * IRQ status the mailbox/status_block protocol the chip
  2.4330 +	 * uses with the cpu is race prone.
  2.4331 +	 */
  2.4332 +	if (tp->hw_status->status & SD_STATUS_UPDATED) {
  2.4333 +		tw32(GRC_LOCAL_CTRL,
  2.4334 +		     tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  2.4335 +	} else {
  2.4336 +		tw32(HOSTCC_MODE, tp->coalesce_mode |
  2.4337 +		     (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  2.4338 +	}
  2.4339 +
  2.4340 +	if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  2.4341 +		tg3_halt(tp);
  2.4342 +		tg3_init_rings(tp);
  2.4343 +		tg3_init_hw(tp);
  2.4344 +	}
  2.4345 +
  2.4346 +	/* This part only runs once per second. */
  2.4347 +	if (!--tp->timer_counter) {
  2.4348 +		if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  2.4349 +			u32 mac_stat;
  2.4350 +			int phy_event;
  2.4351 +
  2.4352 +			mac_stat = tr32(MAC_STATUS);
  2.4353 +
  2.4354 +			phy_event = 0;
  2.4355 +			if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
  2.4356 +				if (mac_stat & MAC_STATUS_MI_INTERRUPT)
  2.4357 +					phy_event = 1;
  2.4358 +			} else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
  2.4359 +				phy_event = 1;
  2.4360 +
  2.4361 +			if (phy_event)
  2.4362 +				tg3_setup_phy(tp);
  2.4363 +		} else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
  2.4364 +			u32 mac_stat = tr32(MAC_STATUS);
  2.4365 +			int need_setup = 0;
  2.4366 +
  2.4367 +			if (netif_carrier_ok(tp->dev) &&
  2.4368 +			    (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
  2.4369 +				need_setup = 1;
  2.4370 +			}
  2.4371 +			if (! netif_carrier_ok(tp->dev) &&
  2.4372 +			    (mac_stat & MAC_STATUS_PCS_SYNCED)) {
  2.4373 +				need_setup = 1;
  2.4374 +			}
  2.4375 +			if (need_setup) {
  2.4376 +				tw32(MAC_MODE,
  2.4377 +				     (tp->mac_mode &
  2.4378 +				      ~MAC_MODE_PORT_MODE_MASK));
  2.4379 +				tr32(MAC_MODE);
  2.4380 +				udelay(40);
  2.4381 +				tw32(MAC_MODE, tp->mac_mode);
  2.4382 +				tr32(MAC_MODE);
  2.4383 +				udelay(40);
  2.4384 +				tg3_setup_phy(tp);
  2.4385 +			}
  2.4386 +		}
  2.4387 +
  2.4388 +		tp->timer_counter = tp->timer_multiplier;
  2.4389 +	}
  2.4390 +
  2.4391 +	/* Heartbeat is only sent once every 120 seconds.  */
  2.4392 +	if (!--tp->asf_counter) {
  2.4393 +		if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  2.4394 +			u32 val;
  2.4395 +
  2.4396 +			tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
  2.4397 +			tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
  2.4398 +			tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
  2.4399 +			val = tr32(GRC_RX_CPU_EVENT);
  2.4400 +			val |= (1 << 14);
  2.4401 +			tw32(GRC_RX_CPU_EVENT, val);
  2.4402 +		}
  2.4403 +		tp->asf_counter = tp->asf_multiplier;
  2.4404 +	}
  2.4405 +
  2.4406 +	spin_unlock(&tp->tx_lock);
  2.4407 +	spin_unlock_irqrestore(&tp->lock, flags);
  2.4408 +
  2.4409 +	tp->timer.expires = jiffies + tp->timer_offset;
  2.4410 +	add_timer(&tp->timer);
  2.4411 +}
  2.4412 +
  2.4413 +static int tg3_open(struct net_device *dev)
  2.4414 +{
  2.4415 +	struct tg3 *tp = dev->priv;
  2.4416 +	int err;
  2.4417 +
  2.4418 +	spin_lock_irq(&tp->lock);
  2.4419 +	spin_lock(&tp->tx_lock);
  2.4420 +
  2.4421 +	tg3_disable_ints(tp);
  2.4422 +	tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  2.4423 +
  2.4424 +	spin_unlock(&tp->tx_lock);
  2.4425 +	spin_unlock_irq(&tp->lock);
  2.4426 +
  2.4427 +	/* If you move this call, make sure TG3_FLAG_HOST_TXDS in
  2.4428 +	 * tp->tg3_flags is accurate at that new place.
  2.4429 +	 */
  2.4430 +	err = tg3_alloc_consistent(tp);
  2.4431 +	if (err)
  2.4432 +		return err;
  2.4433 +
  2.4434 +	err = request_irq(dev->irq, tg3_interrupt,
  2.4435 +			  SA_SHIRQ, dev->name, dev);
  2.4436 +
  2.4437 +	if (err) {
  2.4438 +		tg3_free_consistent(tp);
  2.4439 +		return err;
  2.4440 +	}
  2.4441 +
  2.4442 +	spin_lock_irq(&tp->lock);
  2.4443 +	spin_lock(&tp->tx_lock);
  2.4444 +
  2.4445 +	tg3_init_rings(tp);
  2.4446 +
  2.4447 +	err = tg3_init_hw(tp);
  2.4448 +	if (err) {
  2.4449 +		tg3_halt(tp);
  2.4450 +		tg3_free_rings(tp);
  2.4451 +	} else {
  2.4452 +		tp->timer_offset = HZ / 10;
  2.4453 +		tp->timer_counter = tp->timer_multiplier = 10;
  2.4454 +		tp->asf_counter = tp->asf_multiplier = (10 * 120);
  2.4455 +
  2.4456 +		init_timer(&tp->timer);
  2.4457 +		tp->timer.expires = jiffies + tp->timer_offset;
  2.4458 +		tp->timer.data = (unsigned long) tp;
  2.4459 +		tp->timer.function = tg3_timer;
  2.4460 +		add_timer(&tp->timer);
  2.4461 +
  2.4462 +		tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  2.4463 +	}
  2.4464 +
  2.4465 +	spin_unlock(&tp->tx_lock);
  2.4466 +	spin_unlock_irq(&tp->lock);
  2.4467 +
  2.4468 +	if (err) {
  2.4469 +		free_irq(dev->irq, dev);
  2.4470 +		tg3_free_consistent(tp);
  2.4471 +		return err;
  2.4472 +	}
  2.4473 +
  2.4474 +	netif_start_queue(dev);
  2.4475 +
  2.4476 +	spin_lock_irq(&tp->lock);
  2.4477 +	spin_lock(&tp->tx_lock);
  2.4478 +
  2.4479 +	tg3_enable_ints(tp);
  2.4480 +
  2.4481 +	spin_unlock(&tp->tx_lock);
  2.4482 +	spin_unlock_irq(&tp->lock);
  2.4483 +
  2.4484 +	return 0;
  2.4485 +}
  2.4486 +
  2.4487 +#if 0
  2.4488 +/*static*/ void tg3_dump_state(struct tg3 *tp)
  2.4489 +{
  2.4490 +	u32 val32, val32_2, val32_3, val32_4, val32_5;
  2.4491 +	u16 val16;
  2.4492 +	int i;
  2.4493 +
  2.4494 +	pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
  2.4495 +	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
  2.4496 +	printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
  2.4497 +	       val16, val32);
  2.4498 +
  2.4499 +	/* MAC block */
  2.4500 +	printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
  2.4501 +	       tr32(MAC_MODE), tr32(MAC_STATUS));
  2.4502 +	printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
  2.4503 +	       tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
  2.4504 +	printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
  2.4505 +	       tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
  2.4506 +	printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
  2.4507 +	       tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
  2.4508 +
  2.4509 +	/* Send data initiator control block */
  2.4510 +	printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
  2.4511 +	       tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
  2.4512 +	printk("       SNDDATAI_STATSCTRL[%08x]\n",
  2.4513 +	       tr32(SNDDATAI_STATSCTRL));
  2.4514 +
  2.4515 +	/* Send data completion control block */
  2.4516 +	printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
  2.4517 +
  2.4518 +	/* Send BD ring selector block */
  2.4519 +	printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
  2.4520 +	       tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
  2.4521 +
  2.4522 +	/* Send BD initiator control block */
  2.4523 +	printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
  2.4524 +	       tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
  2.4525 +
  2.4526 +	/* Send BD completion control block */
  2.4527 +	printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
  2.4528 +
  2.4529 +	/* Receive list placement control block */
  2.4530 +	printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
  2.4531 +	       tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
  2.4532 +	printk("       RCVLPC_STATSCTRL[%08x]\n",
  2.4533 +	       tr32(RCVLPC_STATSCTRL));
  2.4534 +
  2.4535 +	/* Receive data and receive BD initiator control block */
  2.4536 +	printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
  2.4537 +	       tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
  2.4538 +
  2.4539 +	/* Receive data completion control block */
  2.4540 +	printk("DEBUG: RCVDCC_MODE[%08x]\n",
  2.4541 +	       tr32(RCVDCC_MODE));
  2.4542 +
  2.4543 +	/* Receive BD initiator control block */
  2.4544 +	printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
  2.4545 +	       tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
  2.4546 +
  2.4547 +	/* Receive BD completion control block */
  2.4548 +	printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
  2.4549 +	       tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
  2.4550 +
  2.4551 +	/* Receive list selector control block */
  2.4552 +	printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
  2.4553 +	       tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
  2.4554 +
  2.4555 +	/* Mbuf cluster free block */
  2.4556 +	printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
  2.4557 +	       tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
  2.4558 +
  2.4559 +	/* Host coalescing control block */
  2.4560 +	printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
  2.4561 +	       tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
  2.4562 +	printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
  2.4563 +	       tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  2.4564 +	       tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  2.4565 +	printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
  2.4566 +	       tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  2.4567 +	       tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  2.4568 +	printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
  2.4569 +	       tr32(HOSTCC_STATS_BLK_NIC_ADDR));
  2.4570 +	printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
  2.4571 +	       tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
  2.4572 +
  2.4573 +	/* Memory arbiter control block */
  2.4574 +	printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
  2.4575 +	       tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
  2.4576 +
  2.4577 +	/* Buffer manager control block */
  2.4578 +	printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
  2.4579 +	       tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
  2.4580 +	printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
  2.4581 +	       tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
  2.4582 +	printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
  2.4583 +	       "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
  2.4584 +	       tr32(BUFMGR_DMA_DESC_POOL_ADDR),
  2.4585 +	       tr32(BUFMGR_DMA_DESC_POOL_SIZE));
  2.4586 +
  2.4587 +	/* Read DMA control block */
  2.4588 +	printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
  2.4589 +	       tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
  2.4590 +
  2.4591 +	/* Write DMA control block */
  2.4592 +	printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
  2.4593 +	       tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
  2.4594 +
  2.4595 +	/* DMA completion block */
  2.4596 +	printk("DEBUG: DMAC_MODE[%08x]\n",
  2.4597 +	       tr32(DMAC_MODE));
  2.4598 +
  2.4599 +	/* GRC block */
  2.4600 +	printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
  2.4601 +	       tr32(GRC_MODE), tr32(GRC_MISC_CFG));
  2.4602 +	printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
  2.4603 +	       tr32(GRC_LOCAL_CTRL));
  2.4604 +
  2.4605 +	/* TG3_BDINFOs */
  2.4606 +	printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
  2.4607 +	       tr32(RCVDBDI_JUMBO_BD + 0x0),
  2.4608 +	       tr32(RCVDBDI_JUMBO_BD + 0x4),
  2.4609 +	       tr32(RCVDBDI_JUMBO_BD + 0x8),
  2.4610 +	       tr32(RCVDBDI_JUMBO_BD + 0xc));
  2.4611 +	printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
  2.4612 +	       tr32(RCVDBDI_STD_BD + 0x0),
  2.4613 +	       tr32(RCVDBDI_STD_BD + 0x4),
  2.4614 +	       tr32(RCVDBDI_STD_BD + 0x8),
  2.4615 +	       tr32(RCVDBDI_STD_BD + 0xc));
  2.4616 +	printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
  2.4617 +	       tr32(RCVDBDI_MINI_BD + 0x0),
  2.4618 +	       tr32(RCVDBDI_MINI_BD + 0x4),
  2.4619 +	       tr32(RCVDBDI_MINI_BD + 0x8),
  2.4620 +	       tr32(RCVDBDI_MINI_BD + 0xc));
  2.4621 +
  2.4622 +	tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
  2.4623 +	tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
  2.4624 +	tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
  2.4625 +	tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
  2.4626 +	printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
  2.4627 +	       val32, val32_2, val32_3, val32_4);
  2.4628 +
  2.4629 +	tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
  2.4630 +	tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
  2.4631 +	tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
  2.4632 +	tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
  2.4633 +	printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
  2.4634 +	       val32, val32_2, val32_3, val32_4);
  2.4635 +
  2.4636 +	tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
  2.4637 +	tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
  2.4638 +	tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
  2.4639 +	tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
  2.4640 +	tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
  2.4641 +	printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
  2.4642 +	       val32, val32_2, val32_3, val32_4, val32_5);
  2.4643 +
  2.4644 +	/* SW status block */
  2.4645 +	printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
  2.4646 +	       tp->hw_status->status,
  2.4647 +	       tp->hw_status->status_tag,
  2.4648 +	       tp->hw_status->rx_jumbo_consumer,
  2.4649 +	       tp->hw_status->rx_consumer,
  2.4650 +	       tp->hw_status->rx_mini_consumer,
  2.4651 +	       tp->hw_status->idx[0].rx_producer,
  2.4652 +	       tp->hw_status->idx[0].tx_consumer);
  2.4653 +
  2.4654 +	/* SW statistics block */
  2.4655 +	printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
  2.4656 +	       ((u32 *)tp->hw_stats)[0],
  2.4657 +	       ((u32 *)tp->hw_stats)[1],
  2.4658 +	       ((u32 *)tp->hw_stats)[2],
  2.4659 +	       ((u32 *)tp->hw_stats)[3]);
  2.4660 +
  2.4661 +	/* Mailboxes */
  2.4662 +	printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
  2.4663 +	       tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
  2.4664 +	       tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
  2.4665 +	       tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
  2.4666 +	       tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
  2.4667 +
  2.4668 +	/* NIC side send descriptors. */
  2.4669 +	for (i = 0; i < 6; i++) {
  2.4670 +		unsigned long txd;
  2.4671 +
  2.4672 +		txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
  2.4673 +			+ (i * sizeof(struct tg3_tx_buffer_desc));
  2.4674 +		printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
  2.4675 +		       i,
  2.4676 +		       readl(txd + 0x0), readl(txd + 0x4),
  2.4677 +		       readl(txd + 0x8), readl(txd + 0xc));
  2.4678 +	}
  2.4679 +
  2.4680 +	/* NIC side RX descriptors. */
  2.4681 +	for (i = 0; i < 6; i++) {
  2.4682 +		unsigned long rxd;
  2.4683 +
  2.4684 +		rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
  2.4685 +			+ (i * sizeof(struct tg3_rx_buffer_desc));
  2.4686 +		printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
  2.4687 +		       i,
  2.4688 +		       readl(rxd + 0x0), readl(rxd + 0x4),
  2.4689 +		       readl(rxd + 0x8), readl(rxd + 0xc));
  2.4690 +		rxd += (4 * sizeof(u32));
  2.4691 +		printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
  2.4692 +		       i,
  2.4693 +		       readl(rxd + 0x0), readl(rxd + 0x4),
  2.4694 +		       readl(rxd + 0x8), readl(rxd + 0xc));
  2.4695 +	}
  2.4696 +
  2.4697 +	for (i = 0; i < 6; i++) {
  2.4698 +		unsigned long rxd;
  2.4699 +
  2.4700 +		rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
  2.4701 +			+ (i * sizeof(struct tg3_rx_buffer_desc));
  2.4702 +		printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
  2.4703 +		       i,
  2.4704 +		       readl(rxd + 0x0), readl(rxd + 0x4),
  2.4705 +		       readl(rxd + 0x8), readl(rxd + 0xc));
  2.4706 +		rxd += (4 * sizeof(u32));
  2.4707 +		printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
  2.4708 +		       i,
  2.4709 +		       readl(rxd + 0x0), readl(rxd + 0x4),
  2.4710 +		       readl(rxd + 0x8), readl(rxd + 0xc));
  2.4711 +	}
  2.4712 +}
  2.4713 +#endif
  2.4714 +
  2.4715 +static struct net_device_stats *tg3_get_stats(struct net_device *);
  2.4716 +
  2.4717 +static int tg3_close(struct net_device *dev)
  2.4718 +{
  2.4719 +	struct tg3 *tp = dev->priv;
  2.4720 +
  2.4721 +	netif_stop_queue(dev);
  2.4722 +
  2.4723 +	del_timer_sync(&tp->timer);
  2.4724 +
  2.4725 +	spin_lock_irq(&tp->lock);
  2.4726 +	spin_lock(&tp->tx_lock);
  2.4727 +#if 0
  2.4728 +	tg3_dump_state(tp);
  2.4729 +#endif
  2.4730 +
  2.4731 +	tg3_disable_ints(tp);
  2.4732 +
  2.4733 +	tg3_halt(tp);
  2.4734 +	tg3_free_rings(tp);
  2.4735 +	tp->tg3_flags &=
  2.4736 +		~(TG3_FLAG_INIT_COMPLETE |
  2.4737 +		  TG3_FLAG_GOT_SERDES_FLOWCTL);
  2.4738 +	netif_carrier_off(tp->dev);
  2.4739 +
  2.4740 +	spin_unlock(&tp->tx_lock);
  2.4741 +	spin_unlock_irq(&tp->lock);
  2.4742 +
  2.4743 +	free_irq(dev->irq, dev);
  2.4744 +
  2.4745 +	memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
  2.4746 +	       sizeof(tp->net_stats_prev));
  2.4747 +
  2.4748 +	tg3_free_consistent(tp);
  2.4749 +
  2.4750 +	return 0;
  2.4751 +}
  2.4752 +
  2.4753 +static inline unsigned long get_stat64(tg3_stat64_t *val)
  2.4754 +{
  2.4755 +	unsigned long ret;
  2.4756 +
  2.4757 +#if (BITS_PER_LONG == 32)
  2.4758 +	ret = val->low;
  2.4759 +#else
  2.4760 +	ret = ((u64)val->high << 32) | ((u64)val->low);
  2.4761 +#endif
  2.4762 +	return ret;
  2.4763 +}
  2.4764 +
  2.4765 +static unsigned long calc_crc_errors(struct tg3 *tp)
  2.4766 +{
  2.4767 +	struct tg3_hw_stats *hw_stats = tp->hw_stats;
  2.4768 +
  2.4769 +	if (tp->phy_id != PHY_ID_SERDES &&
  2.4770 +	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2.4771 +	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  2.4772 +		unsigned long flags;
  2.4773 +		u32 val;
  2.4774 +
  2.4775 +		spin_lock_irqsave(&tp->lock, flags);
  2.4776 +		tg3_readphy(tp, 0x1e, &val);
  2.4777 +		tg3_writephy(tp, 0x1e, val | 0x8000);
  2.4778 +		tg3_readphy(tp, 0x14, &val);
  2.4779 +		spin_unlock_irqrestore(&tp->lock, flags);
  2.4780 +
  2.4781 +		tp->phy_crc_errors += val;
  2.4782 +
  2.4783 +		return tp->phy_crc_errors;
  2.4784 +	}
  2.4785 +
  2.4786 +	return get_stat64(&hw_stats->rx_fcs_errors);
  2.4787 +}
  2.4788 +
  2.4789 +static struct net_device_stats *tg3_get_stats(struct net_device *dev)
  2.4790 +{
  2.4791 +	struct tg3 *tp = dev->priv;
  2.4792 +	struct net_device_stats *stats = &tp->net_stats;
  2.4793 +	struct net_device_stats *old_stats = &tp->net_stats_prev;
  2.4794 +	struct tg3_hw_stats *hw_stats = tp->hw_stats;
  2.4795 +
  2.4796 +	if (!hw_stats)
  2.4797 +		return old_stats;
  2.4798 +
  2.4799 +	stats->rx_packets = old_stats->rx_packets +
  2.4800 +		get_stat64(&hw_stats->rx_ucast_packets) +
  2.4801 +		get_stat64(&hw_stats->rx_mcast_packets) +
  2.4802 +		get_stat64(&hw_stats->rx_bcast_packets);
  2.4803 +		
  2.4804 +	stats->tx_packets = old_stats->tx_packets +
  2.4805 +		get_stat64(&hw_stats->COS_out_packets[0]);
  2.4806 +
  2.4807 +	stats->rx_bytes = old_stats->rx_bytes +
  2.4808 +		get_stat64(&hw_stats->rx_octets);
  2.4809 +	stats->tx_bytes = old_stats->tx_bytes +
  2.4810 +		get_stat64(&hw_stats->tx_octets);
  2.4811 +
  2.4812 +	stats->rx_errors = old_stats->rx_errors +
  2.4813 +		get_stat64(&hw_stats->rx_errors);
  2.4814 +	stats->tx_errors = old_stats->tx_errors +
  2.4815 +		get_stat64(&hw_stats->tx_errors) +
  2.4816 +		get_stat64(&hw_stats->tx_mac_errors) +
  2.4817 +		get_stat64(&hw_stats->tx_carrier_sense_errors) +
  2.4818 +		get_stat64(&hw_stats->tx_discards);
  2.4819 +
  2.4820 +	stats->multicast = old_stats->multicast +
  2.4821 +		get_stat64(&hw_stats->rx_mcast_packets);
  2.4822 +	stats->collisions = old_stats->collisions +
  2.4823 +		get_stat64(&hw_stats->tx_collisions);
  2.4824 +
  2.4825 +	stats->rx_length_errors = old_stats->rx_length_errors +
  2.4826 +		get_stat64(&hw_stats->rx_frame_too_long_errors) +
  2.4827 +		get_stat64(&hw_stats->rx_undersize_packets);
  2.4828 +
  2.4829 +	stats->rx_over_errors = old_stats->rx_over_errors +
  2.4830 +		get_stat64(&hw_stats->rxbds_empty);
  2.4831 +	stats->rx_frame_errors = old_stats->rx_frame_errors +
  2.4832 +		get_stat64(&hw_stats->rx_align_errors);
  2.4833 +	stats->tx_aborted_errors = old_stats->tx_aborted_errors +
  2.4834 +		get_stat64(&hw_stats->tx_discards);
  2.4835 +	stats->tx_carrier_errors = old_stats->tx_carrier_errors +
  2.4836 +		get_stat64(&hw_stats->tx_carrier_sense_errors);
  2.4837 +
  2.4838 +	stats->rx_crc_errors = old_stats->rx_crc_errors +
  2.4839 +		calc_crc_errors(tp);
  2.4840 +
  2.4841 +	return stats;
  2.4842 +}
  2.4843 +
  2.4844 +static inline u32 calc_crc(unsigned char *buf, int len)
  2.4845 +{
  2.4846 +	u32 reg;
  2.4847 +	u32 tmp;
  2.4848 +	int j, k;
  2.4849 +
  2.4850 +	reg = 0xffffffff;
  2.4851 +
  2.4852 +	for (j = 0; j < len; j++) {
  2.4853 +		reg ^= buf[j];
  2.4854 +
  2.4855 +		for (k = 0; k < 8; k++) {
  2.4856 +			tmp = reg & 0x01;
  2.4857 +
  2.4858 +			reg >>= 1;
  2.4859 +
  2.4860 +			if (tmp) {
  2.4861 +				reg ^= 0xedb88320;
  2.4862 +			}
  2.4863 +		}
  2.4864 +	}
  2.4865 +
  2.4866 +	return ~reg;
  2.4867 +}
  2.4868 +
  2.4869 +static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
  2.4870 +{
  2.4871 +	/* accept or reject all multicast frames */
  2.4872 +	tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
  2.4873 +	tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
  2.4874 +	tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
  2.4875 +	tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
  2.4876 +}
  2.4877 +
  2.4878 +static void __tg3_set_rx_mode(struct net_device *dev)
  2.4879 +{
  2.4880 +	struct tg3 *tp = dev->priv;
  2.4881 +	u32 rx_mode;
  2.4882 +
  2.4883 +	rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
  2.4884 +				  RX_MODE_KEEP_VLAN_TAG);
  2.4885 +#if TG3_VLAN_TAG_USED
  2.4886 +	if (!tp->vlgrp)
  2.4887 +		rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  2.4888 +#else
  2.4889 +	/* By definition, VLAN is disabled always in this
  2.4890 +	 * case.
  2.4891 +	 */
  2.4892 +	rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  2.4893 +#endif
  2.4894 +
  2.4895 +	if (dev->flags & IFF_PROMISC) {
  2.4896 +		/* Promiscuous mode. */
  2.4897 +		rx_mode |= RX_MODE_PROMISC;
  2.4898 +	} else if (dev->flags & IFF_ALLMULTI) {
  2.4899 +		/* Accept all multicast. */
  2.4900 +		tg3_set_multi (tp, 1);
  2.4901 +	} else if (dev->mc_count < 1) {
  2.4902 +		/* Reject all multicast. */
  2.4903 +		tg3_set_multi (tp, 0);
  2.4904 +	} else {
  2.4905 +		/* Accept one or more multicast(s). */
  2.4906 +		struct dev_mc_list *mclist;
  2.4907 +		unsigned int i;
  2.4908 +		u32 mc_filter[4] = { 0, };
  2.4909 +		u32 regidx;
  2.4910 +		u32 bit;
  2.4911 +		u32 crc;
  2.4912 +
  2.4913 +		for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  2.4914 +		     i++, mclist = mclist->next) {
  2.4915 +
  2.4916 +			crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
  2.4917 +			bit = ~crc & 0x7f;
  2.4918 +			regidx = (bit & 0x60) >> 5;
  2.4919 +			bit &= 0x1f;
  2.4920 +			mc_filter[regidx] |= (1 << bit);
  2.4921 +		}
  2.4922 +
  2.4923 +		tw32(MAC_HASH_REG_0, mc_filter[0]);
  2.4924 +		tw32(MAC_HASH_REG_1, mc_filter[1]);
  2.4925 +		tw32(MAC_HASH_REG_2, mc_filter[2]);
  2.4926 +		tw32(MAC_HASH_REG_3, mc_filter[3]);
  2.4927 +	}
  2.4928 +
  2.4929 +	if (rx_mode != tp->rx_mode) {
  2.4930 +		tp->rx_mode = rx_mode;
  2.4931 +		tw32(MAC_RX_MODE, rx_mode);
  2.4932 +		tr32(MAC_RX_MODE);
  2.4933 +		udelay(10);
  2.4934 +	}
  2.4935 +}
  2.4936 +
  2.4937 +static void tg3_set_rx_mode(struct net_device *dev)
  2.4938 +{
  2.4939 +	struct tg3 *tp = dev->priv;
  2.4940 +
  2.4941 +	spin_lock_irq(&tp->lock);
  2.4942 +	__tg3_set_rx_mode(dev);
  2.4943 +	spin_unlock_irq(&tp->lock);
  2.4944 +}
  2.4945 +
  2.4946 +#define TG3_REGDUMP_LEN		(32 * 1024)
  2.4947 +
  2.4948 +static u8 *tg3_get_regs(struct tg3 *tp)
  2.4949 +{
  2.4950 +	u8 *orig_p = kmalloc(TG3_REGDUMP_LEN, GFP_KERNEL);
  2.4951 +	u8 *p;
  2.4952 +	int i;
  2.4953 +
  2.4954 +	if (orig_p == NULL)
  2.4955 +		return NULL;
  2.4956 +
  2.4957 +	memset(orig_p, 0, TG3_REGDUMP_LEN);
  2.4958 +
  2.4959 +	spin_lock_irq(&tp->lock);
  2.4960 +	spin_lock(&tp->tx_lock);
  2.4961 +
  2.4962 +#define __GET_REG32(reg)	(*((u32 *)(p))++ = tr32(reg))
  2.4963 +#define GET_REG32_LOOP(base,len)		\
  2.4964 +do {	p = orig_p + (base);			\
  2.4965 +	for (i = 0; i < len; i += 4)		\
  2.4966 +		__GET_REG32((base) + i);	\
  2.4967 +} while (0)
  2.4968 +#define GET_REG32_1(reg)	\
  2.4969 +do {	p = orig_p + (reg);	\
  2.4970 +	__GET_REG32((reg));	\
  2.4971 +} while (0)
  2.4972 +
  2.4973 +	GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
  2.4974 +	GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
  2.4975 +	GET_REG32_LOOP(MAC_MODE, 0x4f0);
  2.4976 +	GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
  2.4977 +	GET_REG32_1(SNDDATAC_MODE);
  2.4978 +	GET_REG32_LOOP(SNDBDS_MODE, 0x80);
  2.4979 +	GET_REG32_LOOP(SNDBDI_MODE, 0x48);
  2.4980 +	GET_REG32_1(SNDBDC_MODE);
  2.4981 +	GET_REG32_LOOP(RCVLPC_MODE, 0x20);
  2.4982 +	GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
  2.4983 +	GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
  2.4984 +	GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
  2.4985 +	GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
  2.4986 +	GET_REG32_1(RCVDCC_MODE);
  2.4987 +	GET_REG32_LOOP(RCVBDI_MODE, 0x20);
  2.4988 +	GET_REG32_LOOP(RCVCC_MODE, 0x14);
  2.4989 +	GET_REG32_LOOP(RCVLSC_MODE, 0x08);
  2.4990 +	GET_REG32_1(MBFREE_MODE);
  2.4991 +	GET_REG32_LOOP(HOSTCC_MODE, 0x100);
  2.4992 +	GET_REG32_LOOP(MEMARB_MODE, 0x10);
  2.4993 +	GET_REG32_LOOP(BUFMGR_MODE, 0x58);
  2.4994 +	GET_REG32_LOOP(RDMAC_MODE, 0x08);
  2.4995 +	GET_REG32_LOOP(WDMAC_MODE, 0x08);
  2.4996 +	GET_REG32_LOOP(RX_CPU_BASE, 0x280);
  2.4997 +	GET_REG32_LOOP(TX_CPU_BASE, 0x280);
  2.4998 +	GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
  2.4999 +	GET_REG32_LOOP(FTQ_RESET, 0x120);
  2.5000 +	GET_REG32_LOOP(MSGINT_MODE, 0x0c);
  2.5001 +	GET_REG32_1(DMAC_MODE);
  2.5002 +	GET_REG32_LOOP(GRC_MODE, 0x4c);
  2.5003 +	GET_REG32_LOOP(NVRAM_CMD, 0x24);
  2.5004 +
  2.5005 +#undef __GET_REG32
  2.5006 +#undef GET_REG32_LOOP
  2.5007 +#undef GET_REG32_1
  2.5008 +
  2.5009 +	spin_unlock(&tp->tx_lock);
  2.5010 +	spin_unlock_irq(&tp->lock);
  2.5011 +
  2.5012 +	return orig_p;
  2.5013 +}
  2.5014 +
  2.5015 +static int tg3_ethtool_ioctl (struct net_device *dev, void *useraddr)
  2.5016 +{
  2.5017 +	struct tg3 *tp = dev->priv;
  2.5018 +	struct pci_dev *pci_dev = tp->pdev;
  2.5019 +	u32 ethcmd;
  2.5020 +
  2.5021 +	if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
  2.5022 +		return -EFAULT;
  2.5023 +
  2.5024 +	switch (ethcmd) {
  2.5025 +	case ETHTOOL_GDRVINFO:{
  2.5026 +		struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
  2.5027 +		strcpy (info.driver, DRV_MODULE_NAME);
  2.5028 +		strcpy (info.version, DRV_MODULE_VERSION);
  2.5029 +		memset(&info.fw_version, 0, sizeof(info.fw_version));
  2.5030 +		strcpy (info.bus_info, pci_dev->slot_name);
  2.5031 +		info.eedump_len = 0;
  2.5032 +		info.regdump_len = TG3_REGDUMP_LEN;
  2.5033 +		if (copy_to_user (useraddr, &info, sizeof (info)))
  2.5034 +			return -EFAULT;
  2.5035 +		return 0;
  2.5036 +	}
  2.5037 +
  2.5038 +	case ETHTOOL_GSET: {
  2.5039 +		struct ethtool_cmd cmd = { ETHTOOL_GSET };
  2.5040 +
  2.5041 +		if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
  2.5042 +		    tp->link_config.phy_is_low_power)
  2.5043 +			return -EAGAIN;
  2.5044 +		cmd.supported = (SUPPORTED_Autoneg);
  2.5045 +
  2.5046 +		if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  2.5047 +			cmd.supported |= (SUPPORTED_1000baseT_Half |
  2.5048 +					  SUPPORTED_1000baseT_Full);
  2.5049 +
  2.5050 +		if (tp->phy_id != PHY_ID_SERDES)
  2.5051 +			cmd.supported |= (SUPPORTED_100baseT_Half |
  2.5052 +					  SUPPORTED_100baseT_Full |
  2.5053 +					  SUPPORTED_10baseT_Half |
  2.5054 +					  SUPPORTED_10baseT_Full |
  2.5055 +					  SUPPORTED_MII);
  2.5056 +		else
  2.5057 +			cmd.supported |= SUPPORTED_FIBRE;
  2.5058 +
  2.5059 +		cmd.advertising = tp->link_config.advertising;
  2.5060 +		cmd.speed = tp->link_config.active_speed;
  2.5061 +		cmd.duplex = tp->link_config.active_duplex;
  2.5062 +		cmd.port = 0;
  2.5063 +		cmd.phy_address = PHY_ADDR;
  2.5064 +		cmd.transceiver = 0;
  2.5065 +		cmd.autoneg = tp->link_config.autoneg;
  2.5066 +		cmd.maxtxpkt = 0;
  2.5067 +		cmd.maxrxpkt = 0;
  2.5068 +		if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
  2.5069 +			return -EFAULT;
  2.5070 +		return 0;
  2.5071 +	}
  2.5072 +	case ETHTOOL_SSET: {
  2.5073 +		struct ethtool_cmd cmd;
  2.5074 +
  2.5075 +		if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
  2.5076 +		    tp->link_config.phy_is_low_power)
  2.5077 +			return -EAGAIN;
  2.5078 +
  2.5079 +		if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
  2.5080 +			return -EFAULT;
  2.5081 +
  2.5082 +		/* Fiber PHY only supports 1000 full/half */
  2.5083 +		if (cmd.autoneg == AUTONEG_ENABLE) {
  2.5084 +			if (tp->phy_id == PHY_ID_SERDES &&
  2.5085 +			    (cmd.advertising &
  2.5086 +			     (ADVERTISED_10baseT_Half |
  2.5087 +			      ADVERTISED_10baseT_Full |
  2.5088 +			      ADVERTISED_100baseT_Half |
  2.5089 +			      ADVERTISED_100baseT_Full)))
  2.5090 +				return -EINVAL;
  2.5091 +			if ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
  2.5092 +			    (cmd.advertising &
  2.5093 +			     (ADVERTISED_1000baseT_Half |
  2.5094 +			      ADVERTISED_1000baseT_Full)))
  2.5095 +				return -EINVAL;
  2.5096 +		} else {
  2.5097 +			if (tp->phy_id == PHY_ID_SERDES &&
  2.5098 +			    (cmd.speed == SPEED_10 ||
  2.5099 +			     cmd.speed == SPEED_100))
  2.5100 +				return -EINVAL;
  2.5101 +			if ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
  2.5102 +			    (cmd.speed == SPEED_10 ||
  2.5103 +			     cmd.speed == SPEED_100))
  2.5104 +				return -EINVAL;
  2.5105 +		}
  2.5106 +
  2.5107 +		spin_lock_irq(&tp->lock);
  2.5108 +		spin_lock(&tp->tx_lock);
  2.5109 +
  2.5110 +		tp->link_config.autoneg = cmd.autoneg;
  2.5111 +		if (cmd.autoneg == AUTONEG_ENABLE) {
  2.5112 +			tp->link_config.advertising = cmd.advertising;
  2.5113 +			tp->link_config.speed = SPEED_INVALID;
  2.5114 +			tp->link_config.duplex = DUPLEX_INVALID;
  2.5115 +		} else {
  2.5116 +			tp->link_config.speed = cmd.speed;
  2.5117 +			tp->link_config.duplex = cmd.duplex;
  2.5118 +		}
  2.5119 +
  2.5120 +		tg3_setup_phy(tp);
  2.5121 +		spin_unlock(&tp->tx_lock);
  2.5122 +		spin_unlock_irq(&tp->lock);
  2.5123 +
  2.5124 +		return 0;
  2.5125 +	}
  2.5126 +
  2.5127 +	case ETHTOOL_GREGS: {
  2.5128 +		struct ethtool_regs regs;
  2.5129 +		u8 *regbuf;
  2.5130 +		int ret;
  2.5131 +
  2.5132 +		if (copy_from_user(&regs, useraddr, sizeof(regs)))
  2.5133 +			return -EFAULT;
  2.5134 +		if (regs.len > TG3_REGDUMP_LEN)
  2.5135 +			regs.len = TG3_REGDUMP_LEN;
  2.5136 +		regs.version = 0;
  2.5137 +		if (copy_to_user(useraddr, &regs, sizeof(regs)))
  2.5138 +			return -EFAULT;
  2.5139 +
  2.5140 +		regbuf = tg3_get_regs(tp);
  2.5141 +		if (!regbuf)
  2.5142 +			return -ENOMEM;
  2.5143 +
  2.5144 +		useraddr += offsetof(struct ethtool_regs, data);
  2.5145 +		ret = 0;
  2.5146 +		if (copy_to_user(useraddr, regbuf, regs.len))
  2.5147 +			ret = -EFAULT;
  2.5148 +		kfree(regbuf);
  2.5149 +		return ret;
  2.5150 +	}
  2.5151 +	case ETHTOOL_GWOL: {
  2.5152 +		struct ethtool_wolinfo wol = { ETHTOOL_GWOL };
  2.5153 +
  2.5154 +		wol.supported = WAKE_MAGIC;
  2.5155 +		wol.wolopts = 0;
  2.5156 +		if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
  2.5157 +			wol.wolopts = WAKE_MAGIC;
  2.5158 +		memset(&wol.sopass, 0, sizeof(wol.sopass));
  2.5159 +		if (copy_to_user(useraddr, &wol, sizeof(wol)))
  2.5160 +			return -EFAULT;
  2.5161 +		return 0;
  2.5162 +	}
  2.5163 +	case ETHTOOL_SWOL: {
  2.5164 +		struct ethtool_wolinfo wol;
  2.5165 +
  2.5166 +		if (copy_from_user(&wol, useraddr, sizeof(wol)))
  2.5167 +			return -EFAULT;
  2.5168 +		if (wol.wolopts & ~WAKE_MAGIC)
  2.5169 +			return -EINVAL;
  2.5170 +		if ((wol.wolopts & WAKE_MAGIC) &&
  2.5171 +		    tp->phy_id == PHY_ID_SERDES &&
  2.5172 +		    !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
  2.5173 +			return -EINVAL;
  2.5174 +
  2.5175 +		spin_lock_irq(&tp->lock);
  2.5176 +		if (wol.wolopts & WAKE_MAGIC)
  2.5177 +			tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  2.5178 +		else
  2.5179 +			tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  2.5180 +		spin_unlock_irq(&tp->lock);
  2.5181 +
  2.5182 +		return 0;
  2.5183 +	}
  2.5184 +	case ETHTOOL_GMSGLVL: {
  2.5185 +		struct ethtool_value edata = { ETHTOOL_GMSGLVL };
  2.5186 +		edata.data = tp->msg_enable;
  2.5187 +		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.5188 +			return -EFAULT;
  2.5189 +		return 0;
  2.5190 +	}
  2.5191 +	case ETHTOOL_SMSGLVL: {
  2.5192 +		struct ethtool_value edata;
  2.5193 +		if (copy_from_user(&edata, useraddr, sizeof(edata)))
  2.5194 +			return -EFAULT;
  2.5195 +		tp->msg_enable = edata.data;
  2.5196 +		return 0;
  2.5197 +	}
  2.5198 +	case ETHTOOL_NWAY_RST: {
  2.5199 +		u32 bmcr;
  2.5200 +		int r;
  2.5201 +
  2.5202 +		spin_lock_irq(&tp->lock);
  2.5203 +		tg3_readphy(tp, MII_BMCR, &bmcr);
  2.5204 +		tg3_readphy(tp, MII_BMCR, &bmcr);
  2.5205 +		r = -EINVAL;
  2.5206 +		if (bmcr & BMCR_ANENABLE) {
  2.5207 +			tg3_writephy(tp, MII_BMCR,
  2.5208 +				     bmcr | BMCR_ANRESTART);
  2.5209 +			r = 0;
  2.5210 +		}
  2.5211 +		spin_unlock_irq(&tp->lock);
  2.5212 +
  2.5213 +		return r;
  2.5214 +	}
  2.5215 +	case ETHTOOL_GLINK: {
  2.5216 +		struct ethtool_value edata = { ETHTOOL_GLINK };
  2.5217 +		edata.data = netif_carrier_ok(tp->dev) ? 1 : 0;
  2.5218 +		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.5219 +			return -EFAULT;
  2.5220 +		return 0;
  2.5221 +	}
  2.5222 +	case ETHTOOL_GRINGPARAM: {
  2.5223 +		struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
  2.5224 +
  2.5225 +		ering.rx_max_pending = TG3_RX_RING_SIZE - 1;
  2.5226 +		ering.rx_mini_max_pending = 0;
  2.5227 +		ering.rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
  2.5228 +
  2.5229 +		ering.rx_pending = tp->rx_pending;
  2.5230 +		ering.rx_mini_pending = 0;
  2.5231 +		ering.rx_jumbo_pending = tp->rx_jumbo_pending;
  2.5232 +		ering.tx_pending = tp->tx_pending;
  2.5233 +
  2.5234 +		if (copy_to_user(useraddr, &ering, sizeof(ering)))
  2.5235 +			return -EFAULT;
  2.5236 +		return 0;
  2.5237 +	}
  2.5238 +	case ETHTOOL_SRINGPARAM: {
  2.5239 +		struct ethtool_ringparam ering;
  2.5240 +
  2.5241 +		if (copy_from_user(&ering, useraddr, sizeof(ering)))
  2.5242 +			return -EFAULT;
  2.5243 +
  2.5244 +		if ((ering.rx_pending > TG3_RX_RING_SIZE - 1) ||
  2.5245 +		    (ering.rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
  2.5246 +		    (ering.tx_pending > TG3_TX_RING_SIZE - 1))
  2.5247 +			return -EINVAL;
  2.5248 +
  2.5249 +		spin_lock_irq(&tp->lock);
  2.5250 +		spin_lock(&tp->tx_lock);
  2.5251 +
  2.5252 +		tp->rx_pending = ering.rx_pending;
  2.5253 +		tp->rx_jumbo_pending = ering.rx_jumbo_pending;
  2.5254 +		tp->tx_pending = ering.tx_pending;
  2.5255 +
  2.5256 +		tg3_halt(tp);
  2.5257 +		tg3_init_rings(tp);
  2.5258 +		tg3_init_hw(tp);
  2.5259 +		netif_wake_queue(tp->dev);
  2.5260 +		spin_unlock(&tp->tx_lock);
  2.5261 +		spin_unlock_irq(&tp->lock);
  2.5262 +
  2.5263 +		return 0;
  2.5264 +	}
  2.5265 +	case ETHTOOL_GPAUSEPARAM: {
  2.5266 +		struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
  2.5267 +
  2.5268 +		epause.autoneg =
  2.5269 +			(tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
  2.5270 +		epause.rx_pause =
  2.5271 +			(tp->tg3_flags & TG3_FLAG_PAUSE_RX) != 0;
  2.5272 +		epause.tx_pause =
  2.5273 +			(tp->tg3_flags & TG3_FLAG_PAUSE_TX) != 0;
  2.5274 +		if (copy_to_user(useraddr, &epause, sizeof(epause)))
  2.5275 +			return -EFAULT;
  2.5276 +		return 0;
  2.5277 +	}
  2.5278 +	case ETHTOOL_SPAUSEPARAM: {
  2.5279 +		struct ethtool_pauseparam epause;
  2.5280 +
  2.5281 +		if (copy_from_user(&epause, useraddr, sizeof(epause)))
  2.5282 +			return -EFAULT;
  2.5283 +
  2.5284 +		spin_lock_irq(&tp->lock);
  2.5285 +		spin_lock(&tp->tx_lock);
  2.5286 +		if (epause.autoneg)
  2.5287 +			tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  2.5288 +		else
  2.5289 +			tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
  2.5290 +		if (epause.rx_pause)
  2.5291 +			tp->tg3_flags |= TG3_FLAG_PAUSE_RX;
  2.5292 +		else
  2.5293 +			tp->tg3_flags &= ~TG3_FLAG_PAUSE_RX;
  2.5294 +		if (epause.tx_pause)
  2.5295 +			tp->tg3_flags |= TG3_FLAG_PAUSE_TX;
  2.5296 +		else
  2.5297 +			tp->tg3_flags &= ~TG3_FLAG_PAUSE_TX;
  2.5298 +		tg3_halt(tp);
  2.5299 +		tg3_init_rings(tp);
  2.5300 +		tg3_init_hw(tp);
  2.5301 +		spin_unlock(&tp->tx_lock);
  2.5302 +		spin_unlock_irq(&tp->lock);
  2.5303 +
  2.5304 +		return 0;
  2.5305 +	}
  2.5306 +	case ETHTOOL_GRXCSUM: {
  2.5307 +		struct ethtool_value edata = { ETHTOOL_GRXCSUM };
  2.5308 +
  2.5309 +		edata.data =
  2.5310 +			(tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
  2.5311 +		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.5312 +			return -EFAULT;
  2.5313 +		return 0;
  2.5314 +	}
  2.5315 +	case ETHTOOL_SRXCSUM: {
  2.5316 +		struct ethtool_value edata;
  2.5317 +
  2.5318 +		if (copy_from_user(&edata, useraddr, sizeof(edata)))
  2.5319 +			return -EFAULT;
  2.5320 +
  2.5321 +		if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  2.5322 +			if (edata.data != 0)
  2.5323 +				return -EINVAL;
  2.5324 +			return 0;
  2.5325 +		}
  2.5326 +
  2.5327 +		spin_lock_irq(&tp->lock);
  2.5328 +		if (edata.data)
  2.5329 +			tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  2.5330 +		else
  2.5331 +			tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  2.5332 +		spin_unlock_irq(&tp->lock);
  2.5333 +
  2.5334 +		return 0;
  2.5335 +	}
  2.5336 +	case ETHTOOL_GTXCSUM: {
  2.5337 +		struct ethtool_value edata = { ETHTOOL_GTXCSUM };
  2.5338 +
  2.5339 +		edata.data =
  2.5340 +			(tp->dev->features & NETIF_F_IP_CSUM) != 0;
  2.5341 +		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.5342 +			return -EFAULT;
  2.5343 +		return 0;
  2.5344 +	}
  2.5345 +	case ETHTOOL_STXCSUM: {
  2.5346 +		struct ethtool_value edata;
  2.5347 +
  2.5348 +		if (copy_from_user(&edata, useraddr, sizeof(edata)))
  2.5349 +			return -EFAULT;
  2.5350 +
  2.5351 +		if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  2.5352 +			if (edata.data != 0)
  2.5353 +				return -EINVAL;
  2.5354 +			return 0;
  2.5355 +		}
  2.5356 +
  2.5357 +		if (edata.data)
  2.5358 +			tp->dev->features |= NETIF_F_IP_CSUM;
  2.5359 +		else
  2.5360 +			tp->dev->features &= ~NETIF_F_IP_CSUM;
  2.5361 +
  2.5362 +		return 0;
  2.5363 +	}
  2.5364 +	case ETHTOOL_GSG: {
  2.5365 +		struct ethtool_value edata = { ETHTOOL_GSG };
  2.5366 +
  2.5367 +		edata.data =
  2.5368 +			(tp->dev->features & NETIF_F_SG) != 0;
  2.5369 +		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.5370 +			return -EFAULT;
  2.5371 +		return 0;
  2.5372 +	}
  2.5373 +	case ETHTOOL_SSG: {
  2.5374 +		struct ethtool_value edata;
  2.5375 +
  2.5376 +		if (copy_from_user(&edata, useraddr, sizeof(edata)))
  2.5377 +			return -EFAULT;
  2.5378 +
  2.5379 +		if (edata.data)
  2.5380 +			tp->dev->features |= NETIF_F_SG;
  2.5381 +		else
  2.5382 +			tp->dev->features &= ~NETIF_F_SG;
  2.5383 +
  2.5384 +		return 0;
  2.5385 +	}
  2.5386 +	};
  2.5387 +
  2.5388 +	return -EOPNOTSUPP;
  2.5389 +}
  2.5390 +
  2.5391 +static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  2.5392 +{
  2.5393 +	struct mii_ioctl_data *data = (struct mii_ioctl_data *)&ifr->ifr_data;
  2.5394 +	struct tg3 *tp = dev->priv;
  2.5395 +	int err;
  2.5396 +
  2.5397 +	switch(cmd) {
  2.5398 +	case SIOCETHTOOL:
  2.5399 +		return tg3_ethtool_ioctl(dev, (void *) ifr->ifr_data);
  2.5400 +	case SIOCGMIIPHY:
  2.5401 +		data->phy_id = PHY_ADDR;
  2.5402 +
  2.5403 +		/* fallthru */
  2.5404 +	case SIOCGMIIREG: {
  2.5405 +		u32 mii_regval;
  2.5406 +
  2.5407 +		spin_lock_irq(&tp->lock);
  2.5408 +		err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
  2.5409 +		spin_unlock_irq(&tp->lock);
  2.5410 +
  2.5411 +		data->val_out = mii_regval;
  2.5412 +
  2.5413 +		return err;
  2.5414 +	}
  2.5415 +
  2.5416 +	case SIOCSMIIREG:
  2.5417 +		if (!capable(CAP_NET_ADMIN))
  2.5418 +			return -EPERM;
  2.5419 +
  2.5420 +		spin_lock_irq(&tp->lock);
  2.5421 +		err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
  2.5422 +		spin_unlock_irq(&tp->lock);
  2.5423 +
  2.5424 +		return err;
  2.5425 +
  2.5426 +	default:
  2.5427 +		/* do nothing */
  2.5428 +		break;
  2.5429 +	}
  2.5430 +	return -EOPNOTSUPP;
  2.5431 +}
  2.5432 +
  2.5433 +#if TG3_VLAN_TAG_USED
  2.5434 +static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  2.5435 +{
  2.5436 +	struct tg3 *tp = dev->priv;
  2.5437 +
  2.5438 +	spin_lock_irq(&tp->lock);
  2.5439 +	spin_lock(&tp->tx_lock);
  2.5440 +
  2.5441 +	tp->vlgrp = grp;
  2.5442 +
  2.5443 +	/* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
  2.5444 +	__tg3_set_rx_mode(dev);
  2.5445 +
  2.5446 +	spin_unlock(&tp->tx_lock);
  2.5447 +	spin_unlock_irq(&tp->lock);
  2.5448 +}
  2.5449 +
  2.5450 +static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
  2.5451 +{
  2.5452 +	struct tg3 *tp = dev->priv;
  2.5453 +
  2.5454 +	spin_lock_irq(&tp->lock);
  2.5455 +	spin_lock(&tp->tx_lock);
  2.5456 +	if (tp->vlgrp)
  2.5457 +		tp->vlgrp->vlan_devices[vid] = NULL;
  2.5458 +	spin_unlock(&tp->tx_lock);
  2.5459 +	spin_unlock_irq(&tp->lock);
  2.5460 +}
  2.5461 +#endif
  2.5462 +
  2.5463 +/* Chips other than 5700/5701 use the NVRAM for fetching info. */
  2.5464 +static void __devinit tg3_nvram_init(struct tg3 *tp)
  2.5465 +{
  2.5466 +	int j;
  2.5467 +
  2.5468 +	tw32(GRC_EEPROM_ADDR,
  2.5469 +	     (EEPROM_ADDR_FSM_RESET |
  2.5470 +	      (EEPROM_DEFAULT_CLOCK_PERIOD <<
  2.5471 +	       EEPROM_ADDR_CLKPERD_SHIFT)));
  2.5472 +
  2.5473 +	/* XXX schedule_timeout() ... */
  2.5474 +	for (j = 0; j < 100; j++)
  2.5475 +		udelay(10);
  2.5476 +
  2.5477 +	/* Enable seeprom accesses. */
  2.5478 +	tw32(GRC_LOCAL_CTRL,
  2.5479 +	     tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
  2.5480 +	tr32(GRC_LOCAL_CTRL);
  2.5481 +	udelay(100);
  2.5482 +
  2.5483 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  2.5484 +	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  2.5485 +		u32 nvcfg1 = tr32(NVRAM_CFG1);
  2.5486 +
  2.5487 +		tp->tg3_flags |= TG3_FLAG_NVRAM;
  2.5488 +		if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
  2.5489 +			if (nvcfg1 & NVRAM_CFG1_BUFFERED_MODE)
  2.5490 +				tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  2.5491 +		} else {
  2.5492 +			nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  2.5493 +			tw32(NVRAM_CFG1, nvcfg1);
  2.5494 +		}
  2.5495 +
  2.5496 +	} else {
  2.5497 +		tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
  2.5498 +	}
  2.5499 +}
  2.5500 +
  2.5501 +static int __devinit tg3_nvram_read_using_eeprom(struct tg3 *tp,
  2.5502 +						 u32 offset, u32 *val)
  2.5503 +{
  2.5504 +	u32 tmp;
  2.5505 +	int i;
  2.5506 +
  2.5507 +	if (offset > EEPROM_ADDR_ADDR_MASK ||
  2.5508 +	    (offset % 4) != 0)
  2.5509 +		return -EINVAL;
  2.5510 +
  2.5511 +	tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
  2.5512 +					EEPROM_ADDR_DEVID_MASK |
  2.5513 +					EEPROM_ADDR_READ);
  2.5514 +	tw32(GRC_EEPROM_ADDR,
  2.5515 +	     tmp |
  2.5516 +	     (0 << EEPROM_ADDR_DEVID_SHIFT) |
  2.5517 +	     ((offset << EEPROM_ADDR_ADDR_SHIFT) &
  2.5518 +	      EEPROM_ADDR_ADDR_MASK) |
  2.5519 +	     EEPROM_ADDR_READ | EEPROM_ADDR_START);
  2.5520 +
  2.5521 +	for (i = 0; i < 10000; i++) {
  2.5522 +		tmp = tr32(GRC_EEPROM_ADDR);
  2.5523 +
  2.5524 +		if (tmp & EEPROM_ADDR_COMPLETE)
  2.5525 +			break;
  2.5526 +		udelay(100);
  2.5527 +	}
  2.5528 +	if (!(tmp & EEPROM_ADDR_COMPLETE))
  2.5529 +		return -EBUSY;
  2.5530 +
  2.5531 +	*val = tr32(GRC_EEPROM_DATA);
  2.5532 +	return 0;
  2.5533 +}
  2.5534 +
  2.5535 +static int __devinit tg3_nvram_read(struct tg3 *tp,
  2.5536 +				    u32 offset, u32 *val)
  2.5537 +{
  2.5538 +	int i, saw_done_clear;
  2.5539 +
  2.5540 +	if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
  2.5541 +		return tg3_nvram_read_using_eeprom(tp, offset, val);
  2.5542 +
  2.5543 +	if (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED)
  2.5544 +		offset = ((offset / NVRAM_BUFFERED_PAGE_SIZE) <<
  2.5545 +			  NVRAM_BUFFERED_PAGE_POS) +
  2.5546 +			(offset % NVRAM_BUFFERED_PAGE_SIZE);
  2.5547 +
  2.5548 +	if (offset > NVRAM_ADDR_MSK)
  2.5549 +		return -EINVAL;
  2.5550 +
  2.5551 +	tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  2.5552 +	for (i = 0; i < 1000; i++) {
  2.5553 +		if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  2.5554 +			break;
  2.5555 +		udelay(20);
  2.5556 +	}
  2.5557 +
  2.5558 +	tw32(NVRAM_ADDR, offset);
  2.5559 +	tw32(NVRAM_CMD,
  2.5560 +	     NVRAM_CMD_RD | NVRAM_CMD_GO |
  2.5561 +	     NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
  2.5562 +
  2.5563 +	/* Wait for done bit to clear then set again. */
  2.5564 +	saw_done_clear = 0;
  2.5565 +	for (i = 0; i < 1000; i++) {
  2.5566 +		udelay(10);
  2.5567 +		if (!saw_done_clear &&
  2.5568 +		    !(tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
  2.5569 +			saw_done_clear = 1;
  2.5570 +		else if (saw_done_clear &&
  2.5571 +			 (tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
  2.5572 +			break;
  2.5573 +	}
  2.5574 +	if (i >= 1000) {
  2.5575 +		tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
  2.5576 +		return -EBUSY;
  2.5577 +	}
  2.5578 +
  2.5579 +	*val = swab32(tr32(NVRAM_RDDATA));
  2.5580 +	tw32(NVRAM_SWARB, 0x20);
  2.5581 +
  2.5582 +	return 0;
  2.5583 +}
  2.5584 +
  2.5585 +struct subsys_tbl_ent {
  2.5586 +	u16 subsys_vendor, subsys_devid;
  2.5587 +	u32 phy_id;
  2.5588 +};
  2.5589 +
  2.5590 +static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
  2.5591 +	/* Broadcom boards. */
  2.5592 +	{ 0x14e4, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
  2.5593 +	{ 0x14e4, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
  2.5594 +	{ 0x14e4, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
  2.5595 +	{ 0x14e4, 0x0003, PHY_ID_SERDES  }, /* BCM95700A9 */
  2.5596 +	{ 0x14e4, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
  2.5597 +	{ 0x14e4, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
  2.5598 +	{ 0x14e4, 0x0007, PHY_ID_SERDES  }, /* BCM95701A7 */
  2.5599 +	{ 0x14e4, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
  2.5600 +	{ 0x14e4, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
  2.5601 +	{ 0x14e4, 0x0009, PHY_ID_BCM5701 }, /* BCM95703Ax1 */
  2.5602 +	{ 0x14e4, 0x8009, PHY_ID_BCM5701 }, /* BCM95703Ax2 */
  2.5603 +
  2.5604 +	/* 3com boards. */
  2.5605 +	{ PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
  2.5606 +	{ PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
  2.5607 +	/* { PCI_VENDOR_ID_3COM, 0x1002, PHY_ID_XXX },     3C996CT */
  2.5608 +	/* { PCI_VENDOR_ID_3COM, 0x1003, PHY_ID_XXX },     3C997T */
  2.5609 +	{ PCI_VENDOR_ID_3COM, 0x1004, PHY_ID_SERDES  }, /* 3C996SX */
  2.5610 +	/* { PCI_VENDOR_ID_3COM, 0x1005, PHY_ID_XXX },     3C997SZ */
  2.5611 +	{ PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
  2.5612 +	{ PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
  2.5613 +
  2.5614 +	/* DELL boards. */
  2.5615 +	{ PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
  2.5616 +	{ PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
  2.5617 +	{ PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
  2.5618 +	{ PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
  2.5619 +
  2.5620 +	/* Compaq boards. */
  2.5621 +	{ PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
  2.5622 +	{ PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
  2.5623 +	{ PCI_VENDOR_ID_COMPAQ, 0x007d, PHY_ID_SERDES  }, /* CHANGELING */
  2.5624 +	{ PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
  2.5625 +	{ PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }  /* NC7780_2 */
  2.5626 +};
  2.5627 +
  2.5628 +static int __devinit tg3_phy_probe(struct tg3 *tp)
  2.5629 +{
  2.5630 +	u32 eeprom_phy_id, hw_phy_id_1, hw_phy_id_2;
  2.5631 +	u32 hw_phy_id, hw_phy_id_masked;
  2.5632 +	enum phy_led_mode eeprom_led_mode;
  2.5633 +	u32 val;
  2.5634 +	int i, eeprom_signature_found, err;
  2.5635 +
  2.5636 +	tp->phy_id = PHY_ID_INVALID;
  2.5637 +	for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
  2.5638 +		if ((subsys_id_to_phy_id[i].subsys_vendor ==
  2.5639 +		     tp->pdev->subsystem_vendor) &&
  2.5640 +		    (subsys_id_to_phy_id[i].subsys_devid ==
  2.5641 +		     tp->pdev->subsystem_device)) {
  2.5642 +			tp->phy_id = subsys_id_to_phy_id[i].phy_id;
  2.5643 +			break;
  2.5644 +		}
  2.5645 +	}
  2.5646 +
  2.5647 +	eeprom_phy_id = PHY_ID_INVALID;
  2.5648 +	eeprom_led_mode = led_mode_auto;
  2.5649 +	eeprom_signature_found = 0;
  2.5650 +	tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  2.5651 +	if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  2.5652 +		u32 nic_cfg;
  2.5653 +
  2.5654 +		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  2.5655 +
  2.5656 +		eeprom_signature_found = 1;
  2.5657 +
  2.5658 +		if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
  2.5659 +		    NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) {
  2.5660 +			eeprom_phy_id = PHY_ID_SERDES;
  2.5661 +		} else {
  2.5662 +			u32 nic_phy_id;
  2.5663 +
  2.5664 +			tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
  2.5665 +			if (nic_phy_id != 0) {
  2.5666 +				u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
  2.5667 +				u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
  2.5668 +
  2.5669 +				eeprom_phy_id  = (id1 >> 16) << 10;
  2.5670 +				eeprom_phy_id |= (id2 & 0xfc00) << 16;
  2.5671 +				eeprom_phy_id |= (id2 & 0x03ff) <<  0;
  2.5672 +			}
  2.5673 +		}
  2.5674 +
  2.5675 +		switch (nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK) {
  2.5676 +		case NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD:
  2.5677 +			eeprom_led_mode = led_mode_three_link;
  2.5678 +			break;
  2.5679 +
  2.5680 +		case NIC_SRAM_DATA_CFG_LED_LINK_SPD:
  2.5681 +			eeprom_led_mode = led_mode_link10;
  2.5682 +			break;
  2.5683 +
  2.5684 +		default:
  2.5685 +			eeprom_led_mode = led_mode_auto;
  2.5686 +			break;
  2.5687 +		};
  2.5688 +		if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1 ||
  2.5689 +		     tp->pci_chip_rev_id == CHIPREV_ID_5703_A2) &&
  2.5690 +		    (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
  2.5691 +			tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
  2.5692 +
  2.5693 +		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE)
  2.5694 +			tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  2.5695 +		if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
  2.5696 +			tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
  2.5697 +	}
  2.5698 +
  2.5699 +	/* Now read the physical PHY_ID from the chip and verify
  2.5700 +	 * that it is sane.  If it doesn't look good, we fall back
  2.5701 +	 * to either the hard-coded table based PHY_ID and failing
  2.5702 +	 * that the value found in the eeprom area.
  2.5703 +	 */
  2.5704 +	err  = tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
  2.5705 +	err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
  2.5706 +
  2.5707 +	hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
  2.5708 +	hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
  2.5709 +	hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
  2.5710 +
  2.5711 +	hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
  2.5712 +
  2.5713 +	if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
  2.5714 +		tp->phy_id = hw_phy_id;
  2.5715 +	} else {
  2.5716 +		/* phy_id currently holds the value found in the
  2.5717 +		 * subsys_id_to_phy_id[] table or PHY_ID_INVALID
  2.5718 +		 * if a match was not found there.
  2.5719 +		 */
  2.5720 +		if (tp->phy_id == PHY_ID_INVALID) {
  2.5721 +			if (!eeprom_signature_found ||
  2.5722 +			    !KNOWN_PHY_ID(eeprom_phy_id & PHY_ID_MASK))
  2.5723 +				return -ENODEV;
  2.5724 +			tp->phy_id = eeprom_phy_id;
  2.5725 +		}
  2.5726 +	}
  2.5727 +
  2.5728 +	err = tg3_phy_reset(tp, 1);
  2.5729 +	if (err)
  2.5730 +		return err;
  2.5731 +
  2.5732 +	if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  2.5733 +	    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
  2.5734 +		u32 mii_tg3_ctrl;
  2.5735 +		
  2.5736 +		/* These chips, when reset, only advertise 10Mb
  2.5737 +		 * capabilities.  Fix that.
  2.5738 +		 */
  2.5739 +		err  = tg3_writephy(tp, MII_ADVERTISE,
  2.5740 +				    (ADVERTISE_CSMA |
  2.5741 +				     ADVERTISE_PAUSE_CAP |
  2.5742 +				     ADVERTISE_10HALF |
  2.5743 +				     ADVERTISE_10FULL |
  2.5744 +				     ADVERTISE_100HALF |
  2.5745 +				     ADVERTISE_100FULL));
  2.5746 +		mii_tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
  2.5747 +				MII_TG3_CTRL_ADV_1000_FULL |
  2.5748 +				MII_TG3_CTRL_AS_MASTER |
  2.5749 +				MII_TG3_CTRL_ENABLE_AS_MASTER);
  2.5750 +		if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  2.5751 +			mii_tg3_ctrl = 0;
  2.5752 +
  2.5753 +		err |= tg3_writephy(tp, MII_TG3_CTRL, mii_tg3_ctrl);
  2.5754 +		err |= tg3_writephy(tp, MII_BMCR,
  2.5755 +				    (BMCR_ANRESTART | BMCR_ANENABLE));
  2.5756 +	}
  2.5757 +
  2.5758 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
  2.5759 +		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  2.5760 +		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  2.5761 +		tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
  2.5762 +	}
  2.5763 +
  2.5764 +	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
  2.5765 +	    (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)) {
  2.5766 +		tg3_writephy(tp, 0x1c, 0x8d68);
  2.5767 +		tg3_writephy(tp, 0x1c, 0x8d68);
  2.5768 +	}
  2.5769 +
  2.5770 +	/* Enable Ethernet@WireSpeed */
  2.5771 +	tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
  2.5772 +	tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
  2.5773 +	tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
  2.5774 +
  2.5775 +	if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
  2.5776 +		err = tg3_init_5401phy_dsp(tp);
  2.5777 +	}
  2.5778 +
  2.5779 +	/* Determine the PHY led mode. */
  2.5780 +	if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) {
  2.5781 +		tp->led_mode = led_mode_link10;
  2.5782 +	} else {
  2.5783 +		tp->led_mode = led_mode_three_link;
  2.5784 +		if (eeprom_signature_found &&
  2.5785 +		    eeprom_led_mode != led_mode_auto)
  2.5786 +			tp->led_mode = eeprom_led_mode;
  2.5787 +	}
  2.5788 +
  2.5789 +	if (tp->phy_id == PHY_ID_SERDES)
  2.5790 +		tp->link_config.advertising =
  2.5791 +			(ADVERTISED_1000baseT_Half |
  2.5792 +			 ADVERTISED_1000baseT_Full |
  2.5793 +			 ADVERTISED_Autoneg |
  2.5794 +			 ADVERTISED_FIBRE);
  2.5795 +	if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  2.5796 +		tp->link_config.advertising &=
  2.5797 +			~(ADVERTISED_1000baseT_Half |
  2.5798 +			  ADVERTISED_1000baseT_Full);
  2.5799 +
  2.5800 +	return err;
  2.5801 +}
  2.5802 +
  2.5803 +static void __devinit tg3_read_partno(struct tg3 *tp)
  2.5804 +{
  2.5805 +	unsigned char vpd_data[256];
  2.5806 +	int i;
  2.5807 +
  2.5808 +	for (i = 0; i < 256; i += 4) {
  2.5809 +		u32 tmp;
  2.5810 +
  2.5811 +		if (tg3_nvram_read(tp, 0x100 + i, &tmp))
  2.5812 +			goto out_not_found;
  2.5813 +
  2.5814 +		vpd_data[i + 0] = ((tmp >>  0) & 0xff);
  2.5815 +		vpd_data[i + 1] = ((tmp >>  8) & 0xff);
  2.5816 +		vpd_data[i + 2] = ((tmp >> 16) & 0xff);
  2.5817 +		vpd_data[i + 3] = ((tmp >> 24) & 0xff);
  2.5818 +	}
  2.5819 +
  2.5820 +	/* Now parse and find the part number. */
  2.5821 +	for (i = 0; i < 256; ) {
  2.5822 +		unsigned char val = vpd_data[i];
  2.5823 +		int block_end;
  2.5824 +
  2.5825 +		if (val == 0x82 || val == 0x91) {
  2.5826 +			i = (i + 3 +
  2.5827 +			     (vpd_data[i + 1] +
  2.5828 +			      (vpd_data[i + 2] << 8)));
  2.5829 +			continue;
  2.5830 +		}
  2.5831 +
  2.5832 +		if (val != 0x90)
  2.5833 +			goto out_not_found;
  2.5834 +
  2.5835 +		block_end = (i + 3 +
  2.5836 +			     (vpd_data[i + 1] +
  2.5837 +			      (vpd_data[i + 2] << 8)));
  2.5838 +		i += 3;
  2.5839 +		while (i < block_end) {
  2.5840 +			if (vpd_data[i + 0] == 'P' &&
  2.5841 +			    vpd_data[i + 1] == 'N') {
  2.5842 +				int partno_len = vpd_data[i + 2];
  2.5843 +
  2.5844 +				if (partno_len > 24)
  2.5845 +					goto out_not_found;
  2.5846 +
  2.5847 +				memcpy(tp->board_part_number,
  2.5848 +				       &vpd_data[i + 3],
  2.5849 +				       partno_len);
  2.5850 +
  2.5851 +				/* Success. */
  2.5852 +				return;
  2.5853 +			}
  2.5854 +		}
  2.5855 +
  2.5856 +		/* Part number not found. */
  2.5857 +		goto out_not_found;
  2.5858 +	}
  2.5859 +
  2.5860 +out_not_found:
  2.5861 +	strcpy(tp->board_part_number, "none");
  2.5862 +}
  2.5863 +
  2.5864 +static int __devinit tg3_get_invariants(struct tg3 *tp)
  2.5865 +{
  2.5866 +	u32 misc_ctrl_reg;
  2.5867 +	u32 cacheline_sz_reg;
  2.5868 +	u32 pci_state_reg, grc_misc_cfg;
  2.5869 +	u16 pci_cmd;
  2.5870 +	int err;
  2.5871 +
  2.5872 +	/* If we have an AMD 762 or Intel ICH/ICH0 chipset, write
  2.5873 +	 * reordering to the mailbox registers done by the host
  2.5874 +	 * controller can cause major troubles.  We read back from
  2.5875 +	 * every mailbox register write to force the writes to be
  2.5876 +	 * posted to the chip in order.
  2.5877 +	 */
  2.5878 +	if (pci_find_device(PCI_VENDOR_ID_INTEL,
  2.5879 +			    PCI_DEVICE_ID_INTEL_82801AA_8, NULL) ||
  2.5880 +	    pci_find_device(PCI_VENDOR_ID_INTEL,
  2.5881 +			    PCI_DEVICE_ID_INTEL_82801AB_8, NULL) ||
  2.5882 +	    pci_find_device(PCI_VENDOR_ID_AMD,
  2.5883 +			    PCI_DEVICE_ID_AMD_FE_GATE_700C, NULL))
  2.5884 +		tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  2.5885 +
  2.5886 +	/* Force memory write invalidate off.  If we leave it on,
  2.5887 +	 * then on 5700_BX chips we have to enable a workaround.
  2.5888 +	 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundry
  2.5889 +	 * to match the cacheline size.  The Broadcom driver have this
  2.5890 +	 * workaround but turns MWI off all the times so never uses
  2.5891 +	 * it.  This seems to suggest that the workaround is insufficient.
  2.5892 +	 */
  2.5893 +	pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  2.5894 +	pci_cmd &= ~PCI_COMMAND_INVALIDATE;
  2.5895 +	pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  2.5896 +
  2.5897 +	/* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
  2.5898 +	 * has the register indirect write enable bit set before
  2.5899 +	 * we try to access any of the MMIO registers.  It is also
  2.5900 +	 * critical that the PCI-X hw workaround situation is decided
  2.5901 +	 * before that as well.
  2.5902 +	 */
  2.5903 +	pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  2.5904 +			      &misc_ctrl_reg);
  2.5905 +
  2.5906 +	tp->pci_chip_rev_id = (misc_ctrl_reg >>
  2.5907 +			       MISC_HOST_CTRL_CHIPREV_SHIFT);
  2.5908 +
  2.5909 +	/* Initialize misc host control in PCI block. */
  2.5910 +	tp->misc_host_ctrl |= (misc_ctrl_reg &
  2.5911 +			       MISC_HOST_CTRL_CHIPREV);
  2.5912 +	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  2.5913 +			       tp->misc_host_ctrl);
  2.5914 +
  2.5915 +	pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
  2.5916 +			      &cacheline_sz_reg);
  2.5917 +
  2.5918 +	tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
  2.5919 +	tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
  2.5920 +	tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
  2.5921 +	tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
  2.5922 +
  2.5923 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  2.5924 +	    tp->pci_lat_timer < 64) {
  2.5925 +		tp->pci_lat_timer = 64;
  2.5926 +
  2.5927 +		cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
  2.5928 +		cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
  2.5929 +		cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
  2.5930 +		cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
  2.5931 +
  2.5932 +		pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
  2.5933 +				       cacheline_sz_reg);
  2.5934 +	}
  2.5935 +
  2.5936 +	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  2.5937 +			      &pci_state_reg);
  2.5938 +
  2.5939 +	if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
  2.5940 +		tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
  2.5941 +
  2.5942 +		/* If this is a 5700 BX chipset, and we are in PCI-X
  2.5943 +		 * mode, enable register write workaround.
  2.5944 +		 *
  2.5945 +		 * The workaround is to use indirect register accesses
  2.5946 +		 * for all chip writes not to mailbox registers.
  2.5947 +		 */
  2.5948 +		if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
  2.5949 +			u32 pm_reg;
  2.5950 +			u16 pci_cmd;
  2.5951 +
  2.5952 +			tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  2.5953 +
  2.5954 +			/* The chip can have it's power management PCI config
  2.5955 +			 * space registers clobbered due to this bug.
  2.5956 +			 * So explicitly force the chip into D0 here.
  2.5957 +			 */
  2.5958 +			pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
  2.5959 +					      &pm_reg);
  2.5960 +			pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
  2.5961 +			pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
  2.5962 +			pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
  2.5963 +					       pm_reg);
  2.5964 +
  2.5965 +			/* Also, force SERR#/PERR# in PCI command. */
  2.5966 +			pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  2.5967 +			pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  2.5968 +			pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  2.5969 +		}
  2.5970 +	}
  2.5971 +	if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
  2.5972 +		tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
  2.5973 +	if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
  2.5974 +		tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
  2.5975 +
  2.5976 +	/* Chip-specific fixup from Broadcom driver */
  2.5977 +	if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
  2.5978 +	    (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
  2.5979 +		pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
  2.5980 +		pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  2.5981 +	}
  2.5982 +
  2.5983 +	/* Force the chip into D0. */
  2.5984 +	err = tg3_set_power_state(tp, 0);
  2.5985 +	if (err) {
  2.5986 +		printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
  2.5987 +		       tp->pdev->slot_name);
  2.5988 +		return err;
  2.5989 +	}
  2.5990 +
  2.5991 +	/* 5700 B0 chips do not support checksumming correctly due
  2.5992 +	 * to hardware bugs.
  2.5993 +	 */
  2.5994 +	if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
  2.5995 +		tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
  2.5996 +
  2.5997 +	/* Regardless of whether checksums work or not, we configure
  2.5998 +	 * the StrongARM chips to not compute the pseudo header checksums
  2.5999 +	 * in either direction.  Because of the way Linux checksum support
  2.6000 +	 * works we do not need the chips to do this, and taking the load
  2.6001 +	 * off of the TX/RX onboard StrongARM cpus means that they will not be
  2.6002 +	 * the bottleneck.  Whoever wrote Broadcom's driver did not
  2.6003 +	 * understand the situation at all.  He could have bothered
  2.6004 +	 * to read Jes's Acenic driver because the logic (and this part of
  2.6005 +	 * the Tigon2 hardware/firmware) is pretty much identical.
  2.6006 +	 */
  2.6007 +	tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
  2.6008 +	tp->tg3_flags |= TG3_FLAG_NO_RX_PSEUDO_CSUM;
  2.6009 +
  2.6010 +	/* Derive initial jumbo mode from MTU assigned in
  2.6011 +	 * ether_setup() via the alloc_etherdev() call
  2.6012 +	 */
  2.6013 +	if (tp->dev->mtu > ETH_DATA_LEN)
  2.6014 +		tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
  2.6015 +
  2.6016 +	/* Determine WakeOnLan speed to use. */
  2.6017 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2.6018 +	    tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  2.6019 +	    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
  2.6020 +	    tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
  2.6021 +		tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
  2.6022 +	} else {
  2.6023 +		tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
  2.6024 +	}
  2.6025 +
  2.6026 +	/* Only 5701 and later support tagged irq status mode.
  2.6027 +	 *
  2.6028 +	 * However, since we are using NAPI avoid tagged irq status
  2.6029 +	 * because the interrupt condition is more difficult to
  2.6030 +	 * fully clear in that mode.
  2.6031 +	 */
  2.6032 +	tp->coalesce_mode = 0;
  2.6033 +
  2.6034 +	if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
  2.6035 +	    GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
  2.6036 +		tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
  2.6037 +
  2.6038 +	/* Initialize MAC MI mode, polling disabled. */
  2.6039 +	tw32(MAC_MI_MODE, tp->mi_mode);
  2.6040 +	tr32(MAC_MI_MODE);
  2.6041 +	udelay(40);
  2.6042 +
  2.6043 +	/* Initialize data/descriptor byte/word swapping. */
  2.6044 +	tw32(GRC_MODE, tp->grc_mode);
  2.6045 +
  2.6046 +	tg3_switch_clocks(tp);
  2.6047 +
  2.6048 +	/* Clear this out for sanity. */
  2.6049 +	tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  2.6050 +
  2.6051 +	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  2.6052 +			      &pci_state_reg);
  2.6053 +	if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
  2.6054 +	    (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
  2.6055 +		u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
  2.6056 +
  2.6057 +		if (chiprevid == CHIPREV_ID_5701_A0 ||
  2.6058 +		    chiprevid == CHIPREV_ID_5701_B0 ||
  2.6059 +		    chiprevid == CHIPREV_ID_5701_B2 ||
  2.6060 +		    chiprevid == CHIPREV_ID_5701_B5) {
  2.6061 +			unsigned long sram_base;
  2.6062 +
  2.6063 +			/* Write some dummy words into the SRAM status block
  2.6064 +			 * area, see if it reads back correctly.  If the return
  2.6065 +			 * value is bad, force enable the PCIX workaround.
  2.6066 +			 */
  2.6067 +			sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
  2.6068 +
  2.6069 +			writel(0x00000000, sram_base);
  2.6070 +			writel(0x00000000, sram_base + 4);
  2.6071 +			writel(0xffffffff, sram_base + 4);
  2.6072 +			if (readl(sram_base) != 0x00000000)
  2.6073 +				tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  2.6074 +		}
  2.6075 +	}
  2.6076 +
  2.6077 +	udelay(50);
  2.6078 +	tg3_nvram_init(tp);
  2.6079 +
  2.6080 +	/* Determine if TX descriptors will reside in
  2.6081 +	 * main memory or in the chip SRAM.
  2.6082 +	 */
  2.6083 +	if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
  2.6084 +		tp->tg3_flags |= TG3_FLAG_HOST_TXDS;
  2.6085 +
  2.6086 +	/* Quick sanity check.  Make sure we see an expected
  2.6087 +	 * value here.
  2.6088 +	 */
  2.6089 +	grc_misc_cfg = tr32(GRC_MISC_CFG);
  2.6090 +	grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
  2.6091 +	if (grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5700 &&
  2.6092 +	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5701 &&
  2.6093 +	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5702FE &&
  2.6094 +	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5703 &&
  2.6095 +	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5703S &&
  2.6096 +	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5704 &&
  2.6097 +	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5704_A2 &&
  2.6098 +	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5704_X &&
  2.6099 +	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_AC91002A1) {
  2.6100 +		printk(KERN_ERR PFX "(%s) unknown board id 0x%08X\n",
  2.6101 +		       tp->pdev->slot_name, grc_misc_cfg);
  2.6102 +		return -ENODEV;
  2.6103 +	}
  2.6104 +
  2.6105 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
  2.6106 +	    grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
  2.6107 +		tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
  2.6108 +		tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
  2.6109 +	}
  2.6110 +
  2.6111 +	/* ROFL, you should see Broadcom's driver code implementing
  2.6112 +	 * this, stuff like "if (a || b)" where a and b are always
  2.6113 +	 * mutually exclusive.  DaveM finds like 6 bugs today, hello!
  2.6114 +	 */
  2.6115 +	if (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5702FE)
  2.6116 +		tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
  2.6117 +
  2.6118 +	err = tg3_phy_probe(tp);
  2.6119 +	if (err) {
  2.6120 +		printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
  2.6121 +		       tp->pdev->slot_name, err);
  2.6122 +		/* ... but do not return immediately ... */
  2.6123 +	}
  2.6124 +
  2.6125 +	tg3_read_partno(tp);
  2.6126 +
  2.6127 +	if (tp->phy_id == PHY_ID_SERDES) {
  2.6128 +		tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  2.6129 +
  2.6130 +		/* And override led_mode in case Dell ever makes
  2.6131 +		 * a fibre board.
  2.6132 +		 */
  2.6133 +		tp->led_mode = led_mode_three_link;
  2.6134 +	} else {
  2.6135 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  2.6136 +			tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
  2.6137 +		else
  2.6138 +			tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  2.6139 +	}
  2.6140 +
  2.6141 +	/* 5700 {AX,BX} chips have a broken status block link
  2.6142 +	 * change bit implementation, so we must use the
  2.6143 +	 * status register in those cases.
  2.6144 +	 */
  2.6145 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  2.6146 +		tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
  2.6147 +	else
  2.6148 +		tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
  2.6149 +
  2.6150 +	/* The led_mode is set during tg3_phy_probe, here we might
  2.6151 +	 * have to force the link status polling mechanism based
  2.6152 +	 * upon subsystem IDs.
  2.6153 +	 */
  2.6154 +	if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  2.6155 +	    tp->phy_id != PHY_ID_SERDES) {
  2.6156 +		tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
  2.6157 +				  TG3_FLAG_USE_LINKCHG_REG);
  2.6158 +	}
  2.6159 +
  2.6160 +	/* For all SERDES we poll the MAC status register. */
  2.6161 +	if (tp->phy_id == PHY_ID_SERDES)
  2.6162 +		tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
  2.6163 +	else
  2.6164 +		tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
  2.6165 +
  2.6166 +	/* 5700 BX chips need to have their TX producer index mailboxes
  2.6167 +	 * written twice to workaround a bug.
  2.6168 +	 */
  2.6169 +	if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
  2.6170 +		tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
  2.6171 +	else
  2.6172 +		tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
  2.6173 +
  2.6174 +	/* 5700 chips can get confused if TX buffers straddle the
  2.6175 +	 * 4GB address boundary in some cases.
  2.6176 +	 */
  2.6177 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  2.6178 +		/* ROFL!  Latest Broadcom driver disables NETIF_F_HIGHDMA
  2.6179 +		 * in this case instead of fixing their workaround code.
  2.6180 +		 *
  2.6181 +		 * Like, hey, there is this skb_copy() thing guys,
  2.6182 +		 * use it.  Oh I can't stop laughing...
  2.6183 +		 */
  2.6184 +		tp->dev->hard_start_xmit = tg3_start_xmit_4gbug;
  2.6185 +	} else {
  2.6186 +		tp->dev->hard_start_xmit = tg3_start_xmit;
  2.6187 +	}
  2.6188 +
  2.6189 +	tp->rx_offset = 2;
  2.6190 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  2.6191 +	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
  2.6192 +		tp->rx_offset = 0;
  2.6193 +
  2.6194 +	/* By default, disable wake-on-lan.  User can change this
  2.6195 +	 * using ETHTOOL_SWOL.
  2.6196 +	 */
  2.6197 +	tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  2.6198 +
  2.6199 +	return err;
  2.6200 +}
  2.6201 +
  2.6202 +static int __devinit tg3_get_device_address(struct tg3 *tp)
  2.6203 +{
  2.6204 +	struct net_device *dev = tp->dev;
  2.6205 +	u32 hi, lo, mac_offset;
  2.6206 +
  2.6207 +	if (PCI_FUNC(tp->pdev->devfn) == 0)
  2.6208 +		mac_offset = 0x7c;
  2.6209 +	else
  2.6210 +		mac_offset = 0xcc;
  2.6211 +
  2.6212 +	/* First try to get it from MAC address mailbox. */
  2.6213 +	tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
  2.6214 +	if ((hi >> 16) == 0x484b) {
  2.6215 +		dev->dev_addr[0] = (hi >>  8) & 0xff;
  2.6216 +		dev->dev_addr[1] = (hi >>  0) & 0xff;
  2.6217 +
  2.6218 +		tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
  2.6219 +		dev->dev_addr[2] = (lo >> 24) & 0xff;
  2.6220 +		dev->dev_addr[3] = (lo >> 16) & 0xff;
  2.6221 +		dev->dev_addr[4] = (lo >>  8) & 0xff;
  2.6222 +		dev->dev_addr[5] = (lo >>  0) & 0xff;
  2.6223 +	}
  2.6224 +	/* Next, try NVRAM. */
  2.6225 +	else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
  2.6226 +		 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
  2.6227 +		dev->dev_addr[0] = ((hi >> 16) & 0xff);
  2.6228 +		dev->dev_addr[1] = ((hi >> 24) & 0xff);
  2.6229 +		dev->dev_addr[2] = ((lo >>  0) & 0xff);
  2.6230 +		dev->dev_addr[3] = ((lo >>  8) & 0xff);
  2.6231 +		dev->dev_addr[4] = ((lo >> 16) & 0xff);
  2.6232 +		dev->dev_addr[5] = ((lo >> 24) & 0xff);
  2.6233 +	}
  2.6234 +	/* Finally just fetch it out of the MAC control regs. */
  2.6235 +	else {
  2.6236 +		hi = tr32(MAC_ADDR_0_HIGH);
  2.6237 +		lo = tr32(MAC_ADDR_0_LOW);
  2.6238 +
  2.6239 +		dev->dev_addr[5] = lo & 0xff;
  2.6240 +		dev->dev_addr[4] = (lo >> 8) & 0xff;
  2.6241 +		dev->dev_addr[3] = (lo >> 16) & 0xff;
  2.6242 +		dev->dev_addr[2] = (lo >> 24) & 0xff;
  2.6243 +		dev->dev_addr[1] = hi & 0xff;
  2.6244 +		dev->dev_addr[0] = (hi >> 8) & 0xff;
  2.6245 +	}
  2.6246 +
  2.6247 +	if (!is_valid_ether_addr(&dev->dev_addr[0]))
  2.6248 +		return -EINVAL;
  2.6249 +
  2.6250 +	return 0;
  2.6251 +}
  2.6252 +
  2.6253 +static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
  2.6254 +{
  2.6255 +	struct tg3_internal_buffer_desc test_desc;
  2.6256 +	u32 sram_dma_descs;
  2.6257 +	int i, ret;
  2.6258 +
  2.6259 +	sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
  2.6260 +
  2.6261 +	tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
  2.6262 +	tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
  2.6263 +	tw32(RDMAC_STATUS, 0);
  2.6264 +	tw32(WDMAC_STATUS, 0);
  2.6265 +
  2.6266 +	tw32(BUFMGR_MODE, 0);
  2.6267 +	tw32(FTQ_RESET, 0);
  2.6268 +
  2.6269 +	/* pci_alloc_consistent gives only non-DAC addresses */
  2.6270 +	test_desc.addr_hi = 0;
  2.6271 +	test_desc.addr_lo = buf_dma & 0xffffffff;
  2.6272 +	test_desc.nic_mbuf = 0x00002100;
  2.6273 +	test_desc.len = size;
  2.6274 +	if (to_device) {
  2.6275 +		test_desc.cqid_sqid = (13 << 8) | 2;
  2.6276 +		tw32(RDMAC_MODE, RDMAC_MODE_RESET);
  2.6277 +		tr32(RDMAC_MODE);
  2.6278 +		udelay(40);
  2.6279 +
  2.6280 +		tw32(RDMAC_MODE, RDMAC_MODE_ENABLE);
  2.6281 +		tr32(RDMAC_MODE);
  2.6282 +		udelay(40);
  2.6283 +	} else {
  2.6284 +		test_desc.cqid_sqid = (16 << 8) | 7;
  2.6285 +		tw32(WDMAC_MODE, WDMAC_MODE_RESET);
  2.6286 +		tr32(WDMAC_MODE);
  2.6287 +		udelay(40);
  2.6288 +
  2.6289 +		tw32(WDMAC_MODE, WDMAC_MODE_ENABLE);
  2.6290 +		tr32(WDMAC_MODE);
  2.6291 +		udelay(40);
  2.6292 +	}
  2.6293 +	test_desc.flags = 0x00000004;
  2.6294 +
  2.6295 +	for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
  2.6296 +		u32 val;
  2.6297 +
  2.6298 +		val = *(((u32 *)&test_desc) + i);
  2.6299 +		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
  2.6300 +				       sram_dma_descs + (i * sizeof(u32)));
  2.6301 +		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  2.6302 +	}
  2.6303 +	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  2.6304 +
  2.6305 +	if (to_device) {
  2.6306 +		tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
  2.6307 +	} else {
  2.6308 +		tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
  2.6309 +	}
  2.6310 +
  2.6311 +	ret = -ENODEV;
  2.6312 +	for (i = 0; i < 40; i++) {
  2.6313 +		u32 val;
  2.6314 +
  2.6315 +		if (to_device)
  2.6316 +			val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
  2.6317 +		else
  2.6318 +			val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
  2.6319 +		if ((val & 0xffff) == sram_dma_descs) {
  2.6320 +			ret = 0;
  2.6321 +			break;
  2.6322 +		}
  2.6323 +
  2.6324 +		udelay(100);
  2.6325 +	}
  2.6326 +
  2.6327 +	return ret;
  2.6328 +}
  2.6329 +
  2.6330 +#define TEST_BUFFER_SIZE	0x400
  2.6331 +
  2.6332 +static int __devinit tg3_test_dma(struct tg3 *tp)
  2.6333 +{
  2.6334 +	dma_addr_t buf_dma;
  2.6335 +	u32 *buf;
  2.6336 +	int ret;
  2.6337 +
  2.6338 +	buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
  2.6339 +	if (!buf) {
  2.6340 +		ret = -ENOMEM;
  2.6341 +		goto out_nofree;
  2.6342 +	}
  2.6343 +
  2.6344 +	tw32(TG3PCI_CLOCK_CTRL, 0);
  2.6345 +
  2.6346 +	if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) {
  2.6347 +		tp->dma_rwctrl =
  2.6348 +			(0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  2.6349 +			(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
  2.6350 +			(0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  2.6351 +			(0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
  2.6352 +			(0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
  2.6353 +	} else {
  2.6354 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  2.6355 +			tp->dma_rwctrl =
  2.6356 +				(0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  2.6357 +				(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
  2.6358 +				(0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  2.6359 +				(0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
  2.6360 +				(0x00 << DMA_RWCTRL_MIN_DMA_SHIFT);
  2.6361 +		else
  2.6362 +			tp->dma_rwctrl =
  2.6363 +				(0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  2.6364 +				(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
  2.6365 +				(0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  2.6366 +				(0x3 << DMA_RWCTRL_READ_WATER_SHIFT) |
  2.6367 +				(0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
  2.6368 +
  2.6369 +		/* Wheee, some more chip bugs... */
  2.6370 +		if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1 ||
  2.6371 +		    tp->pci_chip_rev_id == CHIPREV_ID_5703_A2 ||
  2.6372 +		    tp->pci_chip_rev_id == CHIPREV_ID_5703_A3 ||
  2.6373 +		    tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
  2.6374 +			tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  2.6375 +	}
  2.6376 +
  2.6377 +	/* We don't do this on x86 because it seems to hurt performace.
  2.6378 +	 * It does help things on other platforms though.
  2.6379 +	 */
  2.6380 +#ifndef CONFIG_X86
  2.6381 +	{
  2.6382 +		u8 byte;
  2.6383 +		int cacheline_size;
  2.6384 +		pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
  2.6385 +
  2.6386 +		if (byte == 0)
  2.6387 +			cacheline_size = 1024;
  2.6388 +		else
  2.6389 +			cacheline_size = (int) byte * 4;
  2.6390 +
  2.6391 +		tp->dma_rwctrl &= ~(DMA_RWCTRL_READ_BNDRY_MASK |
  2.6392 +				    DMA_RWCTRL_WRITE_BNDRY_MASK);
  2.6393 +
  2.6394 +		switch (cacheline_size) {
  2.6395 +		case 16:
  2.6396 +			tp->dma_rwctrl |=
  2.6397 +				(DMA_RWCTRL_READ_BNDRY_16 |
  2.6398 +				 DMA_RWCTRL_WRITE_BNDRY_16);
  2.6399 +			break;
  2.6400 +
  2.6401 +		case 32:
  2.6402 +			tp->dma_rwctrl |=
  2.6403 +				(DMA_RWCTRL_READ_BNDRY_32 |
  2.6404 +				 DMA_RWCTRL_WRITE_BNDRY_32);
  2.6405 +			break;
  2.6406 +
  2.6407 +		case 64:
  2.6408 +			tp->dma_rwctrl |=
  2.6409 +				(DMA_RWCTRL_READ_BNDRY_64 |
  2.6410 +				 DMA_RWCTRL_WRITE_BNDRY_64);
  2.6411 +			break;
  2.6412 +
  2.6413 +		case 128:
  2.6414 +			tp->dma_rwctrl |=
  2.6415 +				(DMA_RWCTRL_READ_BNDRY_128 |
  2.6416 +				 DMA_RWCTRL_WRITE_BNDRY_128);
  2.6417 +			break;
  2.6418 +
  2.6419 +		case 256:
  2.6420 +			tp->dma_rwctrl |=
  2.6421 +				(DMA_RWCTRL_READ_BNDRY_256 |
  2.6422 +				 DMA_RWCTRL_WRITE_BNDRY_256);
  2.6423 +			break;
  2.6424 +
  2.6425 +		case 512:
  2.6426 +			tp->dma_rwctrl |=
  2.6427 +				(DMA_RWCTRL_READ_BNDRY_512 |
  2.6428 +				 DMA_RWCTRL_WRITE_BNDRY_512);
  2.6429 +			break;
  2.6430 +
  2.6431 +		case 1024:
  2.6432 +			tp->dma_rwctrl |=
  2.6433 +				(DMA_RWCTRL_READ_BNDRY_1024 |
  2.6434 +				 DMA_RWCTRL_WRITE_BNDRY_1024);
  2.6435 +			break;
  2.6436 +		};
  2.6437 +	}
  2.6438 +#endif
  2.6439 +
  2.6440 +	/* Remove this if it causes problems for some boards. */
  2.6441 +	tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  2.6442 +
  2.6443 +	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  2.6444 +
  2.6445 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  2.6446 +	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  2.6447 +		return 0;
  2.6448 +
  2.6449 +	ret = 0;
  2.6450 +	while (1) {
  2.6451 +		u32 *p, i;
  2.6452 +
  2.6453 +		p = buf;
  2.6454 +		for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  2.6455 +			p[i] = i;
  2.6456 +
  2.6457 +		/* Send the buffer to the chip. */
  2.6458 +		ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
  2.6459 +		if (ret)
  2.6460 +			break;
  2.6461 +
  2.6462 +		p = buf;
  2.6463 +		for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  2.6464 +			p[i] = 0;
  2.6465 +
  2.6466 +		/* Now read it back. */
  2.6467 +		ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
  2.6468 +		if (ret)
  2.6469 +			break;
  2.6470 +
  2.6471 +		/* Verify it. */
  2.6472 +		p = buf;
  2.6473 +		for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  2.6474 +			if (p[i] == i)
  2.6475 +				continue;
  2.6476 +
  2.6477 +			if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) ==
  2.6478 +			    DMA_RWCTRL_WRITE_BNDRY_DISAB) {
  2.6479 +				tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  2.6480 +				tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  2.6481 +				break;
  2.6482 +			} else {
  2.6483 +				ret = -ENODEV;
  2.6484 +				goto out;
  2.6485 +			}
  2.6486 +		}
  2.6487 +
  2.6488 +		if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
  2.6489 +			/* Success. */
  2.6490 +			ret = 0;
  2.6491 +			break;
  2.6492 +		}
  2.6493 +	}
  2.6494 +
  2.6495 +out:
  2.6496 +	pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
  2.6497 +out_nofree:
  2.6498 +	return ret;
  2.6499 +}
  2.6500 +
  2.6501 +static void __devinit tg3_init_link_config(struct tg3 *tp)
  2.6502 +{
  2.6503 +	tp->link_config.advertising =
  2.6504 +		(ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  2.6505 +		 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  2.6506 +		 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
  2.6507 +		 ADVERTISED_Autoneg | ADVERTISED_MII);
  2.6508 +	tp->link_config.speed = SPEED_INVALID;
  2.6509 +	tp->link_config.duplex = DUPLEX_INVALID;
  2.6510 +	tp->link_config.autoneg = AUTONEG_ENABLE;
  2.6511 +	netif_carrier_off(tp->dev);
  2.6512 +	tp->link_config.active_speed = SPEED_INVALID;
  2.6513 +	tp->link_config.active_duplex = DUPLEX_INVALID;
  2.6514 +	tp->link_config.phy_is_low_power = 0;
  2.6515 +	tp->link_config.orig_speed = SPEED_INVALID;
  2.6516 +	tp->link_config.orig_duplex = DUPLEX_INVALID;
  2.6517 +	tp->link_config.orig_autoneg = AUTONEG_INVALID;
  2.6518 +}
  2.6519 +
  2.6520 +static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
  2.6521 +{
  2.6522 +	tp->bufmgr_config.mbuf_read_dma_low_water =
  2.6523 +		DEFAULT_MB_RDMA_LOW_WATER;
  2.6524 +	tp->bufmgr_config.mbuf_mac_rx_low_water =
  2.6525 +		DEFAULT_MB_MACRX_LOW_WATER;
  2.6526 +	tp->bufmgr_config.mbuf_high_water =
  2.6527 +		DEFAULT_MB_HIGH_WATER;
  2.6528 +
  2.6529 +	tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  2.6530 +		DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
  2.6531 +	tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  2.6532 +		DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
  2.6533 +	tp->bufmgr_config.mbuf_high_water_jumbo =
  2.6534 +		DEFAULT_MB_HIGH_WATER_JUMBO;
  2.6535 +
  2.6536 +	tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
  2.6537 +	tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
  2.6538 +}
  2.6539 +
  2.6540 +static char * __devinit tg3_phy_string(struct tg3 *tp)
  2.6541 +{
  2.6542 +	switch (tp->phy_id & PHY_ID_MASK) {
  2.6543 +	case PHY_ID_BCM5400:	return "5400";
  2.6544 +	case PHY_ID_BCM5401:	return "5401";
  2.6545 +	case PHY_ID_BCM5411:	return "5411";
  2.6546 +	case PHY_ID_BCM5701:	return "5701";
  2.6547 +	case PHY_ID_BCM5703:	return "5703";
  2.6548 +	case PHY_ID_BCM5704:	return "5704";
  2.6549 +	case PHY_ID_BCM8002:	return "8002";
  2.6550 +	case PHY_ID_SERDES:	return "serdes";
  2.6551 +	default:		return "unknown";
  2.6552 +	};
  2.6553 +}
  2.6554 +
  2.6555 +static int __devinit tg3_init_one(struct pci_dev *pdev,
  2.6556 +				  const struct pci_device_id *ent)
  2.6557 +{
  2.6558 +	static int tg3_version_printed = 0;
  2.6559 +	unsigned long tg3reg_base, tg3reg_len;
  2.6560 +	struct net_device *dev;
  2.6561 +	struct tg3 *tp;
  2.6562 +	int i, err, pci_using_dac, pm_cap;
  2.6563 +
  2.6564 +	if (tg3_version_printed++ == 0)
  2.6565 +		printk(KERN_INFO "%s", version);
  2.6566 +
  2.6567 +	err = pci_enable_device(pdev);
  2.6568 +	if (err) {
  2.6569 +		printk(KERN_ERR PFX "Cannot enable PCI device, "
  2.6570 +		       "aborting.\n");
  2.6571 +		return err;
  2.6572 +	}
  2.6573 +
  2.6574 +	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  2.6575 +		printk(KERN_ERR PFX "Cannot find proper PCI device "
  2.6576 +		       "base address, aborting.\n");
  2.6577 +		err = -ENODEV;
  2.6578 +		goto err_out_disable_pdev;
  2.6579 +	}
  2.6580 +
  2.6581 +	err = pci_request_regions(pdev, DRV_MODULE_NAME);
  2.6582 +	if (err) {
  2.6583 +		printk(KERN_ERR PFX "Cannot obtain PCI resources, "
  2.6584 +		       "aborting.\n");
  2.6585 +		goto err_out_disable_pdev;
  2.6586 +	}
  2.6587 +
  2.6588 +	pci_set_master(pdev);
  2.6589 +
  2.6590 +	/* Find power-management capability. */
  2.6591 +	pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  2.6592 +	if (pm_cap == 0) {
  2.6593 +		printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
  2.6594 +		       "aborting.\n");
  2.6595 +		goto err_out_free_res;
  2.6596 +	}
  2.6597 +
  2.6598 +	/* Configure DMA attributes. */
  2.6599 +	if (!pci_set_dma_mask(pdev, (u64) 0xffffffffffffffff)) {
  2.6600 +		pci_using_dac = 1;
  2.6601 +	} else {
  2.6602 +		err = pci_set_dma_mask(pdev, (u64) 0xffffffff);
  2.6603 +		if (err) {
  2.6604 +			printk(KERN_ERR PFX "No usable DMA configuration, "
  2.6605 +			       "aborting.\n");
  2.6606 +			goto err_out_free_res;
  2.6607 +		}
  2.6608 +		pci_using_dac = 0;
  2.6609 +	}
  2.6610 +
  2.6611 +	tg3reg_base = pci_resource_start(pdev, 0);
  2.6612 +	tg3reg_len = pci_resource_len(pdev, 0);
  2.6613 +
  2.6614 +	dev = alloc_etherdev(sizeof(*tp));
  2.6615 +	if (!dev) {
  2.6616 +		printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
  2.6617 +		err = -ENOMEM;
  2.6618 +		goto err_out_free_res;
  2.6619 +	}
  2.6620 +
  2.6621 +	SET_MODULE_OWNER(dev);
  2.6622 +
  2.6623 +	if (pci_using_dac)
  2.6624 +		dev->features |= NETIF_F_HIGHDMA;
  2.6625 +#if TG3_VLAN_TAG_USED
  2.6626 +	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  2.6627 +	dev->vlan_rx_register = tg3_vlan_rx_register;
  2.6628 +	dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
  2.6629 +#endif
  2.6630 +#if TG3_DO_TSO != 0
  2.6631 +	dev->features |= NETIF_F_TSO;
  2.6632 +#endif
  2.6633 +
  2.6634 +	tp = dev->priv;
  2.6635 +	tp->pdev = pdev;
  2.6636 +	tp->dev = dev;
  2.6637 +	tp->pm_cap = pm_cap;
  2.6638 +	tp->mac_mode = TG3_DEF_MAC_MODE;
  2.6639 +	tp->rx_mode = TG3_DEF_RX_MODE;
  2.6640 +	tp->tx_mode = TG3_DEF_TX_MODE;
  2.6641 +	tp->mi_mode = MAC_MI_MODE_BASE;
  2.6642 +	if (tg3_debug > 0)
  2.6643 +		tp->msg_enable = tg3_debug;
  2.6644 +	else
  2.6645 +		tp->msg_enable = TG3_DEF_MSG_ENABLE;
  2.6646 +
  2.6647 +	/* The word/byte swap controls here control register access byte
  2.6648 +	 * swapping.  DMA data byte swapping is controlled in the GRC_MODE
  2.6649 +	 * setting below.
  2.6650 +	 */
  2.6651 +	tp->misc_host_ctrl =
  2.6652 +		MISC_HOST_CTRL_MASK_PCI_INT |
  2.6653 +		MISC_HOST_CTRL_WORD_SWAP |
  2.6654 +		MISC_HOST_CTRL_INDIR_ACCESS |
  2.6655 +		MISC_HOST_CTRL_PCISTATE_RW;
  2.6656 +
  2.6657 +	/* The NONFRM (non-frame) byte/word swap controls take effect
  2.6658 +	 * on descriptor entries, anything which isn't packet data.
  2.6659 +	 *
  2.6660 +	 * The StrongARM chips on the board (one for tx, one for rx)
  2.6661 +	 * are running in big-endian mode.
  2.6662 +	 */
  2.6663 +	tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
  2.6664 +			GRC_MODE_WSWAP_NONFRM_DATA);
  2.6665 +#ifdef __BIG_ENDIAN
  2.6666 +	tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
  2.6667 +#endif
  2.6668 +	spin_lock_init(&tp->lock);
  2.6669 +	spin_lock_init(&tp->tx_lock);
  2.6670 +	spin_lock_init(&tp->indirect_lock);
  2.6671 +
  2.6672 +	tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len);
  2.6673 +	if (tp->regs == 0UL) {
  2.6674 +		printk(KERN_ERR PFX "Cannot map device registers, "
  2.6675 +		       "aborting.\n");
  2.6676 +		err = -ENOMEM;
  2.6677 +		goto err_out_free_dev;
  2.6678 +	}
  2.6679 +
  2.6680 +	tg3_init_link_config(tp);
  2.6681 +
  2.6682 +	tg3_init_bufmgr_config(tp);
  2.6683 +
  2.6684 +	tp->rx_pending = TG3_DEF_RX_RING_PENDING;
  2.6685 +	tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
  2.6686 +	tp->tx_pending = TG3_DEF_TX_RING_PENDING;
  2.6687 +
  2.6688 +	dev->open = tg3_open;
  2.6689 +	dev->stop = tg3_close;
  2.6690 +	dev->get_stats = tg3_get_stats;
  2.6691 +	dev->set_multicast_list = tg3_set_rx_mode;
  2.6692 +	dev->set_mac_address = tg3_set_mac_addr;
  2.6693 +	dev->do_ioctl = tg3_ioctl;
  2.6694 +	dev->tx_timeout = tg3_tx_timeout;
  2.6695 +#ifdef NAPI
  2.6696 +	dev->poll = tg3_poll;
  2.6697 +	dev->weight = 64;
  2.6698 +#endif
  2.6699 +	dev->watchdog_timeo = TG3_TX_TIMEOUT;
  2.6700 +	dev->change_mtu = tg3_change_mtu;
  2.6701 +	dev->irq = pdev->irq;
  2.6702 +
  2.6703 +	err = tg3_get_invariants(tp);
  2.6704 +	if (err) {
  2.6705 +		printk(KERN_ERR PFX "Problem fetching invariants of chip, "
  2.6706 +		       "aborting.\n");
  2.6707 +		goto err_out_iounmap;
  2.6708 +	}
  2.6709 +
  2.6710 +	err = tg3_get_device_address(tp);
  2.6711 +	if (err) {
  2.6712 +		printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
  2.6713 +		       "aborting.\n");
  2.6714 +		goto err_out_iounmap;
  2.6715 +	}
  2.6716 +
  2.6717 +	err = tg3_test_dma(tp);
  2.6718 +	if (err) {
  2.6719 +		printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
  2.6720 +		goto err_out_iounmap;
  2.6721 +	}
  2.6722 +
  2.6723 +	/* Tigon3 can do ipv4 only... and some chips have buggy
  2.6724 +	 * checksumming.
  2.6725 +	 */
  2.6726 +	if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
  2.6727 +		dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
  2.6728 +		tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  2.6729 +	} else
  2.6730 +		tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  2.6731 +
  2.6732 +	err = register_netdev(dev);
  2.6733 +	if (err) {
  2.6734 +		printk(KERN_ERR PFX "Cannot register net device, "
  2.6735 +		       "aborting.\n");
  2.6736 +		goto err_out_iounmap;
  2.6737 +	}
  2.6738 +
  2.6739 +	pci_set_drvdata(pdev, dev);
  2.6740 +
  2.6741 +	/* Now that we have fully setup the chip, save away a snapshot
  2.6742 +	 * of the PCI config space.  We need to restore this after
  2.6743 +	 * GRC_MISC_CFG core clock resets and some resume events.
  2.6744 +	 */
  2.6745 +	pci_save_state(tp->pdev, tp->pci_cfg_state);
  2.6746 +
  2.6747 +	printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
  2.6748 +	       dev->name,
  2.6749 +	       tp->board_part_number,
  2.6750 +	       tp->pci_chip_rev_id,
  2.6751 +	       tg3_phy_string(tp),
  2.6752 +	       ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
  2.6753 +	       ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
  2.6754 +		((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
  2.6755 +		((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
  2.6756 +	       ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
  2.6757 +	       (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
  2.6758 +
  2.6759 +	for (i = 0; i < 6; i++)
  2.6760 +		printk("%2.2x%c", dev->dev_addr[i],
  2.6761 +		       i == 5 ? '\n' : ':');
  2.6762 +
  2.6763 +	return 0;
  2.6764 +
  2.6765 +err_out_iounmap:
  2.6766 +	iounmap((void *) tp->regs);
  2.6767 +
  2.6768 +err_out_free_dev:
  2.6769 +	kfree(dev);
  2.6770 +
  2.6771 +err_out_free_res:
  2.6772 +	pci_release_regions(pdev);
  2.6773 +
  2.6774 +err_out_disable_pdev:
  2.6775 +	pci_disable_device(pdev);
  2.6776 +	pci_set_drvdata(pdev, NULL);
  2.6777 +	return err;
  2.6778 +}
  2.6779 +
  2.6780 +static void __devexit tg3_remove_one(struct pci_dev *pdev)
  2.6781 +{
  2.6782 +	struct net_device *dev = pci_get_drvdata(pdev);
  2.6783 +
  2.6784 +	if (dev) {
  2.6785 +		unregister_netdev(dev);
  2.6786 +		iounmap((void *) ((struct tg3 *)(dev->priv))->regs);
  2.6787 +		kfree(dev);
  2.6788 +		pci_release_regions(pdev);
  2.6789 +		pci_disable_device(pdev);
  2.6790 +		pci_set_drvdata(pdev, NULL);
  2.6791 +	}
  2.6792 +}
  2.6793 +
  2.6794 +static int tg3_suspend(struct pci_dev *pdev, u32 state)
  2.6795 +{
  2.6796 +	struct net_device *dev = pci_get_drvdata(pdev);
  2.6797 +	struct tg3 *tp = dev->priv;
  2.6798 +	int err;
  2.6799 +
  2.6800 +	if (!netif_running(dev))
  2.6801 +		return 0;
  2.6802 +
  2.6803 +	spin_lock_irq(&tp->lock);
  2.6804 +	spin_lock(&tp->tx_lock);
  2.6805 +	tg3_disable_ints(tp);
  2.6806 +	spin_unlock(&tp->tx_lock);
  2.6807 +	spin_unlock_irq(&tp->lock);
  2.6808 +
  2.6809 +	netif_device_detach(dev);
  2.6810 +
  2.6811 +	spin_lock_irq(&tp->lock);
  2.6812 +	spin_lock(&tp->tx_lock);
  2.6813 +	tg3_halt(tp);
  2.6814 +	spin_unlock(&tp->tx_lock);
  2.6815 +	spin_unlock_irq(&tp->lock);
  2.6816 +
  2.6817 +	err = tg3_set_power_state(tp, state);
  2.6818 +	if (err) {
  2.6819 +		spin_lock_irq(&tp->lock);
  2.6820 +		spin_lock(&tp->tx_lock);
  2.6821 +
  2.6822 +		tg3_init_rings(tp);
  2.6823 +		tg3_init_hw(tp);
  2.6824 +
  2.6825 +		spin_unlock(&tp->tx_lock);
  2.6826 +		spin_unlock_irq(&tp->lock);
  2.6827 +
  2.6828 +		netif_device_attach(dev);
  2.6829 +	}
  2.6830 +
  2.6831 +	return err;
  2.6832 +}
  2.6833 +
  2.6834 +static int tg3_resume(struct pci_dev *pdev)
  2.6835 +{
  2.6836 +	struct net_device *dev = pci_get_drvdata(pdev);
  2.6837 +	struct tg3 *tp = dev->priv;
  2.6838 +	int err;
  2.6839 +
  2.6840 +	if (!netif_running(dev))
  2.6841 +		return 0;
  2.6842 +
  2.6843 +	err = tg3_set_power_state(tp, 0);
  2.6844 +	if (err)
  2.6845 +		return err;
  2.6846 +
  2.6847 +	netif_device_attach(dev);
  2.6848 +
  2.6849 +	spin_lock_irq(&tp->lock);
  2.6850 +	spin_lock(&tp->tx_lock);
  2.6851 +
  2.6852 +	tg3_init_rings(tp);
  2.6853 +	tg3_init_hw(tp);
  2.6854 +	tg3_enable_ints(tp);
  2.6855 +
  2.6856 +	spin_unlock(&tp->tx_lock);
  2.6857 +	spin_unlock_irq(&tp->lock);
  2.6858 +
  2.6859 +	return 0;
  2.6860 +}
  2.6861 +
  2.6862 +static struct pci_driver tg3_driver = {
  2.6863 +	.name		= DRV_MODULE_NAME,
  2.6864 +	.id_table	= tg3_pci_tbl,
  2.6865 +	.probe		= tg3_init_one,
  2.6866 +	.remove		= __devexit_p(tg3_remove_one),
  2.6867 +	.suspend	= tg3_suspend,
  2.6868 +	.resume		= tg3_resume
  2.6869 +};
  2.6870 +
  2.6871 +static int __init tg3_init(void)
  2.6872 +{
  2.6873 +	return pci_module_init(&tg3_driver);
  2.6874 +}
  2.6875 +
  2.6876 +static void __exit tg3_cleanup(void)
  2.6877 +{
  2.6878 +	pci_unregister_driver(&tg3_driver);
  2.6879 +}
  2.6880 +
  2.6881 +module_init(tg3_init);
  2.6882 +module_exit(tg3_cleanup);
     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/xen-2.4.16/drivers/net/tg3.h	Sun Feb 09 00:29:16 2003 +0000
     3.3 @@ -0,0 +1,1893 @@
     3.4 +/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
     3.5 + * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
     3.6 + *
     3.7 + * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
     3.8 + * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
     3.9 + */
    3.10 +
    3.11 +#ifndef _T3_H
    3.12 +#define _T3_H
    3.13 +
    3.14 +#define TG3_64BIT_REG_HIGH		0x00UL
    3.15 +#define TG3_64BIT_REG_LOW		0x04UL
    3.16 +
    3.17 +/* Descriptor block info. */
    3.18 +#define TG3_BDINFO_HOST_ADDR		0x0UL /* 64-bit */
    3.19 +#define TG3_BDINFO_MAXLEN_FLAGS		0x8UL /* 32-bit */
    3.20 +#define  BDINFO_FLAGS_USE_EXT_RECV	 0x00000001 /* ext rx_buffer_desc */
    3.21 +#define  BDINFO_FLAGS_DISABLED		 0x00000002
    3.22 +#define  BDINFO_FLAGS_MAXLEN_MASK	 0xffff0000
    3.23 +#define  BDINFO_FLAGS_MAXLEN_SHIFT	 16
    3.24 +#define TG3_BDINFO_NIC_ADDR		0xcUL /* 32-bit */
    3.25 +#define TG3_BDINFO_SIZE			0x10UL
    3.26 +
    3.27 +#define RX_COPY_THRESHOLD  		256
    3.28 +
    3.29 +#define RX_STD_MAX_SIZE			1536
    3.30 +#define RX_JUMBO_MAX_SIZE		0xdeadbeef /* XXX */
    3.31 +
    3.32 +/* First 256 bytes are a mirror of PCI config space. */
    3.33 +#define TG3PCI_VENDOR			0x00000000
    3.34 +#define  TG3PCI_VENDOR_BROADCOM		 0x14e4
    3.35 +#define TG3PCI_DEVICE			0x00000002
    3.36 +#define  TG3PCI_DEVICE_TIGON3_1		 0x1644 /* BCM5700 */
    3.37 +#define  TG3PCI_DEVICE_TIGON3_2		 0x1645 /* BCM5701 */
    3.38 +#define  TG3PCI_DEVICE_TIGON3_3		 0x1646 /* BCM5702 */
    3.39 +#define  TG3PCI_DEVICE_TIGON3_4		 0x1647 /* BCM5703 */
    3.40 +#define TG3PCI_COMMAND			0x00000004
    3.41 +#define TG3PCI_STATUS			0x00000006
    3.42 +#define TG3PCI_CCREVID			0x00000008
    3.43 +#define TG3PCI_CACHELINESZ		0x0000000c
    3.44 +#define TG3PCI_LATTIMER			0x0000000d
    3.45 +#define TG3PCI_HEADERTYPE		0x0000000e
    3.46 +#define TG3PCI_BIST			0x0000000f
    3.47 +#define TG3PCI_BASE0_LOW		0x00000010
    3.48 +#define TG3PCI_BASE0_HIGH		0x00000014
    3.49 +/* 0x18 --> 0x2c unused */
    3.50 +#define TG3PCI_SUBSYSVENID		0x0000002c
    3.51 +#define TG3PCI_SUBSYSID			0x0000002e
    3.52 +#define TG3PCI_ROMADDR			0x00000030
    3.53 +#define TG3PCI_CAPLIST			0x00000034
    3.54 +/* 0x35 --> 0x3c unused */
    3.55 +#define TG3PCI_IRQ_LINE			0x0000003c
    3.56 +#define TG3PCI_IRQ_PIN			0x0000003d
    3.57 +#define TG3PCI_MIN_GNT			0x0000003e
    3.58 +#define TG3PCI_MAX_LAT			0x0000003f
    3.59 +#define TG3PCI_X_CAPS			0x00000040
    3.60 +#define  PCIX_CAPS_RELAXED_ORDERING	 0x00020000
    3.61 +#define  PCIX_CAPS_SPLIT_MASK		 0x00700000
    3.62 +#define  PCIX_CAPS_SPLIT_SHIFT		 20
    3.63 +#define  PCIX_CAPS_BURST_MASK		 0x000c0000
    3.64 +#define  PCIX_CAPS_BURST_SHIFT		 18
    3.65 +#define  PCIX_CAPS_MAX_BURST_5704	 2
    3.66 +#define TG3PCI_PM_CAP_PTR		0x00000041
    3.67 +#define TG3PCI_X_COMMAND		0x00000042
    3.68 +#define TG3PCI_X_STATUS			0x00000044
    3.69 +#define TG3PCI_PM_CAP_ID		0x00000048
    3.70 +#define TG3PCI_VPD_CAP_PTR		0x00000049
    3.71 +#define TG3PCI_PM_CAPS			0x0000004a
    3.72 +#define TG3PCI_PM_CTRL_STAT		0x0000004c
    3.73 +#define TG3PCI_BR_SUPP_EXT		0x0000004e
    3.74 +#define TG3PCI_PM_DATA			0x0000004f
    3.75 +#define TG3PCI_VPD_CAP_ID		0x00000050
    3.76 +#define TG3PCI_MSI_CAP_PTR		0x00000051
    3.77 +#define TG3PCI_VPD_ADDR_FLAG		0x00000052
    3.78 +#define  VPD_ADDR_FLAG_WRITE		0x00008000
    3.79 +#define TG3PCI_VPD_DATA			0x00000054
    3.80 +#define TG3PCI_MSI_CAP_ID		0x00000058
    3.81 +#define TG3PCI_NXT_CAP_PTR		0x00000059
    3.82 +#define TG3PCI_MSI_CTRL			0x0000005a
    3.83 +#define TG3PCI_MSI_ADDR_LOW		0x0000005c
    3.84 +#define TG3PCI_MSI_ADDR_HIGH		0x00000060
    3.85 +#define TG3PCI_MSI_DATA			0x00000064
    3.86 +/* 0x66 --> 0x68 unused */
    3.87 +#define TG3PCI_MISC_HOST_CTRL		0x00000068
    3.88 +#define  MISC_HOST_CTRL_CLEAR_INT	 0x00000001
    3.89 +#define  MISC_HOST_CTRL_MASK_PCI_INT	 0x00000002
    3.90 +#define  MISC_HOST_CTRL_BYTE_SWAP	 0x00000004
    3.91 +#define  MISC_HOST_CTRL_WORD_SWAP	 0x00000008
    3.92 +#define  MISC_HOST_CTRL_PCISTATE_RW	 0x00000010
    3.93 +#define  MISC_HOST_CTRL_CLKREG_RW	 0x00000020
    3.94 +#define  MISC_HOST_CTRL_REGWORD_SWAP	 0x00000040
    3.95 +#define  MISC_HOST_CTRL_INDIR_ACCESS	 0x00000080
    3.96 +#define  MISC_HOST_CTRL_IRQ_MASK_MODE	 0x00000100
    3.97 +#define  MISC_HOST_CTRL_TAGGED_STATUS	 0x00000200
    3.98 +#define  MISC_HOST_CTRL_CHIPREV		 0xffff0000
    3.99 +#define  MISC_HOST_CTRL_CHIPREV_SHIFT	 16
   3.100 +#define  GET_CHIP_REV_ID(MISC_HOST_CTRL) \
   3.101 +	 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
   3.102 +	  MISC_HOST_CTRL_CHIPREV_SHIFT)
   3.103 +#define  CHIPREV_ID_5700_A0		 0x7000
   3.104 +#define  CHIPREV_ID_5700_A1		 0x7001
   3.105 +#define  CHIPREV_ID_5700_B0		 0x7100
   3.106 +#define  CHIPREV_ID_5700_B1		 0x7101
   3.107 +#define  CHIPREV_ID_5700_B3		 0x7102
   3.108 +#define  CHIPREV_ID_5700_ALTIMA		 0x7104
   3.109 +#define  CHIPREV_ID_5700_C0		 0x7200
   3.110 +#define  CHIPREV_ID_5701_A0		 0x0000
   3.111 +#define  CHIPREV_ID_5701_B0		 0x0100
   3.112 +#define  CHIPREV_ID_5701_B2		 0x0102
   3.113 +#define  CHIPREV_ID_5701_B5		 0x0105
   3.114 +#define  CHIPREV_ID_5703_A0		 0x1000
   3.115 +#define  CHIPREV_ID_5703_A1		 0x1001
   3.116 +#define  CHIPREV_ID_5703_A2		 0x1002
   3.117 +#define  CHIPREV_ID_5703_A3		 0x1003
   3.118 +#define  CHIPREV_ID_5704_A0		 0x2000
   3.119 +#define  CHIPREV_ID_5704_A1		 0x2001
   3.120 +#define  CHIPREV_ID_5704_A2		 0x2002
   3.121 +#define  GET_ASIC_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 12)
   3.122 +#define   ASIC_REV_5700			 0x07
   3.123 +#define   ASIC_REV_5701			 0x00
   3.124 +#define   ASIC_REV_5703			 0x01
   3.125 +#define   ASIC_REV_5704			 0x02
   3.126 +#define  GET_CHIP_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 8)
   3.127 +#define   CHIPREV_5700_AX		 0x70
   3.128 +#define   CHIPREV_5700_BX		 0x71
   3.129 +#define   CHIPREV_5700_CX		 0x72
   3.130 +#define   CHIPREV_5701_AX		 0x00
   3.131 +#define  GET_METAL_REV(CHIP_REV_ID)	((CHIP_REV_ID) & 0xff)
   3.132 +#define   METAL_REV_A0			 0x00
   3.133 +#define   METAL_REV_A1			 0x01
   3.134 +#define   METAL_REV_B0			 0x00
   3.135 +#define   METAL_REV_B1			 0x01
   3.136 +#define   METAL_REV_B2			 0x02
   3.137 +#define TG3PCI_DMA_RW_CTRL		0x0000006c
   3.138 +#define  DMA_RWCTRL_MIN_DMA		 0x000000ff
   3.139 +#define  DMA_RWCTRL_MIN_DMA_SHIFT	 0
   3.140 +#define  DMA_RWCTRL_READ_BNDRY_MASK	 0x00000700
   3.141 +#define  DMA_RWCTRL_READ_BNDRY_DISAB	 0x00000000
   3.142 +#define  DMA_RWCTRL_READ_BNDRY_16	 0x00000100
   3.143 +#define  DMA_RWCTRL_READ_BNDRY_32	 0x00000200
   3.144 +#define  DMA_RWCTRL_READ_BNDRY_64	 0x00000300
   3.145 +#define  DMA_RWCTRL_READ_BNDRY_128	 0x00000400
   3.146 +#define  DMA_RWCTRL_READ_BNDRY_256	 0x00000500
   3.147 +#define  DMA_RWCTRL_READ_BNDRY_512	 0x00000600
   3.148 +#define  DMA_RWCTRL_READ_BNDRY_1024	 0x00000700
   3.149 +#define  DMA_RWCTRL_WRITE_BNDRY_MASK	 0x00003800
   3.150 +#define  DMA_RWCTRL_WRITE_BNDRY_DISAB	 0x00000000
   3.151 +#define  DMA_RWCTRL_WRITE_BNDRY_16	 0x00000800
   3.152 +#define  DMA_RWCTRL_WRITE_BNDRY_32	 0x00001000
   3.153 +#define  DMA_RWCTRL_WRITE_BNDRY_64	 0x00001800
   3.154 +#define  DMA_RWCTRL_WRITE_BNDRY_128	 0x00002000
   3.155 +#define  DMA_RWCTRL_WRITE_BNDRY_256	 0x00002800
   3.156 +#define  DMA_RWCTRL_WRITE_BNDRY_512	 0x00003000
   3.157 +#define  DMA_RWCTRL_WRITE_BNDRY_1024	 0x00003800
   3.158 +#define  DMA_RWCTRL_ONE_DMA		 0x00004000
   3.159 +#define  DMA_RWCTRL_READ_WATER		 0x00070000
   3.160 +#define  DMA_RWCTRL_READ_WATER_SHIFT	 16
   3.161 +#define  DMA_RWCTRL_WRITE_WATER		 0x00380000
   3.162 +#define  DMA_RWCTRL_WRITE_WATER_SHIFT	 19
   3.163 +#define  DMA_RWCTRL_USE_MEM_READ_MULT	 0x00400000
   3.164 +#define  DMA_RWCTRL_ASSERT_ALL_BE	 0x00800000
   3.165 +#define  DMA_RWCTRL_PCI_READ_CMD	 0x0f000000
   3.166 +#define  DMA_RWCTRL_PCI_READ_CMD_SHIFT	 24
   3.167 +#define  DMA_RWCTRL_PCI_WRITE_CMD	 0xf0000000
   3.168 +#define  DMA_RWCTRL_PCI_WRITE_CMD_SHIFT	 28
   3.169 +#define TG3PCI_PCISTATE			0x00000070
   3.170 +#define  PCISTATE_FORCE_RESET		 0x00000001
   3.171 +#define  PCISTATE_INT_NOT_ACTIVE	 0x00000002
   3.172 +#define  PCISTATE_CONV_PCI_MODE		 0x00000004
   3.173 +#define  PCISTATE_BUS_SPEED_HIGH	 0x00000008
   3.174 +#define  PCISTATE_BUS_32BIT		 0x00000010
   3.175 +#define  PCISTATE_ROM_ENABLE		 0x00000020
   3.176 +#define  PCISTATE_ROM_RETRY_ENABLE	 0x00000040
   3.177 +#define  PCISTATE_FLAT_VIEW		 0x00000100
   3.178 +#define  PCISTATE_RETRY_SAME_DMA	 0x00002000
   3.179 +#define TG3PCI_CLOCK_CTRL		0x00000074
   3.180 +#define  CLOCK_CTRL_CORECLK_DISABLE	 0x00000200
   3.181 +#define  CLOCK_CTRL_RXCLK_DISABLE	 0x00000400
   3.182 +#define  CLOCK_CTRL_TXCLK_DISABLE	 0x00000800
   3.183 +#define  CLOCK_CTRL_ALTCLK		 0x00001000
   3.184 +#define  CLOCK_CTRL_PWRDOWN_PLL133	 0x00008000
   3.185 +#define  CLOCK_CTRL_44MHZ_CORE		 0x00040000
   3.186 +#define  CLOCK_CTRL_DELAY_PCI_GRANT	 0x80000000
   3.187 +#define TG3PCI_REG_BASE_ADDR		0x00000078
   3.188 +#define TG3PCI_MEM_WIN_BASE_ADDR	0x0000007c
   3.189 +#define TG3PCI_REG_DATA			0x00000080
   3.190 +#define TG3PCI_MEM_WIN_DATA		0x00000084
   3.191 +#define TG3PCI_MODE_CTRL		0x00000088
   3.192 +#define TG3PCI_MISC_CFG			0x0000008c
   3.193 +#define TG3PCI_MISC_LOCAL_CTRL		0x00000090
   3.194 +/* 0x94 --> 0x98 unused */
   3.195 +#define TG3PCI_STD_RING_PROD_IDX	0x00000098 /* 64-bit */
   3.196 +#define TG3PCI_RCV_RET_RING_CON_IDX	0x000000a0 /* 64-bit */
   3.197 +#define TG3PCI_SND_PROD_IDX		0x000000a8 /* 64-bit */
   3.198 +/* 0xb0 --> 0x100 unused */
   3.199 +
   3.200 +/* 0x100 --> 0x200 unused */
   3.201 +
   3.202 +/* Mailbox registers */
   3.203 +#define MAILBOX_INTERRUPT_0		0x00000200 /* 64-bit */
   3.204 +#define MAILBOX_INTERRUPT_1		0x00000208 /* 64-bit */
   3.205 +#define MAILBOX_INTERRUPT_2		0x00000210 /* 64-bit */
   3.206 +#define MAILBOX_INTERRUPT_3		0x00000218 /* 64-bit */
   3.207 +#define MAILBOX_GENERAL_0		0x00000220 /* 64-bit */
   3.208 +#define MAILBOX_GENERAL_1		0x00000228 /* 64-bit */
   3.209 +#define MAILBOX_GENERAL_2		0x00000230 /* 64-bit */
   3.210 +#define MAILBOX_GENERAL_3		0x00000238 /* 64-bit */
   3.211 +#define MAILBOX_GENERAL_4		0x00000240 /* 64-bit */
   3.212 +#define MAILBOX_GENERAL_5		0x00000248 /* 64-bit */
   3.213 +#define MAILBOX_GENERAL_6		0x00000250 /* 64-bit */
   3.214 +#define MAILBOX_GENERAL_7		0x00000258 /* 64-bit */
   3.215 +#define MAILBOX_RELOAD_STAT		0x00000260 /* 64-bit */
   3.216 +#define MAILBOX_RCV_STD_PROD_IDX	0x00000268 /* 64-bit */
   3.217 +#define MAILBOX_RCV_JUMBO_PROD_IDX	0x00000270 /* 64-bit */
   3.218 +#define MAILBOX_RCV_MINI_PROD_IDX	0x00000278 /* 64-bit */
   3.219 +#define MAILBOX_RCVRET_CON_IDX_0	0x00000280 /* 64-bit */
   3.220 +#define MAILBOX_RCVRET_CON_IDX_1	0x00000288 /* 64-bit */
   3.221 +#define MAILBOX_RCVRET_CON_IDX_2	0x00000290 /* 64-bit */
   3.222 +#define MAILBOX_RCVRET_CON_IDX_3	0x00000298 /* 64-bit */
   3.223 +#define MAILBOX_RCVRET_CON_IDX_4	0x000002a0 /* 64-bit */
   3.224 +#define MAILBOX_RCVRET_CON_IDX_5	0x000002a8 /* 64-bit */
   3.225 +#define MAILBOX_RCVRET_CON_IDX_6	0x000002b0 /* 64-bit */
   3.226 +#define MAILBOX_RCVRET_CON_IDX_7	0x000002b8 /* 64-bit */
   3.227 +#define MAILBOX_RCVRET_CON_IDX_8	0x000002c0 /* 64-bit */
   3.228 +#define MAILBOX_RCVRET_CON_IDX_9	0x000002c8 /* 64-bit */
   3.229 +#define MAILBOX_RCVRET_CON_IDX_10	0x000002d0 /* 64-bit */
   3.230 +#define MAILBOX_RCVRET_CON_IDX_11	0x000002d8 /* 64-bit */
   3.231 +#define MAILBOX_RCVRET_CON_IDX_12	0x000002e0 /* 64-bit */
   3.232 +#define MAILBOX_RCVRET_CON_IDX_13	0x000002e8 /* 64-bit */
   3.233 +#define MAILBOX_RCVRET_CON_IDX_14	0x000002f0 /* 64-bit */
   3.234 +#define MAILBOX_RCVRET_CON_IDX_15	0x000002f8 /* 64-bit */
   3.235 +#define MAILBOX_SNDHOST_PROD_IDX_0	0x00000300 /* 64-bit */
   3.236 +#define MAILBOX_SNDHOST_PROD_IDX_1	0x00000308 /* 64-bit */
   3.237 +#define MAILBOX_SNDHOST_PROD_IDX_2	0x00000310 /* 64-bit */
   3.238 +#define MAILBOX_SNDHOST_PROD_IDX_3	0x00000318 /* 64-bit */
   3.239 +#define MAILBOX_SNDHOST_PROD_IDX_4	0x00000320 /* 64-bit */
   3.240 +#define MAILBOX_SNDHOST_PROD_IDX_5	0x00000328 /* 64-bit */
   3.241 +#define MAILBOX_SNDHOST_PROD_IDX_6	0x00000330 /* 64-bit */
   3.242 +#define MAILBOX_SNDHOST_PROD_IDX_7	0x00000338 /* 64-bit */
   3.243 +#define MAILBOX_SNDHOST_PROD_IDX_8	0x00000340 /* 64-bit */
   3.244 +#define MAILBOX_SNDHOST_PROD_IDX_9	0x00000348 /* 64-bit */
   3.245 +#define MAILBOX_SNDHOST_PROD_IDX_10	0x00000350 /* 64-bit */
   3.246 +#define MAILBOX_SNDHOST_PROD_IDX_11	0x00000358 /* 64-bit */
   3.247 +#define MAILBOX_SNDHOST_PROD_IDX_12	0x00000360 /* 64-bit */
   3.248 +#define MAILBOX_SNDHOST_PROD_IDX_13	0x00000368 /* 64-bit */
   3.249 +#define MAILBOX_SNDHOST_PROD_IDX_14	0x00000370 /* 64-bit */
   3.250 +#define MAILBOX_SNDHOST_PROD_IDX_15	0x00000378 /* 64-bit */
   3.251 +#define MAILBOX_SNDNIC_PROD_IDX_0	0x00000380 /* 64-bit */
   3.252 +#define MAILBOX_SNDNIC_PROD_IDX_1	0x00000388 /* 64-bit */
   3.253 +#define MAILBOX_SNDNIC_PROD_IDX_2	0x00000390 /* 64-bit */
   3.254 +#define MAILBOX_SNDNIC_PROD_IDX_3	0x00000398 /* 64-bit */
   3.255 +#define MAILBOX_SNDNIC_PROD_IDX_4	0x000003a0 /* 64-bit */
   3.256 +#define MAILBOX_SNDNIC_PROD_IDX_5	0x000003a8 /* 64-bit */
   3.257 +#define MAILBOX_SNDNIC_PROD_IDX_6	0x000003b0 /* 64-bit */
   3.258 +#define MAILBOX_SNDNIC_PROD_IDX_7	0x000003b8 /* 64-bit */
   3.259 +#define MAILBOX_SNDNIC_PROD_IDX_8	0x000003c0 /* 64-bit */
   3.260 +#define MAILBOX_SNDNIC_PROD_IDX_9	0x000003c8 /* 64-bit */
   3.261 +#define MAILBOX_SNDNIC_PROD_IDX_10	0x000003d0 /* 64-bit */
   3.262 +#define MAILBOX_SNDNIC_PROD_IDX_11	0x000003d8 /* 64-bit */
   3.263 +#define MAILBOX_SNDNIC_PROD_IDX_12	0x000003e0 /* 64-bit */
   3.264 +#define MAILBOX_SNDNIC_PROD_IDX_13	0x000003e8 /* 64-bit */
   3.265 +#define MAILBOX_SNDNIC_PROD_IDX_14	0x000003f0 /* 64-bit */
   3.266 +#define MAILBOX_SNDNIC_PROD_IDX_15	0x000003f8 /* 64-bit */
   3.267 +
   3.268 +/* MAC control registers */
   3.269 +#define MAC_MODE			0x00000400
   3.270 +#define  MAC_MODE_RESET			 0x00000001
   3.271 +#define  MAC_MODE_HALF_DUPLEX		 0x00000002
   3.272 +#define  MAC_MODE_PORT_MODE_MASK	 0x0000000c
   3.273 +#define  MAC_MODE_PORT_MODE_TBI		 0x0000000c
   3.274 +#define  MAC_MODE_PORT_MODE_GMII	 0x00000008
   3.275 +#define  MAC_MODE_PORT_MODE_MII		 0x00000004
   3.276 +#define  MAC_MODE_PORT_MODE_NONE	 0x00000000
   3.277 +#define  MAC_MODE_PORT_INT_LPBACK	 0x00000010
   3.278 +#define  MAC_MODE_TAGGED_MAC_CTRL	 0x00000080
   3.279 +#define  MAC_MODE_TX_BURSTING		 0x00000100
   3.280 +#define  MAC_MODE_MAX_DEFER		 0x00000200
   3.281 +#define  MAC_MODE_LINK_POLARITY		 0x00000400
   3.282 +#define  MAC_MODE_RXSTAT_ENABLE		 0x00000800
   3.283 +#define  MAC_MODE_RXSTAT_CLEAR		 0x00001000
   3.284 +#define  MAC_MODE_RXSTAT_FLUSH		 0x00002000
   3.285 +#define  MAC_MODE_TXSTAT_ENABLE		 0x00004000
   3.286 +#define  MAC_MODE_TXSTAT_CLEAR		 0x00008000
   3.287 +#define  MAC_MODE_TXSTAT_FLUSH		 0x00010000
   3.288 +#define  MAC_MODE_SEND_CONFIGS		 0x00020000
   3.289 +#define  MAC_MODE_MAGIC_PKT_ENABLE	 0x00040000
   3.290 +#define  MAC_MODE_ACPI_ENABLE		 0x00080000
   3.291 +#define  MAC_MODE_MIP_ENABLE		 0x00100000
   3.292 +#define  MAC_MODE_TDE_ENABLE		 0x00200000
   3.293 +#define  MAC_MODE_RDE_ENABLE		 0x00400000
   3.294 +#define  MAC_MODE_FHDE_ENABLE		 0x00800000
   3.295 +#define MAC_STATUS			0x00000404
   3.296 +#define  MAC_STATUS_PCS_SYNCED		 0x00000001
   3.297 +#define  MAC_STATUS_SIGNAL_DET		 0x00000002
   3.298 +#define  MAC_STATUS_RCVD_CFG		 0x00000004
   3.299 +#define  MAC_STATUS_CFG_CHANGED		 0x00000008
   3.300 +#define  MAC_STATUS_SYNC_CHANGED	 0x00000010
   3.301 +#define  MAC_STATUS_PORT_DEC_ERR	 0x00000400
   3.302 +#define  MAC_STATUS_LNKSTATE_CHANGED	 0x00001000
   3.303 +#define  MAC_STATUS_MI_COMPLETION	 0x00400000
   3.304 +#define  MAC_STATUS_MI_INTERRUPT	 0x00800000
   3.305 +#define  MAC_STATUS_AP_ERROR		 0x01000000
   3.306 +#define  MAC_STATUS_ODI_ERROR		 0x02000000
   3.307 +#define  MAC_STATUS_RXSTAT_OVERRUN	 0x04000000
   3.308 +#define  MAC_STATUS_TXSTAT_OVERRUN	 0x08000000
   3.309 +#define MAC_EVENT			0x00000408
   3.310 +#define  MAC_EVENT_PORT_DECODE_ERR	 0x00000400
   3.311 +#define  MAC_EVENT_LNKSTATE_CHANGED	 0x00001000
   3.312 +#define  MAC_EVENT_MI_COMPLETION	 0x00400000
   3.313 +#define  MAC_EVENT_MI_INTERRUPT		 0x00800000
   3.314 +#define  MAC_EVENT_AP_ERROR		 0x01000000
   3.315 +#define  MAC_EVENT_ODI_ERROR		 0x02000000
   3.316 +#define  MAC_EVENT_RXSTAT_OVERRUN	 0x04000000
   3.317 +#define  MAC_EVENT_TXSTAT_OVERRUN	 0x08000000
   3.318 +#define MAC_LED_CTRL			0x0000040c
   3.319 +#define  LED_CTRL_LNKLED_OVERRIDE	 0x00000001
   3.320 +#define  LED_CTRL_1000MBPS_ON		 0x00000002
   3.321 +#define  LED_CTRL_100MBPS_ON		 0x00000004
   3.322 +#define  LED_CTRL_10MBPS_ON		 0x00000008
   3.323 +#define  LED_CTRL_TRAFFIC_OVERRIDE	 0x00000010
   3.324 +#define  LED_CTRL_TRAFFIC_BLINK		 0x00000020
   3.325 +#define  LED_CTRL_TRAFFIC_LED		 0x00000040
   3.326 +#define  LED_CTRL_1000MBPS_STATUS	 0x00000080
   3.327 +#define  LED_CTRL_100MBPS_STATUS	 0x00000100
   3.328 +#define  LED_CTRL_10MBPS_STATUS		 0x00000200
   3.329 +#define  LED_CTRL_TRAFFIC_STATUS	 0x00000400
   3.330 +#define  LED_CTRL_MAC_MODE		 0x00000000
   3.331 +#define  LED_CTRL_PHY_MODE_1		 0x00000800
   3.332 +#define  LED_CTRL_PHY_MODE_2		 0x00001000
   3.333 +#define  LED_CTRL_BLINK_RATE_MASK	 0x7ff80000
   3.334 +#define  LED_CTRL_BLINK_RATE_SHIFT	 19
   3.335 +#define  LED_CTRL_BLINK_PER_OVERRIDE	 0x00080000
   3.336 +#define  LED_CTRL_BLINK_RATE_OVERRIDE	 0x80000000
   3.337 +#define MAC_ADDR_0_HIGH			0x00000410 /* upper 2 bytes */
   3.338 +#define MAC_ADDR_0_LOW			0x00000414 /* lower 4 bytes */
   3.339 +#define MAC_ADDR_1_HIGH			0x00000418 /* upper 2 bytes */
   3.340 +#define MAC_ADDR_1_LOW			0x0000041c /* lower 4 bytes */
   3.341 +#define MAC_ADDR_2_HIGH			0x00000420 /* upper 2 bytes */
   3.342 +#define MAC_ADDR_2_LOW			0x00000424 /* lower 4 bytes */
   3.343 +#define MAC_ADDR_3_HIGH			0x00000428 /* upper 2 bytes */
   3.344 +#define MAC_ADDR_3_LOW			0x0000042c /* lower 4 bytes */
   3.345 +#define MAC_ACPI_MBUF_PTR		0x00000430
   3.346 +#define MAC_ACPI_LEN_OFFSET		0x00000434
   3.347 +#define  ACPI_LENOFF_LEN_MASK		 0x0000ffff
   3.348 +#define  ACPI_LENOFF_LEN_SHIFT		 0
   3.349 +#define  ACPI_LENOFF_OFF_MASK		 0x0fff0000
   3.350 +#define  ACPI_LENOFF_OFF_SHIFT		 16
   3.351 +#define MAC_TX_BACKOFF_SEED		0x00000438
   3.352 +#define  TX_BACKOFF_SEED_MASK		 0x000003ff
   3.353 +#define MAC_RX_MTU_SIZE			0x0000043c
   3.354 +#define  RX_MTU_SIZE_MASK		 0x0000ffff
   3.355 +#define MAC_PCS_TEST			0x00000440
   3.356 +#define  PCS_TEST_PATTERN_MASK		 0x000fffff
   3.357 +#define  PCS_TEST_PATTERN_SHIFT		 0
   3.358 +#define  PCS_TEST_ENABLE		 0x00100000
   3.359 +#define MAC_TX_AUTO_NEG			0x00000444
   3.360 +#define  TX_AUTO_NEG_MASK		 0x0000ffff
   3.361 +#define  TX_AUTO_NEG_SHIFT		 0
   3.362 +#define MAC_RX_AUTO_NEG			0x00000448
   3.363 +#define  RX_AUTO_NEG_MASK		 0x0000ffff
   3.364 +#define  RX_AUTO_NEG_SHIFT		 0
   3.365 +#define MAC_MI_COM			0x0000044c
   3.366 +#define  MI_COM_CMD_MASK		 0x0c000000
   3.367 +#define  MI_COM_CMD_WRITE		 0x04000000
   3.368 +#define  MI_COM_CMD_READ		 0x08000000
   3.369 +#define  MI_COM_READ_FAILED		 0x10000000
   3.370 +#define  MI_COM_START			 0x20000000
   3.371 +#define  MI_COM_BUSY			 0x20000000
   3.372 +#define  MI_COM_PHY_ADDR_MASK		 0x03e00000
   3.373 +#define  MI_COM_PHY_ADDR_SHIFT		 21
   3.374 +#define  MI_COM_REG_ADDR_MASK		 0x001f0000
   3.375 +#define  MI_COM_REG_ADDR_SHIFT		 16
   3.376 +#define  MI_COM_DATA_MASK		 0x0000ffff
   3.377 +#define MAC_MI_STAT			0x00000450
   3.378 +#define  MAC_MI_STAT_LNKSTAT_ATTN_ENAB	 0x00000001
   3.379 +#define MAC_MI_MODE			0x00000454
   3.380 +#define  MAC_MI_MODE_CLK_10MHZ		 0x00000001
   3.381 +#define  MAC_MI_MODE_SHORT_PREAMBLE	 0x00000002
   3.382 +#define  MAC_MI_MODE_AUTO_POLL		 0x00000010
   3.383 +#define  MAC_MI_MODE_CORE_CLK_62MHZ	 0x00008000
   3.384 +#define  MAC_MI_MODE_BASE		 0x000c0000 /* XXX magic values XXX */
   3.385 +#define MAC_AUTO_POLL_STATUS		0x00000458
   3.386 +#define  MAC_AUTO_POLL_ERROR		 0x00000001
   3.387 +#define MAC_TX_MODE			0x0000045c
   3.388 +#define  TX_MODE_RESET			 0x00000001
   3.389 +#define  TX_MODE_ENABLE			 0x00000002
   3.390 +#define  TX_MODE_FLOW_CTRL_ENABLE	 0x00000010
   3.391 +#define  TX_MODE_BIG_BCKOFF_ENABLE	 0x00000020
   3.392 +#define  TX_MODE_LONG_PAUSE_ENABLE	 0x00000040
   3.393 +#define MAC_TX_STATUS			0x00000460
   3.394 +#define  TX_STATUS_XOFFED		 0x00000001
   3.395 +#define  TX_STATUS_SENT_XOFF		 0x00000002
   3.396 +#define  TX_STATUS_SENT_XON		 0x00000004
   3.397 +#define  TX_STATUS_LINK_UP		 0x00000008
   3.398 +#define  TX_STATUS_ODI_UNDERRUN		 0x00000010
   3.399 +#define  TX_STATUS_ODI_OVERRUN		 0x00000020
   3.400 +#define MAC_TX_LENGTHS			0x00000464
   3.401 +#define  TX_LENGTHS_SLOT_TIME_MASK	 0x000000ff
   3.402 +#define  TX_LENGTHS_SLOT_TIME_SHIFT	 0
   3.403 +#define  TX_LENGTHS_IPG_MASK		 0x00000f00
   3.404 +#define  TX_LENGTHS_IPG_SHIFT		 8
   3.405 +#define  TX_LENGTHS_IPG_CRS_MASK	 0x00003000
   3.406 +#define  TX_LENGTHS_IPG_CRS_SHIFT	 12
   3.407 +#define MAC_RX_MODE			0x00000468
   3.408 +#define  RX_MODE_RESET			 0x00000001
   3.409 +#define  RX_MODE_ENABLE			 0x00000002
   3.410 +#define  RX_MODE_FLOW_CTRL_ENABLE	 0x00000004
   3.411 +#define  RX_MODE_KEEP_MAC_CTRL		 0x00000008
   3.412 +#define  RX_MODE_KEEP_PAUSE		 0x00000010
   3.413 +#define  RX_MODE_ACCEPT_OVERSIZED	 0x00000020
   3.414 +#define  RX_MODE_ACCEPT_RUNTS		 0x00000040
   3.415 +#define  RX_MODE_LEN_CHECK		 0x00000080
   3.416 +#define  RX_MODE_PROMISC		 0x00000100
   3.417 +#define  RX_MODE_NO_CRC_CHECK		 0x00000200
   3.418 +#define  RX_MODE_KEEP_VLAN_TAG		 0x00000400
   3.419 +#define MAC_RX_STATUS			0x0000046c
   3.420 +#define  RX_STATUS_REMOTE_TX_XOFFED	 0x00000001
   3.421 +#define  RX_STATUS_XOFF_RCVD		 0x00000002
   3.422 +#define  RX_STATUS_XON_RCVD		 0x00000004
   3.423 +#define MAC_HASH_REG_0			0x00000470
   3.424 +#define MAC_HASH_REG_1			0x00000474
   3.425 +#define MAC_HASH_REG_2			0x00000478
   3.426 +#define MAC_HASH_REG_3			0x0000047c
   3.427 +#define MAC_RCV_RULE_0			0x00000480
   3.428 +#define MAC_RCV_VALUE_0			0x00000484
   3.429 +#define MAC_RCV_RULE_1			0x00000488
   3.430 +#define MAC_RCV_VALUE_1			0x0000048c
   3.431 +#define MAC_RCV_RULE_2			0x00000490
   3.432 +#define MAC_RCV_VALUE_2			0x00000494
   3.433 +#define MAC_RCV_RULE_3			0x00000498
   3.434 +#define MAC_RCV_VALUE_3			0x0000049c
   3.435 +#define MAC_RCV_RULE_4			0x000004a0
   3.436 +#define MAC_RCV_VALUE_4			0x000004a4
   3.437 +#define MAC_RCV_RULE_5			0x000004a8
   3.438 +#define MAC_RCV_VALUE_5			0x000004ac
   3.439 +#define MAC_RCV_RULE_6			0x000004b0
   3.440 +#define MAC_RCV_VALUE_6			0x000004b4
   3.441 +#define MAC_RCV_RULE_7			0x000004b8
   3.442 +#define MAC_RCV_VALUE_7			0x000004bc
   3.443 +#define MAC_RCV_RULE_8			0x000004c0
   3.444 +#define MAC_RCV_VALUE_8			0x000004c4
   3.445 +#define MAC_RCV_RULE_9			0x000004c8
   3.446 +#define MAC_RCV_VALUE_9			0x000004cc
   3.447 +#define MAC_RCV_RULE_10			0x000004d0
   3.448 +#define MAC_RCV_VALUE_10		0x000004d4
   3.449 +#define MAC_RCV_RULE_11			0x000004d8
   3.450 +#define MAC_RCV_VALUE_11		0x000004dc
   3.451 +#define MAC_RCV_RULE_12			0x000004e0
   3.452 +#define MAC_RCV_VALUE_12		0x000004e4
   3.453 +#define MAC_RCV_RULE_13			0x000004e8
   3.454 +#define MAC_RCV_VALUE_13		0x000004ec
   3.455 +#define MAC_RCV_RULE_14			0x000004f0
   3.456 +#define MAC_RCV_VALUE_14		0x000004f4
   3.457 +#define MAC_RCV_RULE_15			0x000004f8
   3.458 +#define MAC_RCV_VALUE_15		0x000004fc
   3.459 +#define  RCV_RULE_DISABLE_MASK		 0x7fffffff
   3.460 +#define MAC_RCV_RULE_CFG		0x00000500
   3.461 +#define  RCV_RULE_CFG_DEFAULT_CLASS	0x00000008
   3.462 +/* 0x504 --> 0x590 unused */
   3.463 +#define MAC_SERDES_CFG			0x00000590
   3.464 +#define MAC_SERDES_STAT			0x00000594
   3.465 +/* 0x598 --> 0x600 unused */
   3.466 +#define MAC_TX_MAC_STATE_BASE		0x00000600 /* 16 bytes */
   3.467 +#define MAC_RX_MAC_STATE_BASE		0x00000610 /* 20 bytes */
   3.468 +/* 0x624 --> 0x800 unused */
   3.469 +#define MAC_RX_STATS_BASE		0x00000800 /* 26 32-bit words */
   3.470 +/* 0x868 --> 0x880 unused */
   3.471 +#define MAC_TX_STATS_BASE		0x00000880 /* 28 32-bit words */
   3.472 +/* 0x8f0 --> 0xc00 unused */
   3.473 +
   3.474 +/* Send data initiator control registers */
   3.475 +#define SNDDATAI_MODE			0x00000c00
   3.476 +#define  SNDDATAI_MODE_RESET		 0x00000001
   3.477 +#define  SNDDATAI_MODE_ENABLE		 0x00000002
   3.478 +#define  SNDDATAI_MODE_STAT_OFLOW_ENAB	 0x00000004
   3.479 +#define SNDDATAI_STATUS			0x00000c04
   3.480 +#define  SNDDATAI_STATUS_STAT_OFLOW	 0x00000004
   3.481 +#define SNDDATAI_STATSCTRL		0x00000c08
   3.482 +#define  SNDDATAI_SCTRL_ENABLE		 0x00000001
   3.483 +#define  SNDDATAI_SCTRL_FASTUPD		 0x00000002
   3.484 +#define  SNDDATAI_SCTRL_CLEAR		 0x00000004
   3.485 +#define  SNDDATAI_SCTRL_FLUSH		 0x00000008
   3.486 +#define  SNDDATAI_SCTRL_FORCE_ZERO	 0x00000010
   3.487 +#define SNDDATAI_STATSENAB		0x00000c0c
   3.488 +#define SNDDATAI_STATSINCMASK		0x00000c10
   3.489 +/* 0xc14 --> 0xc80 unused */
   3.490 +#define SNDDATAI_COS_CNT_0		0x00000c80
   3.491 +#define SNDDATAI_COS_CNT_1		0x00000c84
   3.492 +#define SNDDATAI_COS_CNT_2		0x00000c88
   3.493 +#define SNDDATAI_COS_CNT_3		0x00000c8c
   3.494 +#define SNDDATAI_COS_CNT_4		0x00000c90
   3.495 +#define SNDDATAI_COS_CNT_5		0x00000c94
   3.496 +#define SNDDATAI_COS_CNT_6		0x00000c98
   3.497 +#define SNDDATAI_COS_CNT_7		0x00000c9c
   3.498 +#define SNDDATAI_COS_CNT_8		0x00000ca0
   3.499 +#define SNDDATAI_COS_CNT_9		0x00000ca4
   3.500 +#define SNDDATAI_COS_CNT_10		0x00000ca8
   3.501 +#define SNDDATAI_COS_CNT_11		0x00000cac
   3.502 +#define SNDDATAI_COS_CNT_12		0x00000cb0
   3.503 +#define SNDDATAI_COS_CNT_13		0x00000cb4
   3.504 +#define SNDDATAI_COS_CNT_14		0x00000cb8
   3.505 +#define SNDDATAI_COS_CNT_15		0x00000cbc
   3.506 +#define SNDDATAI_DMA_RDQ_FULL_CNT	0x00000cc0
   3.507 +#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT	0x00000cc4
   3.508 +#define SNDDATAI_SDCQ_FULL_CNT		0x00000cc8
   3.509 +#define SNDDATAI_NICRNG_SSND_PIDX_CNT	0x00000ccc
   3.510 +#define SNDDATAI_STATS_UPDATED_CNT	0x00000cd0
   3.511 +#define SNDDATAI_INTERRUPTS_CNT		0x00000cd4
   3.512 +#define SNDDATAI_AVOID_INTERRUPTS_CNT	0x00000cd8
   3.513 +#define SNDDATAI_SND_THRESH_HIT_CNT	0x00000cdc
   3.514 +/* 0xce0 --> 0x1000 unused */
   3.515 +
   3.516 +/* Send data completion control registers */
   3.517 +#define SNDDATAC_MODE			0x00001000
   3.518 +#define  SNDDATAC_MODE_RESET		 0x00000001
   3.519 +#define  SNDDATAC_MODE_ENABLE		 0x00000002
   3.520 +/* 0x1004 --> 0x1400 unused */
   3.521 +
   3.522 +/* Send BD ring selector */
   3.523 +#define SNDBDS_MODE			0x00001400
   3.524 +#define  SNDBDS_MODE_RESET		 0x00000001
   3.525 +#define  SNDBDS_MODE_ENABLE		 0x00000002
   3.526 +#define  SNDBDS_MODE_ATTN_ENABLE	 0x00000004
   3.527 +#define SNDBDS_STATUS			0x00001404
   3.528 +#define  SNDBDS_STATUS_ERROR_ATTN	 0x00000004
   3.529 +#define SNDBDS_HWDIAG			0x00001408
   3.530 +/* 0x140c --> 0x1440 */
   3.531 +#define SNDBDS_SEL_CON_IDX_0		0x00001440
   3.532 +#define SNDBDS_SEL_CON_IDX_1		0x00001444
   3.533 +#define SNDBDS_SEL_CON_IDX_2		0x00001448
   3.534 +#define SNDBDS_SEL_CON_IDX_3		0x0000144c
   3.535 +#define SNDBDS_SEL_CON_IDX_4		0x00001450
   3.536 +#define SNDBDS_SEL_CON_IDX_5		0x00001454
   3.537 +#define SNDBDS_SEL_CON_IDX_6		0x00001458
   3.538 +#define SNDBDS_SEL_CON_IDX_7		0x0000145c
   3.539 +#define SNDBDS_SEL_CON_IDX_8		0x00001460
   3.540 +#define SNDBDS_SEL_CON_IDX_9		0x00001464
   3.541 +#define SNDBDS_SEL_CON_IDX_10		0x00001468
   3.542 +#define SNDBDS_SEL_CON_IDX_11		0x0000146c
   3.543 +#define SNDBDS_SEL_CON_IDX_12		0x00001470
   3.544 +#define SNDBDS_SEL_CON_IDX_13		0x00001474
   3.545 +#define SNDBDS_SEL_CON_IDX_14		0x00001478
   3.546 +#define SNDBDS_SEL_CON_IDX_15		0x0000147c
   3.547 +/* 0x1480 --> 0x1800 unused */
   3.548 +
   3.549 +/* Send BD initiator control registers */
   3.550 +#define SNDBDI_MODE			0x00001800
   3.551 +#define  SNDBDI_MODE_RESET		 0x00000001
   3.552 +#define  SNDBDI_MODE_ENABLE		 0x00000002
   3.553 +#define  SNDBDI_MODE_ATTN_ENABLE	 0x00000004
   3.554 +#define SNDBDI_STATUS			0x00001804
   3.555 +#define  SNDBDI_STATUS_ERROR_ATTN	 0x00000004
   3.556 +#define SNDBDI_IN_PROD_IDX_0		0x00001808
   3.557 +#define SNDBDI_IN_PROD_IDX_1		0x0000180c
   3.558 +#define SNDBDI_IN_PROD_IDX_2		0x00001810
   3.559 +#define SNDBDI_IN_PROD_IDX_3		0x00001814
   3.560 +#define SNDBDI_IN_PROD_IDX_4		0x00001818
   3.561 +#define SNDBDI_IN_PROD_IDX_5		0x0000181c
   3.562 +#define SNDBDI_IN_PROD_IDX_6		0x00001820
   3.563 +#define SNDBDI_IN_PROD_IDX_7		0x00001824
   3.564 +#define SNDBDI_IN_PROD_IDX_8		0x00001828
   3.565 +#define SNDBDI_IN_PROD_IDX_9		0x0000182c
   3.566 +#define SNDBDI_IN_PROD_IDX_10		0x00001830
   3.567 +#define SNDBDI_IN_PROD_IDX_11		0x00001834
   3.568 +#define SNDBDI_IN_PROD_IDX_12		0x00001838
   3.569 +#define SNDBDI_IN_PROD_IDX_13		0x0000183c
   3.570 +#define SNDBDI_IN_PROD_IDX_14		0x00001840
   3.571 +#define SNDBDI_IN_PROD_IDX_15		0x00001844
   3.572 +/* 0x1848 --> 0x1c00 unused */
   3.573 +
   3.574 +/* Send BD completion control registers */
   3.575 +#define SNDBDC_MODE			0x00001c00
   3.576 +#define SNDBDC_MODE_RESET		 0x00000001
   3.577 +#define SNDBDC_MODE_ENABLE		 0x00000002
   3.578 +#define SNDBDC_MODE_ATTN_ENABLE		 0x00000004
   3.579 +/* 0x1c04 --> 0x2000 unused */
   3.580 +
   3.581 +/* Receive list placement control registers */
   3.582 +#define RCVLPC_MODE			0x00002000
   3.583 +#define  RCVLPC_MODE_RESET		 0x00000001
   3.584 +#define  RCVLPC_MODE_ENABLE		 0x00000002
   3.585 +#define  RCVLPC_MODE_CLASS0_ATTN_ENAB	 0x00000004
   3.586 +#define  RCVLPC_MODE_MAPOOR_AATTN_ENAB	 0x00000008
   3.587 +#define  RCVLPC_MODE_STAT_OFLOW_ENAB	 0x00000010
   3.588 +#define RCVLPC_STATUS			0x00002004
   3.589 +#define  RCVLPC_STATUS_CLASS0		 0x00000004
   3.590 +#define  RCVLPC_STATUS_MAPOOR		 0x00000008
   3.591 +#define  RCVLPC_STATUS_STAT_OFLOW	 0x00000010
   3.592 +#define RCVLPC_LOCK			0x00002008
   3.593 +#define  RCVLPC_LOCK_REQ_MASK		 0x0000ffff
   3.594 +#define  RCVLPC_LOCK_REQ_SHIFT		 0
   3.595 +#define  RCVLPC_LOCK_GRANT_MASK		 0xffff0000
   3.596 +#define  RCVLPC_LOCK_GRANT_SHIFT	 16
   3.597 +#define RCVLPC_NON_EMPTY_BITS		0x0000200c
   3.598 +#define  RCVLPC_NON_EMPTY_BITS_MASK	 0x0000ffff
   3.599 +#define RCVLPC_CONFIG			0x00002010
   3.600 +#define RCVLPC_STATSCTRL		0x00002014
   3.601 +#define  RCVLPC_STATSCTRL_ENABLE	 0x00000001
   3.602 +#define  RCVLPC_STATSCTRL_FASTUPD	 0x00000002
   3.603 +#define RCVLPC_STATS_ENABLE		0x00002018
   3.604 +#define RCVLPC_STATS_INCMASK		0x0000201c
   3.605 +/* 0x2020 --> 0x2100 unused */
   3.606 +#define RCVLPC_SELLST_BASE		0x00002100 /* 16 16-byte entries */
   3.607 +#define  SELLST_TAIL			0x00000004
   3.608 +#define  SELLST_CONT			0x00000008
   3.609 +#define  SELLST_UNUSED			0x0000000c
   3.610 +#define RCVLPC_COS_CNTL_BASE		0x00002200 /* 16 4-byte entries */
   3.611 +#define RCVLPC_DROP_FILTER_CNT		0x00002240
   3.612 +#define RCVLPC_DMA_WQ_FULL_CNT		0x00002244
   3.613 +#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT	0x00002248
   3.614 +#define RCVLPC_NO_RCV_BD_CNT		0x0000224c
   3.615 +#define RCVLPC_IN_DISCARDS_CNT		0x00002250
   3.616 +#define RCVLPC_IN_ERRORS_CNT		0x00002254
   3.617 +#define RCVLPC_RCV_THRESH_HIT_CNT	0x00002258
   3.618 +/* 0x225c --> 0x2400 unused */
   3.619 +
   3.620 +/* Receive Data and Receive BD Initiator Control */
   3.621 +#define RCVDBDI_MODE			0x00002400
   3.622 +#define  RCVDBDI_MODE_RESET		 0x00000001
   3.623 +#define  RCVDBDI_MODE_ENABLE		 0x00000002
   3.624 +#define  RCVDBDI_MODE_JUMBOBD_NEEDED	 0x00000004
   3.625 +#define  RCVDBDI_MODE_FRM_TOO_BIG	 0x00000008
   3.626 +#define  RCVDBDI_MODE_INV_RING_SZ	 0x00000010
   3.627 +#define RCVDBDI_STATUS			0x00002404
   3.628 +#define  RCVDBDI_STATUS_JUMBOBD_NEEDED	 0x00000004
   3.629 +#define  RCVDBDI_STATUS_FRM_TOO_BIG	 0x00000008
   3.630 +#define  RCVDBDI_STATUS_INV_RING_SZ	 0x00000010
   3.631 +#define RCVDBDI_SPLIT_FRAME_MINSZ	0x00002408
   3.632 +/* 0x240c --> 0x2440 unused */
   3.633 +#define RCVDBDI_JUMBO_BD		0x00002440 /* TG3_BDINFO_... */
   3.634 +#define RCVDBDI_STD_BD			0x00002450 /* TG3_BDINFO_... */
   3.635 +#define RCVDBDI_MINI_BD			0x00002460 /* TG3_BDINFO_... */
   3.636 +#define RCVDBDI_JUMBO_CON_IDX		0x00002470
   3.637 +#define RCVDBDI_STD_CON_IDX		0x00002474
   3.638 +#define RCVDBDI_MINI_CON_IDX		0x00002478
   3.639 +/* 0x247c --> 0x2480 unused */
   3.640 +#define RCVDBDI_BD_PROD_IDX_0		0x00002480
   3.641 +#define RCVDBDI_BD_PROD_IDX_1		0x00002484
   3.642 +#define RCVDBDI_BD_PROD_IDX_2		0x00002488
   3.643 +#define RCVDBDI_BD_PROD_IDX_3		0x0000248c
   3.644 +#define RCVDBDI_BD_PROD_IDX_4		0x00002490
   3.645 +#define RCVDBDI_BD_PROD_IDX_5		0x00002494
   3.646 +#define RCVDBDI_BD_PROD_IDX_6		0x00002498
   3.647 +#define RCVDBDI_BD_PROD_IDX_7		0x0000249c
   3.648 +#define RCVDBDI_BD_PROD_IDX_8		0x000024a0
   3.649 +#define RCVDBDI_BD_PROD_IDX_9		0x000024a4
   3.650 +#define RCVDBDI_BD_PROD_IDX_10		0x000024a8
   3.651 +#define RCVDBDI_BD_PROD_IDX_11		0x000024ac
   3.652 +#define RCVDBDI_BD_PROD_IDX_12		0x000024b0
   3.653 +#define RCVDBDI_BD_PROD_IDX_13		0x000024b4
   3.654 +#define RCVDBDI_BD_PROD_IDX_14		0x000024b8
   3.655 +#define RCVDBDI_BD_PROD_IDX_15		0x000024bc
   3.656 +#define RCVDBDI_HWDIAG			0x000024c0
   3.657 +/* 0x24c4 --> 0x2800 unused */
   3.658 +
   3.659 +/* Receive Data Completion Control */
   3.660 +#define RCVDCC_MODE			0x00002800
   3.661 +#define  RCVDCC_MODE_RESET		 0x00000001
   3.662 +#define  RCVDCC_MODE_ENABLE		 0x00000002
   3.663 +#define  RCVDCC_MODE_ATTN_ENABLE	 0x00000004
   3.664 +/* 0x2804 --> 0x2c00 unused */
   3.665 +
   3.666 +/* Receive BD Initiator Control Registers */
   3.667 +#define RCVBDI_MODE			0x00002c00
   3.668 +#define  RCVBDI_MODE_RESET		 0x00000001
   3.669 +#define  RCVBDI_MODE_ENABLE		 0x00000002
   3.670 +#define  RCVBDI_MODE_RCB_ATTN_ENAB	 0x00000004
   3.671 +#define RCVBDI_STATUS			0x00002c04
   3.672 +#define  RCVBDI_STATUS_RCB_ATTN		 0x00000004
   3.673 +#define RCVBDI_JUMBO_PROD_IDX		0x00002c08
   3.674 +#define RCVBDI_STD_PROD_IDX		0x00002c0c
   3.675 +#define RCVBDI_MINI_PROD_IDX		0x00002c10
   3.676 +#define RCVBDI_MINI_THRESH		0x00002c14
   3.677 +#define RCVBDI_STD_THRESH		0x00002c18
   3.678 +#define RCVBDI_JUMBO_THRESH		0x00002c1c
   3.679 +/* 0x2c20 --> 0x3000 unused */
   3.680 +
   3.681 +/* Receive BD Completion Control Registers */
   3.682 +#define RCVCC_MODE			0x00003000
   3.683 +#define  RCVCC_MODE_RESET		 0x00000001
   3.684 +#define  RCVCC_MODE_ENABLE		 0x00000002
   3.685 +#define  RCVCC_MODE_ATTN_ENABLE		 0x00000004
   3.686 +#define RCVCC_STATUS			0x00003004
   3.687 +#define  RCVCC_STATUS_ERROR_ATTN	 0x00000004
   3.688 +#define RCVCC_JUMP_PROD_IDX		0x00003008
   3.689 +#define RCVCC_STD_PROD_IDX		0x0000300c
   3.690 +#define RCVCC_MINI_PROD_IDX		0x00003010
   3.691 +/* 0x3014 --> 0x3400 unused */
   3.692 +
   3.693 +/* Receive list selector control registers */
   3.694 +#define RCVLSC_MODE			0x00003400
   3.695 +#define  RCVLSC_MODE_RESET		 0x00000001
   3.696 +#define  RCVLSC_MODE_ENABLE		 0x00000002
   3.697 +#define  RCVLSC_MODE_ATTN_ENABLE	 0x00000004
   3.698 +#define RCVLSC_STATUS			0x00003404
   3.699 +#define  RCVLSC_STATUS_ERROR_ATTN	 0x00000004
   3.700 +/* 0x3408 --> 0x3800 unused */
   3.701 +
   3.702 +/* Mbuf cluster free registers */
   3.703 +#define MBFREE_MODE			0x00003800
   3.704 +#define  MBFREE_MODE_RESET		 0x00000001
   3.705 +#define  MBFREE_MODE_ENABLE		 0x00000002
   3.706 +#define MBFREE_STATUS			0x00003804
   3.707 +/* 0x3808 --> 0x3c00 unused */
   3.708 +
   3.709 +/* Host coalescing control registers */
   3.710 +#define HOSTCC_MODE			0x00003c00
   3.711 +#define  HOSTCC_MODE_RESET		 0x00000001
   3.712 +#define  HOSTCC_MODE_ENABLE		 0x00000002
   3.713 +#define  HOSTCC_MODE_ATTN		 0x00000004
   3.714 +#define  HOSTCC_MODE_NOW		 0x00000008
   3.715 +#define  HOSTCC_MODE_FULL_STATUS	 0x00000000
   3.716 +#define  HOSTCC_MODE_64BYTE		 0x00000080
   3.717 +#define  HOSTCC_MODE_32BYTE		 0x00000100
   3.718 +#define  HOSTCC_MODE_CLRTICK_RXBD	 0x00000200
   3.719 +#define  HOSTCC_MODE_CLRTICK_TXBD	 0x00000400
   3.720 +#define  HOSTCC_MODE_NOINT_ON_NOW	 0x00000800
   3.721 +#define  HOSTCC_MODE_NOINT_ON_FORCE	 0x00001000
   3.722 +#define HOSTCC_STATUS			0x00003c04
   3.723 +#define  HOSTCC_STATUS_ERROR_ATTN	 0x00000004
   3.724 +#define HOSTCC_RXCOL_TICKS		0x00003c08
   3.725 +#define  LOW_RXCOL_TICKS		 0x00000032
   3.726 +#define  DEFAULT_RXCOL_TICKS		 0x00000048
   3.727 +#define  HIGH_RXCOL_TICKS		 0x00000096
   3.728 +#define HOSTCC_TXCOL_TICKS		0x00003c0c
   3.729 +#define  LOW_TXCOL_TICKS		 0x00000096
   3.730 +#define  DEFAULT_TXCOL_TICKS		 0x0000012c
   3.731 +#define  HIGH_TXCOL_TICKS		 0x00000145
   3.732 +#define HOSTCC_RXMAX_FRAMES		0x00003c10
   3.733 +#define  LOW_RXMAX_FRAMES		 0x00000005
   3.734 +#define  DEFAULT_RXMAX_FRAMES		 0x00000008
   3.735 +#define  HIGH_RXMAX_FRAMES		 0x00000012
   3.736 +#define HOSTCC_TXMAX_FRAMES		0x00003c14
   3.737 +#define  LOW_TXMAX_FRAMES		 0x00000035
   3.738 +#define  DEFAULT_TXMAX_FRAMES		 0x0000004b
   3.739 +#define  HIGH_TXMAX_FRAMES		 0x00000052
   3.740 +#define HOSTCC_RXCOAL_TICK_INT		0x00003c18
   3.741 +#define  DEFAULT_RXCOAL_TICK_INT	 0x00000019
   3.742 +#define HOSTCC_TXCOAL_TICK_INT		0x00003c1c
   3.743 +#define  DEFAULT_TXCOAL_TICK_INT	 0x00000019
   3.744 +#define HOSTCC_RXCOAL_MAXF_INT		0x00003c20
   3.745 +#define  DEFAULT_RXCOAL_MAXF_INT	 0x00000005
   3.746 +#define HOSTCC_TXCOAL_MAXF_INT		0x00003c24
   3.747 +#define  DEFAULT_TXCOAL_MAXF_INT	 0x00000005
   3.748 +#define HOSTCC_STAT_COAL_TICKS		0x00003c28
   3.749 +#define  DEFAULT_STAT_COAL_TICKS	 0x000f4240
   3.750 +/* 0x3c2c --> 0x3c30 unused */
   3.751 +#define HOSTCC_STATS_BLK_HOST_ADDR	0x00003c30 /* 64-bit */
   3.752 +#define HOSTCC_STATUS_BLK_HOST_ADDR	0x00003c38 /* 64-bit */
   3.753 +#define HOSTCC_STATS_BLK_NIC_ADDR	0x00003c40
   3.754 +#define HOSTCC_STATUS_BLK_NIC_ADDR	0x00003c44
   3.755 +#define HOSTCC_FLOW_ATTN		0x00003c48
   3.756 +/* 0x3c4c --> 0x3c50 unused */
   3.757 +#define HOSTCC_JUMBO_CON_IDX		0x00003c50
   3.758 +#define HOSTCC_STD_CON_IDX		0x00003c54
   3.759 +#define HOSTCC_MINI_CON_IDX		0x00003c58
   3.760 +/* 0x3c5c --> 0x3c80 unused */
   3.761 +#define HOSTCC_RET_PROD_IDX_0		0x00003c80
   3.762 +#define HOSTCC_RET_PROD_IDX_1		0x00003c84
   3.763 +#define HOSTCC_RET_PROD_IDX_2		0x00003c88
   3.764 +#define HOSTCC_RET_PROD_IDX_3		0x00003c8c
   3.765 +#define HOSTCC_RET_PROD_IDX_4		0x00003c90
   3.766 +#define HOSTCC_RET_PROD_IDX_5		0x00003c94
   3.767 +#define HOSTCC_RET_PROD_IDX_6		0x00003c98
   3.768 +#define HOSTCC_RET_PROD_IDX_7		0x00003c9c
   3.769 +#define HOSTCC_RET_PROD_IDX_8		0x00003ca0
   3.770 +#define HOSTCC_RET_PROD_IDX_9		0x00003ca4
   3.771 +#define HOSTCC_RET_PROD_IDX_10		0x00003ca8
   3.772 +#define HOSTCC_RET_PROD_IDX_11		0x00003cac
   3.773 +#define HOSTCC_RET_PROD_IDX_12		0x00003cb0
   3.774 +#define HOSTCC_RET_PROD_IDX_13		0x00003cb4
   3.775 +#define HOSTCC_RET_PROD_IDX_14		0x00003cb8
   3.776 +#define HOSTCC_RET_PROD_IDX_15		0x00003cbc
   3.777 +#define HOSTCC_SND_CON_IDX_0		0x00003cc0
   3.778 +#define HOSTCC_SND_CON_IDX_1		0x00003cc4
   3.779 +#define HOSTCC_SND_CON_IDX_2		0x00003cc8
   3.780 +#define HOSTCC_SND_CON_IDX_3		0x00003ccc
   3.781 +#define HOSTCC_SND_CON_IDX_4		0x00003cd0
   3.782 +#define HOSTCC_SND_CON_IDX_5		0x00003cd4
   3.783 +#define HOSTCC_SND_CON_IDX_6		0x00003cd8
   3.784 +#define HOSTCC_SND_CON_IDX_7		0x00003cdc
   3.785 +#define HOSTCC_SND_CON_IDX_8		0x00003ce0
   3.786 +#define HOSTCC_SND_CON_IDX_9		0x00003ce4
   3.787 +#define HOSTCC_SND_CON_IDX_10		0x00003ce8
   3.788 +#define HOSTCC_SND_CON_IDX_11		0x00003cec
   3.789 +#define HOSTCC_SND_CON_IDX_12		0x00003cf0
   3.790 +#define HOSTCC_SND_CON_IDX_13		0x00003cf4
   3.791 +#define HOSTCC_SND_CON_IDX_14		0x00003cf8
   3.792 +#define HOSTCC_SND_CON_IDX_15		0x00003cfc
   3.793 +/* 0x3d00 --> 0x4000 unused */
   3.794 +
   3.795 +/* Memory arbiter control registers */
   3.796 +#define MEMARB_MODE			0x00004000
   3.797 +#define  MEMARB_MODE_RESET		 0x00000001
   3.798 +#define  MEMARB_MODE_ENABLE		 0x00000002
   3.799 +#define MEMARB_STATUS			0x00004004
   3.800 +#define MEMARB_TRAP_ADDR_LOW		0x00004008
   3.801 +#define MEMARB_TRAP_ADDR_HIGH		0x0000400c
   3.802 +/* 0x4010 --> 0x4400 unused */
   3.803 +
   3.804 +/* Buffer manager control registers */
   3.805 +#define BUFMGR_MODE			0x00004400
   3.806 +#define  BUFMGR_MODE_RESET		 0x00000001
   3.807 +#define  BUFMGR_MODE_ENABLE		 0x00000002
   3.808 +#define  BUFMGR_MODE_ATTN_ENABLE	 0x00000004
   3.809 +#define  BUFMGR_MODE_BM_TEST		 0x00000008
   3.810 +#define  BUFMGR_MODE_MBLOW_ATTN_ENAB	 0x00000010
   3.811 +#define BUFMGR_STATUS			0x00004404
   3.812 +#define  BUFMGR_STATUS_ERROR		 0x00000004
   3.813 +#define  BUFMGR_STATUS_MBLOW		 0x00000010
   3.814 +#define BUFMGR_MB_POOL_ADDR		0x00004408
   3.815 +#define BUFMGR_MB_POOL_SIZE		0x0000440c
   3.816 +#define BUFMGR_MB_RDMA_LOW_WATER	0x00004410
   3.817 +#define  DEFAULT_MB_RDMA_LOW_WATER	 0x00000040
   3.818 +#define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
   3.819 +#define BUFMGR_MB_MACRX_LOW_WATER	0x00004414
   3.820 +#define  DEFAULT_MB_MACRX_LOW_WATER	  0x00000020
   3.821 +#define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
   3.822 +#define BUFMGR_MB_HIGH_WATER		0x00004418
   3.823 +#define  DEFAULT_MB_HIGH_WATER		 0x00000060
   3.824 +#define  DEFAULT_MB_HIGH_WATER_JUMBO	 0x0000017c
   3.825 +#define BUFMGR_RX_MB_ALLOC_REQ		0x0000441c
   3.826 +#define  BUFMGR_MB_ALLOC_BIT		 0x10000000
   3.827 +#define BUFMGR_RX_MB_ALLOC_RESP		0x00004420
   3.828 +#define BUFMGR_TX_MB_ALLOC_REQ		0x00004424
   3.829 +#define BUFMGR_TX_MB_ALLOC_RESP		0x00004428
   3.830 +#define BUFMGR_DMA_DESC_POOL_ADDR	0x0000442c
   3.831 +#define BUFMGR_DMA_DESC_POOL_SIZE	0x00004430
   3.832 +#define BUFMGR_DMA_LOW_WATER		0x00004434
   3.833 +#define  DEFAULT_DMA_LOW_WATER		 0x00000005
   3.834 +#define BUFMGR_DMA_HIGH_WATER		0x00004438
   3.835 +#define  DEFAULT_DMA_HIGH_WATER		 0x0000000a
   3.836 +#define BUFMGR_RX_DMA_ALLOC_REQ		0x0000443c
   3.837 +#define BUFMGR_RX_DMA_ALLOC_RESP	0x00004440
   3.838 +#define BUFMGR_TX_DMA_ALLOC_REQ		0x00004444
   3.839 +#define BUFMGR_TX_DMA_ALLOC_RESP	0x00004448
   3.840 +#define BUFMGR_HWDIAG_0			0x0000444c
   3.841 +#define BUFMGR_HWDIAG_1			0x00004450
   3.842 +#define BUFMGR_HWDIAG_2			0x00004454
   3.843 +/* 0x4458 --> 0x4800 unused */
   3.844 +
   3.845 +/* Read DMA control registers */
   3.846 +#define RDMAC_MODE			0x00004800
   3.847 +#define  RDMAC_MODE_RESET		 0x00000001
   3.848 +#define  RDMAC_MODE_ENABLE		 0x00000002
   3.849 +#define  RDMAC_MODE_TGTABORT_ENAB	 0x00000004
   3.850 +#define  RDMAC_MODE_MSTABORT_ENAB	 0x00000008
   3.851 +#define  RDMAC_MODE_PARITYERR_ENAB	 0x00000010
   3.852 +#define  RDMAC_MODE_ADDROFLOW_ENAB	 0x00000020
   3.853 +#define  RDMAC_MODE_FIFOOFLOW_ENAB	 0x00000040
   3.854 +#define  RDMAC_MODE_FIFOURUN_ENAB	 0x00000080
   3.855 +#define  RDMAC_MODE_FIFOOREAD_ENAB	 0x00000100
   3.856 +#define  RDMAC_MODE_LNGREAD_ENAB	 0x00000200
   3.857 +#define  RDMAC_MODE_SPLIT_ENABLE	 0x00000800
   3.858 +#define  RDMAC_MODE_SPLIT_RESET		 0x00001000
   3.859 +#define RDMAC_STATUS			0x00004804
   3.860 +#define  RDMAC_STATUS_TGTABORT		 0x00000004
   3.861 +#define  RDMAC_STATUS_MSTABORT		 0x00000008
   3.862 +#define  RDMAC_STATUS_PARITYERR		 0x00000010
   3.863 +#define  RDMAC_STATUS_ADDROFLOW		 0x00000020
   3.864 +#define  RDMAC_STATUS_FIFOOFLOW		 0x00000040
   3.865 +#define  RDMAC_STATUS_FIFOURUN		 0x00000080
   3.866 +#define  RDMAC_STATUS_FIFOOREAD		 0x00000100
   3.867 +#define  RDMAC_STATUS_LNGREAD		 0x00000200
   3.868 +/* 0x4808 --> 0x4c00 unused */
   3.869 +
   3.870 +/* Write DMA control registers */
   3.871 +#define WDMAC_MODE			0x00004c00
   3.872 +#define  WDMAC_MODE_RESET		 0x00000001
   3.873 +#define  WDMAC_MODE_ENABLE		 0x00000002
   3.874 +#define  WDMAC_MODE_TGTABORT_ENAB	 0x00000004
   3.875 +#define  WDMAC_MODE_MSTABORT_ENAB	 0x00000008
   3.876 +#define  WDMAC_MODE_PARITYERR_ENAB	 0x00000010
   3.877 +#define  WDMAC_MODE_ADDROFLOW_ENAB	 0x00000020
   3.878 +#define  WDMAC_MODE_FIFOOFLOW_ENAB	 0x00000040
   3.879 +#define  WDMAC_MODE_FIFOURUN_ENAB	 0x00000080
   3.880 +#define  WDMAC_MODE_FIFOOREAD_ENAB	 0x00000100
   3.881 +#define  WDMAC_MODE_LNGREAD_ENAB	 0x00000200
   3.882 +#define WDMAC_STATUS			0x00004c04
   3.883 +#define  WDMAC_STATUS_TGTABORT		 0x00000004
   3.884 +#define  WDMAC_STATUS_MSTABORT		 0x00000008
   3.885 +#define  WDMAC_STATUS_PARITYERR		 0x00000010
   3.886 +#define  WDMAC_STATUS_ADDROFLOW		 0x00000020
   3.887 +#define  WDMAC_STATUS_FIFOOFLOW		 0x00000040
   3.888 +#define  WDMAC_STATUS_FIFOURUN		 0x00000080
   3.889 +#define  WDMAC_STATUS_FIFOOREAD		 0x00000100
   3.890 +#define  WDMAC_STATUS_LNGREAD		 0x00000200
   3.891 +/* 0x4c08 --> 0x5000 unused */
   3.892 +
   3.893 +/* Per-cpu register offsets (arm9) */
   3.894 +#define CPU_MODE			0x00000000
   3.895 +#define  CPU_MODE_RESET			 0x00000001
   3.896 +#define  CPU_MODE_HALT			 0x00000400
   3.897 +#define CPU_STATE			0x00000004
   3.898 +#define CPU_EVTMASK			0x00000008
   3.899 +/* 0xc --> 0x1c reserved */
   3.900 +#define CPU_PC				0x0000001c
   3.901 +#define CPU_INSN			0x00000020
   3.902 +#define CPU_SPAD_UFLOW			0x00000024
   3.903 +#define CPU_WDOG_CLEAR			0x00000028
   3.904 +#define CPU_WDOG_VECTOR			0x0000002c
   3.905 +#define CPU_WDOG_PC			0x00000030
   3.906 +#define CPU_HW_BP			0x00000034
   3.907 +/* 0x38 --> 0x44 unused */
   3.908 +#define CPU_WDOG_SAVED_STATE		0x00000044
   3.909 +#define CPU_LAST_BRANCH_ADDR		0x00000048
   3.910 +#define CPU_SPAD_UFLOW_SET		0x0000004c
   3.911 +/* 0x50 --> 0x200 unused */
   3.912 +#define CPU_R0				0x00000200
   3.913 +#define CPU_R1				0x00000204
   3.914 +#define CPU_R2				0x00000208
   3.915 +#define CPU_R3				0x0000020c
   3.916 +#define CPU_R4				0x00000210
   3.917 +#define CPU_R5				0x00000214
   3.918 +#define CPU_R6				0x00000218
   3.919 +#define CPU_R7				0x0000021c
   3.920 +#define CPU_R8				0x00000220
   3.921 +#define CPU_R9				0x00000224
   3.922 +#define CPU_R10				0x00000228
   3.923 +#define CPU_R11				0x0000022c
   3.924 +#define CPU_R12				0x00000230
   3.925 +#define CPU_R13				0x00000234
   3.926 +#define CPU_R14				0x00000238
   3.927 +#define CPU_R15				0x0000023c
   3.928 +#define CPU_R16				0x00000240
   3.929 +#define CPU_R17				0x00000244
   3.930 +#define CPU_R18				0x00000248
   3.931 +#define CPU_R19				0x0000024c
   3.932 +#define CPU_R20				0x00000250
   3.933 +#define CPU_R21				0x00000254
   3.934 +#define CPU_R22				0x00000258
   3.935 +#define CPU_R23				0x0000025c
   3.936 +#define CPU_R24				0x00000260
   3.937 +#define CPU_R25				0x00000264
   3.938 +#define CPU_R26				0x00000268
   3.939 +#define CPU_R27				0x0000026c
   3.940 +#define CPU_R28				0x00000270
   3.941 +#define CPU_R29				0x00000274
   3.942 +#define CPU_R30				0x00000278
   3.943 +#define CPU_R31				0x0000027c
   3.944 +/* 0x280 --> 0x400 unused */
   3.945 +
   3.946 +#define RX_CPU_BASE			0x00005000
   3.947 +#define TX_CPU_BASE			0x00005400
   3.948 +
   3.949 +/* Mailboxes */
   3.950 +#define GRCMBOX_INTERRUPT_0		0x00005800 /* 64-bit */
   3.951 +#define GRCMBOX_INTERRUPT_1		0x00005808 /* 64-bit */
   3.952 +#define GRCMBOX_INTERRUPT_2		0x00005810 /* 64-bit */
   3.953 +#define GRCMBOX_INTERRUPT_3		0x00005818 /* 64-bit */
   3.954 +#define GRCMBOX_GENERAL_0		0x00005820 /* 64-bit */
   3.955 +#define GRCMBOX_GENERAL_1		0x00005828 /* 64-bit */
   3.956 +#define GRCMBOX_GENERAL_2		0x00005830 /* 64-bit */
   3.957 +#define GRCMBOX_GENERAL_3		0x00005838 /* 64-bit */
   3.958 +#define GRCMBOX_GENERAL_4		0x00005840 /* 64-bit */
   3.959 +#define GRCMBOX_GENERAL_5		0x00005848 /* 64-bit */
   3.960 +#define GRCMBOX_GENERAL_6		0x00005850 /* 64-bit */
   3.961 +#define GRCMBOX_GENERAL_7		0x00005858 /* 64-bit */
   3.962 +#define GRCMBOX_RELOAD_STAT		0x00005860 /* 64-bit */
   3.963 +#define GRCMBOX_RCVSTD_PROD_IDX		0x00005868 /* 64-bit */
   3.964 +#define GRCMBOX_RCVJUMBO_PROD_IDX	0x00005870 /* 64-bit */
   3.965 +#define GRCMBOX_RCVMINI_PROD_IDX	0x00005878 /* 64-bit */
   3.966 +#define GRCMBOX_RCVRET_CON_IDX_0	0x00005880 /* 64-bit */
   3.967 +#define GRCMBOX_RCVRET_CON_IDX_1	0x00005888 /* 64-bit */
   3.968 +#define GRCMBOX_RCVRET_CON_IDX_2	0x00005890 /* 64-bit */
   3.969 +#define GRCMBOX_RCVRET_CON_IDX_3	0x00005898 /* 64-bit */
   3.970 +#define GRCMBOX_RCVRET_CON_IDX_4	0x000058a0 /* 64-bit */
   3.971 +#define GRCMBOX_RCVRET_CON_IDX_5	0x000058a8 /* 64-bit */
   3.972 +#define GRCMBOX_RCVRET_CON_IDX_6	0x000058b0 /* 64-bit */
   3.973 +#define GRCMBOX_RCVRET_CON_IDX_7	0x000058b8 /* 64-bit */
   3.974 +#define GRCMBOX_RCVRET_CON_IDX_8	0x000058c0 /* 64-bit */
   3.975 +#define GRCMBOX_RCVRET_CON_IDX_9	0x000058c8 /* 64-bit */
   3.976 +#define GRCMBOX_RCVRET_CON_IDX_10	0x000058d0 /* 64-bit */
   3.977 +#define GRCMBOX_RCVRET_CON_IDX_11	0x000058d8 /* 64-bit */
   3.978 +#define GRCMBOX_RCVRET_CON_IDX_12	0x000058e0 /* 64-bit */
   3.979 +#define GRCMBOX_RCVRET_CON_IDX_13	0x000058e8 /* 64-bit */
   3.980 +#define GRCMBOX_RCVRET_CON_IDX_14	0x000058f0 /* 64-bit */
   3.981 +#define GRCMBOX_RCVRET_CON_IDX_15	0x000058f8 /* 64-bit */
   3.982 +#define GRCMBOX_SNDHOST_PROD_IDX_0	0x00005900 /* 64-bit */
   3.983 +#define GRCMBOX_SNDHOST_PROD_IDX_1	0x00005908 /* 64-bit */
   3.984 +#define GRCMBOX_SNDHOST_PROD_IDX_2	0x00005910 /* 64-bit */
   3.985 +#define GRCMBOX_SNDHOST_PROD_IDX_3	0x00005918 /* 64-bit */
   3.986 +#define GRCMBOX_SNDHOST_PROD_IDX_4	0x00005920 /* 64-bit */
   3.987 +#define GRCMBOX_SNDHOST_PROD_IDX_5	0x00005928 /* 64-bit */
   3.988 +#define GRCMBOX_SNDHOST_PROD_IDX_6	0x00005930 /* 64-bit */
   3.989 +#define GRCMBOX_SNDHOST_PROD_IDX_7	0x00005938 /* 64-bit */
   3.990 +#define GRCMBOX_SNDHOST_PROD_IDX_8	0x00005940 /* 64-bit */
   3.991 +#define GRCMBOX_SNDHOST_PROD_IDX_9	0x00005948 /* 64-bit */
   3.992 +#define GRCMBOX_SNDHOST_PROD_IDX_10	0x00005950 /* 64-bit */
   3.993 +#define GRCMBOX_SNDHOST_PROD_IDX_11	0x00005958 /* 64-bit */
   3.994 +#define GRCMBOX_SNDHOST_PROD_IDX_12	0x00005960 /* 64-bit */
   3.995 +#define GRCMBOX_SNDHOST_PROD_IDX_13	0x00005968 /* 64-bit */
   3.996 +#define GRCMBOX_SNDHOST_PROD_IDX_14	0x00005970 /* 64-bit */
   3.997 +#define GRCMBOX_SNDHOST_PROD_IDX_15	0x00005978 /* 64-bit */
   3.998 +#define GRCMBOX_SNDNIC_PROD_IDX_0	0x00005980 /* 64-bit */
   3.999 +#define GRCMBOX_SNDNIC_PROD_IDX_1	0x00005988 /* 64-bit */
  3.1000 +#define GRCMBOX_SNDNIC_PROD_IDX_2	0x00005990 /* 64-bit */
  3.1001 +#define GRCMBOX_SNDNIC_PROD_IDX_3	0x00005998 /* 64-bit */
  3.1002 +#define GRCMBOX_SNDNIC_PROD_IDX_4	0x000059a0 /* 64-bit */
  3.1003 +#define GRCMBOX_SNDNIC_PROD_IDX_5	0x000059a8 /* 64-bit */
  3.1004 +#define GRCMBOX_SNDNIC_PROD_IDX_6	0x000059b0 /* 64-bit */
  3.1005 +#define GRCMBOX_SNDNIC_PROD_IDX_7	0x000059b8 /* 64-bit */
  3.1006 +#define GRCMBOX_SNDNIC_PROD_IDX_8	0x000059c0 /* 64-bit */
  3.1007 +#define GRCMBOX_SNDNIC_PROD_IDX_9	0x000059c8 /* 64-bit */
  3.1008 +#define GRCMBOX_SNDNIC_PROD_IDX_10	0x000059d0 /* 64-bit */
  3.1009 +#define GRCMBOX_SNDNIC_PROD_IDX_11	0x000059d8 /* 64-bit */
  3.1010 +#define GRCMBOX_SNDNIC_PROD_IDX_12	0x000059e0 /* 64-bit */
  3.1011 +#define GRCMBOX_SNDNIC_PROD_IDX_13	0x000059e8 /* 64-bit */
  3.1012 +#define GRCMBOX_SNDNIC_PROD_IDX_14	0x000059f0 /* 64-bit */
  3.1013 +#define GRCMBOX_SNDNIC_PROD_IDX_15	0x000059f8 /* 64-bit */
  3.1014 +#define GRCMBOX_HIGH_PRIO_EV_VECTOR	0x00005a00
  3.1015 +#define GRCMBOX_HIGH_PRIO_EV_MASK	0x00005a04
  3.1016 +#define GRCMBOX_LOW_PRIO_EV_VEC		0x00005a08
  3.1017 +#define GRCMBOX_LOW_PRIO_EV_MASK	0x00005a0c
  3.1018 +/* 0x5a10 --> 0x5c00 */
  3.1019 +
  3.1020 +/* Flow Through queues */
  3.1021 +#define FTQ_RESET			0x00005c00
  3.1022 +/* 0x5c04 --> 0x5c10 unused */
  3.1023 +#define FTQ_DMA_NORM_READ_CTL		0x00005c10
  3.1024 +#define FTQ_DMA_NORM_READ_FULL_CNT	0x00005c14
  3.1025 +#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ	0x00005c18
  3.1026 +#define FTQ_DMA_NORM_READ_WRITE_PEEK	0x00005c1c
  3.1027 +#define FTQ_DMA_HIGH_READ_CTL		0x00005c20
  3.1028 +#define FTQ_DMA_HIGH_READ_FULL_CNT	0x00005c24
  3.1029 +#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ	0x00005c28
  3.1030 +#define FTQ_DMA_HIGH_READ_WRITE_PEEK	0x00005c2c
  3.1031 +#define FTQ_DMA_COMP_DISC_CTL		0x00005c30
  3.1032 +#define FTQ_DMA_COMP_DISC_FULL_CNT	0x00005c34
  3.1033 +#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ	0x00005c38
  3.1034 +#define FTQ_DMA_COMP_DISC_WRITE_PEEK	0x00005c3c
  3.1035 +#define FTQ_SEND_BD_COMP_CTL		0x00005c40
  3.1036 +#define FTQ_SEND_BD_COMP_FULL_CNT	0x00005c44
  3.1037 +#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ	0x00005c48
  3.1038 +#define FTQ_SEND_BD_COMP_WRITE_PEEK	0x00005c4c
  3.1039 +#define FTQ_SEND_DATA_INIT_CTL		0x00005c50
  3.1040 +#define FTQ_SEND_DATA_INIT_FULL_CNT	0x00005c54
  3.1041 +#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ	0x00005c58
  3.1042 +#define FTQ_SEND_DATA_INIT_WRITE_PEEK	0x00005c5c
  3.1043 +#define FTQ_DMA_NORM_WRITE_CTL		0x00005c60
  3.1044 +#define FTQ_DMA_NORM_WRITE_FULL_CNT	0x00005c64
  3.1045 +#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ	0x00005c68
  3.1046 +#define FTQ_DMA_NORM_WRITE_WRITE_PEEK	0x00005c6c
  3.1047 +#define FTQ_DMA_HIGH_WRITE_CTL		0x00005c70
  3.1048 +#define FTQ_DMA_HIGH_WRITE_FULL_CNT	0x00005c74
  3.1049 +#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ	0x00005c78
  3.1050 +#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK	0x00005c7c
  3.1051 +#define FTQ_SWTYPE1_CTL			0x00005c80
  3.1052 +#define FTQ_SWTYPE1_FULL_CNT		0x00005c84
  3.1053 +#define FTQ_SWTYPE1_FIFO_ENQDEQ		0x00005c88
  3.1054 +#define FTQ_SWTYPE1_WRITE_PEEK		0x00005c8c
  3.1055 +#define FTQ_SEND_DATA_COMP_CTL		0x00005c90
  3.1056 +#define FTQ_SEND_DATA_COMP_FULL_CNT	0x00005c94
  3.1057 +#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ	0x00005c98
  3.1058 +#define FTQ_SEND_DATA_COMP_WRITE_PEEK	0x00005c9c
  3.1059 +#define FTQ_HOST_COAL_CTL		0x00005ca0
  3.1060 +#define FTQ_HOST_COAL_FULL_CNT		0x00005ca4
  3.1061 +#define FTQ_HOST_COAL_FIFO_ENQDEQ	0x00005ca8
  3.1062 +#define FTQ_HOST_COAL_WRITE_PEEK	0x00005cac
  3.1063 +#define FTQ_MAC_TX_CTL			0x00005cb0
  3.1064 +#define FTQ_MAC_TX_FULL_CNT		0x00005cb4
  3.1065 +#define FTQ_MAC_TX_FIFO_ENQDEQ		0x00005cb8
  3.1066 +#define FTQ_MAC_TX_WRITE_PEEK		0x00005cbc
  3.1067 +#define FTQ_MB_FREE_CTL			0x00005cc0
  3.1068 +#define FTQ_MB_FREE_FULL_CNT		0x00005cc4
  3.1069 +#define FTQ_MB_FREE_FIFO_ENQDEQ		0x00005cc8
  3.1070 +#define FTQ_MB_FREE_WRITE_PEEK		0x00005ccc
  3.1071 +#define FTQ_RCVBD_COMP_CTL		0x00005cd0
  3.1072 +#define FTQ_RCVBD_COMP_FULL_CNT		0x00005cd4
  3.1073 +#define FTQ_RCVBD_COMP_FIFO_ENQDEQ	0x00005cd8
  3.1074 +#define FTQ_RCVBD_COMP_WRITE_PEEK	0x00005cdc
  3.1075 +#define FTQ_RCVLST_PLMT_CTL		0x00005ce0
  3.1076 +#define FTQ_RCVLST_PLMT_FULL_CNT	0x00005ce4
  3.1077 +#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ	0x00005ce8
  3.1078 +#define FTQ_RCVLST_PLMT_WRITE_PEEK	0x00005cec
  3.1079 +#define FTQ_RCVDATA_INI_CTL		0x00005cf0
  3.1080 +#define FTQ_RCVDATA_INI_FULL_CNT	0x00005cf4
  3.1081 +#define FTQ_RCVDATA_INI_FIFO_ENQDEQ	0x00005cf8
  3.1082 +#define FTQ_RCVDATA_INI_WRITE_PEEK	0x00005cfc
  3.1083 +#define FTQ_RCVDATA_COMP_CTL		0x00005d00
  3.1084 +#define FTQ_RCVDATA_COMP_FULL_CNT	0x00005d04
  3.1085 +#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ	0x00005d08
  3.1086 +#define FTQ_RCVDATA_COMP_WRITE_PEEK	0x00005d0c
  3.1087 +#define FTQ_SWTYPE2_CTL			0x00005d10
  3.1088 +#define FTQ_SWTYPE2_FULL_CNT		0x00005d14
  3.1089 +#define FTQ_SWTYPE2_FIFO_ENQDEQ		0x00005d18
  3.1090 +#define FTQ_SWTYPE2_WRITE_PEEK		0x00005d1c
  3.1091 +/* 0x5d20 --> 0x6000 unused */
  3.1092 +
  3.1093 +/* Message signaled interrupt registers */
  3.1094 +#define MSGINT_MODE			0x00006000
  3.1095 +#define  MSGINT_MODE_RESET		 0x00000001
  3.1096 +#define  MSGINT_MODE_ENABLE		 0x00000002
  3.1097 +#define MSGINT_STATUS			0x00006004
  3.1098 +#define MSGINT_FIFO			0x00006008
  3.1099 +/* 0x600c --> 0x6400 unused */
  3.1100 +
  3.1101 +/* DMA completion registers */
  3.1102 +#define DMAC_MODE			0x00006400
  3.1103 +#define  DMAC_MODE_RESET		 0x00000001
  3.1104 +#define  DMAC_MODE_ENABLE		 0x00000002
  3.1105 +/* 0x6404 --> 0x6800 unused */
  3.1106 +
  3.1107 +/* GRC registers */
  3.1108 +#define GRC_MODE			0x00006800
  3.1109 +#define  GRC_MODE_UPD_ON_COAL		0x00000001
  3.1110 +#define  GRC_MODE_BSWAP_NONFRM_DATA	0x00000002
  3.1111 +#define  GRC_MODE_WSWAP_NONFRM_DATA	0x00000004
  3.1112 +#define  GRC_MODE_BSWAP_DATA		0x00000010
  3.1113 +#define  GRC_MODE_WSWAP_DATA		0x00000020
  3.1114 +#define  GRC_MODE_SPLITHDR		0x00000100
  3.1115 +#define  GRC_MODE_NOFRM_CRACKING	0x00000200
  3.1116 +#define  GRC_MODE_INCL_CRC		0x00000400
  3.1117 +#define  GRC_MODE_ALLOW_BAD_FRMS	0x00000800
  3.1118 +#define  GRC_MODE_NOIRQ_ON_SENDS	0x00002000
  3.1119 +#define  GRC_MODE_NOIRQ_ON_RCV		0x00004000
  3.1120 +#define  GRC_MODE_FORCE_PCI32BIT	0x00008000
  3.1121 +#define  GRC_MODE_HOST_STACKUP		0x00010000
  3.1122 +#define  GRC_MODE_HOST_SENDBDS		0x00020000
  3.1123 +#define  GRC_MODE_NO_TX_PHDR_CSUM	0x00100000
  3.1124 +#define  GRC_MODE_NO_RX_PHDR_CSUM	0x00800000
  3.1125 +#define  GRC_MODE_IRQ_ON_TX_CPU_ATTN	0x01000000
  3.1126 +#define  GRC_MODE_IRQ_ON_RX_CPU_ATTN	0x02000000
  3.1127 +#define  GRC_MODE_IRQ_ON_MAC_ATTN	0x04000000
  3.1128 +#define  GRC_MODE_IRQ_ON_DMA_ATTN	0x08000000
  3.1129 +#define  GRC_MODE_IRQ_ON_FLOW_ATTN	0x10000000
  3.1130 +#define  GRC_MODE_4X_NIC_SEND_RINGS	0x20000000
  3.1131 +#define  GRC_MODE_MCAST_FRM_ENABLE	0x40000000
  3.1132 +#define GRC_MISC_CFG			0x00006804
  3.1133 +#define  GRC_MISC_CFG_CORECLK_RESET	0x00000001
  3.1134 +#define  GRC_MISC_CFG_PRESCALAR_MASK	0x000000fe
  3.1135 +#define  GRC_MISC_CFG_PRESCALAR_SHIFT	1
  3.1136 +#define  GRC_MISC_CFG_BOARD_ID_MASK	0x0001e000
  3.1137 +#define  GRC_MISC_CFG_BOARD_ID_5700	0x0001e000
  3.1138 +#define  GRC_MISC_CFG_BOARD_ID_5701	0x00000000
  3.1139 +#define  GRC_MISC_CFG_BOARD_ID_5702FE	0x00004000
  3.1140 +#define  GRC_MISC_CFG_BOARD_ID_5703	0x00000000
  3.1141 +#define  GRC_MISC_CFG_BOARD_ID_5703S	0x00002000
  3.1142 +#define  GRC_MISC_CFG_BOARD_ID_5704	0x00000000
  3.1143 +#define  GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
  3.1144 +#define  GRC_MISC_CFG_BOARD_ID_5704_A2	0x00008000
  3.1145 +#define  GRC_MISC_CFG_BOARD_ID_5704_X	0x0000C000
  3.1146 +#define  GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
  3.1147 +#define GRC_LOCAL_CTRL			0x00006808
  3.1148 +#define  GRC_LCLCTRL_INT_ACTIVE		0x00000001
  3.1149 +#define  GRC_LCLCTRL_CLEARINT		0x00000002
  3.1150 +#define  GRC_LCLCTRL_SETINT		0x00000004
  3.1151 +#define  GRC_LCLCTRL_INT_ON_ATTN	0x00000008
  3.1152 +#define  GRC_LCLCTRL_GPIO_INPUT0	0x00000100
  3.1153 +#define  GRC_LCLCTRL_GPIO_INPUT1	0x00000200
  3.1154 +#define  GRC_LCLCTRL_GPIO_INPUT2	0x00000400
  3.1155 +#define  GRC_LCLCTRL_GPIO_OE0		0x00000800
  3.1156 +#define  GRC_LCLCTRL_GPIO_OE1		0x00001000
  3.1157 +#define  GRC_LCLCTRL_GPIO_OE2		0x00002000
  3.1158 +#define  GRC_LCLCTRL_GPIO_OUTPUT0	0x00004000
  3.1159 +#define  GRC_LCLCTRL_GPIO_OUTPUT1	0x00008000
  3.1160 +#define  GRC_LCLCTRL_GPIO_OUTPUT2	0x00010000
  3.1161 +#define  GRC_LCLCTRL_EXTMEM_ENABLE	0x00020000
  3.1162 +#define  GRC_LCLCTRL_MEMSZ_MASK		0x001c0000
  3.1163 +#define  GRC_LCLCTRL_MEMSZ_256K		0x00000000
  3.1164 +#define  GRC_LCLCTRL_MEMSZ_512K		0x00040000
  3.1165 +#define  GRC_LCLCTRL_MEMSZ_1M		0x00080000
  3.1166 +#define  GRC_LCLCTRL_MEMSZ_2M		0x000c0000
  3.1167 +#define  GRC_LCLCTRL_MEMSZ_4M		0x00100000
  3.1168 +#define  GRC_LCLCTRL_MEMSZ_8M		0x00140000
  3.1169 +#define  GRC_LCLCTRL_MEMSZ_16M		0x00180000
  3.1170 +#define  GRC_LCLCTRL_BANK_SELECT	0x00200000
  3.1171 +#define  GRC_LCLCTRL_SSRAM_TYPE		0x00400000
  3.1172 +#define  GRC_LCLCTRL_AUTO_SEEPROM	0x01000000
  3.1173 +#define GRC_TIMER			0x0000680c
  3.1174 +#define GRC_RX_CPU_EVENT		0x00006810
  3.1175 +#define GRC_RX_TIMER_REF		0x00006814
  3.1176 +#define GRC_RX_CPU_SEM			0x00006818
  3.1177 +#define GRC_REMOTE_RX_CPU_ATTN		0x0000681c
  3.1178 +#define GRC_TX_CPU_EVENT		0x00006820
  3.1179 +#define GRC_TX_TIMER_REF		0x00006824
  3.1180 +#define GRC_TX_CPU_SEM			0x00006828
  3.1181 +#define GRC_REMOTE_TX_CPU_ATTN		0x0000682c
  3.1182 +#define GRC_MEM_POWER_UP		0x00006830 /* 64-bit */
  3.1183 +#define GRC_EEPROM_ADDR			0x00006838
  3.1184 +#define  EEPROM_ADDR_WRITE		0x00000000
  3.1185 +#define  EEPROM_ADDR_READ		0x80000000
  3.1186 +#define  EEPROM_ADDR_COMPLETE		0x40000000
  3.1187 +#define  EEPROM_ADDR_FSM_RESET		0x20000000
  3.1188 +#define  EEPROM_ADDR_DEVID_MASK		0x1c000000
  3.1189 +#define  EEPROM_ADDR_DEVID_SHIFT	26
  3.1190 +#define  EEPROM_ADDR_START		0x02000000
  3.1191 +#define  EEPROM_ADDR_CLKPERD_SHIFT	16
  3.1192 +#define  EEPROM_ADDR_ADDR_MASK		0x0000ffff
  3.1193 +#define  EEPROM_ADDR_ADDR_SHIFT		0
  3.1194 +#define  EEPROM_DEFAULT_CLOCK_PERIOD	0x60
  3.1195 +#define  EEPROM_CHIP_SIZE		(64 * 1024)
  3.1196 +#define GRC_EEPROM_DATA			0x0000683c
  3.1197 +#define GRC_EEPROM_CTRL			0x00006840
  3.1198 +#define GRC_MDI_CTRL			0x00006844
  3.1199 +#define GRC_SEEPROM_DELAY		0x00006848
  3.1200 +/* 0x684c --> 0x6c00 unused */
  3.1201 +
  3.1202 +/* 0x6c00 --> 0x7000 unused */
  3.1203 +
  3.1204 +/* NVRAM Control registers */
  3.1205 +#define NVRAM_CMD			0x00007000
  3.1206 +#define  NVRAM_CMD_RESET		 0x00000001
  3.1207 +#define  NVRAM_CMD_DONE			 0x00000008
  3.1208 +#define  NVRAM_CMD_GO			 0x00000010
  3.1209 +#define  NVRAM_CMD_WR			 0x00000020
  3.1210 +#define  NVRAM_CMD_RD			 0x00000000
  3.1211 +#define  NVRAM_CMD_ERASE		 0x00000040
  3.1212 +#define  NVRAM_CMD_FIRST		 0x00000080
  3.1213 +#define  NVRAM_CMD_LAST			 0x00000100
  3.1214 +#define NVRAM_STAT			0x00007004
  3.1215 +#define NVRAM_WRDATA			0x00007008
  3.1216 +#define NVRAM_ADDR			0x0000700c
  3.1217 +#define  NVRAM_ADDR_MSK			0x00ffffff
  3.1218 +#define NVRAM_RDDATA			0x00007010
  3.1219 +#define NVRAM_CFG1			0x00007014
  3.1220 +#define  NVRAM_CFG1_FLASHIF_ENAB	 0x00000001
  3.1221 +#define  NVRAM_CFG1_BUFFERED_MODE	 0x00000002
  3.1222 +#define  NVRAM_CFG1_PASS_THRU		 0x00000004
  3.1223 +#define  NVRAM_CFG1_BIT_BANG		 0x00000008
  3.1224 +#define  NVRAM_CFG1_COMPAT_BYPASS	 0x80000000
  3.1225 +#define NVRAM_CFG2			0x00007018
  3.1226 +#define NVRAM_CFG3			0x0000701c
  3.1227 +#define NVRAM_SWARB			0x00007020
  3.1228 +#define  SWARB_REQ_SET0			 0x00000001
  3.1229 +#define  SWARB_REQ_SET1			 0x00000002
  3.1230 +#define  SWARB_REQ_SET2			 0x00000004
  3.1231 +#define  SWARB_REQ_SET3			 0x00000008
  3.1232 +#define  SWARB_REQ_CLR0			 0x00000010
  3.1233 +#define  SWARB_REQ_CLR1			 0x00000020
  3.1234 +#define  SWARB_REQ_CLR2			 0x00000040
  3.1235 +#define  SWARB_REQ_CLR3			 0x00000080
  3.1236 +#define  SWARB_GNT0			 0x00000100
  3.1237 +#define  SWARB_GNT1			 0x00000200
  3.1238 +#define  SWARB_GNT2			 0x00000400
  3.1239 +#define  SWARB_GNT3			 0x00000800
  3.1240 +#define  SWARB_REQ0			 0x00001000
  3.1241 +#define  SWARB_REQ1			 0x00002000
  3.1242 +#define  SWARB_REQ2			 0x00004000
  3.1243 +#define  SWARB_REQ3			 0x00008000
  3.1244 +#define    NVRAM_BUFFERED_PAGE_SIZE	   264
  3.1245 +#define    NVRAM_BUFFERED_PAGE_POS	   9
  3.1246 +/* 0x7024 --> 0x7400 unused */
  3.1247 +
  3.1248 +/* 0x7400 --> 0x8000 unused */
  3.1249 +
  3.1250 +/* 32K Window into NIC internal memory */
  3.1251 +#define NIC_SRAM_WIN_BASE		0x00008000
  3.1252 +
  3.1253 +/* Offsets into first 32k of NIC internal memory. */
  3.1254 +#define NIC_SRAM_PAGE_ZERO		0x00000000
  3.1255 +#define NIC_SRAM_SEND_RCB		0x00000100 /* 16 * TG3_BDINFO_... */
  3.1256 +#define NIC_SRAM_RCV_RET_RCB		0x00000200 /* 16 * TG3_BDINFO_... */
  3.1257 +#define NIC_SRAM_STATS_BLK		0x00000300
  3.1258 +#define NIC_SRAM_STATUS_BLK		0x00000b00
  3.1259 +
  3.1260 +#define NIC_SRAM_FIRMWARE_MBOX		0x00000b50
  3.1261 +#define  NIC_SRAM_FIRMWARE_MBOX_MAGIC1	 0x4B657654
  3.1262 +#define  NIC_SRAM_FIRMWARE_MBOX_MAGIC2	 0x4861764b /* !dma on linkchg */
  3.1263 +
  3.1264 +#define NIC_SRAM_DATA_SIG		0x00000b54
  3.1265 +#define  NIC_SRAM_DATA_SIG_MAGIC	 0x4b657654 /* ascii for 'KevT' */
  3.1266 +
  3.1267 +#define NIC_SRAM_DATA_CFG			0x00000b58
  3.1268 +#define  NIC_SRAM_DATA_CFG_LED_MODE_MASK	 0x0000000c
  3.1269 +#define  NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN	 0x00000000
  3.1270 +#define  NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD	 0x00000004
  3.1271 +#define  NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN	 0x00000004
  3.1272 +#define  NIC_SRAM_DATA_CFG_LED_LINK_SPD		 0x00000008
  3.1273 +#define  NIC_SRAM_DATA_CFG_LED_OUTPUT		 0x00000008
  3.1274 +#define  NIC_SRAM_DATA_CFG_PHY_TYPE_MASK	 0x00000030
  3.1275 +#define  NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN	 0x00000000
  3.1276 +#define  NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER	 0x00000010
  3.1277 +#define  NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER	 0x00000020
  3.1278 +#define  NIC_SRAM_DATA_CFG_WOL_ENABLE		 0x00000040
  3.1279 +#define  NIC_SRAM_DATA_CFG_ASF_ENABLE		 0x00000080
  3.1280 +#define  NIC_SRAM_DATA_CFG_EEPROM_WP		 0x00000100
  3.1281 +#define  NIC_SRAM_DATA_CFG_FIBER_WOL		 0x00004000
  3.1282 +
  3.1283 +#define NIC_SRAM_DATA_PHY_ID		0x00000b74
  3.1284 +#define  NIC_SRAM_DATA_PHY_ID1_MASK	 0xffff0000
  3.1285 +#define  NIC_SRAM_DATA_PHY_ID2_MASK	 0x0000ffff
  3.1286 +
  3.1287 +#define NIC_SRAM_FW_CMD_MBOX		0x00000b78
  3.1288 +#define  FWCMD_NICDRV_ALIVE		 0x00000001
  3.1289 +#define  FWCMD_NICDRV_PAUSE_FW		 0x00000002
  3.1290 +#define  FWCMD_NICDRV_IPV4ADDR_CHG	 0x00000003
  3.1291 +#define  FWCMD_NICDRV_IPV6ADDR_CHG	 0x00000004
  3.1292 +#define  FWCMD_NICDRV_FIX_DMAR		 0x00000005
  3.1293 +#define  FWCMD_NICDRV_FIX_DMAW		 0x00000006
  3.1294 +#define NIC_SRAM_FW_CMD_LEN_MBOX	0x00000b7c
  3.1295 +#define NIC_SRAM_FW_CMD_DATA_MBOX	0x00000b80
  3.1296 +#define NIC_SRAM_FW_ASF_STATUS_MBOX	0x00000c00
  3.1297 +#define NIC_SRAM_FW_DRV_STATE_MBOX	0x00000c04
  3.1298 +#define  DRV_STATE_START		 0x00000001
  3.1299 +#define  DRV_STATE_UNLOAD		 0x00000002
  3.1300 +#define  DRV_STATE_WOL			 0x00000003
  3.1301 +#define  DRV_STATE_SUSPEND		 0x00000004
  3.1302 +
  3.1303 +#define NIC_SRAM_FW_RESET_TYPE_MBOX	0x00000c08
  3.1304 +
  3.1305 +#define NIC_SRAM_MAC_ADDR_HIGH_MBOX	0x00000c14
  3.1306 +#define NIC_SRAM_MAC_ADDR_LOW_MBOX	0x00000c18
  3.1307 +
  3.1308 +#define NIC_SRAM_RX_MINI_BUFFER_DESC	0x00001000
  3.1309 +
  3.1310 +#define NIC_SRAM_DMA_DESC_POOL_BASE	0x00002000
  3.1311 +#define  NIC_SRAM_DMA_DESC_POOL_SIZE	 0x00002000
  3.1312 +#define NIC_SRAM_TX_BUFFER_DESC		0x00004000 /* 512 entries */
  3.1313 +#define NIC_SRAM_RX_BUFFER_DESC		0x00006000 /* 256 entries */
  3.1314 +#define NIC_SRAM_RX_JUMBO_BUFFER_DESC	0x00007000 /* 256 entries */
  3.1315 +#define NIC_SRAM_MBUF_POOL_BASE		0x00008000
  3.1316 +#define  NIC_SRAM_MBUF_POOL_SIZE96	 0x00018000
  3.1317 +#define  NIC_SRAM_MBUF_POOL_SIZE64	 0x00010000
  3.1318 +
  3.1319 +/* Currently this is fixed. */
  3.1320 +#define PHY_ADDR		0x01
  3.1321 +
  3.1322 +/* Tigon3 specific PHY MII registers. */
  3.1323 +#define  TG3_BMCR_SPEED1000		0x0040
  3.1324 +
  3.1325 +#define MII_TG3_CTRL			0x09 /* 1000-baseT control register */
  3.1326 +#define  MII_TG3_CTRL_ADV_1000_HALF	0x0100
  3.1327 +#define  MII_TG3_CTRL_ADV_1000_FULL	0x0200
  3.1328 +#define  MII_TG3_CTRL_AS_MASTER		0x0800
  3.1329 +#define  MII_TG3_CTRL_ENABLE_AS_MASTER	0x1000
  3.1330 +
  3.1331 +#define MII_TG3_EXT_CTRL		0x10 /* Extended control register */
  3.1332 +#define  MII_TG3_EXT_CTRL_LNK3_LED_MODE	0x0002
  3.1333 +#define  MII_TG3_EXT_CTRL_TBI		0x8000
  3.1334 +
  3.1335 +#define MII_TG3_EXT_STAT		0x11 /* Extended status register */
  3.1336 +#define  MII_TG3_EXT_STAT_LPASS		0x0100
  3.1337 +
  3.1338 +#define MII_TG3_DSP_RW_PORT		0x15 /* DSP coefficient read/write port */
  3.1339 +
  3.1340 +#define MII_TG3_DSP_ADDRESS		0x17 /* DSP address register */
  3.1341 +
  3.1342 +#define MII_TG3_AUX_CTRL		0x18 /* auxilliary control register */
  3.1343 +
  3.1344 +#define MII_TG3_AUX_STAT		0x19 /* auxilliary status register */
  3.1345 +#define MII_TG3_AUX_STAT_LPASS		0x0004
  3.1346 +#define MII_TG3_AUX_STAT_SPDMASK	0x0700
  3.1347 +#define MII_TG3_AUX_STAT_10HALF		0x0100
  3.1348 +#define MII_TG3_AUX_STAT_10FULL		0x0200
  3.1349 +#define MII_TG3_AUX_STAT_100HALF	0x0300
  3.1350 +#define MII_TG3_AUX_STAT_100_4		0x0400
  3.1351 +#define MII_TG3_AUX_STAT_100FULL	0x0500
  3.1352 +#define MII_TG3_AUX_STAT_1000HALF	0x0600
  3.1353 +#define MII_TG3_AUX_STAT_1000FULL	0x0700
  3.1354 +
  3.1355 +#define MII_TG3_ISTAT			0x1a /* IRQ status register */
  3.1356 +#define MII_TG3_IMASK			0x1b /* IRQ mask register */
  3.1357 +
  3.1358 +/* ISTAT/IMASK event bits */
  3.1359 +#define MII_TG3_INT_LINKCHG		0x0002
  3.1360 +#define MII_TG3_INT_SPEEDCHG		0x0004
  3.1361 +#define MII_TG3_INT_DUPLEXCHG		0x0008
  3.1362 +#define MII_TG3_INT_ANEG_PAGE_RX	0x0400
  3.1363 +
  3.1364 +/* XXX Add this to mii.h */
  3.1365 +#ifndef ADVERTISE_PAUSE
  3.1366 +#define ADVERTISE_PAUSE_CAP		0x0400
  3.1367 +#endif
  3.1368 +#ifndef ADVERTISE_PAUSE_ASYM
  3.1369 +#define ADVERTISE_PAUSE_ASYM		0x0800
  3.1370 +#endif
  3.1371 +#ifndef LPA_PAUSE
  3.1372 +#define LPA_PAUSE_CAP			0x0400
  3.1373 +#endif
  3.1374 +#ifndef LPA_PAUSE_ASYM
  3.1375 +#define LPA_PAUSE_ASYM			0x0800
  3.1376 +#endif
  3.1377 +
  3.1378 +/* There are two ways to manage the TX descriptors on the tigon3.
  3.1379 + * Either the descriptors are in host DMA'able memory, or they
  3.1380 + * exist only in the cards on-chip SRAM.  All 16 send bds are under
  3.1381 + * the same mode, they may not be configured individually.
  3.1382 + *
  3.1383 + * The mode we use is controlled by TG3_FLAG_HOST_TXDS in tp->tg3_flags.
  3.1384 + *
  3.1385 + * To use host memory TX descriptors:
  3.1386 + *	1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
  3.1387 + *	   Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
  3.1388 + *	2) Allocate DMA'able memory.
  3.1389 + *	3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
  3.1390 + *	   a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
  3.1391 + *	      obtained in step 2
  3.1392 + *	   b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
  3.1393 + *	   c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
  3.1394 + *            of TX descriptors.  Leave flags field clear.
  3.1395 + *	4) Access TX descriptors via host memory.  The chip
  3.1396 + *	   will refetch into local SRAM as needed when producer
  3.1397 + *	   index mailboxes are updated.
  3.1398 + *
  3.1399 + * To use on-chip TX descriptors:
  3.1400 + *	1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
  3.1401 + *	   Make sure GRC_MODE_HOST_SENDBDS is clear.
  3.1402 + *	2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
  3.1403 + *	   a) Set TG3_BDINFO_HOST_ADDR to zero.
  3.1404 + *	   b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
  3.1405 + *	   c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
  3.1406 + *	3) Access TX descriptors directly in on-chip SRAM
  3.1407 + *	   using normal {read,write}l().  (and not using
  3.1408 + *         pointer dereferencing of ioremap()'d memory like
  3.1409 + *	   the broken Broadcom driver does)
  3.1410 + *
  3.1411 + * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
  3.1412 + * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
  3.1413 + */
  3.1414 +struct tg3_tx_buffer_desc {
  3.1415 +	u32				addr_hi;
  3.1416 +	u32				addr_lo;
  3.1417 +
  3.1418 +	u32				len_flags;
  3.1419 +#define TXD_FLAG_TCPUDP_CSUM		0x0001
  3.1420 +#define TXD_FLAG_IP_CSUM		0x0002
  3.1421 +#define TXD_FLAG_END			0x0004
  3.1422 +#define TXD_FLAG_IP_FRAG		0x0008
  3.1423 +#define TXD_FLAG_IP_FRAG_END		0x0010
  3.1424 +#define TXD_FLAG_VLAN			0x0040
  3.1425 +#define TXD_FLAG_COAL_NOW		0x0080
  3.1426 +#define TXD_FLAG_CPU_PRE_DMA		0x0100
  3.1427 +#define TXD_FLAG_CPU_POST_DMA		0x0200
  3.1428 +#define TXD_FLAG_ADD_SRC_ADDR		0x1000
  3.1429 +#define TXD_FLAG_CHOOSE_SRC_ADDR	0x6000
  3.1430 +#define TXD_FLAG_NO_CRC			0x8000
  3.1431 +#define TXD_LEN_SHIFT			16
  3.1432 +
  3.1433 +	u32				vlan_tag;
  3.1434 +#define TXD_VLAN_TAG_SHIFT		0
  3.1435 +#define TXD_MSS_SHIFT			16
  3.1436 +};
  3.1437 +
  3.1438 +#define TXD_ADDR			0x00UL /* 64-bit */
  3.1439 +#define TXD_LEN_FLAGS			0x08UL /* 32-bit (upper 16-bits are len) */
  3.1440 +#define TXD_VLAN_TAG			0x0cUL /* 32-bit (upper 16-bits are tag) */
  3.1441 +#define TXD_SIZE			0x10UL
  3.1442 +
  3.1443 +struct tg3_rx_buffer_desc {
  3.1444 +	u32				addr_hi;
  3.1445 +	u32				addr_lo;
  3.1446 +
  3.1447 +	u32				idx_len;
  3.1448 +#define RXD_IDX_MASK	0xffff0000
  3.1449 +#define RXD_IDX_SHIFT	16
  3.1450 +#define RXD_LEN_MASK	0x0000ffff
  3.1451 +#define RXD_LEN_SHIFT	0
  3.1452 +
  3.1453 +	u32				type_flags;
  3.1454 +#define RXD_TYPE_SHIFT	16
  3.1455 +#define RXD_FLAGS_SHIFT	0
  3.1456 +
  3.1457 +#define RXD_FLAG_END			0x0004
  3.1458 +#define RXD_FLAG_MINI			0x0800
  3.1459 +#define RXD_FLAG_JUMBO			0x0020
  3.1460 +#define RXD_FLAG_VLAN			0x0040
  3.1461 +#define RXD_FLAG_ERROR			0x0400
  3.1462 +#define RXD_FLAG_IP_CSUM		0x1000
  3.1463 +#define RXD_FLAG_TCPUDP_CSUM		0x2000
  3.1464 +#define RXD_FLAG_IS_TCP			0x4000
  3.1465 +
  3.1466 +	u32				ip_tcp_csum;
  3.1467 +#define RXD_IPCSUM_MASK		0xffff0000
  3.1468 +#define RXD_IPCSUM_SHIFT	16
  3.1469 +#define RXD_TCPCSUM_MASK	0x0000ffff
  3.1470 +#define RXD_TCPCSUM_SHIFT	0
  3.1471 +
  3.1472 +	u32				err_vlan;
  3.1473 +
  3.1474 +#define RXD_VLAN_MASK			0x0000ffff
  3.1475 +
  3.1476 +#define RXD_ERR_BAD_CRC			0x00010000
  3.1477 +#define RXD_ERR_COLLISION		0x00020000
  3.1478 +#define RXD_ERR_LINK_LOST		0x00040000
  3.1479 +#define RXD_ERR_PHY_DECODE		0x00080000
  3.1480 +#define RXD_ERR_ODD_NIBBLE_RCVD_MII	0x00100000
  3.1481 +#define RXD_ERR_MAC_ABRT		0x00200000
  3.1482 +#define RXD_ERR_TOO_SMALL		0x00400000
  3.1483 +#define RXD_ERR_NO_RESOURCES		0x00800000
  3.1484 +#define RXD_ERR_HUGE_FRAME		0x01000000
  3.1485 +#define RXD_ERR_MASK			0xffff0000
  3.1486 +
  3.1487 +	u32				reserved;
  3.1488 +	u32				opaque;
  3.1489 +#define RXD_OPAQUE_INDEX_MASK		0x0000ffff
  3.1490 +#define RXD_OPAQUE_INDEX_SHIFT		0
  3.1491 +#define RXD_OPAQUE_RING_STD		0x00010000
  3.1492 +#define RXD_OPAQUE_RING_JUMBO		0x00020000
  3.1493 +#define RXD_OPAQUE_RING_MINI		0x00040000
  3.1494 +#define RXD_OPAQUE_RING_MASK		0x00070000
  3.1495 +};
  3.1496 +
  3.1497 +struct tg3_ext_rx_buffer_desc {
  3.1498 +	struct {
  3.1499 +		u32			addr_hi;
  3.1500 +		u32			addr_lo;
  3.1501 +	}				addrlist[3];
  3.1502 +	u32				len2_len1;
  3.1503 +	u32				resv_len3;
  3.1504 +	struct tg3_rx_buffer_desc	std;
  3.1505 +};
  3.1506 +
  3.1507 +/* We only use this when testing out the DMA engine
  3.1508 + * at probe time.  This is the internal format of buffer
  3.1509 + * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
  3.1510 + */
  3.1511 +struct tg3_internal_buffer_desc {
  3.1512 +	u32				addr_hi;
  3.1513 +	u32				addr_lo;
  3.1514 +	u32				nic_mbuf;
  3.1515 +	/* XXX FIX THIS */
  3.1516 +#ifdef __BIG_ENDIAN
  3.1517 +	u16				cqid_sqid;
  3.1518 +	u16				len;
  3.1519 +#else
  3.1520 +	u16				len;
  3.1521 +	u16				cqid_sqid;
  3.1522 +#endif
  3.1523 +	u32				flags;
  3.1524 +	u32				__cookie1;
  3.1525 +	u32				__cookie2;
  3.1526 +	u32				__cookie3;
  3.1527 +};
  3.1528 +
  3.1529 +#define TG3_HW_STATUS_SIZE		0x50
  3.1530 +struct tg3_hw_status {
  3.1531 +	u32				status;
  3.1532 +#define SD_STATUS_UPDATED		0x00000001
  3.1533 +#define SD_STATUS_LINK_CHG		0x00000002
  3.1534 +#define SD_STATUS_ERROR			0x00000004
  3.1535 +
  3.1536 +	u32				status_tag;
  3.1537 +
  3.1538 +#ifdef __BIG_ENDIAN
  3.1539 +	u16				rx_consumer;
  3.1540 +	u16				rx_jumbo_consumer;
  3.1541 +#else
  3.1542 +	u16				rx_jumbo_consumer;
  3.1543 +	u16				rx_consumer;
  3.1544 +#endif
  3.1545 +
  3.1546 +#ifdef __BIG_ENDIAN
  3.1547 +	u16				reserved;
  3.1548 +	u16				rx_mini_consumer;
  3.1549 +#else
  3.1550 +	u16				rx_mini_consumer;
  3.1551 +	u16				reserved;
  3.1552 +#endif
  3.1553 +	struct {
  3.1554 +#ifdef __BIG_ENDIAN
  3.1555 +		u16			tx_consumer;
  3.1556 +		u16			rx_producer;
  3.1557 +#else
  3.1558 +		u16			rx_producer;
  3.1559 +		u16			tx_consumer;
  3.1560 +#endif
  3.1561 +	}				idx[16];
  3.1562 +};
  3.1563 +
  3.1564 +typedef struct {
  3.1565 +	u32 high, low;
  3.1566 +} tg3_stat64_t;
  3.1567 +
  3.1568 +struct tg3_hw_stats {
  3.1569 +	u8				__reserved0[0x400-0x300];
  3.1570 +
  3.1571 +	/* Statistics maintained by Receive MAC. */
  3.1572 +	tg3_stat64_t			rx_octets;
  3.1573 +	u64				__reserved1;
  3.1574 +	tg3_stat64_t			rx_fragments;
  3.1575 +	tg3_stat64_t			rx_ucast_packets;
  3.1576 +	tg3_stat64_t			rx_mcast_packets;
  3.1577 +	tg3_stat64_t			rx_bcast_packets;
  3.1578 +	tg3_stat64_t			rx_fcs_errors;
  3.1579 +	tg3_stat64_t			rx_align_errors;
  3.1580 +	tg3_stat64_t			rx_xon_pause_rcvd;
  3.1581 +	tg3_stat64_t			rx_xoff_pause_rcvd;
  3.1582 +	tg3_stat64_t			rx_mac_ctrl_rcvd;
  3.1583 +	tg3_stat64_t			rx_xoff_entered;
  3.1584 +	tg3_stat64_t			rx_frame_too_long_errors;
  3.1585 +	tg3_stat64_t			rx_jabbers;
  3.1586 +	tg3_stat64_t			rx_undersize_packets;
  3.1587 +	tg3_stat64_t			rx_in_length_errors;
  3.1588 +	tg3_stat64_t			rx_out_length_errors;
  3.1589 +	tg3_stat64_t			rx_64_or_less_octet_packets;
  3.1590 +	tg3_stat64_t			rx_65_to_127_octet_packets;
  3.1591 +	tg3_stat64_t			rx_128_to_255_octet_packets;
  3.1592 +	tg3_stat64_t			rx_256_to_511_octet_packets;
  3.1593 +	tg3_stat64_t			rx_512_to_1023_octet_packets;
  3.1594 +	tg3_stat64_t			rx_1024_to_1522_octet_packets;
  3.1595 +	tg3_stat64_t			rx_1523_to_2047_octet_packets;
  3.1596 +	tg3_stat64_t			rx_2048_to_4095_octet_packets;
  3.1597 +	tg3_stat64_t			rx_4096_to_8191_octet_packets;
  3.1598 +	tg3_stat64_t			rx_8192_to_9022_octet_packets;
  3.1599 +
  3.1600 +	u64				__unused0[37];
  3.1601 +
  3.1602 +	/* Statistics maintained by Transmit MAC. */
  3.1603 +	tg3_stat64_t			tx_octets;
  3.1604 +	u64				__reserved2;
  3.1605 +	tg3_stat64_t			tx_collisions;
  3.1606 +	tg3_stat64_t			tx_xon_sent;
  3.1607 +	tg3_stat64_t			tx_xoff_sent;
  3.1608 +	tg3_stat64_t			tx_flow_control;
  3.1609 +	tg3_stat64_t			tx_mac_errors;
  3.1610 +	tg3_stat64_t			tx_single_collisions;
  3.1611 +	tg3_stat64_t			tx_mult_collisions;
  3.1612 +	tg3_stat64_t			tx_deferred;
  3.1613 +	u64				__reserved3;
  3.1614 +	tg3_stat64_t			tx_excessive_collisions;
  3.1615 +	tg3_stat64_t			tx_late_collisions;
  3.1616 +	tg3_stat64_t			tx_collide_2times;
  3.1617 +	tg3_stat64_t			tx_collide_3times;
  3.1618 +	tg3_stat64_t			tx_collide_4times;
  3.1619 +	tg3_stat64_t			tx_collide_5times;
  3.1620 +	tg3_stat64_t			tx_collide_6times;
  3.1621 +	tg3_stat64_t			tx_collide_7times;
  3.1622 +	tg3_stat64_t			tx_collide_8times;
  3.1623 +	tg3_stat64_t			tx_collide_9times;
  3.1624 +	tg3_stat64_t			tx_collide_10times;
  3.1625 +	tg3_stat64_t			tx_collide_11times;
  3.1626 +	tg3_stat64_t			tx_collide_12times;
  3.1627 +	tg3_stat64_t			tx_collide_13times;
  3.1628 +	tg3_stat64_t			tx_collide_14times;
  3.1629 +	tg3_stat64_t			tx_collide_15times;
  3.1630 +	tg3_stat64_t			tx_ucast_packets;
  3.1631 +	tg3_stat64_t			tx_mcast_packets;
  3.1632 +	tg3_stat64_t			tx_bcast_packets;
  3.1633 +	tg3_stat64_t			tx_carrier_sense_errors;
  3.1634 +	tg3_stat64_t			tx_discards;
  3.1635 +	tg3_stat64_t			tx_errors;
  3.1636 +
  3.1637 +	u64				__unused1[31];
  3.1638 +
  3.1639 +	/* Statistics maintained by Receive List Placement. */
  3.1640 +	tg3_stat64_t			COS_rx_packets[16];
  3.1641 +	tg3_stat64_t			COS_rx_filter_dropped;
  3.1642 +	tg3_stat64_t			dma_writeq_full;
  3.1643 +	tg3_stat64_t			dma_write_prioq_full;
  3.1644 +	tg3_stat64_t			rxbds_empty;
  3.1645 +	tg3_stat64_t			rx_discards;
  3.1646 +	tg3_stat64_t			rx_errors;
  3.1647 +	tg3_stat64_t			rx_threshold_hit;
  3.1648 +
  3.1649 +	u64				__unused2[9];
  3.1650 +
  3.1651 +	/* Statistics maintained by Send Data Initiator. */
  3.1652 +	tg3_stat64_t			COS_out_packets[16];
  3.1653 +	tg3_stat64_t			dma_readq_full;
  3.1654 +	tg3_stat64_t			dma_read_prioq_full;
  3.1655 +	tg3_stat64_t			tx_comp_queue_full;
  3.1656 +
  3.1657 +	/* Statistics maintained by Host Coalescing. */
  3.1658 +	tg3_stat64_t			ring_set_send_prod_index;
  3.1659 +	tg3_stat64_t			ring_status_update;
  3.1660 +	tg3_stat64_t			nic_irqs;
  3.1661 +	tg3_stat64_t			nic_avoided_irqs;
  3.1662 +	tg3_stat64_t			nic_tx_threshold_hit;
  3.1663 +
  3.1664 +	u8				__reserved4[0xb00-0x9c0];
  3.1665 +};
  3.1666 +
  3.1667 +enum phy_led_mode {
  3.1668 +	led_mode_auto,
  3.1669 +	led_mode_three_link,
  3.1670 +	led_mode_link10
  3.1671 +};
  3.1672 +
  3.1673 +/* 'mapping' is superfluous as the chip does not write into
  3.1674 + * the tx/rx post rings so we could just fetch it from there.
  3.1675 + * But the cache behavior is better how we are doing it now.
  3.1676 + */
  3.1677 +struct ring_info {
  3.1678 +	struct sk_buff			*skb;
  3.1679 +	DECLARE_PCI_UNMAP_ADDR(mapping)
  3.1680 +};
  3.1681 +
  3.1682 +struct tx_ring_info {
  3.1683 +	struct sk_buff			*skb;
  3.1684 +	DECLARE_PCI_UNMAP_ADDR(mapping)
  3.1685 +	u32				prev_vlan_tag;
  3.1686 +};
  3.1687 +
  3.1688 +struct tg3_config_info {
  3.1689 +	u32				flags;
  3.1690 +};
  3.1691 +
  3.1692 +struct tg3_link_config {
  3.1693 +	/* Describes what we're trying to get. */
  3.1694 +	u32				advertising;
  3.1695 +	u16				speed;
  3.1696 +	u8				duplex;
  3.1697 +	u8				autoneg;
  3.1698 +
  3.1699 +	/* Describes what we actually have. */
  3.1700 +	u16				active_speed;
  3.1701 +	u8				active_duplex;
  3.1702 +#define SPEED_INVALID		0xffff
  3.1703 +#define DUPLEX_INVALID		0xff
  3.1704 +#define AUTONEG_INVALID		0xff
  3.1705 +
  3.1706 +	/* When we go in and out of low power mode we need
  3.1707 +	 * to swap with this state.
  3.1708 +	 */
  3.1709 +	int				phy_is_low_power;
  3.1710 +	u16				orig_speed;
  3.1711 +	u8				orig_duplex;
  3.1712 +	u8				orig_autoneg;
  3.1713 +};
  3.1714 +
  3.1715 +struct tg3_bufmgr_config {
  3.1716 +	u32		mbuf_read_dma_low_water;
  3.1717 +	u32		mbuf_mac_rx_low_water;
  3.1718 +	u32		mbuf_high_water;
  3.1719 +
  3.1720 +	u32		mbuf_read_dma_low_water_jumbo;
  3.1721 +	u32		mbuf_mac_rx_low_water_jumbo;
  3.1722 +	u32		mbuf_high_water_jumbo;
  3.1723 +
  3.1724 +	u32		dma_low_water;
  3.1725 +	u32		dma_high_water;
  3.1726 +};
  3.1727 +
  3.1728 +struct tg3 {
  3.1729 +	/* begin "general, frequently-used members" cacheline section */
  3.1730 +
  3.1731 +	/* SMP locking strategy:
  3.1732 +	 *
  3.1733 +	 * lock: Held during all operations except TX packet
  3.1734 +	 *       processing.
  3.1735 +	 *
  3.1736 +	 * tx_lock: Held during tg3_start_xmit{,_4gbug} and tg3_tx
  3.1737 +	 *
  3.1738 +	 * If you want to shut up all asynchronous processing you must
  3.1739 +	 * acquire both locks, 'lock' taken before 'tx_lock'.  IRQs must
  3.1740 +	 * be disabled to take 'lock' but only softirq disabling is
  3.1741 +	 * necessary for acquisition of 'tx_lock'.
  3.1742 +	 */
  3.1743 +	spinlock_t			lock;
  3.1744 +	spinlock_t			indirect_lock;
  3.1745 +
  3.1746 +	unsigned long			regs;
  3.1747 +	struct net_device		*dev;
  3.1748 +	struct pci_dev			*pdev;
  3.1749 +
  3.1750 +	struct tg3_hw_status		*hw_status;
  3.1751 +	dma_addr_t			status_mapping;
  3.1752 +
  3.1753 +	u32				msg_enable;
  3.1754 +
  3.1755 +	/* begin "tx thread" cacheline section */
  3.1756 +	u32				tx_prod;
  3.1757 +	u32				tx_cons;
  3.1758 +	u32				tx_pending;
  3.1759 +
  3.1760 +	spinlock_t			tx_lock;
  3.1761 +
  3.1762 +	/* TX descs are only used if TG3_FLAG_HOST_TXDS is set. */
  3.1763 +	struct tg3_tx_buffer_desc	*tx_ring;
  3.1764 +	struct tx_ring_info		*tx_buffers;
  3.1765 +	dma_addr_t			tx_desc_mapping;
  3.1766 +
  3.1767 +	/* begin "rx thread" cacheline section */
  3.1768 +	u32				rx_rcb_ptr;
  3.1769 +	u32				rx_std_ptr;
  3.1770 +	u32				rx_jumbo_ptr;
  3.1771 +	u32				rx_pending;
  3.1772 +	u32				rx_jumbo_pending;
  3.1773 +#if TG3_VLAN_TAG_USED
  3.1774 +	struct vlan_group		*vlgrp;
  3.1775 +#endif
  3.1776 +
  3.1777 +	struct tg3_rx_buffer_desc	*rx_std;
  3.1778 +	struct ring_info		*rx_std_buffers;
  3.1779 +	dma_addr_t			rx_std_mapping;
  3.1780 +
  3.1781 +	struct tg3_rx_buffer_desc	*rx_jumbo;
  3.1782 +	struct ring_info		*rx_jumbo_buffers;
  3.1783 +	dma_addr_t			rx_jumbo_mapping;
  3.1784 +
  3.1785 +	struct tg3_rx_buffer_desc	*rx_rcb;
  3.1786 +	dma_addr_t			rx_rcb_mapping;
  3.1787 +
  3.1788 +	/* begin "everything else" cacheline(s) section */
  3.1789 +	struct net_device_stats		net_stats;
  3.1790 +	struct net_device_stats		net_stats_prev;
  3.1791 +	unsigned long			phy_crc_errors;
  3.1792 +
  3.1793 +	u32				rx_offset;
  3.1794 +	u32				tg3_flags;
  3.1795 +#define TG3_FLAG_HOST_TXDS		0x00000001
  3.1796 +#define TG3_FLAG_TXD_MBOX_HWBUG		0x00000002
  3.1797 +#define TG3_FLAG_RX_CHECKSUMS		0x00000004
  3.1798 +#define TG3_FLAG_USE_LINKCHG_REG	0x00000008
  3.1799 +#define TG3_FLAG_USE_MI_INTERRUPT	0x00000010
  3.1800 +#define TG3_FLAG_ENABLE_ASF		0x00000020
  3.1801 +#define TG3_FLAG_POLL_SERDES		0x00000080
  3.1802 +#define TG3_FLAG_MBOX_WRITE_REORDER	0x00000100
  3.1803 +#define TG3_FLAG_PCIX_TARGET_HWBUG	0x00000200
  3.1804 +#define TG3_FLAG_WOL_SPEED_100MB	0x00000400
  3.1805 +#define TG3_FLAG_WOL_ENABLE		0x00000800
  3.1806 +#define TG3_FLAG_EEPROM_WRITE_PROT	0x00001000
  3.1807 +#define TG3_FLAG_NVRAM			0x00002000
  3.1808 +#define TG3_FLAG_NVRAM_BUFFERED		0x00004000
  3.1809 +#define TG3_FLAG_RX_PAUSE		0x00008000
  3.1810 +#define TG3_FLAG_TX_PAUSE		0x00010000
  3.1811 +#define TG3_FLAG_PCIX_MODE		0x00020000
  3.1812 +#define TG3_FLAG_PCI_HIGH_SPEED		0x00040000
  3.1813 +#define TG3_FLAG_PCI_32BIT		0x00080000
  3.1814 +#define TG3_FLAG_NO_TX_PSEUDO_CSUM	0x00100000
  3.1815 +#define TG3_FLAG_NO_RX_PSEUDO_CSUM	0x00200000
  3.1816 +#define TG3_FLAG_SERDES_WOL_CAP		0x00400000
  3.1817 +#define TG3_FLAG_JUMBO_ENABLE		0x00800000
  3.1818 +#define TG3_FLAG_10_100_ONLY		0x01000000
  3.1819 +#define TG3_FLAG_PAUSE_AUTONEG		0x02000000
  3.1820 +#define TG3_FLAG_PAUSE_RX		0x04000000
  3.1821 +#define TG3_FLAG_PAUSE_TX		0x08000000
  3.1822 +#define TG3_FLAG_BROKEN_CHECKSUMS	0x10000000
  3.1823 +#define TG3_FLAG_GOT_SERDES_FLOWCTL	0x20000000
  3.1824 +#define TG3_FLAG_SPLIT_MODE		0x40000000
  3.1825 +#define TG3_FLAG_INIT_COMPLETE		0x80000000
  3.1826 +
  3.1827 +	u32				split_mode_max_reqs;
  3.1828 +#define SPLIT_MODE_5704_MAX_REQ		3
  3.1829 +
  3.1830 +	struct timer_list		timer;
  3.1831 +	u16				timer_counter;
  3.1832 +	u16				timer_multiplier;
  3.1833 +	u32				timer_offset;
  3.1834 +	u16				asf_counter;
  3.1835 +	u16				asf_multiplier;
  3.1836 +
  3.1837 +	struct tg3_link_config		link_config;
  3.1838 +	struct tg3_bufmgr_config	bufmgr_config;
  3.1839 +
  3.1840 +	/* cache h/w values, often passed straight to h/w */
  3.1841 +	u32				rx_mode;
  3.1842 +	u32				tx_mode;
  3.1843 +	u32				mac_mode;
  3.1844 +	u32				mi_mode;
  3.1845 +	u32				misc_host_ctrl;
  3.1846 +	u32				grc_mode;
  3.1847 +	u32				grc_local_ctrl;
  3.1848 +	u32				dma_rwctrl;
  3.1849 +	u32				coalesce_mode;
  3.1850 +
  3.1851 +	/* PCI block */
  3.1852 +	u16				pci_chip_rev_id;
  3.1853 +	u8				pci_cacheline_sz;
  3.1854 +	u8				pci_lat_timer;
  3.1855 +	u8				pci_hdr_type;
  3.1856 +	u8				pci_bist;
  3.1857 +	u32				pci_cfg_state[64 / sizeof(u32)];
  3.1858 +
  3.1859 +	int				pm_cap;
  3.1860 +
  3.1861 +	/* PHY info */
  3.1862 +	u32				phy_id;
  3.1863 +#define PHY_ID_MASK			0xfffffff0
  3.1864 +#define PHY_ID_BCM5400			0x60008040
  3.1865 +#define PHY_ID_BCM5401			0x60008050
  3.1866 +#define PHY_ID_BCM5411			0x60008070
  3.1867 +#define PHY_ID_BCM5701			0x60008110
  3.1868 +#define PHY_ID_BCM5703			0x60008160
  3.1869 +#define PHY_ID_BCM5704			0x60008190
  3.1870 +#define PHY_ID_BCM8002			0x60010140
  3.1871 +#define PHY_ID_SERDES			0xfeedbee0
  3.1872 +#define PHY_ID_INVALID			0xffffffff
  3.1873 +#define PHY_ID_REV_MASK			0x0000000f
  3.1874 +#define PHY_REV_BCM5401_B0		0x1
  3.1875 +#define PHY_REV_BCM5401_B2		0x3
  3.1876 +#define PHY_REV_BCM5401_C0		0x6
  3.1877 +#define PHY_REV_BCM5411_X0		0x1 /* Found on Netgear GA302T */
  3.1878 +
  3.1879 +	enum phy_led_mode		led_mode;
  3.1880 +
  3.1881 +	char				board_part_number[24];
  3.1882 +
  3.1883 +	/* This macro assumes the passed PHY ID is already masked
  3.1884 +	 * with PHY_ID_MASK.
  3.1885 +	 */
  3.1886 +#define KNOWN_PHY_ID(X)		\
  3.1887 +	((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
  3.1888 +	 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
  3.1889 +	 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
  3.1890 +	 (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
  3.1891 +
  3.1892 +	struct tg3_hw_stats		*hw_stats;
  3.1893 +	dma_addr_t			stats_mapping;
  3.1894 +};
  3.1895 +
  3.1896 +#endif /* !(_T3_H) */
     4.1 --- a/xen-2.4.16/include/asm-i386/pci.h	Sat Feb 08 19:32:15 2003 +0000
     4.2 +++ b/xen-2.4.16/include/asm-i386/pci.h	Sun Feb 09 00:29:16 2003 +0000
     4.3 @@ -114,6 +114,14 @@ static inline void pci_unmap_page(struct
     4.4  	/* Nothing to do */
     4.5  }
     4.6  
     4.7 +/* pci_unmap_{page,single} is a nop so... */
     4.8 +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
     4.9 +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
    4.10 +#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
    4.11 +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
    4.12 +#define pci_unmap_len(PTR, LEN_NAME)            (0)
    4.13 +#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
    4.14 +
    4.15  /* Map a set of buffers described by scatterlist in streaming
    4.16   * mode for DMA.  This is the scather-gather version of the
    4.17   * above pci_map_single interface.  Here the scatter gather list
     5.1 --- a/xen-2.4.16/include/xeno/netdevice.h	Sat Feb 08 19:32:15 2003 +0000
     5.2 +++ b/xen-2.4.16/include/xeno/netdevice.h	Sun Feb 09 00:29:16 2003 +0000
     5.3 @@ -311,13 +311,13 @@ struct net_device
     5.4  	void                    *dn_ptr;        /* DECnet specific data */
     5.5  	void                    *ip6_ptr;       /* IPv6 specific data */
     5.6  	void			*ec_ptr;	/* Econet specific data	*/
     5.7 -
     5.8 +#if 0
     5.9  						/* IAP: add fields but
    5.10  						nothing else */		
    5.11  	struct list_head        poll_list;      /* Link to poll list    */
    5.12  	int                     quota;
    5.13  	int                     weight;
    5.14 -
    5.15 +#endif
    5.16  	struct Qdisc		*qdisc;
    5.17  	struct Qdisc		*qdisc_sleeping;
    5.18  	struct Qdisc		*qdisc_list;
    5.19 @@ -361,7 +361,9 @@ struct net_device
    5.20  	int			(*stop)(struct net_device *dev);
    5.21  	int			(*hard_start_xmit) (struct sk_buff *skb,
    5.22  						    struct net_device *dev);
    5.23 +#if 0
    5.24  	int                     (*poll) (struct net_device *dev, int *quota); /* XXX IAP */
    5.25 +#endif
    5.26  	int			(*hard_header) (struct sk_buff *skb,
    5.27  						struct net_device *dev,
    5.28  						unsigned short type,
     6.1 --- a/xen-2.4.16/include/xeno/pci_ids.h	Sat Feb 08 19:32:15 2003 +0000
     6.2 +++ b/xen-2.4.16/include/xeno/pci_ids.h	Sun Feb 09 00:29:16 2003 +0000
     6.3 @@ -475,19 +475,28 @@
     6.4  #define PCI_DEVICE_ID_SI_635		0x0635
     6.5  #define PCI_DEVICE_ID_SI_640		0x0640
     6.6  #define PCI_DEVICE_ID_SI_645		0x0645
     6.7 +#define PCI_DEVICE_ID_SI_646		0x0646
     6.8 +#define PCI_DEVICE_ID_SI_648		0x0648
     6.9  #define PCI_DEVICE_ID_SI_650		0x0650
    6.10 +#define PCI_DEVICE_ID_SI_651		0x0651
    6.11 +#define PCI_DEVICE_ID_SI_652		0x0652
    6.12  #define PCI_DEVICE_ID_SI_730		0x0730
    6.13  #define PCI_DEVICE_ID_SI_630_VGA	0x6300
    6.14  #define PCI_DEVICE_ID_SI_730_VGA	0x7300
    6.15  #define PCI_DEVICE_ID_SI_735		0x0735
    6.16  #define PCI_DEVICE_ID_SI_740		0x0740
    6.17  #define PCI_DEVICE_ID_SI_745		0x0745
    6.18 +#define PCI_DEVICE_ID_SI_746		0x0746
    6.19 +#define PCI_DEVICE_ID_SI_748		0x0748
    6.20  #define PCI_DEVICE_ID_SI_750		0x0750
    6.21 +#define PCI_DEVICE_ID_SI_751		0x0751
    6.22 +#define PCI_DEVICE_ID_SI_752		0x0752
    6.23  #define PCI_DEVICE_ID_SI_900		0x0900
    6.24  #define PCI_DEVICE_ID_SI_5107		0x5107
    6.25  #define PCI_DEVICE_ID_SI_5300		0x5300
    6.26  #define PCI_DEVICE_ID_SI_5511		0x5511
    6.27  #define PCI_DEVICE_ID_SI_5513		0x5513
    6.28 +#define PCI_DEVICE_ID_SI_5518		0x5518
    6.29  #define PCI_DEVICE_ID_SI_5571		0x5571
    6.30  #define PCI_DEVICE_ID_SI_5591		0x5591
    6.31  #define PCI_DEVICE_ID_SI_5597		0x5597
    6.32 @@ -608,7 +617,8 @@
    6.33  #define PCI_DEVICE_ID_PROMISE_20262	0x4d38
    6.34  #define PCI_DEVICE_ID_PROMISE_20263	0x0D38
    6.35  #define PCI_DEVICE_ID_PROMISE_20268	0x4d68
    6.36 -#define PCI_DEVICE_ID_PROMISE_20270	0x6268
    6.37 +#define PCI_DEVICE_ID_PROMISE_20268R	0x6268
    6.38 +#define PCI_DEVICE_ID_PROMISE_20270     0x6268  /* XXX IAP */
    6.39  #define PCI_DEVICE_ID_PROMISE_20269	0x4d69
    6.40  #define PCI_DEVICE_ID_PROMISE_20271	0x6269
    6.41  #define PCI_DEVICE_ID_PROMISE_20275	0x1275
    6.42 @@ -978,6 +988,7 @@
    6.43  #define PCI_DEVICE_ID_VIA_8233C_0	0x3109
    6.44  #define PCI_DEVICE_ID_VIA_8361		0x3112
    6.45  #define PCI_DEVICE_ID_VIA_8233A		0x3147
    6.46 +#define PCI_DEVICE_ID_VIA_8235		0x3177
    6.47  #define PCI_DEVICE_ID_VIA_86C100A	0x6100
    6.48  #define PCI_DEVICE_ID_VIA_8231		0x8231
    6.49  #define PCI_DEVICE_ID_VIA_8231_4	0x8235
    6.50 @@ -1115,6 +1126,7 @@
    6.51  #define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211
    6.52  #define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212
    6.53  #define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
    6.54 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
    6.55  #define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220
    6.56  #define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB
    6.57  #define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221
    6.58 @@ -1531,6 +1543,7 @@
    6.59  #define PCI_DEVICE_ID_TIGON3_5701	0x1645
    6.60  #define PCI_DEVICE_ID_TIGON3_5702	0x1646
    6.61  #define PCI_DEVICE_ID_TIGON3_5703	0x1647
    6.62 +#define PCI_DEVICE_ID_TIGON3_5704	0x1648
    6.63  #define PCI_DEVICE_ID_TIGON3_5702FE	0x164d
    6.64  #define PCI_DEVICE_ID_TIGON3_5702X	0x16a6
    6.65  #define PCI_DEVICE_ID_TIGON3_5703X	0x16a7
    6.66 @@ -1619,6 +1632,7 @@
    6.67  #define PCI_DEVICE_ID_INTEL_82430	0x0486
    6.68  #define PCI_DEVICE_ID_INTEL_82434	0x04a3
    6.69  #define PCI_DEVICE_ID_INTEL_I960	0x0960
    6.70 +#define PCI_DEVICE_ID_INTEL_I960RM	0x0962
    6.71  #define PCI_DEVICE_ID_INTEL_82562ET	0x1031
    6.72  #define PCI_DEVICE_ID_INTEL_82559ER	0x1209
    6.73  #define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
    6.74 @@ -1675,9 +1689,9 @@
    6.75  #define PCI_DEVICE_ID_INTEL_82801E_2	0x2452
    6.76  #define PCI_DEVICE_ID_INTEL_82801E_3	0x2453
    6.77  #define PCI_DEVICE_ID_INTEL_82801E_9	0x2459
    6.78 -#define PCI_DEVICE_ID_INTEL_82801E_11	0x245b
    6.79 -#define PCI_DEVICE_ID_INTEL_82801E_13	0x245d
    6.80 -#define PCI_DEVICE_ID_INTEL_82801E_14	0x245e
    6.81 +#define PCI_DEVICE_ID_INTEL_82801E_11	0x245B
    6.82 +#define PCI_DEVICE_ID_INTEL_82801E_14	0x245D
    6.83 +#define PCI_DEVICE_ID_INTEL_82801E_15	0x245E
    6.84  #define PCI_DEVICE_ID_INTEL_82801CA_0	0x2480
    6.85  #define PCI_DEVICE_ID_INTEL_82801CA_2	0x2482
    6.86  #define PCI_DEVICE_ID_INTEL_82801CA_3	0x2483