1.1 --- a/xen/arch/ia64/Rules.mk	Wed Apr 19 10:26:50 2006 -0600
     1.2 +++ b/xen/arch/ia64/Rules.mk	Wed Apr 19 10:32:36 2006 -0600
     1.3 @@ -28,7 +28,7 @@ CFLAGS  += -I$(BASEDIR)/include/asm-ia64
     1.4             -I$(BASEDIR)/arch/ia64/linux -I$(BASEDIR)/arch/ia64/linux-xen
     1.5  #CFLAGS  += -Wno-pointer-arith -Wredundant-decls
     1.6  CFLAGS  += -DIA64 -DXEN -DLINUX_2_6 -DV_IOSAPIC_READY
     1.7 -CFLAGS	+= -ffixed-r13 -mfixed-range=f12-f15,f32-f127
     1.8 +CFLAGS	+= -ffixed-r13 -mfixed-range=f2-f5,f12-f127
     1.9  CFLAGS	+= -g
    1.10  #CFLAGS  += -DVTI_DEBUG
    1.11  ifeq ($(VALIDATE_VT),y)

     2.1 --- a/xen/arch/ia64/linux-xen/unaligned.c	Wed Apr 19 10:26:50 2006 -0600
     2.2 +++ b/xen/arch/ia64/linux-xen/unaligned.c	Wed Apr 19 10:32:36 2006 -0600
     2.3 @@ -750,6 +750,154 @@ getfpreg (unsigned long regnum, struct i
     2.4  		}
     2.5  	}
     2.6  }
     2.7 +#else
     2.8 +void
     2.9 +getfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
    2.10 +{
    2.11 +#define CASE_FIXED_FP(reg)			\
    2.12 +	case reg:				\
    2.13 +		ia64_stf_spill(fpval,reg);	\
    2.14 +		break
    2.15 +#define CASE_SAVED_FP(reg)					\
    2.16 +	case reg:						\
    2.17 +		fpval->u.bits[0] = regs->f##reg.u.bits[0];	\
    2.18 +		fpval->u.bits[1] = regs->f##reg.u.bits[1];	\
    2.19 +		break
    2.20 +	switch(regnum) {
    2.21 +		CASE_FIXED_FP(0);
    2.22 +		CASE_FIXED_FP(1);
    2.23 +		CASE_FIXED_FP(2);
    2.24 +		CASE_FIXED_FP(3);
    2.25 +		CASE_FIXED_FP(4);
    2.26 +		CASE_FIXED_FP(5);
    2.27 +
    2.28 +		CASE_SAVED_FP(6);
    2.29 +		CASE_SAVED_FP(7);
    2.30 +		CASE_SAVED_FP(8);
    2.31 +		CASE_SAVED_FP(9);
    2.32 +		CASE_SAVED_FP(10);
    2.33 +		CASE_SAVED_FP(11);
    2.34 +
    2.35 +		CASE_FIXED_FP(12);
    2.36 +		CASE_FIXED_FP(13);
    2.37 +		CASE_FIXED_FP(14);
    2.38 +		CASE_FIXED_FP(15);
    2.39 +		CASE_FIXED_FP(16);
    2.40 +		CASE_FIXED_FP(17);
    2.41 +		CASE_FIXED_FP(18);
    2.42 +		CASE_FIXED_FP(19);
    2.43 +		CASE_FIXED_FP(20);
    2.44 +		CASE_FIXED_FP(21);
    2.45 +		CASE_FIXED_FP(22);
    2.46 +		CASE_FIXED_FP(23);
    2.47 +		CASE_FIXED_FP(24);
    2.48 +		CASE_FIXED_FP(25);
    2.49 +		CASE_FIXED_FP(26);
    2.50 +		CASE_FIXED_FP(27);
    2.51 +		CASE_FIXED_FP(28);
    2.52 +		CASE_FIXED_FP(29);
    2.53 +		CASE_FIXED_FP(30);
    2.54 +		CASE_FIXED_FP(31);
    2.55 +		CASE_FIXED_FP(32);
    2.56 +		CASE_FIXED_FP(33);
    2.57 +		CASE_FIXED_FP(34);
    2.58 +		CASE_FIXED_FP(35);
    2.59 +		CASE_FIXED_FP(36);
    2.60 +		CASE_FIXED_FP(37);
    2.61 +		CASE_FIXED_FP(38);
    2.62 +		CASE_FIXED_FP(39);
    2.63 +		CASE_FIXED_FP(40);
    2.64 +		CASE_FIXED_FP(41);
    2.65 +		CASE_FIXED_FP(42);
    2.66 +		CASE_FIXED_FP(43);
    2.67 +		CASE_FIXED_FP(44);
    2.68 +		CASE_FIXED_FP(45);
    2.69 +		CASE_FIXED_FP(46);
    2.70 +		CASE_FIXED_FP(47);
    2.71 +		CASE_FIXED_FP(48);
    2.72 +		CASE_FIXED_FP(49);
    2.73 +		CASE_FIXED_FP(50);
    2.74 +		CASE_FIXED_FP(51);
    2.75 +		CASE_FIXED_FP(52);
    2.76 +		CASE_FIXED_FP(53);
    2.77 +		CASE_FIXED_FP(54);
    2.78 +		CASE_FIXED_FP(55);
    2.79 +		CASE_FIXED_FP(56);
    2.80 +		CASE_FIXED_FP(57);
    2.81 +		CASE_FIXED_FP(58);
    2.82 +		CASE_FIXED_FP(59);
    2.83 +		CASE_FIXED_FP(60);
    2.84 +		CASE_FIXED_FP(61);
    2.85 +		CASE_FIXED_FP(62);
    2.86 +		CASE_FIXED_FP(63);
    2.87 +		CASE_FIXED_FP(64);
    2.88 +		CASE_FIXED_FP(65);
    2.89 +		CASE_FIXED_FP(66);
    2.90 +		CASE_FIXED_FP(67);
    2.91 +		CASE_FIXED_FP(68);
    2.92 +		CASE_FIXED_FP(69);
    2.93 +		CASE_FIXED_FP(70);
    2.94 +		CASE_FIXED_FP(71);
    2.95 +		CASE_FIXED_FP(72);
    2.96 +		CASE_FIXED_FP(73);
    2.97 +		CASE_FIXED_FP(74);
    2.98 +		CASE_FIXED_FP(75);
    2.99 +		CASE_FIXED_FP(76);
   2.100 +		CASE_FIXED_FP(77);
   2.101 +		CASE_FIXED_FP(78);
   2.102 +		CASE_FIXED_FP(79);
   2.103 +		CASE_FIXED_FP(80);
   2.104 +		CASE_FIXED_FP(81);
   2.105 +		CASE_FIXED_FP(82);
   2.106 +		CASE_FIXED_FP(83);
   2.107 +		CASE_FIXED_FP(84);
   2.108 +		CASE_FIXED_FP(85);
   2.109 +		CASE_FIXED_FP(86);
   2.110 +		CASE_FIXED_FP(87);
   2.111 +		CASE_FIXED_FP(88);
   2.112 +		CASE_FIXED_FP(89);
   2.113 +		CASE_FIXED_FP(90);
   2.114 +		CASE_FIXED_FP(91);
   2.115 +		CASE_FIXED_FP(92);
   2.116 +		CASE_FIXED_FP(93);
   2.117 +		CASE_FIXED_FP(94);
   2.118 +		CASE_FIXED_FP(95);
   2.119 +		CASE_FIXED_FP(96);
   2.120 +		CASE_FIXED_FP(97);
   2.121 +		CASE_FIXED_FP(98);
   2.122 +		CASE_FIXED_FP(99);
   2.123 +		CASE_FIXED_FP(100);
   2.124 +		CASE_FIXED_FP(101);
   2.125 +		CASE_FIXED_FP(102);
   2.126 +		CASE_FIXED_FP(103);
   2.127 +		CASE_FIXED_FP(104);
   2.128 +		CASE_FIXED_FP(105);
   2.129 +		CASE_FIXED_FP(106);
   2.130 +		CASE_FIXED_FP(107);
   2.131 +		CASE_FIXED_FP(108);
   2.132 +		CASE_FIXED_FP(109);
   2.133 +		CASE_FIXED_FP(110);
   2.134 +		CASE_FIXED_FP(111);
   2.135 +		CASE_FIXED_FP(112);
   2.136 +		CASE_FIXED_FP(113);
   2.137 +		CASE_FIXED_FP(114);
   2.138 +		CASE_FIXED_FP(115);
   2.139 +		CASE_FIXED_FP(116);
   2.140 +		CASE_FIXED_FP(117);
   2.141 +		CASE_FIXED_FP(118);
   2.142 +		CASE_FIXED_FP(119);
   2.143 +		CASE_FIXED_FP(120);
   2.144 +		CASE_FIXED_FP(121);
   2.145 +		CASE_FIXED_FP(122);
   2.146 +		CASE_FIXED_FP(123);
   2.147 +		CASE_FIXED_FP(124);
   2.148 +		CASE_FIXED_FP(125);
   2.149 +		CASE_FIXED_FP(126);
   2.150 +		CASE_FIXED_FP(127);
   2.151 +	}
   2.152 +#undef CASE_FIXED_FP
   2.153 +#undef CASE_SAVED_FP
   2.154 +}
   2.155  #endif /* XEN */
   2.156  
   2.157  

     3.1 --- a/xen/arch/ia64/vmx/mmio.c	Wed Apr 19 10:26:50 2006 -0600
     3.2 +++ b/xen/arch/ia64/vmx/mmio.c	Wed Apr 19 10:32:36 2006 -0600
     3.3 @@ -57,20 +57,21 @@ static void pib_write(VCPU *vcpu, void *
     3.4  {
     3.5      switch (pib_off) {
     3.6      case PIB_OFST_INTA:
     3.7 -        panic("Undefined write on PIB INTA\n");
     3.8 +        panic_domain(NULL,"Undefined write on PIB INTA\n");
     3.9          break;
    3.10      case PIB_OFST_XTP:
    3.11          if ( s == 1 && ma == 4 /* UC */) {
    3.12              vmx_vcpu_get_plat(vcpu)->xtp = *(uint8_t *)src;
    3.13          }
    3.14          else {
    3.15 -            panic("Undefined write on PIB XTP\n");
    3.16 +            panic_domain(NULL,"Undefined write on PIB XTP\n");
    3.17          }
    3.18          break;
    3.19      default:
    3.20          if ( PIB_LOW_HALF(pib_off) ) {   // lower half
    3.21              if ( s != 8 || ma != 0x4 /* UC */ ) {
    3.22 -                panic("Undefined IPI-LHF write with s %ld, ma %d!\n", s, ma);
    3.23 +                panic_domain
    3.24 +		  (NULL,"Undefined IPI-LHF write with s %ld, ma %d!\n", s, ma);
    3.25              }
    3.26              else {
    3.27                  write_ipi(vcpu, pib_off, *(uint64_t *)src);
    3.28 @@ -79,7 +80,7 @@ static void pib_write(VCPU *vcpu, void *
    3.29          }
    3.30          else {      // upper half
    3.31              printf("IPI-UHF write %lx\n",pib_off);
    3.32 -            panic("Not support yet for SM-VP\n");
    3.33 +            panic_domain(NULL,"Not support yet for SM-VP\n");
    3.34          }
    3.35          break;
    3.36      }
    3.37 @@ -94,7 +95,7 @@ static void pib_read(VCPU *vcpu, uint64_
    3.38              // TODO: INTA read from IOSAPIC
    3.39          }
    3.40          else {
    3.41 -            panic("Undefined read on PIB INTA\n");
    3.42 +            panic_domain(NULL,"Undefined read on PIB INTA\n");
    3.43          }
    3.44          break;
    3.45      case PIB_OFST_XTP:
    3.46 @@ -102,13 +103,13 @@ static void pib_read(VCPU *vcpu, uint64_
    3.47              *((uint8_t*)dest) = vmx_vcpu_get_plat(vcpu)->xtp;
    3.48          }
    3.49          else {
    3.50 -            panic("Undefined read on PIB XTP\n");
    3.51 +            panic_domain(NULL,"Undefined read on PIB XTP\n");
    3.52          }
    3.53          break;
    3.54      default:
    3.55          if ( PIB_LOW_HALF(pib_off) ) {   // lower half
    3.56              if ( s != 8 || ma != 4 ) {
    3.57 -                panic("Undefined IPI-LHF read!\n");
    3.58 +                panic_domain(NULL,"Undefined IPI-LHF read!\n");
    3.59              }
    3.60              else {
    3.61  #ifdef  IPI_DEBUG
    3.62 @@ -119,7 +120,7 @@ static void pib_read(VCPU *vcpu, uint64_
    3.63          }
    3.64          else {      // upper half
    3.65              if ( s != 1 || ma != 4 ) {
    3.66 -                panic("Undefined PIB-UHF read!\n");
    3.67 +                panic_domain(NULL,"Undefined PIB-UHF read!\n");
    3.68              }
    3.69              else {
    3.70  #ifdef  IPI_DEBUG
    3.71 @@ -140,7 +141,7 @@ static void low_mmio_access(VCPU *vcpu, 
    3.72  
    3.73      vio = get_vio(v->domain, v->vcpu_id);
    3.74      if (vio == 0) {
    3.75 -        panic("bad shared page: %lx", (unsigned long)vio);
    3.76 +        panic_domain(NULL,"bad shared page: %lx", (unsigned long)vio);
    3.77      }
    3.78      p = &vio->vp_ioreq;
    3.79      p->addr = pa;
    3.80 @@ -172,7 +173,7 @@ static void legacy_io_access(VCPU *vcpu,
    3.81  
    3.82      vio = get_vio(v->domain, v->vcpu_id);
    3.83      if (vio == 0) {
    3.84 -        panic("bad shared page\n");
    3.85 +        panic_domain(NULL,"bad shared page\n");
    3.86      }
    3.87      p = &vio->vp_ioreq;
    3.88      p->addr = TO_LEGACY_IO(pa&0x3ffffffUL);
    3.89 @@ -237,7 +238,7 @@ static void mmio_access(VCPU *vcpu, u64 
    3.90          legacy_io_access(vcpu, src_pa, dest, s, dir);
    3.91          break;
    3.92      default:
    3.93 -        panic("Bad I/O access\n");
    3.94 +        panic_domain(NULL,"Bad I/O access\n");
    3.95          break;
    3.96      }
    3.97      return;
    3.98 @@ -285,7 +286,7 @@ memread_v(VCPU *vcpu, thash_data_t *vtlb
    3.99      uint64_t pa;
   3.100  
   3.101      if (!vtlb->nomap)
   3.102 -        panic("Normal memory write shouldn't go to this point!");
   3.103 +        panic_domain(NULL,"Normal memory write shouldn't go to this point!");
   3.104      pa = PPN_2_PA(vtlb->ppn);
   3.105      pa += POFFSET((u64)src, vtlb->ps);
   3.106  
   3.107 @@ -329,14 +330,14 @@ static void deliver_ipi (VCPU *vcpu, uin
   3.108          break;
   3.109      case 2:     // PMI
   3.110          // TODO -- inject guest PMI
   3.111 -        panic ("Inject guest PMI!\n");
   3.112 +        panic_domain (NULL, "Inject guest PMI!\n");
   3.113          break;
   3.114      case 4:     // NMI
   3.115          vmx_vcpu_pend_interrupt (vcpu, 2);
   3.116          break;
   3.117      case 5:     // INIT
   3.118          // TODO -- inject guest INIT
   3.119 -        panic ("Inject guest INIT!\n");
   3.120 +        panic_domain (NULL, "Inject guest INIT!\n");
   3.121          break;
   3.122      case 7:     // ExtINT
   3.123          vmx_vcpu_pend_interrupt (vcpu, 0);
   3.124 @@ -345,7 +346,7 @@ static void deliver_ipi (VCPU *vcpu, uin
   3.125      case 3:
   3.126      case 6:
   3.127      default:
   3.128 -        panic ("Deliver reserved IPI!\n");
   3.129 +        panic_domain (NULL, "Deliver reserved IPI!\n");
   3.130          break;
   3.131      }
   3.132  }
   3.133 @@ -379,7 +380,7 @@ static int write_ipi (VCPU *vcpu, uint64
   3.134   
   3.135      target_cpu = lid_2_vcpu(vcpu->domain, 
   3.136      				((ipi_a_t)addr).id, ((ipi_a_t)addr).eid);
   3.137 -    if ( target_cpu == NULL ) panic("Unknown IPI cpu\n");
   3.138 +    if ( target_cpu == NULL ) panic_domain (NULL,"Unknown IPI cpu\n");
   3.139      if ( target_cpu == vcpu ) {
   3.140      	// IPI to self
   3.141          deliver_ipi (vcpu, ((ipi_d_t)value).dm, 
   3.142 @@ -388,7 +389,7 @@ static int write_ipi (VCPU *vcpu, uint64
   3.143      }
   3.144      else {
   3.145      	// TODO: send Host IPI to inject guest SMP IPI interruption
   3.146 -        panic ("No SM-VP supported!\n");
   3.147 +        panic_domain (NULL, "No SM-VP supported!\n");
   3.148          return 0;
   3.149      }
   3.150  }
   3.151 @@ -473,15 +474,65 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
   3.152  
   3.153          }
   3.154      }
   3.155 -    // Floating-point Load/Store
   3.156 +    // Floating-point spill + Imm update
   3.157 +    else if(inst.M10.major==7&&inst.M10.x6==0x3B){
   3.158 +        struct ia64_fpreg v;
   3.159 +	inst_type=SL_FLOATING;
   3.160 +	dir=IOREQ_WRITE;
   3.161 +	vcpu_get_fpreg(vcpu,inst.M10.f2,&v);
   3.162 +	vcpu_get_gr_nat(vcpu,inst.M10.r3,&temp);
   3.163 +	post_update = (inst.M10.i<<7)+inst.M10.imm7;
   3.164 +	if(inst.M10.s)
   3.165 +            temp -= post_update;
   3.166 +	else
   3.167 +            temp += post_update;
   3.168 +	vcpu_set_gr(vcpu,inst.M10.r3,temp,0);
   3.169 +
   3.170 +	/* Write high word.
   3.171 +	   FIXME: this is a kludge!  */
   3.172 +	v.u.bits[1] &= 0x3ffff;
   3.173 +	mmio_access(vcpu, padr + 8, &v.u.bits[1], 8, ma, IOREQ_WRITE);
   3.174 +	data = v.u.bits[0];
   3.175 +	size = 3;
   3.176 +    }
   3.177 +    // Floating-point stf8 + Imm update
   3.178 +    else if(inst.M10.major==7&&inst.M10.x6==0x31){
   3.179 +        struct ia64_fpreg v;
   3.180 +	inst_type=SL_FLOATING;
   3.181 +	dir=IOREQ_WRITE;
   3.182 +	size=3;
   3.183 +	vcpu_get_fpreg(vcpu,inst.M10.f2,&v);
   3.184 +	data = v.u.bits[0]; /* Significand.  */
   3.185 +	vcpu_get_gr_nat(vcpu,inst.M10.r3,&temp);
   3.186 +	post_update = (inst.M10.i<<7)+inst.M10.imm7;
   3.187 +	if(inst.M10.s)
   3.188 +            temp -= post_update;
   3.189 +	else
   3.190 +            temp += post_update;
   3.191 +	vcpu_set_gr(vcpu,inst.M10.r3,temp,0);
   3.192 +    }
   3.193  //    else if(inst.M6.major==6&&inst.M6.m==0&&inst.M6.x==0&&inst.M6.x6==3){
   3.194  //        inst_type=SL_FLOATING;  //fp
   3.195  //        dir=IOREQ_READ;
   3.196  //        size=3;     //ldfd
   3.197  //    }
   3.198 +    //  lfetch - do not perform accesses.
   3.199 +    else if(inst.M15.major==7&&inst.M15.x6>=0x2c&&inst.M15.x6<=0x2f){
   3.200 +	vcpu_get_gr_nat(vcpu,inst.M15.r3,&temp);
   3.201 +	post_update = (inst.M15.i<<7)+inst.M15.imm7;
   3.202 +	if(inst.M15.s)
   3.203 +            temp -= post_update;
   3.204 +	else
   3.205 +            temp += post_update;
   3.206 +	vcpu_set_gr(vcpu,inst.M15.r3,temp,0);
   3.207 +
   3.208 +	vmx_vcpu_increment_iip(vcpu);
   3.209 +	return;
   3.210 +    }
   3.211      else{
   3.212 -        printf("This memory access instruction can't be emulated two: %lx\n ",inst.inst);
   3.213 -        while(1);
   3.214 +        panic_domain
   3.215 +	  (NULL,"This memory access instr can't be emulated: %lx pc=%lx\n ",
   3.216 +	   inst.inst, regs->cr_iip);
   3.217      }
   3.218  
   3.219      size = 1 << size;
   3.220 @@ -499,7 +550,7 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
   3.221          if(inst_type==SL_INTEGER){       //gp
   3.222              vcpu_set_gr(vcpu,inst.M1.r1,data,0);
   3.223          }else{
   3.224 -            panic("Don't support ldfd now !");
   3.225 +            panic_domain(NULL, "Don't support ldfd now !");
   3.226  /*            switch(inst.M6.f1){
   3.227  
   3.228              case 6:

     4.1 --- a/xen/arch/ia64/xen/vcpu.c	Wed Apr 19 10:26:50 2006 -0600
     4.2 +++ b/xen/arch/ia64/xen/vcpu.c	Wed Apr 19 10:32:36 2006 -0600
     4.3 @@ -22,6 +22,8 @@
     4.4  /* FIXME: where these declarations should be there ? */
     4.5  extern void getreg(unsigned long regnum, unsigned long *val, int *nat, struct pt_regs *regs);
     4.6  extern void setreg(unsigned long regnum, unsigned long val, int nat, struct pt_regs *regs);
     4.7 +extern void getfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs);
     4.8 +
     4.9  extern void panic_domain(struct pt_regs *, const char *, ...);
    4.10  extern unsigned long translate_domain_pte(UINT64,UINT64,UINT64);
    4.11  extern unsigned long translate_domain_mpaddr(unsigned long);
    4.12 @@ -104,6 +106,15 @@ vcpu_set_gr(VCPU *vcpu, unsigned long re
    4.13  	setreg(reg,value,nat,regs);	// FIXME: handle NATs later
    4.14  	return IA64_NO_FAULT;
    4.15  }
    4.16 +
    4.17 +IA64FAULT
    4.18 +vcpu_get_fpreg(VCPU *vcpu, unsigned long reg, struct ia64_fpreg *val)
    4.19 +{
    4.20 +	REGS *regs = vcpu_regs(vcpu);
    4.21 +	getfpreg(reg,val,regs);	// FIXME: handle NATs later
    4.22 +	return 0;
    4.23 +}
    4.24 +
    4.25  #else
    4.26  // returns:
    4.27  //   IA64_ILLOP_FAULT if the register would cause an Illegal Operation fault

     5.1 --- a/xen/include/asm-ia64/privop.h	Wed Apr 19 10:26:50 2006 -0600
     5.2 +++ b/xen/include/asm-ia64/privop.h	Wed Apr 19 10:32:36 2006 -0600
     5.3 @@ -170,6 +170,21 @@ typedef union U_INST64_M6 {
     5.4      struct { unsigned long qp:6, f1:7, un7:7, r3:7, x:1, hint:2, x6:6, m:1, major:4; };
     5.5  } INST64_M6;
     5.6  
     5.7 +typedef union U_INST64_M9 {
     5.8 +    IA64_INST inst;
     5.9 +    struct { unsigned long qp:6, :7, f2:7, r3:7, x:1, hint:2, x6:6, m:1, major:4; };
    5.10 +} INST64_M9;
    5.11 +
    5.12 +typedef union U_INST64_M10 {
    5.13 +    IA64_INST inst;
    5.14 +    struct { unsigned long qp:6, imm7:7, f2:7, r3:7, i:1, hint:2, x6:6, s:1, major:4; };
    5.15 +} INST64_M10;
    5.16 +
    5.17 +typedef union U_INST64_M15 {
    5.18 +    IA64_INST inst;
    5.19 +    struct { unsigned long qp:6, :7, imm7:7, r3:7, i:1, hint:2, x6:6, s:1, major:4; };
    5.20 +} INST64_M15;
    5.21 +
    5.22  typedef union U_INST64 {
    5.23      IA64_INST inst;
    5.24      struct { unsigned long :37, major:4; } generic;
    5.25 @@ -187,6 +202,9 @@ typedef union U_INST64 {
    5.26      INST64_M4  M4;	// st integer
    5.27      INST64_M5  M5;
    5.28      INST64_M6  M6;	// ldfd floating pointer
    5.29 +    INST64_M9  M9;	// stfd floating pointer
    5.30 +    INST64_M10 M10;	// stfd floating pointer
    5.31 +    INST64_M15 M15;	// lfetch + imm update
    5.32      INST64_M28 M28;	// purge translation cache entry
    5.33      INST64_M29 M29;	// mov register to ar (M unit)
    5.34      INST64_M30 M30;	// mov immediate to ar (M unit)

     6.1 --- a/xen/include/asm-ia64/vcpu.h	Wed Apr 19 10:26:50 2006 -0600
     6.2 +++ b/xen/include/asm-ia64/vcpu.h	Wed Apr 19 10:32:36 2006 -0600
     6.3 @@ -40,6 +40,8 @@ struct privop_addr_count {
     6.4  extern UINT64 vcpu_get_gr(VCPU *vcpu, unsigned long reg);
     6.5  extern IA64FAULT vcpu_get_gr_nat(VCPU *vcpu, unsigned long reg, UINT64 *val);
     6.6  extern IA64FAULT vcpu_set_gr(VCPU *vcpu, unsigned long reg, UINT64 value, int nat);
     6.7 +extern IA64FAULT vcpu_get_fpreg(VCPU *vcpu, unsigned long reg, struct ia64_fpreg *val);
     6.8 +
     6.9  /* application registers */
    6.10  extern void vcpu_load_kernel_regs(VCPU *vcpu);
    6.11  extern IA64FAULT vcpu_set_ar(VCPU *vcpu, UINT64 reg, UINT64 val);