ia64/xen-unstable

changeset 4791:c2364cd47a54

bitkeeper revision 1.1389.5.29 (427c91f4-NwTlq2np5GYzwS7yWmzGA)

Move serial definitions into serial.h where they can be picked up
by arch-specific code.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Sat May 07 10:01:24 2005 +0000 (2005-05-07)
parents c08ca4f9f375
children 3a473cbbb826
files xen/drivers/char/serial.c xen/include/asm-ia64/serial.h xen/include/xen/serial.h
line diff
     1.1 --- a/xen/drivers/char/serial.c	Sat May 07 09:47:18 2005 +0000
     1.2 +++ b/xen/drivers/char/serial.c	Sat May 07 10:01:24 2005 +0000
     1.3 @@ -26,71 +26,6 @@ static char opt_com1[30] = OPT_COM1_STR,
     1.4  string_param("com1", opt_com1);
     1.5  string_param("com2", opt_com2);
     1.6  
     1.7 -/* Register offsets */
     1.8 -#define RBR             0x00    /* receive buffer       */
     1.9 -#define THR             0x00    /* transmit holding     */
    1.10 -#define IER             0x01    /* interrupt enable     */
    1.11 -#define IIR             0x02    /* interrupt identity   */
    1.12 -#define FCR             0x02    /* FIFO control         */
    1.13 -#define LCR             0x03    /* line control         */
    1.14 -#define MCR             0x04    /* Modem control        */
    1.15 -#define LSR             0x05    /* line status          */
    1.16 -#define MSR             0x06    /* Modem status         */
    1.17 -#define DLL             0x00    /* divisor latch (ls) (DLAB=1) */
    1.18 -#define DLM             0x01    /* divisor latch (ms) (DLAB=1) */
    1.19 -
    1.20 -/* Interrupt Enable Register */
    1.21 -#define IER_ERDAI       0x01    /* rx data recv'd       */
    1.22 -#define IER_ETHREI      0x02    /* tx reg. empty        */
    1.23 -#define IER_ELSI        0x04    /* rx line status       */
    1.24 -#define IER_EMSI        0x08    /* MODEM status         */
    1.25 -
    1.26 -/* FIFO control register */
    1.27 -#define FCR_ENABLE      0x01    /* enable FIFO          */
    1.28 -#define FCR_CLRX        0x02    /* clear Rx FIFO        */
    1.29 -#define FCR_CLTX        0x04    /* clear Tx FIFO        */
    1.30 -#define FCR_DMA         0x10    /* enter DMA mode       */
    1.31 -#define FCR_TRG1        0x00    /* Rx FIFO trig lev 1   */
    1.32 -#define FCR_TRG4        0x40    /* Rx FIFO trig lev 4   */
    1.33 -#define FCR_TRG8        0x80    /* Rx FIFO trig lev 8   */
    1.34 -#define FCR_TRG14       0xc0    /* Rx FIFO trig lev 14  */
    1.35 -
    1.36 -/* Line control register */
    1.37 -#define LCR_DLAB        0x80    /* Divisor Latch Access */
    1.38 -
    1.39 -/* Modem Control Register */
    1.40 -#define MCR_DTR         0x01    /* Data Terminal Ready  */
    1.41 -#define MCR_RTS         0x02    /* Request to Send      */
    1.42 -#define MCR_OUT2        0x08    /* OUT2: interrupt mask */
    1.43 -
    1.44 -/* Line Status Register */
    1.45 -#define LSR_DR          0x01    /* Data ready           */
    1.46 -#define LSR_OE          0x02    /* Overrun              */
    1.47 -#define LSR_PE          0x04    /* Parity error         */
    1.48 -#define LSR_FE          0x08    /* Framing error        */
    1.49 -#define LSR_BI          0x10    /* Break                */
    1.50 -#define LSR_THRE        0x20    /* Xmit hold reg empty  */
    1.51 -#define LSR_TEMT        0x40    /* Xmitter empty        */
    1.52 -#define LSR_ERR         0x80    /* Error                */
    1.53 -
    1.54 -/* These parity settings can be ORed directly into the LCR. */
    1.55 -#define PARITY_NONE     (0<<3)
    1.56 -#define PARITY_ODD      (1<<3)
    1.57 -#define PARITY_EVEN     (3<<3)
    1.58 -#define PARITY_MARK     (5<<3)
    1.59 -#define PARITY_SPACE    (7<<3)
    1.60 -
    1.61 -#define RXBUFSZ 32
    1.62 -#define MASK_RXBUF_IDX(_i) ((_i)&(RXBUFSZ-1))
    1.63 -struct uart {
    1.64 -    int              baud, data_bits, parity, stop_bits, io_base, irq;
    1.65 -    serial_rx_fn     rx_lo, rx_hi, rx;
    1.66 -    spinlock_t       lock;
    1.67 -    unsigned char    rxbuf[RXBUFSZ];
    1.68 -    unsigned int     rxbufp, rxbufc;
    1.69 -    struct irqaction irqaction;
    1.70 -};
    1.71 -
    1.72  static struct uart com[2] = {
    1.73      { 0, 0, 0, 0, 0x3f8, 4,
    1.74        NULL, NULL, NULL,
     2.1 --- a/xen/include/asm-ia64/serial.h	Sat May 07 09:47:18 2005 +0000
     2.2 +++ b/xen/include/asm-ia64/serial.h	Sat May 07 10:01:24 2005 +0000
     2.3 @@ -21,69 +21,6 @@
     2.4  #define OPT_COM1_STR "115200"
     2.5  #define OPT_COM2_STR ""
     2.6  
     2.7 -/* Register offsets */
     2.8 -#define RBR             0x00    /* receive buffer       */
     2.9 -#define THR             0x00    /* transmit holding     */
    2.10 -#define IER             0x01    /* interrupt enable     */
    2.11 -#define IIR             0x02    /* interrupt identity   */
    2.12 -#define FCR             0x02    /* FIFO control         */
    2.13 -#define LCR             0x03    /* line control         */
    2.14 -#define MCR             0x04    /* Modem control        */
    2.15 -#define LSR             0x05    /* line status          */
    2.16 -#define MSR             0x06    /* Modem status         */
    2.17 -#define DLL             0x00    /* divisor latch (ls) (DLAB=1) */
    2.18 -#define DLM             0x01    /* divisor latch (ms) (DLAB=1) */
    2.19 -
    2.20 -/* Interrupt Enable Register */
    2.21 -#define IER_ERDAI       0x01    /* rx data recv'd       */
    2.22 -#define IER_ETHREI      0x02    /* tx reg. empty        */
    2.23 -#define IER_ELSI        0x04    /* rx line status       */
    2.24 -#define IER_EMSI        0x08    /* MODEM status         */
    2.25 -
    2.26 -/* FIFO control register */
    2.27 -#define FCR_ENABLE      0x01    /* enable FIFO          */
    2.28 -#define FCR_CLRX        0x02    /* clear Rx FIFO        */
    2.29 -#define FCR_CLTX        0x04    /* clear Tx FIFO        */
    2.30 -#define FCR_DMA         0x10    /* enter DMA mode       */
    2.31 -#define FCR_TRG1        0x00    /* Rx FIFO trig lev 1   */
    2.32 -#define FCR_TRG4        0x40    /* Rx FIFO trig lev 4   */
    2.33 -#define FCR_TRG8        0x80    /* Rx FIFO trig lev 8   */
    2.34 -#define FCR_TRG14       0xc0    /* Rx FIFO trig lev 14  */
    2.35 -
    2.36 -/* Line control register */
    2.37 -#define LCR_DLAB        0x80    /* Divisor Latch Access */
    2.38 -
    2.39 -/* Modem Control Register */
    2.40 -#define MCR_DTR         0x01    /* Data Terminal Ready  */
    2.41 -#define MCR_RTS         0x02    /* Request to Send      */
    2.42 -#define MCR_OUT2        0x08    /* OUT2: interrupt mask */
    2.43 -
    2.44 -/* Line Status Register */
    2.45 -#define LSR_DR          0x01    /* Data ready           */
    2.46 -#define LSR_OE          0x02    /* Overrun              */
    2.47 -#define LSR_PE          0x04    /* Parity error         */
    2.48 -#define LSR_FE          0x08    /* Framing error        */
    2.49 -#define LSR_BI          0x10    /* Break                */
    2.50 -#define LSR_THRE        0x20    /* Xmit hold reg empty  */
    2.51 -#define LSR_TEMT        0x40    /* Xmitter empty        */
    2.52 -#define LSR_ERR         0x80    /* Error                */
    2.53 -
    2.54 -/* These parity settings can be ORed directly into the LCR. */
    2.55 -#define PARITY_NONE     (0<<3)
    2.56 -#define PARITY_ODD      (1<<3)
    2.57 -#define PARITY_EVEN     (3<<3)
    2.58 -#define PARITY_MARK     (5<<3)
    2.59 -#define PARITY_SPACE    (7<<3)
    2.60 -
    2.61 -#define RXBUFSZ 32
    2.62 -#define MASK_RXBUF_IDX(_i) ((_i)&(RXBUFSZ-1))
    2.63 -
    2.64 -#define UART_ENABLED(_u) ((_u)->baud != 0)
    2.65 -#define DISABLE_UART(_u) ((_u)->baud = 0)
    2.66 -
    2.67 -/* 'Serial handles' are comprise the following fields. */
    2.68 -#define SERHND_IDX      (1<<0) /* COM1 or COM2?                           */
    2.69 -
    2.70  unsigned char irq_serial_getc(int handle);
    2.71  
    2.72  void serial_force_unlock(int handle);
     3.1 --- a/xen/include/xen/serial.h	Sat May 07 09:47:18 2005 +0000
     3.2 +++ b/xen/include/xen/serial.h	Sat May 07 10:01:24 2005 +0000
     3.3 @@ -11,9 +11,79 @@
     3.4  #ifndef __XEN_SERIAL_H__
     3.5  #define __XEN_SERIAL_H__
     3.6  
     3.7 +#include <xen/irq.h>
     3.8  #include <asm/regs.h>
     3.9  #include <asm/serial.h>
    3.10  
    3.11 +/* Register offsets */
    3.12 +#define RBR             0x00    /* receive buffer       */
    3.13 +#define THR             0x00    /* transmit holding     */
    3.14 +#define IER             0x01    /* interrupt enable     */
    3.15 +#define IIR             0x02    /* interrupt identity   */
    3.16 +#define FCR             0x02    /* FIFO control         */
    3.17 +#define LCR             0x03    /* line control         */
    3.18 +#define MCR             0x04    /* Modem control        */
    3.19 +#define LSR             0x05    /* line status          */
    3.20 +#define MSR             0x06    /* Modem status         */
    3.21 +#define DLL             0x00    /* divisor latch (ls) (DLAB=1) */
    3.22 +#define DLM             0x01    /* divisor latch (ms) (DLAB=1) */
    3.23 +
    3.24 +/* Interrupt Enable Register */
    3.25 +#define IER_ERDAI       0x01    /* rx data recv'd       */
    3.26 +#define IER_ETHREI      0x02    /* tx reg. empty        */
    3.27 +#define IER_ELSI        0x04    /* rx line status       */
    3.28 +#define IER_EMSI        0x08    /* MODEM status         */
    3.29 +
    3.30 +/* FIFO control register */
    3.31 +#define FCR_ENABLE      0x01    /* enable FIFO          */
    3.32 +#define FCR_CLRX        0x02    /* clear Rx FIFO        */
    3.33 +#define FCR_CLTX        0x04    /* clear Tx FIFO        */
    3.34 +#define FCR_DMA         0x10    /* enter DMA mode       */
    3.35 +#define FCR_TRG1        0x00    /* Rx FIFO trig lev 1   */
    3.36 +#define FCR_TRG4        0x40    /* Rx FIFO trig lev 4   */
    3.37 +#define FCR_TRG8        0x80    /* Rx FIFO trig lev 8   */
    3.38 +#define FCR_TRG14       0xc0    /* Rx FIFO trig lev 14  */
    3.39 +
    3.40 +/* Line control register */
    3.41 +#define LCR_DLAB        0x80    /* Divisor Latch Access */
    3.42 +
    3.43 +/* Modem Control Register */
    3.44 +#define MCR_DTR         0x01    /* Data Terminal Ready  */
    3.45 +#define MCR_RTS         0x02    /* Request to Send      */
    3.46 +#define MCR_OUT2        0x08    /* OUT2: interrupt mask */
    3.47 +
    3.48 +/* Line Status Register */
    3.49 +#define LSR_DR          0x01    /* Data ready           */
    3.50 +#define LSR_OE          0x02    /* Overrun              */
    3.51 +#define LSR_PE          0x04    /* Parity error         */
    3.52 +#define LSR_FE          0x08    /* Framing error        */
    3.53 +#define LSR_BI          0x10    /* Break                */
    3.54 +#define LSR_THRE        0x20    /* Xmit hold reg empty  */
    3.55 +#define LSR_TEMT        0x40    /* Xmitter empty        */
    3.56 +#define LSR_ERR         0x80    /* Error                */
    3.57 +
    3.58 +/* These parity settings can be ORed directly into the LCR. */
    3.59 +#define PARITY_NONE     (0<<3)
    3.60 +#define PARITY_ODD      (1<<3)
    3.61 +#define PARITY_EVEN     (3<<3)
    3.62 +#define PARITY_MARK     (5<<3)
    3.63 +#define PARITY_SPACE    (7<<3)
    3.64 +
    3.65 +/* Register a character-receive hook on the specified COM port. */
    3.66 +typedef void (*serial_rx_fn)(unsigned char, struct cpu_user_regs *);
    3.67 +void serial_set_rx_handler(int handle, serial_rx_fn fn);
    3.68 +
    3.69 +#define RXBUFSZ 32
    3.70 +#define MASK_RXBUF_IDX(_i) ((_i)&(RXBUFSZ-1))
    3.71 +struct uart {
    3.72 +    int              baud, data_bits, parity, stop_bits, io_base, irq;
    3.73 +    serial_rx_fn     rx_lo, rx_hi, rx;
    3.74 +    spinlock_t       lock;
    3.75 +    unsigned char    rxbuf[RXBUFSZ];
    3.76 +    unsigned int     rxbufp, rxbufc;
    3.77 +    struct irqaction irqaction;
    3.78 +};
    3.79 +
    3.80  /* 'Serial handles' are comprise the following fields. */
    3.81  #define SERHND_IDX      (1<<0) /* COM1 or COM2?                           */
    3.82  #define SERHND_HI       (1<<1) /* Mux/demux each transferred char by MSB. */
    3.83 @@ -27,10 +97,6 @@ void serial_init_stage2(void);
    3.84  /* Takes a config string and creates a numeric handle on the COM port. */
    3.85  int parse_serial_handle(char *conf);
    3.86  
    3.87 -/* Register a character-receive hook on the specified COM port. */
    3.88 -typedef void (*serial_rx_fn)(unsigned char, struct cpu_user_regs *);
    3.89 -void serial_set_rx_handler(int handle, serial_rx_fn fn);
    3.90 -
    3.91  /* Transmit a single character via the specified COM port. */
    3.92  void serial_putc(int handle, unsigned char c);
    3.93