ia64/xen-unstable

changeset 16202:c05ec22a9106

x86, cpufreq: Allow dom0 kernel to govern cpufreq via the Intel
Enahanced SpeedStep MSR.
From: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
author Keir Fraser <keir@xensource.com>
date Wed Oct 24 10:20:03 2007 +0100 (2007-10-24)
parents 2ad8550033cb
children 4393255607be
files xen/arch/x86/traps.c
line diff
     1.1 --- a/xen/arch/x86/traps.c	Tue Oct 23 11:27:56 2007 -0600
     1.2 +++ b/xen/arch/x86/traps.c	Wed Oct 24 10:20:03 2007 +0100
     1.3 @@ -1773,6 +1773,12 @@ static int emulate_privileged_op(struct 
     1.4                   wrmsr_safe(regs->ecx, eax, edx) )
     1.5                  goto fail;
     1.6              break;
     1.7 +        case MSR_IA32_PERF_CTL:
     1.8 +            if ( (cpufreq_controller != FREQCTL_dom0_kernel) ||
     1.9 +                 (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) ||
    1.10 +                 wrmsr_safe(regs->ecx, eax, edx) )
    1.11 +                goto fail;
    1.12 +            break;
    1.13          default:
    1.14              if ( wrmsr_hypervisor_regs(regs->ecx, eax, edx) )
    1.15                  break;