ia64/xen-unstable

changeset 18008:be20b11656bb

Some latest Intel CPU models support cpuid feature mask.

CPUID.1.EAX>0x00010674.CPUID mask feature is intended to be used to
limit the feature flags reported by CPUID.1.EDX:ECX.

Signed-off-by: Liping Ke <liping.ke@intel.com>
Signed-off-by: Jun Nakajima <nakajima.jun@intel.com>
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Jul 09 11:42:45 2008 +0100 (2008-07-09)
parents af555a012e67
children 4743bfaa9259
files xen/arch/x86/cpu/intel.c xen/include/asm-x86/msr-index.h
line diff
     1.1 --- a/xen/arch/x86/cpu/intel.c	Wed Jul 09 11:05:26 2008 +0100
     1.2 +++ b/xen/arch/x86/cpu/intel.c	Wed Jul 09 11:42:45 2008 +0100
     1.3 @@ -18,6 +18,16 @@
     1.4  
     1.5  extern int trap_init_f00f_bug(void);
     1.6  
     1.7 +/*
     1.8 + * opt_cpuid_mask_ecx/edx: cpuid.1[ecx, edx] feature mask.
     1.9 + * For example, E8400[Intel Core 2 Duo Processor series] ecx = 0x0008E3FD, 
    1.10 + * edx = 0xBFEBFBFF when executing CPUID.EAX = 1 normally. If you want to
    1.11 + * 'rev down' to E8400, you can set these values in these Xen boot parameters.
    1.12 + */
    1.13 +static unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
    1.14 +integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
    1.15 +integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
    1.16 +
    1.17  #ifdef CONFIG_X86_INTEL_USERCOPY
    1.18  /*
    1.19   * Alignment at which movsl is preferred for bulk memory copies.
    1.20 @@ -25,6 +35,25 @@ extern int trap_init_f00f_bug(void);
    1.21  struct movsl_mask movsl_mask __read_mostly;
    1.22  #endif
    1.23  
    1.24 +static void __devinit set_cpuidmask(void)
    1.25 +{
    1.26 +	unsigned int eax, ebx, ecx, edx;
    1.27 +
    1.28 +	if (!(opt_cpuid_mask_ecx | opt_cpuid_mask_edx))
    1.29 +		return;
    1.30 +
    1.31 +	cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
    1.32 +	if (eax < 0x00010674) {
    1.33 +		printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",
    1.34 +		       smp_processor_id());
    1.35 +		return;
    1.36 +	}
    1.37 +
    1.38 +	wrmsr(MSR_IA32_CPUID_FEATURE_MASK1,
    1.39 +	      opt_cpuid_mask_ecx ? : ~0u,
    1.40 +	      opt_cpuid_mask_edx ? : ~0u);
    1.41 +}
    1.42 +
    1.43  void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
    1.44  {
    1.45  	if (c->x86_vendor != X86_VENDOR_INTEL)
    1.46 @@ -158,6 +187,8 @@ static void __devinit init_intel(struct 
    1.47  
    1.48  	detect_ht(c);
    1.49  
    1.50 +	set_cpuidmask();
    1.51 +
    1.52  	/* Work around errata */
    1.53  	Intel_errata_workarounds(c);
    1.54  
     2.1 --- a/xen/include/asm-x86/msr-index.h	Wed Jul 09 11:05:26 2008 +0100
     2.2 +++ b/xen/include/asm-x86/msr-index.h	Wed Jul 09 11:42:45 2008 +0100
     2.3 @@ -123,6 +123,9 @@
     2.4  #define MSR_P6_EVNTSEL0			0x00000186
     2.5  #define MSR_P6_EVNTSEL1			0x00000187
     2.6  
     2.7 +/* MSR for cpuid feature mask */
     2.8 +#define MSR_IA32_CPUID_FEATURE_MASK1	0x00000478
     2.9 +
    2.10  /* MSRs & bits used for VMX enabling */
    2.11  #define MSR_IA32_VMX_BASIC                      0x480
    2.12  #define MSR_IA32_VMX_PINBASED_CTLS              0x481