ia64/xen-unstable

changeset 9751:bbf325d76768

[IA64] translate_domain_pte must handle ED bit and ignre bit[63:53]

made translate_domain_pte() aware _PAGE_ED bits.
_PAGE_PPN_MASK doesn't mask ED bit.
ED bit must be handled explicitly.
This case can occur by vcpu_itc_d().

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author awilliam@xenbuild.aw
date Fri Apr 21 09:20:13 2006 -0600 (2006-04-21)
parents bd264ded5bec
children de0c04ed4ab7
files xen/arch/ia64/xen/process.c
line diff
     1.1 --- a/xen/arch/ia64/xen/process.c	Fri Apr 21 09:11:46 2006 -0600
     1.2 +++ b/xen/arch/ia64/xen/process.c	Fri Apr 21 09:20:13 2006 -0600
     1.3 @@ -87,9 +87,12 @@ unsigned long translate_domain_pte(unsig
     1.4  	struct domain *d = current->domain;
     1.5  	unsigned long mask, pteval2, mpaddr;
     1.6  
     1.7 +	pteval &= ((1UL << 53) - 1);// ignore [63:53] bits
     1.8 +
     1.9  	// FIXME address had better be pre-validated on insert
    1.10  	mask = ~itir_mask(itir);
    1.11 -	mpaddr = ((pteval & _PAGE_PPN_MASK) & ~mask) | (address & mask);
    1.12 +	mpaddr = (((pteval & ~_PAGE_ED) & _PAGE_PPN_MASK) & ~mask) |
    1.13 +	         (address & mask);
    1.14  	if (d == dom0) {
    1.15  		if (mpaddr < dom0_start || mpaddr >= dom0_start + dom0_size) {
    1.16  			/*
    1.17 @@ -114,6 +117,7 @@ unsigned long translate_domain_pte(unsig
    1.18  	}
    1.19  	pteval2 = lookup_domain_mpa(d,mpaddr);
    1.20  	pteval2 &= _PAGE_PPN_MASK; // ignore non-addr bits
    1.21 +	pteval2 |= (pteval & _PAGE_ED);
    1.22  	pteval2 |= _PAGE_PL_2; // force PL0->2 (PL3 is unaffected)
    1.23  	pteval2 = (pteval & ~_PAGE_PPN_MASK) | pteval2;
    1.24  	return pteval2;