ia64/xen-unstable

changeset 18426:b6eea72ea9dc

x86: allow Dom0 to control a few more MSR bits

Linux 2.6.27 adds code to enable extended config space accesses in the
Northbridge Configuration MSR; Xen should allow Dom0 to control the
respective bit.

Likewise, 2.6.26 added support to enable the MMIO config space access
method for certain Sun systems, so similarly Xen should allow Dom0 to
control the respective fields of the MMIO Configuration Base Address
Register.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Sep 01 11:29:01 2008 +0100 (2008-09-01)
parents 86b956d8cf04
children e2a8e3be7bfa
files xen/arch/x86/traps.c xen/include/asm-x86/msr-index.h
line diff
     1.1 --- a/xen/arch/x86/traps.c	Mon Sep 01 10:52:05 2008 +0100
     1.2 +++ b/xen/arch/x86/traps.c	Mon Sep 01 11:29:01 2008 +0100
     1.3 @@ -2116,6 +2116,36 @@ static int emulate_privileged_op(struct 
     1.4              if ( wrmsr_safe(regs->ecx, eax, edx) != 0 )
     1.5                  goto fail;
     1.6              break;
     1.7 +        case MSR_AMD64_NB_CFG:
     1.8 +            if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
     1.9 +                 boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x11 )
    1.10 +                goto fail;
    1.11 +            if ( !IS_PRIV(v->domain) )
    1.12 +                break;
    1.13 +            if ( (rdmsr_safe(MSR_AMD64_NB_CFG, l, h) != 0) ||
    1.14 +                 (eax != l) ||
    1.15 +                 ((edx ^ h) & ~(1 << (AMD64_NB_CFG_CF8_EXT_ENABLE_BIT - 32))) )
    1.16 +                goto invalid;
    1.17 +            if ( wrmsr_safe(MSR_AMD64_NB_CFG, eax, edx) != 0 )
    1.18 +                goto fail;
    1.19 +            break;
    1.20 +        case MSR_FAM10H_MMIO_CONF_BASE:
    1.21 +            if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
    1.22 +                 boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x11 )
    1.23 +                goto fail;
    1.24 +            if ( !IS_PRIV(v->domain) )
    1.25 +                break;
    1.26 +            if ( (rdmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, l, h) != 0) ||
    1.27 +                 (((((u64)h << 32) | l) ^ res) &
    1.28 +                  ~((1 << FAM10H_MMIO_CONF_ENABLE_BIT) |
    1.29 +                    (FAM10H_MMIO_CONF_BUSRANGE_MASK <<
    1.30 +                     FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
    1.31 +                    ((u64)FAM10H_MMIO_CONF_BASE_MASK <<
    1.32 +                     FAM10H_MMIO_CONF_BASE_SHIFT))) )
    1.33 +                goto invalid;
    1.34 +            if ( wrmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, eax, edx) != 0 )
    1.35 +                goto fail;
    1.36 +            break;
    1.37          case MSR_IA32_PERF_CTL:
    1.38              if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
    1.39                  goto fail;
    1.40 @@ -2129,6 +2159,7 @@ static int emulate_privileged_op(struct 
    1.41                  break;
    1.42              if ( (rdmsr_safe(regs->ecx, l, h) != 0) ||
    1.43                   (eax != l) || (edx != h) )
    1.44 +        invalid:
    1.45                  gdprintk(XENLOG_WARNING, "Domain attempted WRMSR %p from "
    1.46                          "%08x:%08x to %08x:%08x.\n",
    1.47                          _p(regs->ecx), h, l, edx, eax);
     2.1 --- a/xen/include/asm-x86/msr-index.h	Mon Sep 01 10:52:05 2008 +0100
     2.2 +++ b/xen/include/asm-x86/msr-index.h	Mon Sep 01 11:29:01 2008 +0100
     2.3 @@ -194,11 +194,23 @@
     2.4  #define _K8_VMCR_SVME_DISABLE		4
     2.5  #define K8_VMCR_SVME_DISABLE		(1 << _K8_VMCR_SVME_DISABLE)
     2.6  
     2.7 +/* AMD64 MSRs */
     2.8 +#define MSR_AMD64_NB_CFG		0xc001001f
     2.9 +#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT	46
    2.10 +
    2.11  /* AMD Family10h machine check MSRs */
    2.12  #define MSR_F10_MC4_MISC1		0xc0000408
    2.13  #define MSR_F10_MC4_MISC2		0xc0000409
    2.14  #define MSR_F10_MC4_MISC3		0xc000040A
    2.15  
    2.16 +/* Other AMD Fam10h MSRs */
    2.17 +#define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058
    2.18 +#define FAM10H_MMIO_CONF_ENABLE_BIT	0
    2.19 +#define FAM10H_MMIO_CONF_BUSRANGE_MASK	0xf
    2.20 +#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
    2.21 +#define FAM10H_MMIO_CONF_BASE_MASK	0xfffffff
    2.22 +#define FAM10H_MMIO_CONF_BASE_SHIFT	20
    2.23 +
    2.24  /* K6 MSRs */
    2.25  #define MSR_K6_EFER			0xc0000080
    2.26  #define MSR_K6_STAR			0xc0000081