ia64/xen-unstable

changeset 19556:b44db970f6b7

cpuidle: Add support for Always Running APIC timer, CPUID_0x6_EAX_Bit2.

This bit means the APIC timer continues to run even when CPU is
in deep C-states.

The advantage is that we can use LAPIC timer on these CPUs
always, and there is no need for "slow to read and program"
external timers (HPET/PIT) and the timer broadcast logic
and related code in C-state entry and exit.

Refer to the latest Intel SDM Vol 2A
(http://www.intel.com/products/processor/manuals/index.htm)

Signed-off-by: Wei Gang <gang.wei@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Apr 17 13:14:01 2009 +0100 (2009-04-17)
parents 150662e5adfc
children 226ef307cd2e
files xen/arch/x86/acpi/cpu_idle.c xen/arch/x86/cpu/intel.c xen/arch/x86/time.c xen/include/asm-x86/cpufeature.h
line diff
     1.1 --- a/xen/arch/x86/acpi/cpu_idle.c	Fri Apr 17 13:07:06 2009 +0100
     1.2 +++ b/xen/arch/x86/acpi/cpu_idle.c	Fri Apr 17 13:14:01 2009 +0100
     1.3 @@ -51,6 +51,7 @@
     1.4  
     1.5  /*#define DEBUG_PM_CX*/
     1.6  
     1.7 +static void lapic_timer_nop(void) { }
     1.8  static void (*lapic_timer_off)(void);
     1.9  static void (*lapic_timer_on)(void);
    1.10  
    1.11 @@ -538,8 +539,12 @@ static int check_cx(struct acpi_processo
    1.12          if ( local_apic_timer_c2_ok )
    1.13              break;
    1.14      case ACPI_STATE_C3:
    1.15 -        /* We must be able to use HPET in place of LAPIC timers. */
    1.16 -        if ( hpet_broadcast_is_available() )
    1.17 +        if ( boot_cpu_has(X86_FEATURE_ARAT) )
    1.18 +        {
    1.19 +            lapic_timer_off = lapic_timer_nop;
    1.20 +            lapic_timer_on = lapic_timer_nop;
    1.21 +        }
    1.22 +        else if ( hpet_broadcast_is_available() )
    1.23          {
    1.24              lapic_timer_off = hpet_broadcast_enter;
    1.25              lapic_timer_on = hpet_broadcast_exit;
     2.1 --- a/xen/arch/x86/cpu/intel.c	Fri Apr 17 13:07:06 2009 +0100
     2.2 +++ b/xen/arch/x86/cpu/intel.c	Fri Apr 17 13:14:01 2009 +0100
     2.3 @@ -222,6 +222,9 @@ static void __devinit init_intel(struct 
     2.4  		set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
     2.5  		set_bit(X86_FEATURE_NOSTOP_TSC, c->x86_capability);
     2.6  	}
     2.7 +	if ((c->cpuid_level >= 0x00000006) &&
     2.8 +	    (cpuid_eax(0x00000006) & (1u<<2)))
     2.9 +		set_bit(X86_FEATURE_ARAT, c->x86_capability);
    2.10  
    2.11  	start_vmx();
    2.12  }
     3.1 --- a/xen/arch/x86/time.c	Fri Apr 17 13:07:06 2009 +0100
     3.2 +++ b/xen/arch/x86/time.c	Fri Apr 17 13:14:01 2009 +0100
     3.3 @@ -1274,7 +1274,7 @@ static int disable_pit_irq(void)
     3.4       * XXX dom0 may rely on RTC interrupt delivery, so only enable
     3.5       * hpet_broadcast if FSB mode available or if force_hpet_broadcast.
     3.6       */
     3.7 -    if ( xen_cpuidle )
     3.8 +    if ( xen_cpuidle && !boot_cpu_has(X86_FEATURE_ARAT) )
     3.9      {
    3.10          hpet_broadcast_init();
    3.11          if ( !hpet_broadcast_is_available() )
     4.1 --- a/xen/include/asm-x86/cpufeature.h	Fri Apr 17 13:07:06 2009 +0100
     4.2 +++ b/xen/include/asm-x86/cpufeature.h	Fri Apr 17 13:14:01 2009 +0100
     4.3 @@ -75,6 +75,7 @@
     4.4  #define X86_FEATURE_P4		(3*32+ 7) /* P4 */
     4.5  #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
     4.6  #define X86_FEATURE_NOSTOP_TSC	(3*32+ 9) /* TSC does not stop in C states */
     4.7 +#define X86_FEATURE_ARAT	(3*32+ 10) /* Always running APIC timer */
     4.8  
     4.9  /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
    4.10  #define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */