ia64/xen-unstable

changeset 13364:b440f5dbca1f

[IA64] Use original itir when inserting into the single-entry TLB

http://lists.xensource.com/archives/html/xen-ia64-devel/2006-11/msg00349.html

The real VHPT insertion is done based on the machine PTE returned from
translate_domain_pte, which does the appropriate offset calculations.

However, the insertion into the one-entry TLB uses the original PTE, but
the page size has been reset to PAGE_SIZE [1]. Thus the entry in the
one-entry TLB incorrectly maps the PAGE_SIZE sub-page which was faulted
on to the PAGE_SIZE sub-page at the bottom of the superpage.

I think it makes most sense to simply use the original itir when
inserting into the single-entry TLB, as per attached patch. I've moved
the vcpu_set_tr_entry calls up a level into vcpu_itc_d and vcpu_itc_i;
the third caller previously used the 4 flag to specify "don't do that".

[1] In fact, this is enforced twice, once in translate_domain_pte and
again in vcpu_itc_no_srlz.

Signed-off-by: Matthew Chapman <matthewc@cse.unsw.edu.au>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author awilliam@xenbuild2.aw
date Fri Jan 12 12:52:54 2007 -0700 (2007-01-12)
parents 5d328ef9da71
children d607d575ec6a
files xen/arch/ia64/xen/faults.c xen/arch/ia64/xen/vcpu.c
line diff
     1.1 --- a/xen/arch/ia64/xen/faults.c	Fri Jan 12 12:14:05 2007 -0700
     1.2 +++ b/xen/arch/ia64/xen/faults.c	Fri Jan 12 12:52:54 2007 -0700
     1.3 @@ -215,8 +215,8 @@ void ia64_do_page_fault(unsigned long ad
     1.4  		unsigned long m_pteval;
     1.5  		m_pteval = translate_domain_pte(pteval, address, itir,
     1.6  		                                &logps, &entry);
     1.7 -		vcpu_itc_no_srlz(current, (is_data ? 2 : 1) | 4,
     1.8 -		                 address, m_pteval, pteval, logps, &entry);
     1.9 +		vcpu_itc_no_srlz(current, is_data ? 2 : 1, address,
    1.10 +		                 m_pteval, pteval, logps, &entry);
    1.11  		if ((fault == IA64_USE_TLB && !current->arch.dtlb.pte.p) ||
    1.12  		    p2m_entry_retry(&entry)) {
    1.13  			/* dtlb has been purged in-between.  This dtlb was
     2.1 --- a/xen/arch/ia64/xen/vcpu.c	Fri Jan 12 12:14:05 2007 -0700
     2.2 +++ b/xen/arch/ia64/xen/vcpu.c	Fri Jan 12 12:52:54 2007 -0700
     2.3 @@ -2181,14 +2181,6 @@ vcpu_itc_no_srlz(VCPU * vcpu, u64 IorD, 
     2.4  	else
     2.5  		vhpt_insert(vaddr, pte, PAGE_SHIFT << 2);
     2.6  #endif
     2.7 -	if (IorD & 0x4)		/* don't place in 1-entry TLB */
     2.8 -		return;
     2.9 -	if (IorD & 0x1) {
    2.10 -		vcpu_set_tr_entry(&PSCBX(vcpu, itlb), mp_pte, ps << 2, vaddr);
    2.11 -	}
    2.12 -	if (IorD & 0x2) {
    2.13 -		vcpu_set_tr_entry(&PSCBX(vcpu, dtlb), mp_pte, ps << 2, vaddr);
    2.14 -	}
    2.15  }
    2.16  
    2.17  IA64FAULT vcpu_itc_d(VCPU * vcpu, u64 pte, u64 itir, u64 ifa)
    2.18 @@ -2215,6 +2207,7 @@ IA64FAULT vcpu_itc_d(VCPU * vcpu, u64 pt
    2.19  		vcpu_flush_tlb_vhpt_range(ifa, logps);
    2.20  		goto again;
    2.21  	}
    2.22 +	vcpu_set_tr_entry(&PSCBX(vcpu, dtlb), pte, itir, ifa);
    2.23  	return IA64_NO_FAULT;
    2.24  }
    2.25  
    2.26 @@ -2241,6 +2234,7 @@ IA64FAULT vcpu_itc_i(VCPU * vcpu, u64 pt
    2.27  		vcpu_flush_tlb_vhpt_range(ifa, logps);
    2.28  		goto again;
    2.29  	}
    2.30 +	vcpu_set_tr_entry(&PSCBX(vcpu, itlb), pte, itir, ifa);
    2.31  	return IA64_NO_FAULT;
    2.32  }
    2.33