ia64/xen-unstable

changeset 16287:b235b68a0f4f

[IA64] Update pal.h and pal.S to linux-2.6.21

Current pal.h is based on linux-2.6.13 and
some procedures are missing. (e.g. PAL_GET_PSTATE)

This patch just updates pal.h and pal.S to linux-2.6.21.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
author Alex Williamson <alex.williamson@hp.com>
date Thu Nov 01 08:55:01 2007 -0600 (2007-11-01)
parents 42e032f52371
children 41c1731c9125
files xen/arch/ia64/linux-xen/README.origin xen/arch/ia64/linux-xen/pal.S xen/include/asm-ia64/linux-xen/asm/README.origin xen/include/asm-ia64/linux-xen/asm/pal.h
line diff
     1.1 --- a/xen/arch/ia64/linux-xen/README.origin	Thu Nov 01 08:50:03 2007 -0600
     1.2 +++ b/xen/arch/ia64/linux-xen/README.origin	Thu Nov 01 08:55:01 2007 -0600
     1.3 @@ -17,7 +17,6 @@ minstate.h		-> linux/arch/ia64/kernel/mi
     1.4  mm_contig.c		-> linux/arch/ia64/mm/contig.c
     1.5  mm_numa.c		-> linux/arch/ia64/mm/numa.c
     1.6  numa.c			-> linux/arch/ia64/kernel/numa.c
     1.7 -pal.S			-> linux/arch/ia64/kernel/pal.S
     1.8  process-linux-xen.c	-> linux/arch/ia64/kernel/process.c
     1.9  sal.c			-> linux/arch/ia64/kernel/sal.c
    1.10  setup.c			-> linux/arch/ia64/kernel/setup.c
    1.11 @@ -44,3 +43,4 @@ perfmon_montecito.h	-> linux/arch/kernel
    1.12  
    1.13  # The files below are from Linux-2.6.21
    1.14  efi.c			-> linux/arch/ia64/kernel/efi.c
    1.15 +pal.S			-> linux/arch/ia64/kernel/pal.S
     2.1 --- a/xen/arch/ia64/linux-xen/pal.S	Thu Nov 01 08:50:03 2007 -0600
     2.2 +++ b/xen/arch/ia64/linux-xen/pal.S	Thu Nov 01 08:55:01 2007 -0600
     2.3 @@ -21,11 +21,12 @@ pal_entry_point:
     2.4  	.text
     2.5  
     2.6  /*
     2.7 - * Set the PAL entry point address.  This could be written in C code, but we do it here
     2.8 - * to keep it all in one module (besides, it's so trivial that it's
     2.9 + * Set the PAL entry point address.  This could be written in C code, but we
    2.10 + * do it here to keep it all in one module (besides, it's so trivial that it's
    2.11   * not a big deal).
    2.12   *
    2.13 - * in0		Address of the PAL entry point (text address, NOT a function descriptor).
    2.14 + * in0		Address of the PAL entry point (text address, NOT a function
    2.15 + *		descriptor).
    2.16   */
    2.17  GLOBAL_ENTRY(ia64_pal_handler_init)
    2.18  	alloc r3=ar.pfs,1,0,0,0
    2.19 @@ -36,9 +37,9 @@ GLOBAL_ENTRY(ia64_pal_handler_init)
    2.20  END(ia64_pal_handler_init)
    2.21  
    2.22  /*
    2.23 - * Default PAL call handler.  This needs to be coded in assembly because it uses
    2.24 - * the static calling convention, i.e., the RSE may not be used and calls are
    2.25 - * done via "br.cond" (not "br.call").
    2.26 + * Default PAL call handler.  This needs to be coded in assembly because it
    2.27 + * uses the static calling convention, i.e., the RSE may not be used and
    2.28 + * calls are done via "br.cond" (not "br.call").
    2.29   */
    2.30  GLOBAL_ENTRY(ia64_pal_default_handler)
    2.31  	mov r8=-1
    2.32 @@ -50,12 +51,10 @@ END(ia64_pal_default_handler)
    2.33   *
    2.34   * in0         Index of PAL service
    2.35   * in1 - in3   Remaining PAL arguments
    2.36 - * in4	       1 ==> clear psr.ic,  0 ==> don't clear psr.ic
    2.37 - *
    2.38   */
    2.39  GLOBAL_ENTRY(ia64_pal_call_static)
    2.40 -	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
    2.41 -	alloc loc1 = ar.pfs,5,5,0,0
    2.42 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
    2.43 +	alloc loc1 = ar.pfs,4,5,0,0
    2.44  	movl loc2 = pal_entry_point
    2.45  1:	{
    2.46  	  mov r28 = in0
    2.47 @@ -64,7 +63,6 @@ 1:	{
    2.48  	}
    2.49  	;;
    2.50  	ld8 loc2 = [loc2]		// loc2 <- entry point
    2.51 -	tbit.nz p6,p7 = in4, 0
    2.52  	adds r8 = 1f-1b,r8
    2.53  	mov loc4=ar.rsc			// save RSE configuration
    2.54  	;;
    2.55 @@ -74,13 +72,11 @@ 1:	{
    2.56  	.body
    2.57  	mov r30 = in2
    2.58  
    2.59 -(p6)	rsm psr.i | psr.ic
    2.60  	mov r31 = in3
    2.61  	mov b7 = loc2
    2.62  
    2.63 -(p7)	rsm psr.i
    2.64 +	rsm psr.i
    2.65  	;;
    2.66 -(p6)	srlz.i
    2.67  	mov rp = r8
    2.68  	br.cond.sptk.many b7
    2.69  1:	mov psr.l = loc3
    2.70 @@ -96,8 +92,8 @@ END(ia64_pal_call_static)
    2.71   * Make a PAL call using the stacked registers calling convention.
    2.72   *
    2.73   * Inputs:
    2.74 - * 	in0         Index of PAL service
    2.75 - * 	in2 - in3   Remaning PAL arguments
    2.76 + *	in0         Index of PAL service
    2.77 + *	in2 - in3   Remaining PAL arguments
    2.78   */
    2.79  GLOBAL_ENTRY(ia64_pal_call_stacked)
    2.80  	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
    2.81 @@ -131,18 +127,18 @@ END(ia64_pal_call_stacked)
    2.82   * Make a physical mode PAL call using the static registers calling convention.
    2.83   *
    2.84   * Inputs:
    2.85 - * 	in0         Index of PAL service
    2.86 - * 	in2 - in3   Remaning PAL arguments
    2.87 + *	in0         Index of PAL service
    2.88 + *	in2 - in3   Remaining PAL arguments
    2.89   *
    2.90   * PSR_LP, PSR_TB, PSR_ID, PSR_DA are never set by the kernel.
    2.91   * So we don't need to clear them.
    2.92   */
    2.93 -#define PAL_PSR_BITS_TO_CLEAR							\
    2.94 -	(IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT  | IA64_PSR_DB | IA64_PSR_RT |	\
    2.95 -	 IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED |		\
    2.96 +#define PAL_PSR_BITS_TO_CLEAR						      \
    2.97 +	(IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT  | IA64_PSR_DB | IA64_PSR_RT |\
    2.98 +	 IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED |	      \
    2.99  	 IA64_PSR_DFL | IA64_PSR_DFH)
   2.100  
   2.101 -#define PAL_PSR_BITS_TO_SET							\
   2.102 +#define PAL_PSR_BITS_TO_SET						      \
   2.103  	(IA64_PSR_BN)
   2.104  
   2.105  
   2.106 @@ -182,7 +178,7 @@ 1:	{
   2.107  	;;
   2.108  	andcm r16=loc3,r16		// removes bits to clear from psr
   2.109  	br.call.sptk.many rp=ia64_switch_mode_phys
   2.110 -.ret1:	mov rp = r8			// install return address (physical)
   2.111 +	mov rp = r8			// install return address (physical)
   2.112  	mov loc5 = r19
   2.113  	mov loc6 = r20
   2.114  	br.cond.sptk.many b7
   2.115 @@ -192,7 +188,6 @@ 1:
   2.116  	mov r19=loc5
   2.117  	mov r20=loc6
   2.118  	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
   2.119 -.ret2:
   2.120  	mov psr.l = loc3		// restore init PSR
   2.121  
   2.122  	mov ar.pfs = loc1
   2.123 @@ -207,8 +202,8 @@ END(ia64_pal_call_phys_static)
   2.124   * Make a PAL call using the stacked registers in physical mode.
   2.125   *
   2.126   * Inputs:
   2.127 - * 	in0         Index of PAL service
   2.128 - * 	in2 - in3   Remaning PAL arguments
   2.129 + *	in0         Index of PAL service
   2.130 + *	in2 - in3   Remaining PAL arguments
   2.131   */
   2.132  GLOBAL_ENTRY(ia64_pal_call_phys_stacked)
   2.133  	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
   2.134 @@ -216,17 +211,12 @@ GLOBAL_ENTRY(ia64_pal_call_phys_stacked)
   2.135  	movl	loc2 = pal_entry_point
   2.136  1:	{
   2.137  	  mov r28  = in0		// copy procedure index
   2.138 -	  mov loc0 = rp		// save rp
   2.139 +	  mov loc0 = rp			// save rp
   2.140  	}
   2.141  	.body
   2.142  	;;
   2.143  	ld8 loc2 = [loc2]		// loc2 <- entry point
   2.144 -	mov out0 = in0		// first argument
   2.145 -	mov out1 = in1		// copy arg2
   2.146 -	mov out2 = in2		// copy arg3
   2.147 -	mov out3 = in3		// copy arg3
   2.148 -	;;
   2.149 -	mov loc3 = psr		// save psr
   2.150 +	mov loc3 = psr			// save psr
   2.151  	;;
   2.152  	mov loc4=ar.rsc			// save RSE configuration
   2.153  #ifdef XEN
   2.154 @@ -244,18 +234,23 @@ 1:	{
   2.155  	;;
   2.156  	andcm r16=loc3,r16		// removes bits to clear from psr
   2.157  	br.call.sptk.many rp=ia64_switch_mode_phys
   2.158 -.ret6:
   2.159 +
   2.160 +	mov out0 = in0			// first argument
   2.161 +	mov out1 = in1			// copy arg2
   2.162 +	mov out2 = in2			// copy arg3
   2.163 +	mov out3 = in3			// copy arg3
   2.164  	mov loc5 = r19
   2.165  	mov loc6 = r20
   2.166 +
   2.167  	br.call.sptk.many rp=b7		// now make the call
   2.168 -.ret7:
   2.169 +
   2.170  	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   2.171  	mov r16=loc3			// r16= original psr
   2.172  	mov r19=loc5
   2.173  	mov r20=loc6
   2.174 -	br.call.sptk.many rp=ia64_switch_mode_virt	// return to virtual mode
   2.175 +	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
   2.176  
   2.177 -.ret8:	mov psr.l  = loc3		// restore init PSR
   2.178 +	mov psr.l  = loc3		// restore init PSR
   2.179  	mov ar.pfs = loc1
   2.180  	mov rp = loc0
   2.181  	;;
   2.182 @@ -265,10 +260,11 @@ 1:	{
   2.183  END(ia64_pal_call_phys_stacked)
   2.184  
   2.185  /*
   2.186 - * Save scratch fp scratch regs which aren't saved in pt_regs already (fp10-fp15).
   2.187 + * Save scratch fp scratch regs which aren't saved in pt_regs already
   2.188 + * (fp10-fp15).
   2.189   *
   2.190 - * NOTE: We need to do this since firmware (SAL and PAL) may use any of the scratch
   2.191 - * regs fp-low partition.
   2.192 + * NOTE: We need to do this since firmware (SAL and PAL) may use any of the
   2.193 + * scratch regs fp-low partition.
   2.194   *
   2.195   * Inputs:
   2.196   *      in0	Address of stack storage for fp regs
     3.1 --- a/xen/include/asm-ia64/linux-xen/asm/README.origin	Thu Nov 01 08:50:03 2007 -0600
     3.2 +++ b/xen/include/asm-ia64/linux-xen/asm/README.origin	Thu Nov 01 08:55:01 2007 -0600
     3.3 @@ -17,7 +17,6 @@ mca_asm.h		-> linux/include/asm-ia64/mca
     3.4  meminit.h		-> linux/include/asm-ia64/meminit.h
     3.5  numa.h			-> linux/include/asm-ia64/numa.h
     3.6  page.h			-> linux/include/asm-ia64/page.h
     3.7 -pal.h			-> linux/include/asm-ia64/pal.h
     3.8  percpu.h		-> linux/include/asm-ia64/percpu.h
     3.9  pgalloc.h		-> linux/include/asm-ia64/pgalloc.h
    3.10  pgtable.h		-> linux/include/asm-ia64/pgtable.h
    3.11 @@ -42,3 +41,6 @@ machvec_dig.h		-> linux/include/asm-ia64
    3.12  machvec_sn2.h		-> linux/include/asm-ia64/machvec_sn2.h
    3.13  machvec_hpzx1.h		-> linux/include/asm-ia64/machvec_hpzx1.h
    3.14  machvec_pci.h		-> linux/include/asm-ia64/pci.h
    3.15 +
    3.16 +# The files below are from Linux-2.6.21
    3.17 +pal.h			-> linux/include/asm-ia64/pal.h
     4.1 --- a/xen/include/asm-ia64/linux-xen/asm/pal.h	Thu Nov 01 08:50:03 2007 -0600
     4.2 +++ b/xen/include/asm-ia64/linux-xen/asm/pal.h	Thu Nov 01 08:55:01 2007 -0600
     4.3 @@ -20,6 +20,8 @@
     4.4   * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
     4.5   * 00/05/25	eranian Support for stack calls, and static physical calls
     4.6   * 00/06/18	eranian Support for stacked physical calls
     4.7 + * 06/10/26	rja	Support for Intel Itanium Architecture Software Developer's
     4.8 + *			Manual Rev 2.2 (Jan 2006)
     4.9   */
    4.10  
    4.11  /*
    4.12 @@ -30,7 +32,7 @@
    4.13  #define PAL_CACHE_FLUSH		1	/* flush i/d cache */
    4.14  #define PAL_CACHE_INFO		2	/* get detailed i/d cache info */
    4.15  #define PAL_CACHE_INIT		3	/* initialize i/d cache */
    4.16 -#define PAL_CACHE_SUMMARY	4	/* get summary of cache heirarchy */
    4.17 +#define PAL_CACHE_SUMMARY	4	/* get summary of cache hierarchy */
    4.18  #define PAL_MEM_ATTRIB		5	/* list supported memory attributes */
    4.19  #define PAL_PTCE_INFO		6	/* purge TLB info */
    4.20  #define PAL_VM_INFO		7	/* return supported virtual memory features */
    4.21 @@ -68,6 +70,9 @@
    4.22  #define PAL_SHUTDOWN		40	/* enter processor shutdown state */
    4.23  #define PAL_PREFETCH_VISIBILITY	41	/* Make Processor Prefetches Visible */
    4.24  #define PAL_LOGICAL_TO_PHYSICAL 42	/* returns information on logical to physical processor mapping */
    4.25 +#define PAL_CACHE_SHARED_INFO	43	/* returns information on caches shared by logical processor */
    4.26 +#define PAL_GET_HW_POLICY	48	/* Get current hardware resource sharing policy */
    4.27 +#define PAL_SET_HW_POLICY	49	/* Set current hardware resource sharing policy */
    4.28  
    4.29  #define PAL_COPY_PAL		256	/* relocate PAL procedures and PAL PMI */
    4.30  #define PAL_HALT_INFO		257	/* return the low power capabilities of processor */
    4.31 @@ -75,6 +80,14 @@
    4.32  #define PAL_CACHE_READ		259	/* read tag & data of cacheline for diagnostic testing */
    4.33  #define PAL_CACHE_WRITE		260	/* write tag & data of cacheline for diagnostic testing */
    4.34  #define PAL_VM_TR_READ		261	/* read contents of translation register */
    4.35 +#define PAL_GET_PSTATE		262	/* get the current P-state */
    4.36 +#define PAL_SET_PSTATE		263	/* set the P-state */
    4.37 +#define PAL_BRAND_INFO		274	/* Processor branding information */
    4.38 +
    4.39 +#define PAL_GET_PSTATE_TYPE_LASTSET	0
    4.40 +#define PAL_GET_PSTATE_TYPE_AVGANDRESET	1
    4.41 +#define PAL_GET_PSTATE_TYPE_AVGNORESET	2
    4.42 +#define PAL_GET_PSTATE_TYPE_INSTANT	3
    4.43  
    4.44  #ifndef __ASSEMBLY__
    4.45  
    4.46 @@ -98,15 +111,16 @@ typedef s64				pal_status_t;
    4.47  						 * cache without sideeffects
    4.48  						 * and "restrict" was 1
    4.49  						 */
    4.50 +#define PAL_STATUS_REQUIRES_MEMORY	(-9)	/* Call requires PAL memory buffer */
    4.51  
    4.52 -/* Processor cache level in the heirarchy */
    4.53 +/* Processor cache level in the hierarchy */
    4.54  typedef u64				pal_cache_level_t;
    4.55  #define PAL_CACHE_LEVEL_L0		0	/* L0 */
    4.56  #define PAL_CACHE_LEVEL_L1		1	/* L1 */
    4.57  #define PAL_CACHE_LEVEL_L2		2	/* L2 */
    4.58  
    4.59  
    4.60 -/* Processor cache type at a particular level in the heirarchy */
    4.61 +/* Processor cache type at a particular level in the hierarchy */
    4.62  
    4.63  typedef u64				pal_cache_type_t;
    4.64  #define PAL_CACHE_TYPE_INSTRUCTION	1	/* Instruction cache */
    4.65 @@ -131,7 +145,7 @@ typedef u64				pal_cache_line_state_t;
    4.66  #define PAL_CACHE_LINE_STATE_MODIFIED	3	/* Modified */
    4.67  
    4.68  typedef struct pal_freq_ratio {
    4.69 -	u64 den : 32, num : 32;	/* numerator & denominator */
    4.70 +	u32 den, num;		/* numerator & denominator */
    4.71  } itc_ratio, proc_ratio;
    4.72  
    4.73  typedef	union  pal_cache_config_info_1_s {
    4.74 @@ -152,10 +166,10 @@ typedef	union  pal_cache_config_info_1_s
    4.75  
    4.76  typedef	union  pal_cache_config_info_2_s {
    4.77  	struct {
    4.78 -		u64		cache_size	: 32,	/*cache size in bytes*/
    4.79 +		u32		cache_size;		/*cache size in bytes*/
    4.80  
    4.81  
    4.82 -				alias_boundary	: 8,	/* 39-32 aliased addr
    4.83 +		u32		alias_boundary	: 8,	/* 39-32 aliased addr
    4.84  							 * separation for max
    4.85  							 * performance.
    4.86  							 */
    4.87 @@ -261,14 +275,14 @@ typedef struct pal_cache_protection_info
    4.88  #define PAL_CACHE_PROT_METHOD_ECC		3	/* ECC protection */
    4.89  
    4.90  
    4.91 -/* Processor cache line identification in the heirarchy */
    4.92 +/* Processor cache line identification in the hierarchy */
    4.93  typedef union pal_cache_line_id_u {
    4.94  	u64			pclid_data;
    4.95  	struct {
    4.96  		u64		cache_type	: 8,	/* 7-0 cache type */
    4.97  				level		: 8,	/* 15-8 level of the
    4.98  							 * cache in the
    4.99 -							 * heirarchy.
   4.100 +							 * hierarchy.
   4.101  							 */
   4.102  				way		: 8,	/* 23-16 way in the set
   4.103  							 */
   4.104 @@ -281,7 +295,7 @@ typedef union pal_cache_line_id_u {
   4.105  		u64		cache_type	: 8,	/* 7-0 cache type */
   4.106  				level		: 8,	/* 15-8 level of the
   4.107  							 * cache in the
   4.108 -							 * heirarchy.
   4.109 +							 * hierarchy.
   4.110  							 */
   4.111  				way		: 8,	/* 23-16 way in the set
   4.112  							 */
   4.113 @@ -360,6 +374,7 @@ typedef u64					pal_mc_info_index_t;
   4.114  							 * dependent
   4.115  							 */
   4.116  
   4.117 +#define PAL_TLB_CHECK_OP_PURGE			8
   4.118  
   4.119  typedef struct pal_process_state_info_s {
   4.120  	u64		reserved1	: 2,
   4.121 @@ -455,7 +470,9 @@ typedef struct pal_process_state_info_s 
   4.122  						 * by the processor
   4.123  						 */
   4.124  
   4.125 -			reserved2	: 11,
   4.126 +			se		: 1,	/* Shared error.  MCA in a
   4.127 +						   shared structure */
   4.128 +			reserved2	: 10,
   4.129  			cc		: 1,	/* Cache check */
   4.130  			tc		: 1,	/* TLB check */
   4.131  			bc		: 1,	/* Bus check */
   4.132 @@ -486,10 +503,12 @@ typedef struct pal_cache_check_info_s {
   4.133  						 * error occurred
   4.134  						 */
   4.135  			wiv		: 1,	/* Way field valid */
   4.136 -			reserved2	: 10,
   4.137 +			reserved2	: 1,
   4.138 +			dp		: 1,	/* Data poisoned on MBE */
   4.139 +			reserved3	: 8,
   4.140  
   4.141  			index		: 20,	/* Cache line index */
   4.142 -			reserved3	: 2,
   4.143 +			reserved4	: 2,
   4.144  
   4.145  			is		: 1,	/* instruction set (1 == ia32) */
   4.146  			iv		: 1,	/* instruction set field valid */
   4.147 @@ -556,7 +575,7 @@ typedef struct pal_bus_check_info_s {
   4.148  			type		: 8,	/* Bus xaction type*/
   4.149  			sev		: 5,	/* Bus error severity*/
   4.150  			hier		: 2,	/* Bus hierarchy level */
   4.151 -			reserved1	: 1,
   4.152 +			dp		: 1,	/* Data poisoned on MBE */
   4.153  			bsi		: 8,	/* Bus error status
   4.154  						 * info
   4.155  						 */
   4.156 @@ -763,7 +782,7 @@ struct ia64_pal_retval {
   4.157   * (generally 0) MUST be passed.  Reserved parameters are not optional
   4.158   * parameters.
   4.159   */
   4.160 -extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64);
   4.161 +extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
   4.162  extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
   4.163  extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
   4.164  extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
   4.165 @@ -773,14 +792,7 @@ extern void ia64_load_scratch_fpregs (st
   4.166  #define PAL_CALL(iprv,a0,a1,a2,a3) do {			\
   4.167  	struct ia64_fpreg fr[6];			\
   4.168  	ia64_save_scratch_fpregs(fr);			\
   4.169 -	iprv = ia64_pal_call_static(a0, a1, a2, a3, 0);	\
   4.170 -	ia64_load_scratch_fpregs(fr);			\
   4.171 -} while (0)
   4.172 -
   4.173 -#define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) do {		\
   4.174 -	struct ia64_fpreg fr[6];			\
   4.175 -	ia64_save_scratch_fpregs(fr);			\
   4.176 -	iprv = ia64_pal_call_static(a0, a1, a2, a3, 1);	\
   4.177 +	iprv = ia64_pal_call_static(a0, a1, a2, a3);	\
   4.178  	ia64_load_scratch_fpregs(fr);			\
   4.179  } while (0)
   4.180  
   4.181 @@ -840,7 +852,9 @@ typedef union pal_bus_features_u {
   4.182  		u64	pbf_req_bus_parking			:	1;
   4.183  		u64	pbf_bus_lock_mask			:	1;
   4.184  		u64	pbf_enable_half_xfer_rate		:	1;
   4.185 -		u64	pbf_reserved2				:	22;
   4.186 +		u64	pbf_reserved2				:	20;
   4.187 +		u64	pbf_enable_shared_line_replace		:	1;
   4.188 +		u64	pbf_enable_exclusive_line_replace	:	1;
   4.189  		u64	pbf_disable_xaction_queueing		:	1;
   4.190  		u64	pbf_disable_resp_err_check		:	1;
   4.191  		u64	pbf_disable_berr_check			:	1;
   4.192 @@ -928,11 +942,7 @@ static inline s64
   4.193  ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
   4.194  {
   4.195  	struct ia64_pal_retval iprv;
   4.196 -#ifdef XEN	/* fix a bug in Linux... PAL has changed */
   4.197  	PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
   4.198 -#else
   4.199 -	PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
   4.200 -#endif
   4.201  	if (vector)
   4.202  		*vector = iprv.v0;
   4.203  	*progress = iprv.v1;
   4.204 @@ -967,11 +977,12 @@ static inline s64
   4.205  ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
   4.206  {
   4.207  	struct ia64_pal_retval iprv;
   4.208 -	PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0);
   4.209 +	PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
   4.210 +				physical_addr, 0);
   4.211  	return iprv.status;
   4.212  }
   4.213  
   4.214 -/* Return summary information about the heirarchy of caches controlled by the processor */
   4.215 +/* Return summary information about the hierarchy of caches controlled by the processor */
   4.216  static inline s64
   4.217  ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
   4.218  {
   4.219 @@ -989,7 +1000,8 @@ static inline s64
   4.220  ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
   4.221  {
   4.222  	struct ia64_pal_retval iprv;
   4.223 -	PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data);
   4.224 +	PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
   4.225 +				physical_addr, data);
   4.226  	return iprv.status;
   4.227  }
   4.228  
   4.229 @@ -1085,6 +1097,24 @@ ia64_pal_freq_ratios (struct pal_freq_ra
   4.230  	return iprv.status;
   4.231  }
   4.232  
   4.233 +/*
   4.234 + * Get the current hardware resource sharing policy of the processor
   4.235 + */
   4.236 +static inline s64
   4.237 +ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
   4.238 +			u64 *la)
   4.239 +{
   4.240 +	struct ia64_pal_retval iprv;
   4.241 +	PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
   4.242 +	if (cur_policy)
   4.243 +		*cur_policy = iprv.v0;
   4.244 +	if (num_impacted)
   4.245 +		*num_impacted = iprv.v1;
   4.246 +	if (la)
   4.247 +		*la = iprv.v2;
   4.248 +	return iprv.status;
   4.249 +}
   4.250 +
   4.251  /* Make the processor enter HALT or one of the implementation dependent low
   4.252   * power states where prefetching and execution are suspended and cache and
   4.253   * TLB coherency is not maintained.
   4.254 @@ -1118,6 +1148,34 @@ ia64_pal_halt_info (pal_power_mgmt_info_
   4.255  	return iprv.status;
   4.256  }
   4.257  
   4.258 +/* Get the current P-state information */
   4.259 +static inline s64
   4.260 +ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
   4.261 +{
   4.262 +	struct ia64_pal_retval iprv;
   4.263 +	PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
   4.264 +	*pstate_index = iprv.v0;
   4.265 +	return iprv.status;
   4.266 +}
   4.267 +
   4.268 +/* Set the P-state */
   4.269 +static inline s64
   4.270 +ia64_pal_set_pstate (u64 pstate_index)
   4.271 +{
   4.272 +	struct ia64_pal_retval iprv;
   4.273 +	PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
   4.274 +	return iprv.status;
   4.275 +}
   4.276 +
   4.277 +/* Processor branding information*/
   4.278 +static inline s64
   4.279 +ia64_pal_get_brand_info (char *brand_info)
   4.280 +{
   4.281 +	struct ia64_pal_retval iprv;
   4.282 +	PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
   4.283 +	return iprv.status;
   4.284 +}
   4.285 +
   4.286  /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
   4.287   * suspended, but cache and TLB coherency is maintained.
   4.288   */
   4.289 @@ -1381,6 +1439,17 @@ ia64_pal_rse_info (u64 *num_phys_stacked
   4.290  	return iprv.status;
   4.291  }
   4.292  
   4.293 +/*
   4.294 + * Set the current hardware resource sharing policy of the processor
   4.295 + */
   4.296 +static inline s64
   4.297 +ia64_pal_set_hw_policy (u64 policy)
   4.298 +{
   4.299 +	struct ia64_pal_retval iprv;
   4.300 +	PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
   4.301 +	return iprv.status;
   4.302 +}
   4.303 +
   4.304  /* Cause the processor to enter	SHUTDOWN state, where prefetching and execution are
   4.305   * suspended, but cause cache and TLB coherency to be maintained.
   4.306   * This is usually called in IA-32 mode.
   4.307 @@ -1418,7 +1487,12 @@ typedef union  pal_version_u {
   4.308  } pal_version_u_t;
   4.309  
   4.310  
   4.311 -/* Return PAL version information */
   4.312 +/*
   4.313 + * Return PAL version information.  While the documentation states that
   4.314 + * PAL_VERSION can be called in either physical or virtual mode, some
   4.315 + * implementations only allow physical calls.  We don't call it very often,
   4.316 + * so the overhead isn't worth eliminating.
   4.317 + */
   4.318  static inline s64
   4.319  ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
   4.320  {
   4.321 @@ -1499,12 +1573,15 @@ typedef union pal_vm_info_1_u {
   4.322  	} pal_vm_info_1_s;
   4.323  } pal_vm_info_1_u_t;
   4.324  
   4.325 +#define PAL_MAX_PURGES		0xFFFF		/* all ones is means unlimited */
   4.326 +
   4.327  typedef union pal_vm_info_2_u {
   4.328  	u64			pvi2_val;
   4.329  	struct {
   4.330  		u64		impl_va_msb	: 8,
   4.331  				rid_size	: 8,
   4.332 -				reserved	: 48;
   4.333 +				max_purges	: 16,
   4.334 +				reserved	: 32;
   4.335  	} pal_vm_info_2_s;
   4.336  } pal_vm_info_2_u_t;
   4.337  
   4.338 @@ -1626,14 +1703,40 @@ ia64_pal_logical_to_phys(u64 proc_number
   4.339  
   4.340  	if (iprv.status == PAL_STATUS_SUCCESS)
   4.341  	{
   4.342 -		if (proc_number == 0)
   4.343 -			mapping->overview.overview_data = iprv.v0;
   4.344 +		mapping->overview.overview_data = iprv.v0;
   4.345  		mapping->ppli1.ppli1_data = iprv.v1;
   4.346  		mapping->ppli2.ppli2_data = iprv.v2;
   4.347  	}
   4.348  
   4.349  	return iprv.status;
   4.350  }
   4.351 +
   4.352 +typedef struct pal_cache_shared_info_s
   4.353 +{
   4.354 +	u64 num_shared;
   4.355 +	pal_proc_n_log_info1_t ppli1;
   4.356 +	pal_proc_n_log_info2_t ppli2;
   4.357 +} pal_cache_shared_info_t;
   4.358 +
   4.359 +/* Get information on logical to physical processor mappings. */
   4.360 +static inline s64
   4.361 +ia64_pal_cache_shared_info(u64 level,
   4.362 +		u64 type,
   4.363 +		u64 proc_number,
   4.364 +		pal_cache_shared_info_t *info)
   4.365 +{
   4.366 +	struct ia64_pal_retval iprv;
   4.367 +
   4.368 +	PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
   4.369 +
   4.370 +	if (iprv.status == PAL_STATUS_SUCCESS) {
   4.371 +		info->num_shared = iprv.v0;
   4.372 +		info->ppli1.ppli1_data = iprv.v1;
   4.373 +		info->ppli2.ppli2_data = iprv.v2;
   4.374 +	}
   4.375 +
   4.376 +	return iprv.status;
   4.377 +}
   4.378  #ifdef XEN
   4.379  #include <asm/vmx_pal.h>
   4.380  #endif