ia64/xen-unstable

changeset 10469:b025491f0ba8

[HVM] Clean up formatting of new piix acpi file.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Sat Jun 17 09:19:16 2006 +0100 (2006-06-17)
parents 58b374f76a71
children ef8cdd1dc836
files tools/ioemu/hw/piix4acpi.c
line diff
     1.1 --- a/tools/ioemu/hw/piix4acpi.c	Sat Jun 17 09:08:14 2006 +0100
     1.2 +++ b/tools/ioemu/hw/piix4acpi.c	Sat Jun 17 09:19:16 2006 +0100
     1.3 @@ -1,9 +1,9 @@
     1.4  /*
     1.5   * PIIX4 ACPI controller emulation
     1.6 - * 
     1.7 + *
     1.8   * Winston liwen Wang, winston.l.wang@intel.com
     1.9   * Copyright (c) 2006 , Intel Corporation.
    1.10 - * 
    1.11 + *
    1.12   * Permission is hereby granted, free of charge, to any person obtaining a copy
    1.13   * of this software and associated documentation files (the "Software"), to deal
    1.14   * in the Software without restriction, including without limitation the rights
    1.15 @@ -22,6 +22,7 @@
    1.16   * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    1.17   * THE SOFTWARE.
    1.18   */
    1.19 +
    1.20  #include "vl.h"
    1.21  #define FREQUENCE_PMTIMER  3753425
    1.22  /* acpi register bit define here  */
    1.23 @@ -44,15 +45,15 @@
    1.24  #define GBL_RLS           (1 << 2)
    1.25  #define SLP_EN   	  (1 << 13)
    1.26  
    1.27 -/* Bits of PM1a register define here  */ 
    1.28 +/* Bits of PM1a register define here  */
    1.29  #define SLP_TYP_MASK    0x1C00
    1.30  #define SLP_VAL         0x1C00
    1.31  
    1.32  typedef struct AcpiDeviceState AcpiDeviceState;
    1.33  AcpiDeviceState *acpi_device_table;
    1.34  
    1.35 -/* Bits of PM1a register define here  */											
    1.36 -typedef struct PMTState {    	  
    1.37 +/* Bits of PM1a register define here  */
    1.38 +typedef struct PMTState {
    1.39      uint32_t count;
    1.40      int irq;
    1.41      uint64_t next_pm_time;
    1.42 @@ -66,7 +67,7 @@ typedef struct PM1Event_BLK {
    1.43  
    1.44  typedef struct PCIAcpiState {
    1.45      PCIDevice dev;
    1.46 -    uint16_t irq;	
    1.47 +    uint16_t irq;
    1.48      uint16_t pm1_status; /* pm1a_EVT_BLK */
    1.49      uint16_t pm1_enable; /* pm1a_EVT_BLK+2 */
    1.50      uint16_t pm1_control; /* pm1a_ECNT_BLK */
    1.51 @@ -75,64 +76,58 @@ typedef struct PCIAcpiState {
    1.52  
    1.53  static PMTState *pmtimer_state;
    1.54  static PCIAcpiState *acpi_state;
    1.55 - 
    1.56 -static void pmtimer_save(QEMUFile *f, void *opaque)       
    1.57 +
    1.58 +static void pmtimer_save(QEMUFile *f, void *opaque)
    1.59  {
    1.60 -	 PMTState *s = opaque; 
    1.61 -	 
    1.62 -	 qemu_put_be32s(f, &s->count);
    1.63 -	 qemu_put_be32s(f, &s->irq);
    1.64 -         qemu_put_be64s(f, &s->next_pm_time);
    1.65 -	 qemu_put_timer(f, s->pm_timer);
    1.66 +    PMTState *s = opaque;
    1.67  
    1.68 +    qemu_put_be32s(f, &s->count);
    1.69 +    qemu_put_be32s(f, &s->irq);
    1.70 +    qemu_put_be64s(f, &s->next_pm_time);
    1.71 +    qemu_put_timer(f, s->pm_timer);
    1.72  }
    1.73  
    1.74  static int pmtimer_load(QEMUFile *f, void *opaque, int version_id)
    1.75  {
    1.76      PMTState *s = opaque;
    1.77  
    1.78 -         if (version_id != 1)
    1.79 -         return -EINVAL;
    1.80 -         qemu_get_be32s(f, &s->count);
    1.81 -         qemu_get_be32s(f, &s->irq);
    1.82 -         qemu_get_be64s(f, &s->next_pm_time);
    1.83 -         qemu_get_timer(f, s->pm_timer);
    1.84 -         return 0;
    1.85 -        
    1.86 +    if (version_id != 1)
    1.87 +        return -EINVAL;
    1.88 +    qemu_get_be32s(f, &s->count);
    1.89 +    qemu_get_be32s(f, &s->irq);
    1.90 +    qemu_get_be64s(f, &s->next_pm_time);
    1.91 +    qemu_get_timer(f, s->pm_timer);
    1.92 +    return 0;
    1.93 +
    1.94  }
    1.95  
    1.96  static inline void acpi_set_irq(PCIAcpiState *s)
    1.97  {
    1.98 -
    1.99  /* no real SCI event need for now, so comment the following line out */
   1.100 -/*        pic_set_irq(s->irq, 1);	*/
   1.101 -         printf("acpi_set_irq: s->irq %x \n",s->irq);
   1.102 -
   1.103 +/*  pic_set_irq(s->irq, 1); */
   1.104 +    printf("acpi_set_irq: s->irq %x \n",s->irq);
   1.105  }
   1.106  
   1.107  static void pm_timer_update(void *opaque)
   1.108  {
   1.109 -        PMTState *s = opaque;            
   1.110 -        s->next_pm_time += muldiv64(1, ticks_per_sec,FREQUENCE_PMTIMER);
   1.111 -        qemu_mod_timer(s->pm_timer, s->next_pm_time);
   1.112 -        acpi_state->pm1_timer ++;
   1.113 -           
   1.114 -        
   1.115 -    /* if pm timer is zero    reset it to zero;  */
   1.116 -        if (acpi_state->pm1_timer >= 0x1000000) 
   1.117 -        {
   1.118 -/*	    printf("pm_timerupdate: timer overflow: %x \n", acpi_state->pm1_timer); */
   1.119 +    PMTState *s = opaque;
   1.120 +    s->next_pm_time += muldiv64(1, ticks_per_sec,FREQUENCE_PMTIMER);
   1.121 +    qemu_mod_timer(s->pm_timer, s->next_pm_time);
   1.122 +    acpi_state->pm1_timer ++;
   1.123 +
   1.124 +    /* If pm timer is zero then reset it to zero. */
   1.125 +    if (acpi_state->pm1_timer >= 0x1000000) {
   1.126 +/*      printf("pm_timerupdate: timer overflow: %x \n", acpi_state->pm1_timer); */
   1.127  
   1.128 -              acpi_state->pm1_timer = 0;
   1.129 -              acpi_state->pm1_status =   acpi_state->pm1_status | TMROF_STS;
   1.130 -                      	//if  TMROF_EN is set send the irq
   1.131 -              if  ((acpi_state->pm1_enable & TMROF_EN) ==  TMROF_EN)
   1.132 -              {
   1.133 -               acpi_set_irq(acpi_state);
   1.134 -               acpi_state->pm1_enable = 0x00; /* only need one time...*/
   1.135 -              }
   1.136 +        acpi_state->pm1_timer = 0;
   1.137 +        acpi_state->pm1_status =   acpi_state->pm1_status | TMROF_STS;
   1.138 +        /* If TMROF_EN is set then send the irq. */
   1.139 +        if ((acpi_state->pm1_enable & TMROF_EN) == TMROF_EN) {
   1.140 +            acpi_set_irq(acpi_state);
   1.141 +            acpi_state->pm1_enable = 0x00; /* only need one time...*/
   1.142          }
   1.143 -        s->count = acpi_state->pm1_timer;
   1.144 +    }
   1.145 +    s->count = acpi_state->pm1_timer;
   1.146  }
   1.147  
   1.148  static PMTState *pmtimer_init(void)
   1.149 @@ -141,31 +136,31 @@ static PMTState *pmtimer_init(void)
   1.150  
   1.151      s = qemu_mallocz(sizeof(PMTState));
   1.152      if (!s)
   1.153 -        return NULL;        
   1.154 +        return NULL;
   1.155  
   1.156      /* s->irq = irq;    */
   1.157 -         
   1.158 +
   1.159      s->pm_timer = qemu_new_timer(vm_clock, pm_timer_update, s);
   1.160 - 
   1.161 +
   1.162      s->count = 0;
   1.163      s->next_pm_time = qemu_get_clock(vm_clock) + muldiv64(1, ticks_per_sec,FREQUENCE_PMTIMER) + 1;
   1.164      qemu_mod_timer(s->pm_timer, s->next_pm_time);
   1.165 - 
   1.166 +
   1.167      register_savevm("pm timer", 1, 1, pmtimer_save, pmtimer_load, s);
   1.168      return s;
   1.169  }
   1.170  
   1.171  static void acpi_reset(PCIAcpiState *s)
   1.172  {
   1.173 -    uint8_t *pci_conf;	
   1.174 +    uint8_t *pci_conf;
   1.175      pci_conf = s->dev.config;
   1.176  
   1.177 -    pci_conf[0x42] = 0x00;     
   1.178 -    pci_conf[0x43] = 0x00;	
   1.179 -    s->irq = 9; 
   1.180 -    s->pm1_status = 0; 
   1.181 -    s->pm1_enable = 0x00;   /*TMROF_EN	  should cleared */
   1.182 -    s->pm1_control = SCI_EN;/*SCI_EN */
   1.183 +    pci_conf[0x42] = 0x00;
   1.184 +    pci_conf[0x43] = 0x00;
   1.185 +    s->irq = 9;
   1.186 +    s->pm1_status = 0;
   1.187 +    s->pm1_enable = 0x00;    /* TMROF_EN should cleared */
   1.188 +    s->pm1_control = SCI_EN; /* SCI_EN */
   1.189      s->pm1_timer = 0;
   1.190  }
   1.191  
   1.192 @@ -173,131 +168,129 @@ static void acpi_reset(PCIAcpiState *s)
   1.193  static void acpiPm1Status_writeb(void *opaque, uint32_t addr, uint32_t val)
   1.194  {
   1.195      PCIAcpiState *s = opaque;
   1.196 +    
   1.197      if ((val&TMROF_STS)==TMROF_STS)
   1.198 -    s->pm1_status = s->pm1_status&!TMROF_STS;
   1.199 -     
   1.200 +        s->pm1_status = s->pm1_status&!TMROF_STS;
   1.201 +
   1.202      if ((val&GBL_STS)==GBL_STS)
   1.203 -    s->pm1_status = s->pm1_status&!GBL_STS;     
   1.204 -    
   1.205 +        s->pm1_status = s->pm1_status&!GBL_STS;
   1.206 +
   1.207  /*     printf("acpiPm1Status_writeb \n addr %x val:%x pm1_status:%x \n", addr, val,s->pm1_status); */
   1.208 -
   1.209 -} 
   1.210 +}
   1.211  
   1.212  static uint32_t acpiPm1Status_readb(void *opaque, uint32_t addr)
   1.213  {
   1.214      PCIAcpiState *s = opaque;
   1.215      uint32_t val;
   1.216  
   1.217 -    val = s->pm1_status;  
   1.218 +    val = s->pm1_status;
   1.219  /*         printf("acpiPm1Status_readb \n addr %x val:%x\n", addr, val); */
   1.220 -	
   1.221 +
   1.222     return val;
   1.223  }
   1.224  
   1.225  static void acpiPm1StatusP1_writeb(void *opaque, uint32_t addr, uint32_t val)
   1.226  {
   1.227      PCIAcpiState *s = opaque;
   1.228 -    
   1.229 -     s->pm1_status = (val<<8)||(s->pm1_status); 
   1.230 +
   1.231 +     s->pm1_status = (val<<8)||(s->pm1_status);
   1.232  /*     printf("acpiPm1StatusP1_writeb \n addr %x val:%x\n", addr, val); */
   1.233 -
   1.234 -} 
   1.235 +}
   1.236  
   1.237  static uint32_t acpiPm1StatusP1_readb(void *opaque, uint32_t addr)
   1.238  {
   1.239      PCIAcpiState *s = opaque;
   1.240      uint32_t val;
   1.241  
   1.242 -    val = (s->pm1_status)>>8;  
   1.243 +    val = (s->pm1_status)>>8;
   1.244      printf("acpiPm1StatusP1_readb \n addr %x val:%x\n", addr, val);
   1.245 -	
   1.246 -	return val;
   1.247 +
   1.248 +    return val;
   1.249  }
   1.250  
   1.251  static void acpiPm1Enable_writeb(void *opaque, uint32_t addr, uint32_t val)
   1.252  {
   1.253      PCIAcpiState *s = opaque;
   1.254 -    
   1.255 -    s->pm1_enable = val; 
   1.256 +
   1.257 +    s->pm1_enable = val;
   1.258  /*   printf("acpiPm1Enable_writeb \n addr %x val:%x\n", addr, val); */
   1.259 -
   1.260 -} 
   1.261 +}
   1.262  
   1.263  static uint32_t acpiPm1Enable_readb(void *opaque, uint32_t addr)
   1.264  {
   1.265      PCIAcpiState *s = opaque;
   1.266      uint32_t val;
   1.267  
   1.268 -    val = (s->pm1_enable)||0x1;  
   1.269 -/*    printf("acpiPm1Enable_readb \n addr %x val:%x\n", addr, val); */
   1.270 -	
   1.271 +    val = (s->pm1_enable)||0x1;
   1.272 +/*  printf("acpiPm1Enable_readb \n addr %x val:%x\n", addr, val); */
   1.273 +
   1.274      return val;
   1.275  }
   1.276 -		
   1.277 +
   1.278  static void acpiPm1EnableP1_writeb(void *opaque, uint32_t addr, uint32_t val)
   1.279  {
   1.280      PCIAcpiState *s = opaque;
   1.281 -    
   1.282 -    s->pm1_enable = (val<<8)||(s->pm1_enable); 
   1.283 +
   1.284 +    s->pm1_enable = (val<<8)||(s->pm1_enable);
   1.285  /*    printf("acpiPm1EnableP1_writeb \n addr %x val:%x\n", addr, val); */
   1.286  
   1.287 -} 
   1.288 +}
   1.289  
   1.290  static uint32_t acpiPm1EnableP1_readb(void *opaque, uint32_t addr)
   1.291  {
   1.292      PCIAcpiState *s = opaque;
   1.293      uint32_t val;
   1.294  
   1.295 -    val = (s->pm1_enable)>>8;  
   1.296 +    val = (s->pm1_enable)>>8;
   1.297  /*  printf("acpiPm1EnableP1_readb \n addr %x val:%x\n", addr, val); */
   1.298 -	
   1.299 +
   1.300      return val;
   1.301  }
   1.302  
   1.303  static void acpiPm1Control_writeb(void *opaque, uint32_t addr, uint32_t val)
   1.304  {
   1.305      PCIAcpiState *s = opaque;
   1.306 -    
   1.307 -    s->pm1_control = val; 
   1.308 +
   1.309 +    s->pm1_control = val;
   1.310  /*  printf("acpiPm1Control_writeb \n addr %x val:%x\n", addr, val); */
   1.311  
   1.312 -} 
   1.313 +}
   1.314  
   1.315  static uint32_t acpiPm1Control_readb(void *opaque, uint32_t addr)
   1.316  {
   1.317      PCIAcpiState *s = opaque;
   1.318      uint32_t val;
   1.319  
   1.320 -    val = s->pm1_control;  
   1.321 +    val = s->pm1_control;
   1.322  /*    printf("acpiPm1Control_readb \n addr %x val:%x\n", addr, val); */
   1.323 -	
   1.324 +
   1.325      return val;
   1.326  }
   1.327  
   1.328  static void acpiPm1ControlP1_writeb(void *opaque, uint32_t addr, uint32_t val)
   1.329  {
   1.330      PCIAcpiState *s = opaque;
   1.331 -    
   1.332 -    s->pm1_control = (val<<8)||(s->pm1_control); 
   1.333 +
   1.334 +    s->pm1_control = (val<<8)||(s->pm1_control);
   1.335  /*    printf("acpiPm1ControlP1_writeb \n addr %x val:%x\n", addr, val); */
   1.336  
   1.337      // Check for power off request
   1.338  
   1.339 -    if ( ( (val & SLP_EN) != 0) &&
   1.340 -         ( (val & SLP_TYP_MASK) == SLP_VAL) ) {
   1.341 -         s->pm1_timer=0x0; //clear ACPI timer
   1.342 -         qemu_system_shutdown_request();
   1.343 -      }
   1.344 -} 
   1.345 +    if (((val & SLP_EN) != 0) &&
   1.346 +        ((val & SLP_TYP_MASK) == SLP_VAL)) {
   1.347 +        s->pm1_timer=0x0; //clear ACPI timer
   1.348 +        qemu_system_shutdown_request();
   1.349 +    }
   1.350 +}
   1.351  
   1.352  static uint32_t acpiPm1ControlP1_readb(void *opaque, uint32_t addr)
   1.353  {
   1.354      PCIAcpiState *s = opaque;
   1.355      uint32_t val;
   1.356  
   1.357 -    val = (s->pm1_control)>>8;  
   1.358 +    val = (s->pm1_control)>>8;
   1.359  /*    printf("acpiPm1ControlP1_readb \n addr %x val:%x\n", addr, val); */
   1.360 -	
   1.361 +
   1.362      return val;
   1.363  }
   1.364  
   1.365 @@ -307,91 +300,91 @@ static uint32_t acpiPm1ControlP1_readb(v
   1.366  static void acpiPm1Status_writew(void *opaque, uint32_t addr, uint32_t val)
   1.367  {
   1.368      PCIAcpiState *s = opaque;
   1.369 +
   1.370      if ((val&TMROF_STS)==TMROF_STS)
   1.371 -    s->pm1_status = s->pm1_status&!TMROF_STS;
   1.372 -     
   1.373 +        s->pm1_status = s->pm1_status&!TMROF_STS;
   1.374 +
   1.375      if ((val&GBL_STS)==GBL_STS)
   1.376 -    s->pm1_status = s->pm1_status&!GBL_STS;     
   1.377 -    
   1.378 +        s->pm1_status = s->pm1_status&!GBL_STS;
   1.379 +
   1.380  /*    printf("acpiPm1Status_writew \n addr %x val:%x pm1_status:%x \n", addr, val,s->pm1_status); */
   1.381 -
   1.382 -} 
   1.383 +}
   1.384  
   1.385  static uint32_t acpiPm1Status_readw(void *opaque, uint32_t addr)
   1.386  {
   1.387      PCIAcpiState *s = opaque;
   1.388      uint32_t val;
   1.389  
   1.390 -    val = s->pm1_status;  
   1.391 +    val = s->pm1_status;
   1.392  /*    printf("acpiPm1Status_readw \n addr %x val:%x\n", addr, val); */
   1.393 -	
   1.394 +
   1.395      return val;
   1.396  }
   1.397  
   1.398  static void acpiPm1Enable_writew(void *opaque, uint32_t addr, uint32_t val)
   1.399  {
   1.400      PCIAcpiState *s = opaque;
   1.401 -    
   1.402 -    s->pm1_enable = val; 
   1.403 +
   1.404 +    s->pm1_enable = val;
   1.405  /*    printf("acpiPm1Enable_writew \n addr %x val:%x\n", addr, val); */
   1.406  
   1.407 -} 
   1.408 +}
   1.409  
   1.410  static uint32_t acpiPm1Enable_readw(void *opaque, uint32_t addr)
   1.411  {
   1.412      PCIAcpiState *s = opaque;
   1.413      uint32_t val;
   1.414  
   1.415 -    val = s->pm1_enable;  
   1.416 +    val = s->pm1_enable;
   1.417  /*    printf("acpiPm1Enable_readw \n addr %x val:%x\n", addr, val); */
   1.418 -	
   1.419 +
   1.420     return val;
   1.421  }
   1.422  
   1.423  static void acpiPm1Control_writew(void *opaque, uint32_t addr, uint32_t val)
   1.424  {
   1.425      PCIAcpiState *s = opaque;
   1.426 -    
   1.427 -    s->pm1_control = val; 
   1.428 +
   1.429 +    s->pm1_control = val;
   1.430  /*    printf("acpiPm1Control_writew \n addr %x val:%x\n", addr, val); */
   1.431  
   1.432      // Check for power off request
   1.433  
   1.434 -    if ( ( (val & SLP_EN) != 0) &&
   1.435 -        ( (val & SLP_TYP_MASK) == SLP_VAL) ) {
   1.436 -         qemu_system_shutdown_request();
   1.437 -      }
   1.438 +    if (((val & SLP_EN) != 0) &&
   1.439 +        ((val & SLP_TYP_MASK) == SLP_VAL)) {
   1.440 +        qemu_system_shutdown_request();
   1.441 +    }
   1.442  
   1.443 -} 
   1.444 +}
   1.445  
   1.446  static uint32_t acpiPm1Control_readw(void *opaque, uint32_t addr)
   1.447  {
   1.448      PCIAcpiState *s = opaque;
   1.449      uint32_t val;
   1.450  
   1.451 -    val = s->pm1_control;  
   1.452 +    val = s->pm1_control;
   1.453  /*    printf("acpiPm1Control_readw \n addr %x val:%x\n", addr, val);  */
   1.454 -	
   1.455 +
   1.456      return val;
   1.457  }
   1.458  
   1.459  /* dword access */
   1.460 -															
   1.461 +
   1.462  static void acpiPm1Event_writel(void *opaque, uint32_t addr, uint32_t val)
   1.463  {
   1.464      PCIAcpiState *s = opaque;
   1.465 -    
   1.466 -    s->pm1_status = val; 
   1.467 +
   1.468 +    s->pm1_status = val;
   1.469      s->pm1_enable = val>>16;
   1.470  /*     printf("acpiPm1Event_writel \n addr %x val:%x \n", addr, val); */
   1.471 -      
   1.472 -} 
   1.473 +
   1.474 +}
   1.475  
   1.476  static uint32_t acpiPm1Event_readl(void *opaque, uint32_t addr)
   1.477  {
   1.478      PCIAcpiState *s = opaque;
   1.479      uint32_t val;
   1.480 -    
   1.481 +
   1.482      val = s->pm1_status|(s->pm1_enable<<16);
   1.483  /*    printf("acpiPm1Event_readl \n addr %x val:%x\n", addr, val);    */
   1.484  
   1.485 @@ -401,89 +394,88 @@ static uint32_t acpiPm1Event_readl(void 
   1.486  static void acpiPm1Timer_writel(void *opaque, uint32_t addr, uint32_t val)
   1.487  {
   1.488      PCIAcpiState *s = opaque;
   1.489 -    
   1.490 -    s->pm1_timer = val; 
   1.491 +
   1.492 +    s->pm1_timer = val;
   1.493  /*    printf("acpiPm1Timer_writel \n addr %x val:%x\n", addr, val); */
   1.494 -
   1.495 -} 
   1.496 +}
   1.497  
   1.498  static uint32_t acpiPm1Timer_readl(void *opaque, uint32_t addr)
   1.499  {
   1.500      PCIAcpiState *s = opaque;
   1.501      uint32_t val;
   1.502  
   1.503 -    val = s->pm1_timer;  
   1.504 +    val = s->pm1_timer;
   1.505  /*    printf("acpiPm1Timer_readl \n addr %x val:%x\n", addr, val); */
   1.506      return val;
   1.507  }
   1.508  
   1.509 -static void acpi_map(PCIDevice *pci_dev, int region_num, 
   1.510 +static void acpi_map(PCIDevice *pci_dev, int region_num,
   1.511                      uint32_t addr, uint32_t size, int type)
   1.512  {
   1.513 -       PCIAcpiState *d = (PCIAcpiState *)pci_dev;
   1.514 -       printf("register acpi io \n ");
   1.515 -       /*Byte access		*/
   1.516 -       register_ioport_write(addr, 1, 1, acpiPm1Status_writeb, d);
   1.517 -       register_ioport_read(addr, 1, 1, acpiPm1Status_readb, d);
   1.518 -       register_ioport_write(addr+1, 1, 1, acpiPm1StatusP1_writeb, d);
   1.519 -       register_ioport_read(addr+1, 1, 1, acpiPm1StatusP1_readb, d);
   1.520 +    PCIAcpiState *d = (PCIAcpiState *)pci_dev;
   1.521 +
   1.522 +    printf("register acpi io\n");
   1.523 +
   1.524 +    /* Byte access */
   1.525 +    register_ioport_write(addr, 1, 1, acpiPm1Status_writeb, d);
   1.526 +    register_ioport_read(addr, 1, 1, acpiPm1Status_readb, d);
   1.527 +    register_ioport_write(addr+1, 1, 1, acpiPm1StatusP1_writeb, d);
   1.528 +    register_ioport_read(addr+1, 1, 1, acpiPm1StatusP1_readb, d);
   1.529  
   1.530 -       register_ioport_write(addr + 2, 1, 1, acpiPm1Enable_writeb, d);
   1.531 -       register_ioport_read(addr + 2, 1, 1, acpiPm1Enable_readb, d);
   1.532 -       register_ioport_write(addr + 2 +1, 1, 1, acpiPm1EnableP1_writeb, d);
   1.533 -       register_ioport_read(addr + 2 +1, 1, 1, acpiPm1EnableP1_readb, d);
   1.534 +    register_ioport_write(addr + 2, 1, 1, acpiPm1Enable_writeb, d);
   1.535 +    register_ioport_read(addr + 2, 1, 1, acpiPm1Enable_readb, d);
   1.536 +    register_ioport_write(addr + 2 +1, 1, 1, acpiPm1EnableP1_writeb, d);
   1.537 +    register_ioport_read(addr + 2 +1, 1, 1, acpiPm1EnableP1_readb, d);
   1.538  
   1.539 -       register_ioport_write(addr + 4, 1, 1, acpiPm1Control_writeb, d);
   1.540 -       register_ioport_read(addr + 4, 1, 1, acpiPm1Control_readb, d);
   1.541 -       register_ioport_write(addr + 4 + 1, 1, 1, acpiPm1ControlP1_writeb, d);
   1.542 -       register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d);	
   1.543 +    register_ioport_write(addr + 4, 1, 1, acpiPm1Control_writeb, d);
   1.544 +    register_ioport_read(addr + 4, 1, 1, acpiPm1Control_readb, d);
   1.545 +    register_ioport_write(addr + 4 + 1, 1, 1, acpiPm1ControlP1_writeb, d);
   1.546 +    register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d);
   1.547  
   1.548 -	/* word access */
   1.549 -        register_ioport_write(addr, 2, 2, acpiPm1Status_writew, d);
   1.550 -        register_ioport_read(addr, 2, 2, acpiPm1Status_readw, d);
   1.551 +    /* Word access */
   1.552 +    register_ioport_write(addr, 2, 2, acpiPm1Status_writew, d);
   1.553 +    register_ioport_read(addr, 2, 2, acpiPm1Status_readw, d);
   1.554  
   1.555 -        register_ioport_write(addr + 2, 2, 2, acpiPm1Enable_writew, d);
   1.556 -        register_ioport_read(addr + 2, 2, 2, acpiPm1Enable_readw, d); 
   1.557 +    register_ioport_write(addr + 2, 2, 2, acpiPm1Enable_writew, d);
   1.558 +    register_ioport_read(addr + 2, 2, 2, acpiPm1Enable_readw, d);
   1.559  
   1.560 -        register_ioport_write(addr + 4, 2, 2, acpiPm1Control_writew, d);
   1.561 -        register_ioport_read(addr + 4, 2, 2, acpiPm1Control_readw, d);
   1.562 +    register_ioport_write(addr + 4, 2, 2, acpiPm1Control_writew, d);
   1.563 +    register_ioport_read(addr + 4, 2, 2, acpiPm1Control_readw, d);
   1.564  
   1.565 -       /* dword access */
   1.566 -        register_ioport_write(addr, 4, 4, acpiPm1Event_writel, d);
   1.567 -        register_ioport_read(addr, 4, 4, acpiPm1Event_readl, d);
   1.568 -		
   1.569 -        register_ioport_write(addr + 8, 4, 4, acpiPm1Timer_writel, d);
   1.570 -        register_ioport_read(addr + 8, 4, 4, acpiPm1Timer_readl, d);
   1.571 +    /* DWord access */
   1.572 +    register_ioport_write(addr, 4, 4, acpiPm1Event_writel, d);
   1.573 +    register_ioport_read(addr, 4, 4, acpiPm1Event_readl, d);
   1.574 +
   1.575 +    register_ioport_write(addr + 8, 4, 4, acpiPm1Timer_writel, d);
   1.576 +    register_ioport_read(addr + 8, 4, 4, acpiPm1Timer_readl, d);
   1.577  }
   1.578 -													
   1.579  
   1.580 -/*  PIIX4 acpi pci configuration space, func 3 */
   1.581 +/* PIIX4 acpi pci configuration space, func 3 */
   1.582  void pci_piix4_acpi_init(PCIBus *bus)
   1.583  {
   1.584 -    PCIAcpiState *d;//,*s;
   1.585 -    uint8_t *pci_conf;//,*pci_conf_usb;
   1.586 +    PCIAcpiState *d;
   1.587 +    uint8_t *pci_conf;
   1.588  
   1.589      /* register a function 3 of PIIX4 */
   1.590 -    d = (PCIAcpiState *)pci_register_device(bus, "PIIX4 ACPI",
   1.591 -                                           sizeof(PCIAcpiState),
   1.592 -                                           ((PCIDevice *)piix3_state)->devfn + 3,
   1.593 -                                           NULL, NULL);
   1.594 +    d = (PCIAcpiState *)pci_register_device(
   1.595 +        bus, "PIIX4 ACPI", sizeof(PCIAcpiState),
   1.596 +        ((PCIDevice *)piix3_state)->devfn + 3, NULL, NULL);
   1.597 +
   1.598      acpi_state = d;
   1.599      pci_conf = d->dev.config;
   1.600 -    pci_conf[0x00] = 0x86; // Intel
   1.601 +    pci_conf[0x00] = 0x86;  /* Intel */
   1.602      pci_conf[0x01] = 0x80;
   1.603      pci_conf[0x02] = 0x13;
   1.604      pci_conf[0x03] = 0x71;
   1.605 -    pci_conf[0x08] = 0x01;  //B0 stepping
   1.606 -    pci_conf[0x09] = 0x00;  //base class
   1.607 -    pci_conf[0x0a] = 0x80;  //Sub class
   1.608 +    pci_conf[0x08] = 0x01;  /* B0 stepping */
   1.609 +    pci_conf[0x09] = 0x00;  /* base class */
   1.610 +    pci_conf[0x0a] = 0x80;  /* Sub class */
   1.611      pci_conf[0x0b] = 0x06;
   1.612      pci_conf[0x0e] = 0x00;
   1.613 -    pci_conf[0x3d] = 0x01; // Hardwired to PIRQA is used
   1.614 -								  
   1.615 -    pci_register_io_region((PCIDevice *)d, 4, 0x10, 
   1.616 +    pci_conf[0x3d] = 0x01;  /* Hardwired to PIRQA is used */
   1.617 +
   1.618 +    pci_register_io_region((PCIDevice *)d, 4, 0x10,
   1.619                             PCI_ADDRESS_SPACE_IO, acpi_map);
   1.620      pmtimer_state = pmtimer_init();
   1.621 -    acpi_reset (d);  
   1.622 -
   1.623 +    acpi_reset (d);
   1.624  }