ia64/xen-unstable

changeset 16121:ac37f61f6908

svm: allow guest to use EFER.FFXSE
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
author Keir Fraser <keir@xensource.com>
date Fri Oct 12 11:00:26 2007 +0100 (2007-10-12)
parents 4746c8c9372f
children e66147d054cf
files xen/arch/x86/hvm/hvm.c xen/arch/x86/hvm/svm/svm.c xen/include/asm-x86/cpufeature.h xen/include/asm-x86/msr-index.h
line diff
     1.1 --- a/xen/arch/x86/hvm/hvm.c	Fri Oct 12 10:19:55 2007 +0100
     1.2 +++ b/xen/arch/x86/hvm/hvm.c	Fri Oct 12 11:00:26 2007 +0100
     1.3 @@ -358,10 +358,12 @@ static int hvm_load_cpu_ctxt(struct doma
     1.4          return -EINVAL;
     1.5      }
     1.6  
     1.7 -    if ( (ctxt.msr_efer & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE)) ||
     1.8 +    if ( (ctxt.msr_efer & ~(EFER_FFXSE | EFER_LME | EFER_LMA |
     1.9 +                            EFER_NX | EFER_SCE)) ||
    1.10           ((sizeof(long) != 8) && (ctxt.msr_efer & EFER_LME)) ||
    1.11           (!cpu_has_nx && (ctxt.msr_efer & EFER_NX)) ||
    1.12           (!cpu_has_syscall && (ctxt.msr_efer & EFER_SCE)) ||
    1.13 +         (!cpu_has_ffxsr && (ctxt.msr_efer & EFER_FFXSE)) ||
    1.14           ((ctxt.msr_efer & (EFER_LME|EFER_LMA)) == EFER_LMA) )
    1.15      {
    1.16          gdprintk(XENLOG_ERR, "HVM restore: bad EFER 0x%"PRIx64"\n",
    1.17 @@ -576,10 +578,11 @@ int hvm_set_efer(uint64_t value)
    1.18  
    1.19      value &= ~EFER_LMA;
    1.20  
    1.21 -    if ( (value & ~(EFER_LME | EFER_NX | EFER_SCE)) ||
    1.22 +    if ( (value & ~(EFER_FFXSE | EFER_LME | EFER_NX | EFER_SCE)) ||
    1.23           ((sizeof(long) != 8) && (value & EFER_LME)) ||
    1.24           (!cpu_has_nx && (value & EFER_NX)) ||
    1.25 -         (!cpu_has_syscall && (value & EFER_SCE)) )
    1.26 +         (!cpu_has_syscall && (value & EFER_SCE)) ||
    1.27 +         (!cpu_has_ffxsr && (value & EFER_FFXSE)) )
    1.28      {
    1.29          gdprintk(XENLOG_WARNING, "Trying to set reserved bit in "
    1.30                   "EFER: %"PRIx64"\n", value);
     2.1 --- a/xen/arch/x86/hvm/svm/svm.c	Fri Oct 12 10:19:55 2007 +0100
     2.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Fri Oct 12 11:00:26 2007 +0100
     2.3 @@ -1036,8 +1036,6 @@ static void svm_vmexit_do_cpuid(struct v
     2.4          /* So far, we do not support 3DNow for the guest. */
     2.5          clear_bit(X86_FEATURE_3DNOW & 31, &edx);
     2.6          clear_bit(X86_FEATURE_3DNOWEXT & 31, &edx);
     2.7 -        /* no FFXSR instructions feature. */
     2.8 -        clear_bit(X86_FEATURE_FFXSR & 31, &edx);
     2.9      }
    2.10      else if ( input == 0x80000007 || input == 0x8000000A )
    2.11      {
     3.1 --- a/xen/include/asm-x86/cpufeature.h	Fri Oct 12 10:19:55 2007 +0100
     3.2 +++ b/xen/include/asm-x86/cpufeature.h	Fri Oct 12 11:00:26 2007 +0100
     3.3 @@ -49,6 +49,7 @@
     3.4  #define X86_FEATURE_MP		(1*32+19) /* MP Capable. */
     3.5  #define X86_FEATURE_NX		(1*32+20) /* Execute Disable */
     3.6  #define X86_FEATURE_MMXEXT	(1*32+22) /* AMD MMX extensions */
     3.7 +#define X86_FEATURE_FFXSR       (1*32+25) /* FFXSR instruction optimizations */
     3.8  #define X86_FEATURE_RDTSCP	(1*32+27) /* RDTSCP */
     3.9  #define X86_FEATURE_LM		(1*32+29) /* Long Mode (x86-64) */
    3.10  #define X86_FEATURE_3DNOWEXT	(1*32+30) /* AMD 3DNow! extensions */
    3.11 @@ -94,7 +95,6 @@
    3.12  #define X86_FEATURE_LAHF_LM	(6*32+ 0) /* LAHF/SAHF in long mode */
    3.13  #define X86_FEATURE_CMP_LEGACY	(6*32+ 1) /* If yes HyperThreading not valid */
    3.14  #define X86_FEATURE_SVME        (6*32+ 2) /* Secure Virtual Machine */
    3.15 -#define X86_FEATURE_FFXSR       (6*32+25) /* FFXSR instruction optimizations */
    3.16  
    3.17  #define cpu_has(c, bit)		test_bit(bit, (c)->x86_capability)
    3.18  #define boot_cpu_has(bit)	test_bit(bit, boot_cpu_data.x86_capability)
    3.19 @@ -147,6 +147,9 @@
    3.20  #define cpu_has_clflush		boot_cpu_has(X86_FEATURE_CLFLSH)
    3.21  #endif
    3.22  
    3.23 +#define cpu_has_ffxsr           ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) \
    3.24 +                                 && boot_cpu_has(X86_FEATURE_FFXSR))
    3.25 +
    3.26  #endif /* __ASM_I386_CPUFEATURE_H */
    3.27  
    3.28  /* 
     4.1 --- a/xen/include/asm-x86/msr-index.h	Fri Oct 12 10:19:55 2007 +0100
     4.2 +++ b/xen/include/asm-x86/msr-index.h	Fri Oct 12 11:00:26 2007 +0100
     4.3 @@ -18,13 +18,17 @@
     4.4  #define _EFER_LME		8  /* Long mode enable */
     4.5  #define _EFER_LMA		10 /* Long mode active (read-only) */
     4.6  #define _EFER_NX		11 /* No execute enable */
     4.7 -#define _EFER_SVME		12
     4.8 +#define _EFER_SVME		12 /* AMD: SVM enable */
     4.9 +#define _EFER_LMSLE		13 /* AMD: Long-mode segment limit enable */
    4.10 +#define _EFER_FFXSE		14 /* AMD: Fast FXSAVE/FXRSTOR enable */
    4.11  
    4.12  #define EFER_SCE		(1<<_EFER_SCE)
    4.13  #define EFER_LME		(1<<_EFER_LME)
    4.14  #define EFER_LMA		(1<<_EFER_LMA)
    4.15  #define EFER_NX			(1<<_EFER_NX)
    4.16  #define EFER_SVME		(1<<_EFER_SVME)
    4.17 +#define EFER_LMSLE		(1<<_EFER_LMSLE)
    4.18 +#define EFER_FFXSE		(1<<_EFER_FFXSE)
    4.19  
    4.20  /* Intel MSRs. Some also available on other CPUs */
    4.21  #define MSR_IA32_PERFCTR0		0x000000c1