ia64/xen-unstable

changeset 11933:aa8ca06d209e

[IA64] xenctx shows more registers for ia64

This patch adds more user registers to show them to xenctx for ia64.
Tested domU/domVTi on ia64.

Sample is the below.
# ./xenctx 1 0
iip: e000000000000810
ipsr: 00001012087a6010 b0: a000000100068a70
b6: a00000010014ff60 b7: e000000000000800
cr_ifs: 800000000000050a ar_unat: 0000000000000000
ar_pfs: 8000000000000209 ar_rsc: 0000000000000008
ar_rnat: 0000000000000000 ar_bspstore: a000000100c19030
ar_fpsr: 0009804c8a70433f event_callback_ip: a000000100067a20
pr: 000000000005aa85 loadrs: 0000000000780000
iva: a000000100008000 dcr: 0000000000007e04

r1: a0000001010369a0
r2: 0000000000001000 r3: 8000000000000209
r4: 0000000000000000 r5: 0000000000000000
r6: 0000000000000000 r7: 0000000000000000
r8: a000000100068a70 r9: 0000000000000100
r10: 0000000000000000 r11: 0000000000050ac5
sp: a000000100c1fd80 tp: a000000100c18000
r14: 0000000000000001 r15: 0000000000000000
r16: fffffffffff04c18 r17: a000000100c1fdb0
r18: a000000100c1fdb1 r19: a000000100c1fe90
r20: a000000100c1fe10 r21: 0000000000000000
r22: 0000000000000001 r23: 0000000000000000
r24: a000000100e5a448 r25: a000000100c18f10
r26: ffffffffffff0030 r27: 0000000000000000
r28: 000000000000001d r29: 0000000000000000
r30: 0000000000000000 r31: 0000000000000000

itr: P rid va pa ps ed pl ar a d ma key
[0] 1 000005 a000000100000000 0000004000000 1a 64M 1 2 3 1 1 0 WB 000000
[1] 1 000007 e000000000000000 0000000000000 18 16M 1 2 3 1 1 0 WB 000000
[2] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[3] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[4] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[5] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[6] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[7] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000

dtr: P rid va pa ps ed pl ar a d ma key
[0] 1 000005 a000000100000000 0000004000000 1a 64M 1 2 3 1 1 0 WB 000000
[1] 1 000007 ffffffffffff0000 0000000010000 10 64K 1 2 3 1 1 0 WB 000000
[2] 1 000007 e000000000000000 0000000000000 18 16M 1 2 3 1 1 0 WB 000000
[3] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[4] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[5] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[6] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[7] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000

Signed-off-by: Akio Takebe <takebe_akio@jp.fujitsu.com>
Signed-off-by: Masaki Kanno <kanno.masaki@jp.fujitsu.com>
author awilliam@xenbuild.aw
date Tue Oct 24 10:08:30 2006 -0600 (2006-10-24)
parents 9e9d8696fb55
children d246b79986d1
files tools/xentrace/xenctx.c
line diff
     1.1 --- a/tools/xentrace/xenctx.c	Tue Oct 24 09:49:31 2006 -0600
     1.2 +++ b/tools/xentrace/xenctx.c	Tue Oct 24 10:08:30 2006 -0600
     1.3 @@ -268,16 +268,68 @@ void print_ctx(vcpu_guest_context_t *ctx
     1.4  
     1.5  }
     1.6  #elif defined(__ia64__)
     1.7 +
     1.8 +#define PTE_ED_SHIFT              52
     1.9 +#define PTE_ED_MASK                1
    1.10 +#define PTE_PPN_SHIFT             12
    1.11 +#define PTE_PPN_MASK    0x3fffffffff
    1.12 +#define PTE_AR_SHIFT               9
    1.13 +#define PTE_AR_MASK                7
    1.14 +#define PTE_PL_SHIFT               7
    1.15 +#define PTE_PL_MASK                3
    1.16 +#define PTE_D_SHIFT                6
    1.17 +#define PTE_D_MASK                 1
    1.18 +#define PTE_A_SHIFT                5
    1.19 +#define PTE_A_MASK                 1
    1.20 +#define PTE_MA_SHIFT               2
    1.21 +#define PTE_MA_MASK                7
    1.22 +#define PTE_P_SHIFT                0
    1.23 +#define PTE_P_MASK                 1
    1.24 +#define ITIR_KEY_SHIFT             8
    1.25 +#define ITIR_KEY_MASK       0xffffff
    1.26 +#define ITIR_PS_SHIFT              2
    1.27 +#define ITIR_PS_MASK            0x3f
    1.28 +#define ITIR_PS_MIN               12
    1.29 +#define ITIR_PS_MAX               28
    1.30 +#define RR_RID_SHIFT               8
    1.31 +#define RR_RID_MASK         0xffffff
    1.32 +
    1.33  void print_ctx(vcpu_guest_context_t *ctx1)
    1.34  {
    1.35      struct cpu_user_regs *regs = &ctx1->user_regs;
    1.36 +    struct vcpu_extra_regs *er = &ctx1->extra_regs;
    1.37 +    int i, ps_val, ma_val;
    1.38 +    unsigned long pa;
    1.39  
    1.40 -    printf("iip:  %016lx  ", regs->cr_iip);
    1.41 +    const char ps[][5] = {"  4K", "  8K", " 16K", "    ",
    1.42 +                          " 64K", "    ", "256K", "    ",
    1.43 +                          "  1M", "    ", "  4M", "    ",
    1.44 +                          " 16M", "    ", " 64M", "    ",
    1.45 +                          "256M"};
    1.46 +    const char ma[][4] = {"WB ", "   ", "   ", "   ",
    1.47 +                          "UC ", "UCE", "WC ", "Nat"};
    1.48 +
    1.49 +    printf(" iip:               %016lx  ", regs->cr_iip);
    1.50      print_symbol(regs->cr_iip);
    1.51      printf("\n");
    1.52 -    printf("psr:  %016lu  ", regs->cr_ipsr);
    1.53 -    printf(" b0:  %016lx\n", regs->b0);
    1.54 +    printf(" ipsr:              %016lx  ", regs->cr_ipsr);
    1.55 +    printf(" b0:                %016lx\n", regs->b0);
    1.56 +    printf(" b6:                %016lx  ", regs->b6);
    1.57 +    printf(" b7:                %016lx\n", regs->b7);
    1.58 +    printf(" cr_ifs:            %016lx  ", regs->cr_ifs);
    1.59 +    printf(" ar_unat:           %016lx\n", regs->ar_unat);
    1.60 +    printf(" ar_pfs:            %016lx  ", regs->ar_pfs);
    1.61 +    printf(" ar_rsc:            %016lx\n", regs->ar_rsc);
    1.62 +    printf(" ar_rnat:           %016lx  ", regs->ar_rnat);
    1.63 +    printf(" ar_bspstore:       %016lx\n", regs->ar_bspstore);
    1.64 +    printf(" ar_fpsr:           %016lx  ", regs->ar_fpsr);
    1.65 +    printf(" event_callback_ip: %016lx\n", er->event_callback_ip);
    1.66 +    printf(" pr:                %016lx  ", regs->pr);
    1.67 +    printf(" loadrs:            %016lx\n", regs->loadrs);
    1.68 +    printf(" iva:               %016lx  ", er->iva);
    1.69 +    printf(" dcr:               %016lx\n", er->dcr);
    1.70  
    1.71 +    printf("\n");
    1.72      printf(" r1:  %016lx\n", regs->r1);
    1.73      printf(" r2:  %016lx  ", regs->r2);
    1.74      printf(" r3:  %016lx\n", regs->r3);
    1.75 @@ -310,6 +362,52 @@ void print_ctx(vcpu_guest_context_t *ctx
    1.76      printf(" r30: %016lx  ", regs->r30);
    1.77      printf(" r31: %016lx\n", regs->r31);
    1.78      
    1.79 +    printf("\n itr: P rid    va               pa            ps      ed pl "
    1.80 +           "ar a d ma    key\n");
    1.81 +    for (i = 0; i < 8; i++) {
    1.82 +        ps_val =  er->itrs[i].itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
    1.83 +        ma_val =  er->itrs[i].pte  >> PTE_MA_SHIFT  & PTE_MA_MASK;
    1.84 +        pa     = (er->itrs[i].pte  >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
    1.85 +                 PTE_PPN_SHIFT;
    1.86 +        pa     = (pa >> ps_val) << ps_val;
    1.87 +        printf(" [%d]  %ld %06lx %016lx %013lx %02x %s %ld  %ld  %ld  %ld "
    1.88 +               "%ld %d %s %06lx\n", i,
    1.89 +               er->itrs[i].pte  >> PTE_P_SHIFT    & PTE_P_MASK,
    1.90 +               er->itrs[i].rid  >> RR_RID_SHIFT   & RR_RID_MASK,
    1.91 +               er->itrs[i].vadr, pa, ps_val,
    1.92 +               ((ps_val >= ITIR_PS_MIN && ps_val <= ITIR_PS_MAX) ?
    1.93 +                ps[ps_val - ITIR_PS_MIN] : "    "),
    1.94 +               er->itrs[i].pte  >> PTE_ED_SHIFT   & PTE_ED_MASK,
    1.95 +               er->itrs[i].pte  >> PTE_PL_SHIFT   & PTE_PL_MASK,
    1.96 +               er->itrs[i].pte  >> PTE_AR_SHIFT   & PTE_AR_MASK,
    1.97 +               er->itrs[i].pte  >> PTE_A_SHIFT    & PTE_A_MASK,
    1.98 +               er->itrs[i].pte  >> PTE_D_SHIFT    & PTE_D_MASK,
    1.99 +               ma_val, ma[ma_val],
   1.100 +               er->itrs[i].itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
   1.101 +    }
   1.102 +    printf("\n dtr: P rid    va               pa            ps      ed pl "
   1.103 +           "ar a d ma    key\n");
   1.104 +    for (i = 0; i < 8; i++) {
   1.105 +        ps_val =  er->dtrs[i].itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
   1.106 +        ma_val =  er->dtrs[i].pte  >> PTE_MA_SHIFT  & PTE_MA_MASK;
   1.107 +        pa     = (er->dtrs[i].pte  >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
   1.108 +                 PTE_PPN_SHIFT;
   1.109 +        pa     = (pa >> ps_val) << ps_val;
   1.110 +        printf(" [%d]  %ld %06lx %016lx %013lx %02x %s %ld  %ld  %ld  %ld "
   1.111 +               "%ld %d %s %06lx\n", i,
   1.112 +               er->dtrs[i].pte  >> PTE_P_SHIFT    & PTE_P_MASK,
   1.113 +               er->dtrs[i].rid  >> RR_RID_SHIFT   & RR_RID_MASK,
   1.114 +               er->dtrs[i].vadr, pa, ps_val,
   1.115 +               ((ps_val >= ITIR_PS_MIN && ps_val <= ITIR_PS_MAX) ?
   1.116 +                ps[ps_val - ITIR_PS_MIN] : "    "),
   1.117 +               er->dtrs[i].pte  >> PTE_ED_SHIFT   & PTE_ED_MASK,
   1.118 +               er->dtrs[i].pte  >> PTE_PL_SHIFT   & PTE_PL_MASK,
   1.119 +               er->dtrs[i].pte  >> PTE_AR_SHIFT   & PTE_AR_MASK,
   1.120 +               er->dtrs[i].pte  >> PTE_A_SHIFT    & PTE_A_MASK,
   1.121 +               er->dtrs[i].pte  >> PTE_D_SHIFT    & PTE_D_MASK,
   1.122 +               ma_val, ma[ma_val],
   1.123 +               er->dtrs[i].itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
   1.124 +    }
   1.125  }
   1.126  #endif
   1.127