ia64/xen-unstable

changeset 6740:aa1adbeecfcd

With this patch, 32-bit binary can work on 64-bit VMX guest.

Signed-off-by: Chengyuan Li <chengyuan.li@intel.com>
Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
Signed-off-by: Asit Mallick <asit.k.mallick@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Sat Sep 10 14:24:39 2005 +0000 (2005-09-10)
parents 20b6be0e1fa1
children 864d936a0482
files xen/arch/x86/vmx.c
line diff
     1.1 --- a/xen/arch/x86/vmx.c	Sat Sep 10 14:22:12 2005 +0000
     1.2 +++ b/xen/arch/x86/vmx.c	Sat Sep 10 14:24:39 2005 +0000
     1.3 @@ -1394,21 +1394,20 @@ static int vmx_cr_access(unsigned long e
     1.4  
     1.5  static inline void vmx_do_msr_read(struct cpu_user_regs *regs)
     1.6  {
     1.7 +    u64 msr_content = 0;
     1.8 +
     1.9      VMX_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read: ecx=%lx, eax=%lx, edx=%lx",
    1.10                  (unsigned long)regs->ecx, (unsigned long)regs->eax, 
    1.11                  (unsigned long)regs->edx);
    1.12      switch (regs->ecx) {
    1.13          case MSR_IA32_SYSENTER_CS:
    1.14 -            __vmread(GUEST_SYSENTER_CS, &regs->eax);
    1.15 -            regs->edx = 0;
    1.16 +            __vmread(GUEST_SYSENTER_CS, (u32 *)&msr_content);
    1.17              break;
    1.18 -        case MSR_IA32_SYSENTER_ESP:	
    1.19 -             __vmread(GUEST_SYSENTER_ESP, &regs->eax);
    1.20 -             regs->edx = 0;
    1.21 +        case MSR_IA32_SYSENTER_ESP:
    1.22 +             __vmread(GUEST_SYSENTER_ESP, &msr_content);
    1.23              break;
    1.24 -        case MSR_IA32_SYSENTER_EIP:		
    1.25 -            __vmread(GUEST_SYSENTER_EIP, &regs->eax);
    1.26 -            regs->edx = 0;
    1.27 +        case MSR_IA32_SYSENTER_EIP:
    1.28 +            __vmread(GUEST_SYSENTER_EIP, &msr_content);
    1.29              break;
    1.30          default:
    1.31              if(long_mode_do_msr_read(regs))
    1.32 @@ -1417,6 +1416,9 @@ static inline void vmx_do_msr_read(struc
    1.33              break;
    1.34      }
    1.35  
    1.36 +    regs->eax = msr_content & 0xFFFFFFFF;
    1.37 +    regs->edx = msr_content >> 32;
    1.38 +
    1.39      VMX_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read returns: "
    1.40                  "ecx=%lx, eax=%lx, edx=%lx",
    1.41                  (unsigned long)regs->ecx, (unsigned long)regs->eax,
    1.42 @@ -1425,18 +1427,23 @@ static inline void vmx_do_msr_read(struc
    1.43  
    1.44  static inline void vmx_do_msr_write(struct cpu_user_regs *regs)
    1.45  {
    1.46 +    u64 msr_content;
    1.47 +
    1.48      VMX_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write: ecx=%lx, eax=%lx, edx=%lx",
    1.49                  (unsigned long)regs->ecx, (unsigned long)regs->eax, 
    1.50                  (unsigned long)regs->edx);
    1.51 +
    1.52 +    msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);
    1.53 +
    1.54      switch (regs->ecx) {
    1.55          case MSR_IA32_SYSENTER_CS:
    1.56 -            __vmwrite(GUEST_SYSENTER_CS, regs->eax);
    1.57 +            __vmwrite(GUEST_SYSENTER_CS, msr_content);
    1.58              break;
    1.59 -        case MSR_IA32_SYSENTER_ESP:	
    1.60 -             __vmwrite(GUEST_SYSENTER_ESP, regs->eax);
    1.61 +        case MSR_IA32_SYSENTER_ESP:
    1.62 +             __vmwrite(GUEST_SYSENTER_ESP, msr_content);
    1.63              break;
    1.64 -        case MSR_IA32_SYSENTER_EIP:		
    1.65 -            __vmwrite(GUEST_SYSENTER_EIP, regs->eax);
    1.66 +        case MSR_IA32_SYSENTER_EIP:
    1.67 +            __vmwrite(GUEST_SYSENTER_EIP, msr_content);
    1.68              break;
    1.69          default:
    1.70              long_mode_do_msr_write(regs);