ia64/xen-unstable

changeset 16378:a7f8ff1ca311

x86: Do not read/write EFER MSR if it doesn't exist.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir@xensource.com>
date Tue Nov 13 20:08:39 2007 +0000 (2007-11-13)
parents 44f24d717299
children ba69fe2dce91
files xen/arch/x86/acpi/power.c xen/arch/x86/boot/head.S xen/arch/x86/setup.c xen/arch/x86/smpboot.c xen/arch/x86/x86_32/asm-offsets.c xen/arch/x86/x86_64/asm-offsets.c xen/include/asm-x86/cpufeature.h
line diff
     1.1 --- a/xen/arch/x86/acpi/power.c	Tue Nov 13 19:26:55 2007 +0000
     1.2 +++ b/xen/arch/x86/acpi/power.c	Tue Nov 13 20:08:39 2007 +0000
     1.3 @@ -166,7 +166,8 @@ static int enter_state(u32 state)
     1.4  
     1.5      /* Restore CR4 and EFER from cached values. */
     1.6      write_cr4(read_cr4());
     1.7 -    write_efer(read_efer());
     1.8 +    if ( cpu_has_efer )
     1.9 +        write_efer(read_efer());
    1.10  
    1.11      device_power_up();
    1.12  
     2.1 --- a/xen/arch/x86/boot/head.S	Tue Nov 13 19:26:55 2007 +0000
     2.2 +++ b/xen/arch/x86/boot/head.S	Tue Nov 13 20:08:39 2007 +0000
     2.3 @@ -98,6 +98,7 @@ gdt_boot_descr:
     2.4          mov     $0x80000001,%eax
     2.5          cpuid
     2.6  1:      mov     %edx,sym_phys(cpuid_ext_features)
     2.7 +        mov     %edx,sym_phys(boot_cpu_data)+CPUINFO_ext_features
     2.8  
     2.9  #if defined(__x86_64__)
    2.10          /* Check for availability of long mode. */
     3.1 --- a/xen/arch/x86/setup.c	Tue Nov 13 19:26:55 2007 +0000
     3.2 +++ b/xen/arch/x86/setup.c	Tue Nov 13 20:08:39 2007 +0000
     3.3 @@ -416,7 +416,8 @@ void __init __start_xen(unsigned long mb
     3.4      set_current((struct vcpu *)0xfffff000); /* debug sanity */
     3.5      idle_vcpu[0] = current;
     3.6      set_processor_id(0); /* needed early, for smp_processor_id() */
     3.7 -    rdmsrl(MSR_EFER, this_cpu(efer));
     3.8 +    if ( cpu_has_efer )
     3.9 +        rdmsrl(MSR_EFER, this_cpu(efer));
    3.10      asm volatile ( "mov %%cr4,%0" : "=r" (this_cpu(cr4)) );
    3.11  
    3.12      smp_prepare_boot_cpu();
     4.1 --- a/xen/arch/x86/smpboot.c	Tue Nov 13 19:26:55 2007 +0000
     4.2 +++ b/xen/arch/x86/smpboot.c	Tue Nov 13 20:08:39 2007 +0000
     4.3 @@ -495,7 +495,8 @@ void __devinit start_secondary(void *unu
     4.4  	set_processor_id(cpu);
     4.5  	set_current(idle_vcpu[cpu]);
     4.6  	this_cpu(curr_vcpu) = idle_vcpu[cpu];
     4.7 -	rdmsrl(MSR_EFER, this_cpu(efer));
     4.8 +        if ( cpu_has_efer )
     4.9 +            rdmsrl(MSR_EFER, this_cpu(efer));
    4.10  	asm volatile ( "mov %%cr4,%0" : "=r" (this_cpu(cr4)) );
    4.11  
    4.12  	percpu_traps_init();
     5.1 --- a/xen/arch/x86/x86_32/asm-offsets.c	Tue Nov 13 19:26:55 2007 +0000
     5.2 +++ b/xen/arch/x86/x86_32/asm-offsets.c	Tue Nov 13 20:08:39 2007 +0000
     5.3 @@ -115,4 +115,7 @@ void __dummy__(void)
     5.4      BLANK();
     5.5  
     5.6      DEFINE(IRQSTAT_shift, LOG_2(sizeof(irq_cpustat_t)));
     5.7 +    BLANK();
     5.8 +
     5.9 +    OFFSET(CPUINFO_ext_features, struct cpuinfo_x86, x86_capability[1]);
    5.10  }
     6.1 --- a/xen/arch/x86/x86_64/asm-offsets.c	Tue Nov 13 19:26:55 2007 +0000
     6.2 +++ b/xen/arch/x86/x86_64/asm-offsets.c	Tue Nov 13 20:08:39 2007 +0000
     6.3 @@ -137,4 +137,7 @@ void __dummy__(void)
     6.4  #endif
     6.5  
     6.6      DEFINE(IRQSTAT_shift, LOG_2(sizeof(irq_cpustat_t)));
     6.7 +    BLANK();
     6.8 +
     6.9 +    OFFSET(CPUINFO_ext_features, struct cpuinfo_x86, x86_capability[1]);
    6.10  }
     7.1 --- a/xen/include/asm-x86/cpufeature.h	Tue Nov 13 19:26:55 2007 +0000
     7.2 +++ b/xen/include/asm-x86/cpufeature.h	Tue Nov 13 20:08:39 2007 +0000
     7.3 @@ -146,6 +146,7 @@
     7.4  #define cpu_has_centaur_mcr	boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
     7.5  #define cpu_has_clflush		boot_cpu_has(X86_FEATURE_CLFLSH)
     7.6  #define cpu_has_page1gb		0
     7.7 +#define cpu_has_efer		(boot_cpu_data.x86_capability[1] & 0x20100800)
     7.8  #else /* __x86_64__ */
     7.9  #define cpu_has_vme		0
    7.10  #define cpu_has_de		1
    7.11 @@ -171,6 +172,7 @@
    7.12  #define cpu_has_centaur_mcr	0
    7.13  #define cpu_has_clflush		boot_cpu_has(X86_FEATURE_CLFLSH)
    7.14  #define cpu_has_page1gb		boot_cpu_has(X86_FEATURE_PAGE1GB)
    7.15 +#define cpu_has_efer		1
    7.16  #endif
    7.17  
    7.18  #define cpu_has_ffxsr           ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) \