ia64/xen-unstable

changeset 5807:a6b64aed65c3

Properly implement PAL_PTCE_INFO for Xen
Pull out PAL_VM_SUMMARY, reimplement later
Turn off ar.unat code in fast paths by default for now
Fix vcpu_fc
Signed-off by: Dan Magenheimer <dan.magenheimer@hp.com>
author djm@kirby.fc.hp.com
date Mon Jul 18 11:48:21 2005 -0700 (2005-07-18)
parents 816b9b3ced2f
children 00a05c6a0acc
files xen/arch/ia64/dom_fw.c xen/arch/ia64/domain.c xen/arch/ia64/hyperprivop.S xen/arch/ia64/vcpu.c
line diff
     1.1 --- a/xen/arch/ia64/dom_fw.c	Fri Jul 15 15:27:06 2005 -0700
     1.2 +++ b/xen/arch/ia64/dom_fw.c	Mon Jul 18 11:48:21 2005 -0700
     1.3 @@ -314,12 +314,10 @@ xen_pal_emulator(unsigned long index, un
     1.4  		break;
     1.5  	    case PAL_PTCE_INFO:
     1.6  		{
     1.7 -			ia64_ptce_info_t ptce;
     1.8 -			status = ia64_get_ptce(&ptce);
     1.9 -			if (status != 0) break;
    1.10 -			r9 = ptce.base;
    1.11 -			r10 = (ptce.count[0]<<32)|(ptce.count[1]&0xffffffffL);
    1.12 -			r11 = (ptce.stride[0]<<32)|(ptce.stride[1]&0xffffffffL);
    1.13 +			// return hard-coded xen-specific values because ptc.e
    1.14 +			// is emulated on xen to always flush everything
    1.15 +			// these values result in only one ptc.e instruction
    1.16 +			status = 0; r9 = 0; r10 = (1L << 32) | 1L; r11 = 0;
    1.17  		}
    1.18  		break;
    1.19  	    case PAL_VERSION:
    1.20 @@ -335,7 +333,10 @@ xen_pal_emulator(unsigned long index, un
    1.21  		status = ia64_pal_cache_summary(&r9,&r10);
    1.22  		break;
    1.23  	    case PAL_VM_SUMMARY:
    1.24 -		status = ia64_pal_vm_summary(&r9,&r10);
    1.25 +		// FIXME: what should xen return for these, figure out later
    1.26 +		// For now, linux does the right thing if pal call fails
    1.27 +		// In particular, rid_size must be set properly!
    1.28 +		//status = ia64_pal_vm_summary(&r9,&r10);
    1.29  		break;
    1.30  	    case PAL_RSE_INFO:
    1.31  		status = ia64_pal_rse_info(&r9,&r10);
     2.1 --- a/xen/arch/ia64/domain.c	Fri Jul 15 15:27:06 2005 -0700
     2.2 +++ b/xen/arch/ia64/domain.c	Mon Jul 18 11:48:21 2005 -0700
     2.3 @@ -311,7 +311,7 @@ int arch_set_info_guest(struct vcpu *v, 
     2.4  	init_all_rr(v);
     2.5  
     2.6  	// this should be in userspace
     2.7 -	regs->r28 = dom_fw_setup(v->domain,"nomca nosmp xencons=tty0 console=tty0",256L);  //FIXME
     2.8 +	regs->r28 = dom_fw_setup(v->domain,"nomca nosmp xencons=tty0 console=tty0 root=/dev/sda1",256L);  //FIXME
     2.9  	v->vcpu_info->arch.banknum = 1;
    2.10  	v->vcpu_info->arch.metaphysical_mode = 1;
    2.11  	v->arch.domain_itm_last = -1L;
     3.1 --- a/xen/arch/ia64/hyperprivop.S	Fri Jul 15 15:27:06 2005 -0700
     3.2 +++ b/xen/arch/ia64/hyperprivop.S	Mon Jul 18 11:48:21 2005 -0700
     3.3 @@ -23,9 +23,13 @@
     3.4  #define FAST_ACCESS_REFLECT
     3.5  #define FAST_RFI
     3.6  #define FAST_SSM_I
     3.7 +#define FAST_PTC_GA
     3.8  #undef RFI_TO_INTERRUPT // not working yet
     3.9  #endif
    3.10  
    3.11 +// FIXME: turn off for now... fix zero'ing regs, should be bank1?
    3.12 +//#define HANDLE_AR_UNAT
    3.13 +
    3.14  // FIXME: This is defined in include/asm-ia64/hw_irq.h but this
    3.15  // doesn't appear to be include'able from assembly?
    3.16  #define IA64_TIMER_VECTOR 0xef
    3.17 @@ -430,7 +434,10 @@ GLOBAL_ENTRY(fast_tick_reflect)
    3.18  	add r24=r24,r23;;
    3.19  	mov cr.iip=r24;;
    3.20  	// OK, now all set to go except for switch to virtual bank0
    3.21 -	mov r30=r2; mov r29=r3;; mov r28=ar.unat;
    3.22 +	mov r30=r2; mov r29=r3;;
    3.23 +#ifdef HANDLE_AR_UNAT
    3.24 +	mov r28=ar.unat;
    3.25 +#endif
    3.26  	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
    3.27  	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
    3.28  	bsw.1;;
    3.29 @@ -452,11 +459,14 @@ GLOBAL_ENTRY(fast_tick_reflect)
    3.30  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
    3.31  	movl r31=XSI_IPSR;;
    3.32  	bsw.0 ;;
    3.33 +	mov r2=r30; mov r3=r29;;
    3.34 +#ifdef HANDLE_AR_UNAT
    3.35  	// bank0 regs have no NaT bit, so ensure they are NaT clean
    3.36  	mov r16=r0; mov r17=r0; mov r19=r0;
    3.37  	mov r21=r0; mov r22=r0; mov r23=r0;
    3.38  	mov r24=r0; mov r25=r0; mov r26=r0; mov r27=r0;
    3.39 -	mov r2=r30; mov r3=r29; mov ar.unat=r28;
    3.40 +	mov ar.unat=r28;
    3.41 +#endif
    3.42  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    3.43  	st4 [r20]=r0 ;;
    3.44  fast_tick_reflect_done:
    3.45 @@ -575,7 +585,10 @@ ENTRY(fast_reflect)
    3.46  	add r20=r20,r23;;
    3.47  	mov cr.iip=r20;;
    3.48  	// OK, now all set to go except for switch to virtual bank0
    3.49 -	mov r30=r2; mov r29=r3;; mov r28=ar.unat;
    3.50 +	mov r30=r2; mov r29=r3;;
    3.51 +#ifdef HANDLE_AR_UNAT
    3.52 +	mov r28=ar.unat;
    3.53 +#endif
    3.54  	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
    3.55  	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
    3.56  	bsw.1;;
    3.57 @@ -597,11 +610,14 @@ ENTRY(fast_reflect)
    3.58  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
    3.59  	movl r31=XSI_IPSR;;
    3.60  	bsw.0 ;;
    3.61 +	mov r2=r30; mov r3=r29;;
    3.62 +#ifdef HANDLE_AR_UNAT
    3.63  	// bank0 regs have no NaT bit, so ensure they are NaT clean
    3.64  	mov r16=r0; mov r17=r0; mov r19=r0;
    3.65  	mov r21=r0; mov r22=r0; mov r23=r0;
    3.66  	mov r24=r0; mov r25=r0; mov r26=r0; mov r27=r0;
    3.67 -	mov r2=r30; mov r3=r29; mov ar.unat=r28;
    3.68 +	mov ar.unat=r28;
    3.69 +#endif
    3.70  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    3.71  	st4 [r20]=r0 ;;
    3.72  	mov pr=r31,-1 ;;
    3.73 @@ -1477,6 +1493,9 @@ ENTRY(hyper_ptc_ga)
    3.74  #ifdef CONFIG_SMP
    3.75  FIXME: ptc.ga instruction requires spinlock for SMP
    3.76  #endif
    3.77 +#ifndef FAST_PTC_GA
    3.78 +	br.spnt.few dispatch_break_fault ;;
    3.79 +#endif
    3.80  	// FIXME: validate not flushing Xen addresses
    3.81  #ifdef FAST_HYPERPRIVOP_CNT
    3.82  	movl r20=fast_hyperpriv_cnt+(8*XEN_HYPER_PTC_GA);;
     4.1 --- a/xen/arch/ia64/vcpu.c	Fri Jul 15 15:27:06 2005 -0700
     4.2 +++ b/xen/arch/ia64/vcpu.c	Mon Jul 18 11:48:21 2005 -0700
     4.3 @@ -214,6 +214,7 @@ IA64FAULT vcpu_set_psr_sm(VCPU *vcpu, UI
     4.4  	if (imm.ic)  PSCB(vcpu,interrupt_collection_enabled) = 1;
     4.5  	// TODO: do this faster
     4.6  	if (imm.mfl) { ipsr->mfl = 1; psr.mfl = 1; }
     4.7 +	if (imm.mfh) { ipsr->mfh = 1; psr.mfh = 1; }
     4.8  	if (imm.ac) { ipsr->ac = 1; psr.ac = 1; }
     4.9  	if (imm.up) { ipsr->up = 1; psr.up = 1; }
    4.10  	if (imm.be) {
    4.11 @@ -262,6 +263,7 @@ IA64FAULT vcpu_set_psr_l(VCPU *vcpu, UIN
    4.12  	}
    4.13  	if (newpsr.ic)  PSCB(vcpu,interrupt_collection_enabled) = 1;
    4.14  	if (newpsr.mfl) { ipsr->mfl = 1; psr.mfl = 1; }
    4.15 +	if (newpsr.mfh) { ipsr->mfh = 1; psr.mfh = 1; }
    4.16  	if (newpsr.ac) { ipsr->ac = 1; psr.ac = 1; }
    4.17  	if (newpsr.up) { ipsr->up = 1; psr.up = 1; }
    4.18  	if (newpsr.dt && newpsr.rt) vcpu_set_metaphysical_mode(vcpu,FALSE);
    4.19 @@ -1263,7 +1265,6 @@ IA64FAULT vcpu_ttag(VCPU *vcpu, UINT64 v
    4.20  #define itir_mask(itir) (~((1UL << itir_ps(itir)) - 1))
    4.21  
    4.22  unsigned long vhpt_translate_count = 0;
    4.23 -int in_vcpu_tpa = 0;
    4.24  
    4.25  IA64FAULT vcpu_translate(VCPU *vcpu, UINT64 address, BOOLEAN is_data, UINT64 *pteval, UINT64 *itir)
    4.26  {
    4.27 @@ -1278,12 +1279,6 @@ IA64FAULT vcpu_translate(VCPU *vcpu, UIN
    4.28  			unsigned long vipsr = PSCB(vcpu,ipsr);
    4.29  			unsigned long iip = regs->cr_iip;
    4.30  			unsigned long ipsr = regs->cr_ipsr;
    4.31 -#if 0
    4.32 -			printk("vcpu_translate: bad address %p, viip=%p, vipsr=%p, iip=%p, ipsr=%p\n", address, viip, vipsr, iip, ipsr);
    4.33 -			if (in_vcpu_tpa) printk("vcpu_translate called from vcpu_tpa\n");
    4.34 -			while(1);
    4.35 -			panic_domain(0,"vcpu_translate: bad address %p\n", address);
    4.36 -#endif
    4.37  			printk("vcpu_translate: bad address %p, viip=%p, vipsr=%p, iip=%p, ipsr=%p continuing\n", address, viip, vipsr, iip, ipsr);
    4.38  		}
    4.39  
    4.40 @@ -1304,7 +1299,6 @@ IA64FAULT vcpu_translate(VCPU *vcpu, UIN
    4.41  	/* check 1-entry TLB */
    4.42  	if ((trp = match_dtlb(vcpu,address))) {
    4.43  		dtlb_translate_count++;
    4.44 -if (!in_vcpu_tpa) printf("vcpu_translate: found in vdtlb\n");
    4.45  		*pteval = trp->page_flags;
    4.46  		*itir = trp->itir;
    4.47  		return IA64_NO_FAULT;
    4.48 @@ -1356,9 +1350,7 @@ IA64FAULT vcpu_tpa(VCPU *vcpu, UINT64 va
    4.49  	UINT64 pteval, itir, mask;
    4.50  	IA64FAULT fault;
    4.51  
    4.52 -in_vcpu_tpa=1;
    4.53  	fault = vcpu_translate(vcpu, vadr, 1, &pteval, &itir);
    4.54 -in_vcpu_tpa=0;
    4.55  	if (fault == IA64_NO_FAULT)
    4.56  	{
    4.57  		mask = itir_mask(itir);
    4.58 @@ -1785,49 +1777,26 @@ IA64FAULT vcpu_ptc_l(VCPU *vcpu, UINT64 
    4.59  IA64FAULT vcpu_fc(VCPU *vcpu, UINT64 vadr)
    4.60  {
    4.61  	// TODO: Only allowed for current vcpu
    4.62 -	UINT64 mpaddr, ps;
    4.63 +	UINT64 mpaddr, paddr;
    4.64  	IA64FAULT fault;
    4.65 -	TR_ENTRY *trp;
    4.66 -	unsigned long lookup_domain_mpa(struct domain *,unsigned long);
    4.67 -	unsigned long pteval, dom_imva;
    4.68 +	unsigned long translate_domain_mpaddr(unsigned long);
    4.69 +	IA64FAULT vcpu_tpa(VCPU *, UINT64, UINT64 *);
    4.70  
    4.71 -	if ((trp = match_dtlb(vcpu,vadr))) {
    4.72 -		pteval = trp->page_flags;
    4.73 -		dom_imva = __va(pteval & _PFN_MASK);
    4.74 -		ia64_fc(dom_imva);
    4.75 -		return IA64_NO_FAULT;
    4.76 -	}
    4.77  	fault = vcpu_tpa(vcpu, vadr, &mpaddr);
    4.78  	if (fault == IA64_NO_FAULT) {
    4.79 -		struct domain *dom0;
    4.80 -		unsigned long dom0_start, dom0_size;
    4.81 -		if (vcpu == dom0) {
    4.82 -			if (mpaddr < dom0_start || mpaddr >= dom0_start + dom0_size) {
    4.83 -				printk("vcpu_fc: bad dom0 mpaddr %p!\n",mpaddr);
    4.84 -			}
    4.85 -		}
    4.86 -		pteval = lookup_domain_mpa(vcpu->domain,mpaddr);
    4.87 -		if (pteval) {
    4.88 -			dom_imva = __va(pteval & _PFN_MASK);
    4.89 -			ia64_fc(dom_imva);
    4.90 -		}
    4.91 -		else {
    4.92 -			REGS *regs = vcpu_regs(vcpu);
    4.93 -			printk("vcpu_fc: can't flush vadr=%p, iip=%p\n",
    4.94 -					vadr,regs->cr_iip);
    4.95 -		}
    4.96 +		paddr = translate_domain_mpaddr(mpaddr);
    4.97 +		ia64_fc(__va(paddr));
    4.98  	}
    4.99  	return fault;
   4.100  }
   4.101  
   4.102 +int ptce_count = 0;
   4.103  IA64FAULT vcpu_ptc_e(VCPU *vcpu, UINT64 vadr)
   4.104  {
   4.105 -
   4.106  	// Note that this only needs to be called once, i.e. the
   4.107  	// architected loop to purge the entire TLB, should use
   4.108  	//  base = stride1 = stride2 = 0, count0 = count 1 = 1
   4.109  
   4.110 -	// FIXME: When VHPT is in place, flush that too!
   4.111  #ifdef VHPT_GLOBAL
   4.112  	vhpt_flush();	// FIXME: This is overdoing it
   4.113  #endif
   4.114 @@ -1850,6 +1819,7 @@ IA64FAULT vcpu_ptc_ga(VCPU *vcpu,UINT64 
   4.115  	// FIXME: validate not flushing Xen addresses
   4.116  	// if (Xen address) return(IA64_ILLOP_FAULT);
   4.117  	// FIXME: ??breaks if domain PAGE_SIZE < Xen PAGE_SIZE
   4.118 +//printf("######## vcpu_ptc_ga(%p,%p) ##############\n",vadr,addr_range);
   4.119  #ifdef VHPT_GLOBAL
   4.120  	vhpt_flush_address(vadr,addr_range);
   4.121  #endif