ia64/xen-unstable

changeset 18121:a0ce4b040114

Revert accidental commit from 18096:fa66b33f975a8f
author Keir Fraser <keir.fraser@citrix.com>
date Mon Jul 21 10:00:18 2008 +0100 (2008-07-21)
parents c433ee4844fb
children 85a83b919653
files xen/arch/x86/time.c
line diff
     1.1 --- a/xen/arch/x86/time.c	Mon Jul 21 09:49:40 2008 +0100
     1.2 +++ b/xen/arch/x86/time.c	Mon Jul 21 10:00:18 2008 +0100
     1.3 @@ -481,46 +481,6 @@ static int init_pmtimer(struct platform_
     1.4  }
     1.5  
     1.6  /************************************************************
     1.7 - * PLATFORM TIMER 5: TSC
     1.8 - */
     1.9 -
    1.10 -#define platform_timer_is_tsc() (!strcmp(plt_src.name, "TSC"))
    1.11 -static u64 tsc_freq;
    1.12 -
    1.13 -static u64 read_tsc_count(void)
    1.14 -{
    1.15 -    u64 tsc;
    1.16 -    rdtscll(tsc);
    1.17 -    return tsc;
    1.18 -}
    1.19 -
    1.20 -static int init_tsctimer(struct platform_timesource *pts)
    1.21 -{
    1.22 -    unsigned int cpu;
    1.23 -
    1.24 -    /*
    1.25 -     * TODO: evaluate stability of TSC here, return 0 if not stable.
    1.26 -     * For now we assume all TSCs are synchronised and hence can all share
    1.27 -     * CPU 0's calibration values.
    1.28 -     */
    1.29 -    for_each_cpu ( cpu )
    1.30 -    {
    1.31 -        if ( cpu == 0 )
    1.32 -            continue;
    1.33 -        memcpy(&per_cpu(cpu_time, cpu),
    1.34 -               &per_cpu(cpu_time, 0),
    1.35 -               sizeof(struct cpu_time));
    1.36 -    }
    1.37 -
    1.38 -    pts->name = "TSC";
    1.39 -    pts->frequency = tsc_freq;
    1.40 -    pts->read_counter = read_tsc_count;
    1.41 -    pts->counter_bits = 64;
    1.42 -
    1.43 -    return 1;
    1.44 -}
    1.45 -
    1.46 -/************************************************************
    1.47   * GENERIC PLATFORM TIMER INFRASTRUCTURE
    1.48   */
    1.49  
    1.50 @@ -605,8 +565,6 @@ static void init_platform_timer(void)
    1.51              rc = init_cyclone(pts);
    1.52          else if ( !strcmp(opt_clocksource, "acpi") )
    1.53              rc = init_pmtimer(pts);
    1.54 -        else if ( !strcmp(opt_clocksource, "tsc") )
    1.55 -            rc = init_tsctimer(pts);
    1.56  
    1.57          if ( rc <= 0 )
    1.58              printk("WARNING: %s clocksource '%s'.\n",
    1.59 @@ -822,10 +780,6 @@ int cpu_frequency_change(u64 freq)
    1.60      struct cpu_time *t = &this_cpu(cpu_time);
    1.61      u64 curr_tsc;
    1.62  
    1.63 -    /* Nothing to do if TSC is platform timer. Assume it is constant-rate. */
    1.64 -    if ( platform_timer_is_tsc() )
    1.65 -        return 0;
    1.66 -
    1.67      /* Sanity check: CPU frequency allegedly dropping below 1MHz? */
    1.68      if ( freq < 1000000u )
    1.69      {
    1.70 @@ -1024,9 +978,6 @@ void init_percpu_time(void)
    1.71      unsigned long flags;
    1.72      s_time_t now;
    1.73  
    1.74 -    if ( platform_timer_is_tsc() )
    1.75 -        return;
    1.76 -
    1.77      local_irq_save(flags);
    1.78      rdtscll(t->local_tsc_stamp);
    1.79      now = !plt_src.read_counter ? 0 : read_platform_stime();
    1.80 @@ -1047,11 +998,11 @@ int __init init_xen_time(void)
    1.81  
    1.82      local_irq_disable();
    1.83  
    1.84 +    init_percpu_time();
    1.85 +
    1.86      stime_platform_stamp = 0;
    1.87      init_platform_timer();
    1.88  
    1.89 -    init_percpu_time();
    1.90 -
    1.91      /* check if TSC is invariant during deep C state
    1.92         this is a new feature introduced by Nehalem*/
    1.93      if ( cpuid_edx(0x80000007) & (1U<<8) )
    1.94 @@ -1068,7 +1019,6 @@ void __init early_time_init(void)
    1.95  {
    1.96      u64 tmp = init_pit_and_calibrate_tsc();
    1.97  
    1.98 -    tsc_freq = tmp;
    1.99      set_time_scale(&this_cpu(cpu_time).tsc_scale, tmp);
   1.100  
   1.101      do_div(tmp, 1000);