ia64/xen-unstable

changeset 18797:a0910b1b5ec0

x86: don't disable MSI in order to mask an IRQ

... as that's not really correct, and there are devices which can't
even cope with that. Instead, check whether an MSI IRQ can be masked,
and if it can't, treat it just like a level triggered IO-APIC IRQ.

There's one other bug fix in here, correcting an off-by-one error on
the entry_nr range check in __pci_enable_msix().

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Nov 13 16:31:08 2008 +0000 (2008-11-13)
parents d44ad6db638c
children 3ba83def85a2
files xen/arch/x86/irq.c xen/arch/x86/msi.c xen/include/asm-x86/msi.h
line diff
     1.1 --- a/xen/arch/x86/irq.c	Thu Nov 13 14:19:56 2008 +0000
     1.2 +++ b/xen/arch/x86/irq.c	Thu Nov 13 16:31:08 2008 +0000
     1.3 @@ -463,14 +463,19 @@ int pirq_acktype(struct domain *d, int i
     1.4      /*
     1.5       * Edge-triggered IO-APIC and LAPIC interrupts need no final
     1.6       * acknowledgement: we ACK early during interrupt processing.
     1.7 -     * MSIs are treated as edge-triggered interrupts.
     1.8       */
     1.9      if ( !strcmp(desc->handler->typename, "IO-APIC-edge") ||
    1.10 -         !strcmp(desc->handler->typename, "local-APIC-edge") ||
    1.11 -         !strcmp(desc->handler->typename, "PCI-MSI") )
    1.12 +         !strcmp(desc->handler->typename, "local-APIC-edge") )
    1.13          return ACKTYPE_NONE;
    1.14  
    1.15      /*
    1.16 +     * MSIs are treated as edge-triggered interrupts, except
    1.17 +     * when there is no proper way to mask them.
    1.18 +     */
    1.19 +    if ( desc->handler == &pci_msi_type )
    1.20 +        return msi_maskable_irq(desc->msi_desc) ? ACKTYPE_NONE : ACKTYPE_EOI;
    1.21 +
    1.22 +    /*
    1.23       * Level-triggered IO-APIC interrupts need to be acknowledged on the CPU
    1.24       * on which they were received. This is because we tickle the LAPIC to EOI.
    1.25       */
     2.1 --- a/xen/arch/x86/msi.c	Thu Nov 13 14:19:56 2008 +0000
     2.2 +++ b/xen/arch/x86/msi.c	Thu Nov 13 16:31:08 2008 +0000
     2.3 @@ -298,6 +298,13 @@ static void msix_flush_writes(unsigned i
     2.4      }
     2.5  }
     2.6  
     2.7 +int msi_maskable_irq(const struct msi_desc *entry)
     2.8 +{
     2.9 +    BUG_ON(!entry);
    2.10 +    return entry->msi_attrib.type != PCI_CAP_ID_MSI
    2.11 +           || entry->msi_attrib.maskbit;
    2.12 +}
    2.13 +
    2.14  static void msi_set_mask_bit(unsigned int irq, int flag)
    2.15  {
    2.16      struct msi_desc *entry = irq_desc[irq].msi_desc;
    2.17 @@ -318,8 +325,6 @@ static void msi_set_mask_bit(unsigned in
    2.18              mask_bits &= ~(1);
    2.19              mask_bits |= flag;
    2.20              pci_conf_write32(bus, slot, func, pos, mask_bits);
    2.21 -        } else {
    2.22 -            msi_set_enable(entry->dev, !flag);
    2.23          }
    2.24          break;
    2.25      case PCI_CAP_ID_MSIX:
    2.26 @@ -649,7 +654,7 @@ static int __pci_enable_msix(struct msi_
    2.27      pos = pci_find_cap_offset(msi->bus, slot, func, PCI_CAP_ID_MSIX);
    2.28      control = pci_conf_read16(msi->bus, slot, func, msi_control_reg(pos));
    2.29      nr_entries = multi_msix_capable(control);
    2.30 -    if (msi->entry_nr > nr_entries)
    2.31 +    if (msi->entry_nr >= nr_entries)
    2.32      {
    2.33          spin_unlock(&pdev->lock);
    2.34          return -EINVAL;
     3.1 --- a/xen/include/asm-x86/msi.h	Thu Nov 13 14:19:56 2008 +0000
     3.2 +++ b/xen/include/asm-x86/msi.h	Thu Nov 13 16:31:08 2008 +0000
     3.3 @@ -97,6 +97,8 @@ struct msi_desc {
     3.4  	int remap_index;		/* index in interrupt remapping table */
     3.5  };
     3.6  
     3.7 +int msi_maskable_irq(const struct msi_desc *);
     3.8 +
     3.9  /*
    3.10   * Assume the maximum number of hot plug slots supported by the system is about
    3.11   * ten. The worstcase is that each of these slots is hot-added with a device,