ia64/xen-unstable
changeset 4312:a01199a95070
bitkeeper revision 1.1264 (4243449d-JwBVsSinjAWdYveMNhEjQ)
Initial attempt at merging shadow code with head of unstable tree.
Signed-off-by: michael.fetterman@cl.cam.ac.uk
Initial attempt at merging shadow code with head of unstable tree.
Signed-off-by: michael.fetterman@cl.cam.ac.uk
line diff
1.1 --- a/.hgtags Thu Mar 24 22:01:38 2005 +0000 1.2 +++ b/.hgtags Thu Mar 24 22:52:13 2005 +0000 1.3 @@ -3,6 +3,7 @@ 475a162b66e2c19b1e9468b234a4ba705334905e 1.4 dc2f08429f17e6614fd2f1ab88cc09ca0a850f32 RELEASE-2.0.2 1.5 6e1bbc13911751efa0b1c018425c1b085820fa02 RELEASE-2.0.3 1.6 fb875591fd72e15c31879c0e9034d99b80225595 RELEASE-2.0.4 1.7 +1a522944f76540ea9d73fcc1b0d13d0f670183f0 RELEASE-2.0.5 1.8 487b2ee37d1cecb5f3e7a546b05ad097a0226f2f beta1 1.9 3d330e41f41ce1bc118c02346e18949ad5d67f6b latest-semistable 1.10 30c521db4c71960b0cf1d9c9e1b658e77b535a3e latest-stable
2.1 --- a/.rootkeys Thu Mar 24 22:01:38 2005 +0000 2.2 +++ b/.rootkeys Thu Mar 24 22:52:13 2005 +0000 2.3 @@ -3,6 +3,7 @@ 3eba336c4BUxP3H1DjQl8sInORf1Yw BitKeeper 2.4 3ddb6b0buTaC5zg1_a8FoAR9FWi_mw BitKeeper/etc/ignore 2.5 3ddb79c9_hgSp-gsQm8HqWM_9W3B_A BitKeeper/etc/logging_ok 2.6 4177dbbfqsi01p2zgZa0geUOgScONw COPYING 2.7 +423fdd91sxkCMaKFcDsEdhsZer54vA Config.mk 2.8 3eb788d6Kleck_Cut0ouGneviGzliQ Makefile 2.9 3f5ef5a24IaQasQE2tyMxrfxskMmvw README 2.10 41880852AtdVfSsfKGtrLdajX1vEXQ buildconfigs/Rules.mk 2.11 @@ -46,6 +47,78 @@ 3f815145vGYx1WY79voKkZB9yKwJKQ extras/mi 2.12 3f815145xlKBAQmal9oces3G_Mvxqw extras/mini-os/traps.c 2.13 3f815145W2mamPMclRLOzm5B38vWUQ extras/mini-os/x86_32.S 2.14 420c983dAE5qEtJMI6wHAQnHVJ1r2g extras/mini-os/x86_64.S 2.15 +423e7e86yUUeeOvTAmjIahrpk1ksaQ freebsd-5.3-xen-sparse/conf/Makefile.i386-xen 2.16 +423e7e86CSWbA9G8OftmMbfhStuQ6Q freebsd-5.3-xen-sparse/conf/files.i386-xen 2.17 +423e7e86m-vV5fQ_32CjcFMEr77Fyg freebsd-5.3-xen-sparse/conf/ldscript.i386-xen 2.18 +423e7e86Fo2PxRS_37IwkpH-x5t5xQ freebsd-5.3-xen-sparse/conf/options.i386-xen 2.19 +423e7e868Yt0iZuEeccnczyToPPvow freebsd-5.3-xen-sparse/fbsdxensetup 2.20 +423e7e87szZMt1H0xhO5vzyXR6d7iQ freebsd-5.3-xen-sparse/i386-xen/Makefile 2.21 +423e7e8785O6DIEVghIvXD6tcNKonQ freebsd-5.3-xen-sparse/i386-xen/compile/.cvsignore 2.22 +423e7e87zkFCb_Z4sHQpbec6jk3MdA freebsd-5.3-xen-sparse/i386-xen/conf/GENERIC 2.23 +423e7e876sW2cYvlk0qy8YnBbPlklQ freebsd-5.3-xen-sparse/i386-xen/conf/GENERIC.hints 2.24 +423e7e87DGOWxuyrh3sr9TmUwddFuQ freebsd-5.3-xen-sparse/i386-xen/conf/Makefile 2.25 +423e7e87eEVyCRO7fX1xtDhf1XJkVg freebsd-5.3-xen-sparse/i386-xen/conf/NOTES 2.26 +423e7e87XB6xpj6WE1bGhL_VMtRYzg freebsd-5.3-xen-sparse/i386-xen/conf/OLDCARD 2.27 +423e7e87a984mQwCH2oAeQuddGgKLg freebsd-5.3-xen-sparse/i386-xen/conf/PAE 2.28 +423e7e87Ol0GS76rWAgsk3LUwcGDxA freebsd-5.3-xen-sparse/i386-xen/conf/XENCONF 2.29 +423e7e87J8ZFS37QDhcVwErFq0MI_Q freebsd-5.3-xen-sparse/i386-xen/conf/gethints.awk 2.30 +423e7e879JhpmoexiNPqXRRcBmZ9gg freebsd-5.3-xen-sparse/i386-xen/i386-xen/clock.c 2.31 +423e7e88URfvmzX5RoVTjlaUHW5-AA freebsd-5.3-xen-sparse/i386-xen/i386-xen/critical.c 2.32 +423e7e88MJxOMvE6pfDvSHp7WuF9DQ freebsd-5.3-xen-sparse/i386-xen/i386-xen/ctrl_if.c 2.33 +423e7e885ZJMOinNI0XzQE4EgL0N8g freebsd-5.3-xen-sparse/i386-xen/i386-xen/db_interface.c 2.34 +423e7e88B5vxFblc-MlhxKk9e4ieBw freebsd-5.3-xen-sparse/i386-xen/i386-xen/evtchn.c 2.35 +423e7e88z_BrFu1O71-Ya4pXJpjAPQ freebsd-5.3-xen-sparse/i386-xen/i386-xen/exception.s 2.36 +423e7e88uDvAZLmABMkqOpmemyVRyw freebsd-5.3-xen-sparse/i386-xen/i386-xen/genassym.c 2.37 +423e7e88yr5NFQudubMnkvdb_y-Gtg freebsd-5.3-xen-sparse/i386-xen/i386-xen/hypervisor.c 2.38 +423e7e88Y-e-4RRf9nrgkVn5PXUv3Q freebsd-5.3-xen-sparse/i386-xen/i386-xen/i686_mem.c 2.39 +423e7e88b8m2cuGtOxVvs4Sok4Vk7Q freebsd-5.3-xen-sparse/i386-xen/i386-xen/initcpu.c 2.40 +423e7e88GWQb_EYd2ifpPwFUkLsuZg freebsd-5.3-xen-sparse/i386-xen/i386-xen/intr_machdep.c 2.41 +423e7e88rk8Ehi__jv3lkHlY5AgJ8g freebsd-5.3-xen-sparse/i386-xen/i386-xen/io_apic.c 2.42 +423e7e89gHdRITIMC8UcCGE8I_b1xA freebsd-5.3-xen-sparse/i386-xen/i386-xen/local_apic.c 2.43 +423e7e89rRVY9tFlFqlknnIz3yeWbA freebsd-5.3-xen-sparse/i386-xen/i386-xen/locore.s 2.44 +423e7e89jeY3Xt1xJzoIaMuJYTvgSA freebsd-5.3-xen-sparse/i386-xen/i386-xen/machdep.c 2.45 +423e7e89heNir7lAB1UbeMMUqePgMw freebsd-5.3-xen-sparse/i386-xen/i386-xen/mp_clock.c 2.46 +423e7e890R-y2KIiLL3gmhxK84t_Hw freebsd-5.3-xen-sparse/i386-xen/i386-xen/mp_machdep.c 2.47 +423e7e890m0CRnOquORvF3Yd328kSQ freebsd-5.3-xen-sparse/i386-xen/i386-xen/mptable.c 2.48 +423e7e89IqeULJgwXuSF9vnCAqpnbA freebsd-5.3-xen-sparse/i386-xen/i386-xen/pmap.c 2.49 +423e7e89gaiMYCEiHavf3VGTvD06JA freebsd-5.3-xen-sparse/i386-xen/i386-xen/support.s 2.50 +423e7e89DDt4jyU_HE0XCkRYRqs76g freebsd-5.3-xen-sparse/i386-xen/i386-xen/swtch.s 2.51 +423e7e89GTxBtczOgi8_jt6vWa9X7g freebsd-5.3-xen-sparse/i386-xen/i386-xen/symbols.raw 2.52 +423e7e8988cR9BIPAYAk4mLhHzfJtw freebsd-5.3-xen-sparse/i386-xen/i386-xen/sys_machdep.c 2.53 +423e7e8a96Rk0vPk2939cEa26JBpeQ freebsd-5.3-xen-sparse/i386-xen/i386-xen/trap.c 2.54 +423e7e8a0PDbz_hWtTKwo4ZKy-FNYw freebsd-5.3-xen-sparse/i386-xen/i386-xen/vm_machdep.c 2.55 +423e7e8aMaZIkzUU5UH-VgwB6uVJDQ freebsd-5.3-xen-sparse/i386-xen/i386-xen/xen_bus.c 2.56 +423e7e8ac9Zkao6o8lF_dpdwz6FoXg freebsd-5.3-xen-sparse/i386-xen/i386-xen/xen_machdep.c 2.57 +423e7e8aVYTynjpZsJxUsFSlIDhpJw freebsd-5.3-xen-sparse/i386-xen/include/cpufunc.h 2.58 +423e7e8avrrUxDugrwq_GJp499DkJw freebsd-5.3-xen-sparse/i386-xen/include/ctrl_if.h 2.59 +423e7e8apY1r9Td-S0eZITNZZbfNTQ freebsd-5.3-xen-sparse/i386-xen/include/evtchn.h 2.60 +423e7e8aL9DsObEegCwtILrF6SWcAQ freebsd-5.3-xen-sparse/i386-xen/include/frame.h 2.61 +423e7e8btv8Gojq50ggnP5A1Dkc4kA freebsd-5.3-xen-sparse/i386-xen/include/hypervisor-ifs.h 2.62 +423e7e8buhTLVFLZ33-5s8-UdADSZg freebsd-5.3-xen-sparse/i386-xen/include/hypervisor.h 2.63 +423e7e8bnHT1kMD-FPC7zHZR7l3VXw freebsd-5.3-xen-sparse/i386-xen/include/md_var.h 2.64 +423e7e8b9iF0oV70F62vNrZt8YbiQA freebsd-5.3-xen-sparse/i386-xen/include/multicall.h 2.65 +423e7e8bpUbyvkZ7a8MWY0A_oWrB0w freebsd-5.3-xen-sparse/i386-xen/include/param.h 2.66 +423e7e8bdz1fj4Rlj8W7OWXgLfBT7w freebsd-5.3-xen-sparse/i386-xen/include/pcb.h 2.67 +423e7e8bHhHGybRm4OXwdq9NEOvZwQ freebsd-5.3-xen-sparse/i386-xen/include/pcpu.h 2.68 +423e7e8bI1dvek3ZR7BKw7dMkVAEkA freebsd-5.3-xen-sparse/i386-xen/include/pmap.h 2.69 +423e7e8bVOoPguCLyNj7pil-PT7Vcw freebsd-5.3-xen-sparse/i386-xen/include/segments.h 2.70 +423e7e8c9AuwksRrt0ptRKHnNVWuNQ freebsd-5.3-xen-sparse/i386-xen/include/synch_bitops.h 2.71 +423e7e8csdWimnMBI2HxEDJ30L42kQ freebsd-5.3-xen-sparse/i386-xen/include/trap.h 2.72 +423e7e8cgVgn9W8sZWwfh_4938fSJQ freebsd-5.3-xen-sparse/i386-xen/include/ucontext.h 2.73 +423e7e8cdsEhPyad2ppDoSiBR4eB9g freebsd-5.3-xen-sparse/i386-xen/include/vmparam.h 2.74 +423e7e8ccGI7kzIlRcEVziGZzm46wg freebsd-5.3-xen-sparse/i386-xen/include/xen-os.h 2.75 +423e7e8cVSqLIOp5vH4ADvAL_MF6Qg freebsd-5.3-xen-sparse/i386-xen/include/xen_intr.h 2.76 +423e7e8c1vzXK91FKaMnZz0NZpb5NA freebsd-5.3-xen-sparse/i386-xen/include/xenfunc.h 2.77 +423e7e8cLPHbgUJHLf1pPqZXlBgVqQ freebsd-5.3-xen-sparse/i386-xen/include/xenpmap.h 2.78 +423e7e8caalqG0UsGxkk9PshfnMFtA freebsd-5.3-xen-sparse/i386-xen/include/xenvar.h 2.79 +423e7e8c8MGTB12W2GZ-mTa-_T5Xuw freebsd-5.3-xen-sparse/i386-xen/xen/blkfront/xb_blkfront.c 2.80 +423e7e8dL_lQk1nbqJ5MPL5cTzXR5g freebsd-5.3-xen-sparse/i386-xen/xen/char/console.c 2.81 +423e7e8d4LBg7lzjHtssnxcZwezLJQ freebsd-5.3-xen-sparse/i386-xen/xen/misc/evtchn_dev.c 2.82 +423e7e8dVX2QkuzWwB2rtZDxD5Y_-w freebsd-5.3-xen-sparse/i386-xen/xen/misc/npx.c 2.83 +423e7e8d_PdWXjQeRg75twh7TleJhQ freebsd-5.3-xen-sparse/i386-xen/xen/netfront/xn_netfront.c 2.84 +423e7e8dlsc1oCW_ul57w0AHY5jZjQ freebsd-5.3-xen-sparse/kern/kern_fork.c 2.85 +423e7e8dVDL1WLfbmQWuXMbetYk4jA freebsd-5.3-xen-sparse/mkbuildtree 2.86 +423e7e8dBrOrAbydK6h49bY0VvDgPw freebsd-5.3-xen-sparse/xenfbsd_kernel_build 2.87 4187ca95_eQN62ugV1zliQcfzXrHnw install.sh 2.88 3e5a4e6589G-U42lFKs43plskXoFxQ linux-2.4.29-xen-sparse/Makefile 2.89 3e5a4e65IEPjnWPZ5w3TxS5scV8Ewg linux-2.4.29-xen-sparse/arch/xen/Makefile 2.90 @@ -72,6 +145,7 @@ 3e5a4e65lWzkiPXsZdzPt2RNnJGG1g linux-2.4 2.91 3e5a4e65_hqfuxtGG8IUy6wRM86Ecg linux-2.4.29-xen-sparse/arch/xen/kernel/entry.S 2.92 3e5a4e65Hy_1iUvMTPsNqGNXd9uFpg linux-2.4.29-xen-sparse/arch/xen/kernel/head.S 2.93 3e5a4e65RMGcuA-HCn3-wNx3fFQwdg linux-2.4.29-xen-sparse/arch/xen/kernel/i386_ksyms.c 2.94 +4241709bNBs1q4Ss32YW0CyFVOGhEg linux-2.4.29-xen-sparse/arch/xen/kernel/ioport.c 2.95 3e5a4e653U6cELGv528IxOLHvCq8iA linux-2.4.29-xen-sparse/arch/xen/kernel/irq.c 2.96 3e5a4e65muT6SU3ck47IP87Q7Ti5hA linux-2.4.29-xen-sparse/arch/xen/kernel/ldt.c 2.97 4051db95N9N99FjsRwi49YKUNHWI8A linux-2.4.29-xen-sparse/arch/xen/kernel/pci-pc.c 2.98 @@ -117,6 +191,7 @@ 3e5a4e68mTr0zcp9SXDbnd-XLrrfxw linux-2.4 2.99 3f1056a9L_kqHcFheV00KbKBzv9j5w linux-2.4.29-xen-sparse/include/asm-xen/vga.h 2.100 40659defgWA92arexpMGn8X3QMDj3w linux-2.4.29-xen-sparse/include/asm-xen/xor.h 2.101 3f056927gMHl7mWB89rb73JahbhQIA linux-2.4.29-xen-sparse/include/linux/blk.h 2.102 +42305f54mFScQCttpj57EIm60BnxIg linux-2.4.29-xen-sparse/include/linux/highmem.h 2.103 419e0488SBzS3mdUhwgsES5a5e3abA linux-2.4.29-xen-sparse/include/linux/irq.h 2.104 4124f66fPHG6yvB_vXmesjvzrJ3yMg linux-2.4.29-xen-sparse/include/linux/mm.h 2.105 401c0590D_kwJDU59X8NyvqSv_Cl2A linux-2.4.29-xen-sparse/include/linux/sched.h 2.106 @@ -133,149 +208,149 @@ 409ba2e7akOFqQUg6Qyg2s28xcXiMg linux-2.4 2.107 3e5a4e683HKVU-sxtagrDasRB8eBVw linux-2.4.29-xen-sparse/mm/swapfile.c 2.108 41180721bNns9Na7w1nJ0ZVt8bhUNA linux-2.4.29-xen-sparse/mm/vmalloc.c 2.109 41505c57WAd5l1rlfCLNSCpx9J13vA linux-2.4.29-xen-sparse/net/core/skbuff.c 2.110 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tools/blktap/README-PARALLAX 2.414 4209033eX_Xw94wHaOCtnU9nOAtSJA tools/blktap/blkaio.c 2.415 4209033egwf6LDxM2hbaqi9rRdZy4A tools/blktap/blkaiolib.c 2.416 4209033f9yELLK85Ipo2oKjr3ickgQ tools/blktap/blkaiolib.h 2.417 @@ -335,10 +414,32 @@ 42090340c7pQbh0Km8zLcEqPd_3zIg tools/blk 2.418 42090340_mvZtozMjghPJO0qsjk4NQ tools/blktap/blkint.h 2.419 42090340rc2q1wmlGn6HtiJAkqhtNQ tools/blktap/blktaplib.c 2.420 42090340C-WkRPT7N3t-8Lzehzogdw tools/blktap/blktaplib.h 2.421 +423f270cAbkh2f-DHtT0hmCtFFXVXg tools/blktap/blockstore-tls.c 2.422 +42277b02WrfP1meTDPv1M5swFq8oHQ tools/blktap/blockstore.c 2.423 +42277b02P1C0FYj3gqwTZUD8sxKCug tools/blktap/blockstore.h 2.424 +42371b8aL1JsxAXOd4bBhmZKDyjiJg tools/blktap/blockstored.c 2.425 +42371b8aD_x3L9MKsXciMNqkuk58eQ tools/blktap/bstest.c 2.426 42090340B3mDvcxvd9ehDHUkg46hvw tools/blktap/libgnbd/Makefile 2.427 42090340ZWkc5Xhf9lpQmDON8HJXww tools/blktap/libgnbd/gnbdtest.c 2.428 42090340ocMiUScJE3OpY7QNunvSbg tools/blktap/libgnbd/libgnbd.c 2.429 42090340G5_F_EeVnPORKB0pTMGGhA tools/blktap/libgnbd/libgnbd.h 2.430 +423f270cbEKiTMapKnCyqkuwGvgOMA tools/blktap/parallax-threaded.c 2.431 +423f270cFdXryIcD7HTPUl_Dbk4DAQ tools/blktap/parallax-threaded.h 2.432 +42277b03930x2TJT3PZlw6o0GERXpw tools/blktap/parallax.c 2.433 +42277b03XQYq8bujXSz7JAZ8N7j_pA tools/blktap/radix.c 2.434 +42277b03vZ4-jno_mgKmAcCW3ycRAg tools/blktap/radix.h 2.435 +42277b03U_wLHL-alMA0bfxGlqldXg tools/blktap/snaplog.c 2.436 +42277b04Ryya-z662BEx8HnxNN0dGQ tools/blktap/snaplog.h 2.437 +42277b04LxFjptgZ75Z98DUAso4Prg tools/blktap/vdi.c 2.438 +42277b04tt5QkIvs8She8CQqH5kwpg tools/blktap/vdi.h 2.439 +42277b04zMAhB0_946sHQ_H2vwnt0Q tools/blktap/vdi_create.c 2.440 +42277b04xB_iUmiSm6nKcy8OV8bckA tools/blktap/vdi_fill.c 2.441 +42277b045CJGD_rKH-ZT_-0X4knhWA tools/blktap/vdi_list.c 2.442 +42277b043ZKx0NJSbcgptQctQ5rerg tools/blktap/vdi_snap.c 2.443 +423f270c_QDjGLQ_YdaOtyBM5n9BDg tools/blktap/vdi_snap_delete.c 2.444 +42277b043Fjy5-H7LyBtUPyDlZFo6A tools/blktap/vdi_snap_list.c 2.445 +42277b04vhqD6Lq3WmGbaESoAAKdhw tools/blktap/vdi_tree.c 2.446 +42277b047H8fTVyUf75BWAjh6Zpsqg tools/blktap/vdi_validate.c 2.447 4124b307nRyK3dhn1hAsvrY76NuV3g tools/check/Makefile 2.448 4124b307vHLUWbfpemVefmaWDcdfag tools/check/README 2.449 4124b307jt7T3CHysgl9LijNHSe1tA tools/check/check_brctl 2.450 @@ -369,6 +470,13 @@ 41dde8af6M2Pm1Rrv_f5jEFC_BIOIA tools/exa 2.451 41090ec8Pj_bkgCBpg2W7WfmNkumEA tools/examples/xmexample1 2.452 40cf2937oKlROYOJTN8GWwWM5AmjBg tools/examples/xmexample2 2.453 41fc0c18_k4iL81hu4pMIWQu9dKpKA tools/examples/xmexample3 2.454 +423d3a7bpoTFd0vqFaocQ-FqC8RuPA tools/gdb/gdb-6.2.1-xen-sparse/gdb/gdbserver/Makefile.in 2.455 +423d3a7b_HtKYGocoTS1adeOpqDFnw tools/gdb/gdb-6.2.1-xen-sparse/gdb/gdbserver/configure 2.456 +423d3a7b2vJq86I8FbYm6up5BsCwfA tools/gdb/gdb-6.2.1-xen-sparse/gdb/gdbserver/configure.in 2.457 +423d3a7bQPownmVb63qOoyq89ebBVA tools/gdb/gdb-6.2.1-xen-sparse/gdb/gdbserver/configure.srv 2.458 +423d3a7bHtqhyOgiRWhjWt-S-6wbYg tools/gdb/gdb-6.2.1-xen-sparse/gdb/gdbserver/linux-xen-low.c 2.459 +423d3a7b2ENk2IskDZYZ98pe5NsvIA tools/gdb/gdb-6.2.1-xen-sparse/mkbuildtree 2.460 +423d3a7buANO_q-kgxIRffUu7lMnUw tools/gdb/gdbbuild 2.461 41e2ff6dNPgvIrdIF6dC1azdex1U3A tools/ioemu/Makefile 2.462 41e2ff6aoF5fgddZi0QpEWqFr89E5g tools/ioemu/font/vga.bitmap.h 2.463 41e2ff6avgnBNvZRiL4ynyGGq2UKlw tools/ioemu/gui/Makefile 2.464 @@ -541,6 +649,7 @@ 3fbba6dbEVkVMX0JuDFzap9jeaucGA tools/lib 2.465 3fbba6dbasJQV-MVElDC0DGSHMiL5w tools/libxc/xc_domain.c 2.466 40278d99BLsfUv3qxv0I8C1sClZ0ow tools/libxc/xc_elf.h 2.467 403e0977Bjsm_e82pwvl9VvaJxh8Gg tools/libxc/xc_evtchn.c 2.468 +4227c129ZKjJPNYooHVzBCyinf7Y6Q tools/libxc/xc_gnttab.c 2.469 40e03333Eegw8czSWvHsbKxrRZJjRA tools/libxc/xc_io.c 2.470 40e03333vrWGbLAhyJjXlqCHaJt7eA tools/libxc/xc_io.h 2.471 3fbba6dbNCU7U6nsMYiXzKkp3ztaJg tools/libxc/xc_linux_build.c 2.472 @@ -551,6 +660,7 @@ 4051bce6CHAsYh8P5t2OHDtRWOP9og tools/lib 2.473 41cc934aO1m6NxEh_8eDr9bJIMoLFA tools/libxc/xc_plan9_build.c 2.474 3fbba6dctWRWlFJkYb6hdix2X4WMuw tools/libxc/xc_private.c 2.475 3fbba6dcbVrG2hPzEzwdeV_UC8kydQ tools/libxc/xc_private.h 2.476 +42337174PxyzzPk62raDiYCIsfStDg tools/libxc/xc_ptrace.c 2.477 40589968UQFnJeOMn8UIFLbXBuwXjw tools/libxc/xc_rrobin.c 2.478 41dde8b0pLfAKMs_L9Uri2hnzHiCRQ tools/libxc/xc_vmx_build.c 2.479 40e1b09dMYB4ItGCqcMIzirdMd9I-w tools/libxutil/Makefile 2.480 @@ -777,6 +887,8 @@ 4104ffca-jPHLVOrW0n0VghEXXtKxg tools/sv/ 2.481 40fcefb3yMSrZvApO9ToIi-iQwnchA tools/sv/images/xen.png 2.482 41013a83z27rKvWIxAfUBMVZ1eDCDg tools/sv/inc/script.js 2.483 40fcefb3zGC9XNBkSwTEobCoq8YClA tools/sv/inc/style.css 2.484 +422f27c8MDeRoOWZNdcRC5VDTcj3TQ tools/tests/Makefile 2.485 +422f27c81CCtXt4Lthf7JF3Ajr0fUA tools/tests/test_x86_emulator.c 2.486 420b963dK3yGNtqxRM8npGZtrCQd1g tools/vnet/00INSTALL 2.487 41a21888_WlknVWjSxb32Fo13_ujsw tools/vnet/00README 2.488 420a9b706I-bN_uPdiy0m3rmDifNNg tools/vnet/INSTALL 2.489 @@ -837,15 +949,12 @@ 41a2188aIf3Xk6uvk7KzjdpOsflAEw tools/vne 2.490 41a2188ar6_vOO3_tEJQjmFVU3409A tools/vnet/vnetd/vcache.h 2.491 41a2188aETrGU60X9WtGhYVfU7z0Pw tools/vnet/vnetd/vnetd.c 2.492 41a2188ahYjemudGyB7078AWMFR-0w tools/vnet/vnetd/vnetd.h 2.493 -4194e861IgTabTt8HOuh143QIJFD1Q tools/x2d2/Makefile 2.494 -4194e861M2gcBz4i94cQYpqzi8n6UA tools/x2d2/cntrl_con.c 2.495 -4194e8612TrrMvC8ZlA4h2ZYCPWz4g tools/x2d2/minixend.c 2.496 -4194e861x2eqNCD61RYPCUEBVdMYuw tools/x2d2/minixend.h 2.497 -4194e861A4V9VbD_FYmgXpYEj5YwVg tools/x2d2/util.c 2.498 41d58ba63w1WfBmd6Cr_18nhLNv7PA tools/xcs/Makefile 2.499 41d58ba6NxgkfzD_rmsGjgd_zJ3H_w tools/xcs/bindings.c 2.500 41d58ba6I2umi60mShq4Pl0RDg7lzQ tools/xcs/connection.c 2.501 41d58ba6YyYu53bFuoIAw9hNNmneEg tools/xcs/ctrl_interface.c 2.502 +423d82c7ZKf2bDOxRcR4Nc1kN5StNQ tools/xcs/dump.c 2.503 +423d82c7U__LHy9dvkUNUvSIhOqnBQ tools/xcs/dump.h 2.504 41d58ba6Ru9ZbhTjgYX_oiszSIwCww tools/xcs/evtchn.c 2.505 41d58ba6x9KO1CQBT7kKOKq_pJYC3g tools/xcs/xcs.c 2.506 41d58ba6R6foSMtSFEcu-yxWFrT8VQ tools/xcs/xcs.h 2.507 @@ -1007,6 +1116,7 @@ 41bf1717XhPz_dNT5OKSjgmbFuWBuA xen/arch/ 2.508 42000d3cMb8o1WuFBXC07c8i3lPZBw xen/arch/x86/x86_64/traps.c 2.509 40e96d3ahBTZqbTViInnq0lM03vs7A xen/arch/x86/x86_64/usercopy.c 2.510 40e96d3akN3Hu_J5Bk-WXD8OGscrYQ xen/arch/x86/x86_64/xen.lds 2.511 +422f27c8J9DQfCpegccMid59XhSmGA xen/arch/x86/x86_emulate.c 2.512 3ddb79bdff-gj-jFGKjOejeHLqL8Lg xen/common/Makefile 2.513 3e397e66AyyD5fYraAySWuwi9uqSXg xen/common/ac_timer.c 2.514 3ddb79bdLX_P6iB7ILiblRLWvebapg xen/common/dom0_ops.c 2.515 @@ -1170,6 +1280,7 @@ 4208e2a3Fktw4ZttKdDxbhvTQ6brfQ xen/inclu 2.516 404f1bb86rAXB3aLS1vYdcqpJiEcyg xen/include/asm-x86/x86_64/regs.h 2.517 40e1966azOJZfNI6Ilthe6Q-T3Hewg xen/include/asm-x86/x86_64/string.h 2.518 404f1bc4tWkB9Qr8RkKtZGW5eMQzhw xen/include/asm-x86/x86_64/uaccess.h 2.519 +422f27c8RHFkePhD34VIEpMMqofZcA xen/include/asm-x86/x86_emulate.h 2.520 400304fcmRQmDdFYEzDh0wcBba9alg xen/include/public/COPYING 2.521 421098b7OKb9YH_EUA_UpCxBjaqtgA xen/include/public/arch-ia64.h 2.522 404f1bc68SXxmv0zQpXBWGrCzSyp8w xen/include/public/arch-x86_32.h 2.523 @@ -1216,6 +1327,7 @@ 3ddb79c2Fg44_PBPVxHSC0gTOMq4Ow xen/inclu 2.524 3ddb79c0MOVXq8qZDQRGb6z64_xAwg xen/include/xen/pci_ids.h 2.525 3e54c38dlSCVdyVM4PKcrSfzLLxWUQ xen/include/xen/perfc.h 2.526 3e54c38de9SUSYSAwxDf_DwkpAnQFA xen/include/xen/perfc_defn.h 2.527 +42422fb0FVX-TJkSvAXnbfwMf19XFA xen/include/xen/physdev.h 2.528 3ddb79c04nQVR3EYM5L4zxDV_MCo1g xen/include/xen/prefetch.h 2.529 3e4540ccU1sgCx8seIMGlahmMfv7yQ xen/include/xen/reboot.h 2.530 40589969nPq3DMzv24RDb5LXE9brHw xen/include/xen/sched-if.h
3.1 --- a/BitKeeper/etc/ignore Thu Mar 24 22:01:38 2005 +0000 3.2 +++ b/BitKeeper/etc/ignore Thu Mar 24 22:52:13 2005 +0000 3.3 @@ -50,6 +50,7 @@ install/* 3.4 linux-*-xen0/* 3.5 linux-*-xenU/* 3.6 linux-*.patch 3.7 +linux-2.6.10-xen-sparse/include/asm-xen/hypervisor.h.smh 3.8 linux-xen-sparse 3.9 mkddbxen 3.10 netbsd-*-tools/* 3.11 @@ -61,14 +62,41 @@ patches/ebtables.diff 3.12 patches/tmp/* 3.13 pristine-* 3.14 tools/*/build/lib*/*.py 3.15 +tools/Makefile.smh 3.16 tools/balloon/balloon 3.17 +tools/blktap/Makefile.smh 3.18 +tools/blktap/blkcow 3.19 +tools/blktap/blkcowgnbd 3.20 +tools/blktap/blkcowimg 3.21 +tools/blktap/blkdump 3.22 +tools/blktap/blkgnbd 3.23 +tools/blktap/blkimg 3.24 +tools/blktap/blockstore.dat 3.25 +tools/blktap/blockstored 3.26 +tools/blktap/bstest 3.27 +tools/blktap/parallax 3.28 +tools/blktap/vdi.dot 3.29 +tools/blktap/vdi.ps 3.30 +tools/blktap/vdi_create 3.31 +tools/blktap/vdi_fill 3.32 +tools/blktap/vdi_list 3.33 +tools/blktap/vdi_snap 3.34 +tools/blktap/vdi_snap_list 3.35 +tools/blktap/vdi_tree 3.36 +tools/blktap/vdi_validate 3.37 +tools/blktap/xen/* 3.38 tools/check/.* 3.39 +tools/cmdline/* 3.40 tools/cmdline/xen/* 3.41 tools/ioemu/iodev/device-model 3.42 tools/libxc/xen/* 3.43 +tools/misc/cpuperf/cpuperf-perfcntr 3.44 +tools/misc/cpuperf/cpuperf-xen 3.45 tools/misc/miniterm/miniterm 3.46 +tools/misc/xc_shadow 3.47 tools/misc/xen_cpuperf 3.48 tools/misc/xenperf 3.49 +tools/tests/test_x86_emulator 3.50 tools/vnet/gc 3.51 tools/vnet/gc*/* 3.52 tools/vnet/vnet-module/*.ko 3.53 @@ -101,6 +129,3 @@ xen/tools/figlet/figlet 3.54 xen/xen 3.55 xen/xen-syms 3.56 xen/xen.* 3.57 -tools/misc/cpuperf/cpuperf-perfcntr 3.58 -tools/misc/cpuperf/cpuperf-xen 3.59 -tools/misc/xc_shadow
4.1 --- a/BitKeeper/etc/logging_ok Thu Mar 24 22:01:38 2005 +0000 4.2 +++ b/BitKeeper/etc/logging_ok Thu Mar 24 22:52:13 2005 +0000 4.3 @@ -19,10 +19,13 @@ cl349@firebug.cl.cam.ac.uk 4.4 cl349@freefall.cl.cam.ac.uk 4.5 cl349@labyrinth.cl.cam.ac.uk 4.6 cwc22@centipede.cl.cam.ac.uk 4.7 +cwc22@donkeykong.cl.cam.ac.uk 4.8 djm@kirby.fc.hp.com 4.9 +doogie@brainfood.com 4.10 gm281@boulderdash.cl.cam.ac.uk 4.11 gm281@tetrapod.cl.cam.ac.uk 4.12 harry@dory.(none) 4.13 +iap10@firebug.cl.cam.ac.uk 4.14 iap10@freefall.cl.cam.ac.uk 4.15 iap10@labyrinth.cl.cam.ac.uk 4.16 iap10@nidd.cl.cam.ac.uk 4.17 @@ -30,6 +33,8 @@ iap10@pb001.cl.cam.ac.uk 4.18 iap10@pb007.cl.cam.ac.uk 4.19 iap10@striker.cl.cam.ac.uk 4.20 iap10@tetris.cl.cam.ac.uk 4.21 +jrb44@plym.cl.cam.ac.uk 4.22 +jrb44@swoop.cl.cam.ac.uk 4.23 jws22@gauntlet.cl.cam.ac.uk 4.24 jws@cairnwell.research 4.25 kaf24@camelot.eng.3leafnetworks.com 4.26 @@ -43,6 +48,7 @@ kaf24@plym.cl.cam.ac.uk 4.27 kaf24@scramble.cl.cam.ac.uk 4.28 kaf24@striker.cl.cam.ac.uk 4.29 kaf24@viper.(none) 4.30 +kmacy@shemp.lab.netapp.com 4.31 laudney@eclipse.(none) 4.32 lynx@idefix.cl.cam.ac.uk 4.33 maf46@burn.cl.cam.ac.uk 4.34 @@ -50,12 +56,15 @@ mafetter@fleming.research 4.35 mark@maw48.kings.cam.ac.uk 4.36 maw48@labyrinth.cl.cam.ac.uk 4.37 mjw@wray-m-3.hpl.hp.com 4.38 +mulix@mulix.org 4.39 mwilli2@anvil.research 4.40 mwilli2@equilibrium.research 4.41 mwilli2@equilibrium.research.intel-research.net 4.42 mwilli2@pug.(none) 4.43 rac61@labyrinth.cl.cam.ac.uk 4.44 rgr22@boulderdash.cl.cam.ac.uk 4.45 +riel@redhat.com 4.46 +rminnich@lanl.gov 4.47 rn@wyvis.camb.intel-research.net 4.48 rn@wyvis.research.intel-research.net 4.49 rneugeba@wyvis.research 4.50 @@ -73,4 +82,7 @@ tlh20@elite.cl.cam.ac.uk 4.51 tlh20@labyrinth.cl.cam.ac.uk 4.52 tw275@labyrinth.cl.cam.ac.uk 4.53 tw275@striker.cl.cam.ac.uk 4.54 +vh249@airwolf.cl.cam.ac.uk 4.55 +vh249@arcadians.cl.cam.ac.uk 4.56 +xen-ia64.adm@bkbits.net 4.57 xenbk@gandalf.hpl.hp.com
5.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 5.2 +++ b/Config.mk Thu Mar 24 22:52:13 2005 +0000 5.3 @@ -0,0 +1,33 @@ 5.4 +# -*- mode: Makefile; -*- 5.5 +# Currently supported architectures: x86_32, x86_64 5.6 +XEN_COMPILE_ARCH ?= $(shell uname -m | sed -e s/i.86/x86_32/) 5.7 +XEN_TARGET_ARCH ?= $(XEN_COMPILE_ARCH) 5.8 + 5.9 +# 5.10 +# Tool configuration Makefile fragment 5.11 +# 5.12 +HOSTCC = gcc 5.13 +HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer 5.14 + 5.15 +AS = $(CROSS_COMPILE)as 5.16 +LD = $(CROSS_COMPILE)ld 5.17 +CC = $(CROSS_COMPILE)gcc 5.18 +CPP = $(CROSS_COMPILE)gcc -E 5.19 +AR = $(CROSS_COMPILE)ar 5.20 +NM = $(CROSS_COMPILE)nm 5.21 +STRIP = $(CROSS_COMPILE)strip 5.22 +OBJCOPY = $(CROSS_COMPILE)objcopy 5.23 +OBJDUMP = $(CROSS_COMPILE)objdump 5.24 + 5.25 + 5.26 +ifneq ($(EXTRA_PREFIX),) 5.27 +EXTRA_INCLUDES += $(EXTRA_PREFIX)/include 5.28 +EXTRA_LIB += $(EXTRA_PREFIX)/lib 5.29 +endif 5.30 + 5.31 +LDFLAGS += $(foreach i, $(EXTRA_LIB), -L$(i)) 5.32 +CFLAGS += $(foreach i, $(EXTRA_INCLUDES), -I$(i)) 5.33 + 5.34 +CFLAGS += -g 5.35 + 5.36 +
6.1 --- a/Makefile Thu Mar 24 22:01:38 2005 +0000 6.2 +++ b/Makefile Thu Mar 24 22:52:13 2005 +0000 6.3 @@ -27,6 +27,7 @@ SUBARCH := $(subst x86_32,i386,$(XEN_TAR 6.4 export XEN_TARGET_ARCH SUBARCH 6.5 endif 6.6 6.7 +include Config.mk 6.8 include buildconfigs/Rules.mk 6.9 6.10 .PHONY: all dist install xen tools kernels docs world clean mkpatches mrproper 6.11 @@ -37,6 +38,11 @@ all: dist 6.12 # build and install everything into the standard system directories 6.13 install: install-xen install-tools install-kernels install-docs 6.14 6.15 +build: kernels 6.16 + $(MAKE) -C xen build 6.17 + $(MAKE) -C tools build 6.18 + $(MAKE) -C docs build 6.19 + 6.20 # build and install everything into local dist directory 6.21 dist: xen tools kernels docs 6.22 $(INSTALL_DIR) $(DISTDIR)/check
7.1 --- a/buildconfigs/Rules.mk Thu Mar 24 22:01:38 2005 +0000 7.2 +++ b/buildconfigs/Rules.mk Thu Mar 24 22:52:13 2005 +0000 7.3 @@ -27,7 +27,7 @@ linux-%.tar.bz2: 7.4 # Expand NetBSD release to NetBSD version 7.5 NETBSD_RELEASE ?= 2.0 7.6 NETBSD_VER ?= $(patsubst netbsd-%-xen-sparse,%,$(wildcard netbsd-$(NETBSD_RELEASE)*-xen-sparse)) 7.7 -NETBSD_CVSSNAP ?= 20041103 7.8 +NETBSD_CVSSNAP ?= 20050309 7.9 7.10 # Setup NetBSD search path 7.11 NETBSD_SRC_PATH ?= .:.. 7.12 @@ -47,6 +47,7 @@ pristine-%: %.tar.bz2 7.13 tar -C tmp-$(@F) -jxf $< 7.14 mv tmp-$(@F)/* $@ 7.15 touch $@ # update timestamp to avoid rebuild 7.16 + touch $@/.bk_skip 7.17 @rm -rf tmp-$(@F) 7.18 [ -d patches/$* ] && \ 7.19 for i in patches/$*/*.patch ; do ( cd $@ ; patch -p1 <../$$i ) ; done || \
8.1 --- a/buildconfigs/mk.netbsd-2.0-xenU Thu Mar 24 22:01:38 2005 +0000 8.2 +++ b/buildconfigs/mk.netbsd-2.0-xenU Thu Mar 24 22:52:13 2005 +0000 8.3 @@ -1,6 +1,6 @@ 8.4 8.5 NETBSD_RELEASE ?= 2.0 8.6 -NETBSD_CVSSNAP ?= 20041103 8.7 +NETBSD_CVSSNAP ?= 20050309 8.8 8.9 EXTRAVERSION = xenU 8.10
9.1 --- a/docs/Makefile Thu Mar 24 22:01:38 2005 +0000 9.2 +++ b/docs/Makefile Thu Mar 24 22:52:13 2005 +0000 9.3 @@ -7,7 +7,6 @@ PS2PDF := ps2pdf 9.4 DVIPS := dvips 9.5 LATEX := latex 9.6 FIG2DEV := fig2dev 9.7 -TGIF := tgif 9.8 LATEX2HTML := latex2html 9.9 9.10 pkgdocdir := /usr/share/doc/xen 9.11 @@ -17,17 +16,19 @@ DOC_PS := $(patsubst src/%.tex,ps/%.ps, 9.12 DOC_PDF := $(patsubst src/%.tex,pdf/%.pdf,$(DOC_TEX)) 9.13 DOC_HTML := $(patsubst src/%.tex,html/%/index.html,$(DOC_TEX)) 9.14 9.15 -GFX = $(patsubst %.obj, %.eps, $(wildcard figs/*.obj)) 9.16 -GFX += $(patsubst %.fig, %.eps, $(wildcard figs/*.fig)) 9.17 +GFX = $(patsubst %.fig, %.eps, $(wildcard figs/*.fig)) 9.18 9.19 -all: ps pdf html 9.20 +all: build 9.21 +build: ps pdf html 9.22 rm -f *.aux *.dvi *.bbl *.blg *.glo *.idx *.ilg *.log *.ind *.toc 9.23 9.24 ps: $(DOC_PS) 9.25 9.26 pdf: $(DOC_PDF) 9.27 9.28 -html: $(DOC_HTML) 9.29 +html: 9.30 + @if which $(LATEX2HTML) 1>/dev/null 2>/dev/null; then \ 9.31 + $(MAKE) $(DOC_HTML); fi 9.32 9.33 clean: 9.34 rm -rf .word_count *.aux *.dvi *.bbl *.blg *.glo *.idx *~ 9.35 @@ -39,7 +40,7 @@ install: all 9.36 $(INSTALL_DIR) $(DESTDIR)$(pkgdocdir) 9.37 cp -dR ps $(DESTDIR)$(pkgdocdir) 9.38 cp -dR pdf $(DESTDIR)$(pkgdocdir) 9.39 - cp -dR html $(DESTDIR)$(pkgdocdir) 9.40 + [ ! -d html ] || cp -dR html $(DESTDIR)$(pkgdocdir) 9.41 9.42 pdf/%.pdf: ps/%.ps 9.43 $(INSTALL_DIR) $(@D) 9.44 @@ -58,9 +59,6 @@ ps/%.ps: %.dvi 9.45 %.eps: %.fig 9.46 $(FIG2DEV) -L eps $< $@ 9.47 9.48 -%.eps: %.obj 9.49 - $(TGIF) -print -color -eps $< 9.50 - 9.51 html/%/index.html: src/%.tex 9.52 $(INSTALL_DIR) $(@D) 9.53 $(LATEX2HTML) -split 0 -show_section_numbers -toc_depth 3 -nonavigation \
10.1 --- a/docs/check_pkgs Thu Mar 24 22:01:38 2005 +0000 10.2 +++ b/docs/check_pkgs Thu Mar 24 22:52:13 2005 +0000 10.3 @@ -13,10 +13,8 @@ silent_which () 10.4 } 10.5 10.6 silent_which latex || exit 1 10.7 -silent_which latex2html || exit 1 10.8 silent_which dvips || exit 1 10.9 silent_which ps2pdf || exit 1 10.10 silent_which fig2dev || exit 1 10.11 -silent_which tgif || exit 1 10.12 10.13 exit 0
11.1 --- a/docs/src/user.tex Thu Mar 24 22:01:38 2005 +0000 11.2 +++ b/docs/src/user.tex Thu Mar 24 22:52:13 2005 +0000 11.3 @@ -229,7 +229,7 @@ tree. 11.4 \item [$*$] Development installation of libcurl (e.g., libcurl-devel) 11.5 \item [$*$] Development installation of zlib (e.g., zlib-dev). 11.6 \item [$*$] Development installation of Python v2.2 or later (e.g., python-dev). 11.7 -\item [$*$] \LaTeX, transfig and tgif are required to build the documentation. 11.8 +\item [$*$] \LaTeX and transfig are required to build the documentation. 11.9 \end{itemize} 11.10 11.11 Once you have satisfied the relevant prerequisites, you can
12.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 12.2 +++ b/freebsd-5.3-xen-sparse/conf/Makefile.i386-xen Thu Mar 24 22:52:13 2005 +0000 12.3 @@ -0,0 +1,51 @@ 12.4 +# Makefile.i386 -- with config changes. 12.5 +# Copyright 1990 W. Jolitz 12.6 +# from: @(#)Makefile.i386 7.1 5/10/91 12.7 +# $FreeBSD: src/sys/conf/Makefile.i386,v 1.259 2003/04/15 21:29:11 phk Exp $ 12.8 +# 12.9 +# Makefile for FreeBSD 12.10 +# 12.11 +# This makefile is constructed from a machine description: 12.12 +# config machineid 12.13 +# Most changes should be made in the machine description 12.14 +# /sys/i386/conf/``machineid'' 12.15 +# after which you should do 12.16 +# config machineid 12.17 +# Generic makefile changes should be made in 12.18 +# /sys/conf/Makefile.i386 12.19 +# after which config should be rerun for all machines. 12.20 +# 12.21 + 12.22 +# Which version of config(8) is required. 12.23 +%VERSREQ= 500013 12.24 + 12.25 +STD8X16FONT?= iso 12.26 + 12.27 + 12.28 + 12.29 +.if !defined(S) 12.30 +.if exists(./@/.) 12.31 +S= ./@ 12.32 +.else 12.33 +S= ../../.. 12.34 +.endif 12.35 +.endif 12.36 +.include "$S/conf/kern.pre.mk" 12.37 +M= i386-xen 12.38 +MKMODULESENV+= MACHINE=i386-xen 12.39 +INCLUDES+= -I../../include/xen-public 12.40 +%BEFORE_DEPEND 12.41 + 12.42 +%OBJS 12.43 + 12.44 +%FILES.c 12.45 + 12.46 +%FILES.s 12.47 + 12.48 +%FILES.m 12.49 + 12.50 +%CLEAN 12.51 + 12.52 +%RULES 12.53 + 12.54 +.include "$S/conf/kern.post.mk"
13.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 13.2 +++ b/freebsd-5.3-xen-sparse/conf/files.i386-xen Thu Mar 24 22:52:13 2005 +0000 13.3 @@ -0,0 +1,294 @@ 13.4 +# This file tells config what files go into building a kernel, 13.5 +# files marked standard are always included. 13.6 +# 13.7 +# $FreeBSD: src/sys/conf/files.i386,v 1.457 2003/12/03 23:06:30 imp Exp $ 13.8 +# 13.9 +# The long compile-with and dependency lines are required because of 13.10 +# limitations in config: backslash-newline doesn't work in strings, and 13.11 +# dependency lines other than the first are silently ignored. 13.12 +# 13.13 +linux_genassym.o optional compat_linux \ 13.14 + dependency "$S/i386/linux/linux_genassym.c" \ 13.15 + compile-with "${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}" \ 13.16 + no-obj no-implicit-rule \ 13.17 + clean "linux_genassym.o" 13.18 +# 13.19 +linux_assym.h optional compat_linux \ 13.20 + dependency "$S/kern/genassym.sh linux_genassym.o" \ 13.21 + compile-with "sh $S/kern/genassym.sh linux_genassym.o > ${.TARGET}" \ 13.22 + no-obj no-implicit-rule before-depend \ 13.23 + clean "linux_assym.h" 13.24 +# 13.25 +svr4_genassym.o optional compat_svr4 \ 13.26 + dependency "$S/i386/svr4/svr4_genassym.c" \ 13.27 + compile-with "${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}" \ 13.28 + no-obj no-implicit-rule \ 13.29 + clean "svr4_genassym.o" 13.30 +# 13.31 +svr4_assym.h optional compat_svr4 \ 13.32 + dependency "$S/kern/genassym.sh svr4_genassym.o" \ 13.33 + compile-with "sh $S/kern/genassym.sh svr4_genassym.o > ${.TARGET}" \ 13.34 + no-obj no-implicit-rule before-depend \ 13.35 + clean "svr4_assym.h" 13.36 +# 13.37 +font.h optional sc_dflt_font \ 13.38 + compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'static u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'static u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'static u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \ 13.39 + no-obj no-implicit-rule before-depend \ 13.40 + clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8" 13.41 +# 13.42 +atkbdmap.h optional atkbd_dflt_keymap \ 13.43 + compile-with "/usr/sbin/kbdcontrol -L ${ATKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > atkbdmap.h" \ 13.44 + no-obj no-implicit-rule before-depend \ 13.45 + clean "atkbdmap.h" 13.46 +# 13.47 +ukbdmap.h optional ukbd_dflt_keymap \ 13.48 + compile-with "/usr/sbin/kbdcontrol -L ${UKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > ukbdmap.h" \ 13.49 + no-obj no-implicit-rule before-depend \ 13.50 + clean "ukbdmap.h" 13.51 +# 13.52 +msysosak.o optional fla \ 13.53 + dependency "$S/contrib/dev/fla/i386/msysosak.o.uu" \ 13.54 + compile-with "uudecode < $S/contrib/dev/fla/i386/msysosak.o.uu" \ 13.55 + no-implicit-rule 13.56 +# 13.57 +trlld.o optional oltr \ 13.58 + dependency "$S/contrib/dev/oltr/i386-elf.trlld.o.uu" \ 13.59 + compile-with "uudecode < $S/contrib/dev/oltr/i386-elf.trlld.o.uu" \ 13.60 + no-implicit-rule 13.61 +# 13.62 +hal.o optional ath_hal \ 13.63 + dependency "$S/contrib/dev/ath/freebsd/i386-elf.hal.o.uu" \ 13.64 + compile-with "uudecode < $S/contrib/dev/ath/freebsd/i386-elf.hal.o.uu" \ 13.65 + no-implicit-rule 13.66 +# 13.67 +# 13.68 +compat/linux/linux_file.c optional compat_linux 13.69 +compat/linux/linux_getcwd.c optional compat_linux 13.70 +compat/linux/linux_ioctl.c optional compat_linux 13.71 +compat/linux/linux_ipc.c optional compat_linux 13.72 +compat/linux/linux_mib.c optional compat_linux 13.73 +compat/linux/linux_misc.c optional compat_linux 13.74 +compat/linux/linux_signal.c optional compat_linux 13.75 +compat/linux/linux_socket.c optional compat_linux 13.76 +compat/linux/linux_stats.c optional compat_linux 13.77 +compat/linux/linux_sysctl.c optional compat_linux 13.78 +compat/linux/linux_uid16.c optional compat_linux 13.79 +compat/linux/linux_util.c optional compat_linux 13.80 +compat/pecoff/imgact_pecoff.c optional pecoff_support 13.81 +compat/svr4/imgact_svr4.c optional compat_svr4 13.82 +compat/svr4/svr4_fcntl.c optional compat_svr4 13.83 +compat/svr4/svr4_filio.c optional compat_svr4 13.84 +compat/svr4/svr4_ioctl.c optional compat_svr4 13.85 +compat/svr4/svr4_ipc.c optional compat_svr4 13.86 +compat/svr4/svr4_misc.c optional compat_svr4 13.87 +compat/svr4/svr4_resource.c optional compat_svr4 13.88 +compat/svr4/svr4_signal.c optional compat_svr4 13.89 +compat/svr4/svr4_socket.c optional compat_svr4 13.90 +compat/svr4/svr4_sockio.c optional compat_svr4 13.91 +compat/svr4/svr4_stat.c optional compat_svr4 13.92 +compat/svr4/svr4_stream.c optional compat_svr4 13.93 +compat/svr4/svr4_syscallnames.c optional compat_svr4 13.94 +compat/svr4/svr4_sysent.c optional compat_svr4 13.95 +compat/svr4/svr4_sysvec.c optional compat_svr4 13.96 +compat/svr4/svr4_termios.c optional compat_svr4 13.97 +compat/svr4/svr4_ttold.c optional compat_svr4 13.98 +contrib/dev/fla/fla.c optional fla 13.99 +contrib/dev/oltr/if_oltr.c optional oltr 13.100 +contrib/dev/oltr/trlldbm.c optional oltr 13.101 +contrib/dev/oltr/trlldhm.c optional oltr 13.102 +contrib/dev/oltr/trlldmac.c optional oltr 13.103 +bf_enc.o optional ipsec ipsec_esp \ 13.104 + dependency "$S/crypto/blowfish/arch/i386/bf_enc.S $S/crypto/blowfish/arch/i386/bf_enc_586.S $S/crypto/blowfish/arch/i386/bf_enc_686.S" \ 13.105 + compile-with "${CC} -c -I$S/crypto/blowfish/arch/i386 ${ASM_CFLAGS} ${WERROR} ${.IMPSRC}" \ 13.106 + no-implicit-rule 13.107 +crypto/des/arch/i386/des_enc.S optional ipsec ipsec_esp 13.108 +crypto/des/des_ecb.c optional netsmbcrypto 13.109 +crypto/des/arch/i386/des_enc.S optional netsmbcrypto 13.110 +crypto/des/des_setkey.c optional netsmbcrypto 13.111 +bf_enc.o optional crypto \ 13.112 + dependency "$S/crypto/blowfish/arch/i386/bf_enc.S $S/crypto/blowfish/arch/i386/bf_enc_586.S $S/crypto/blowfish/arch/i386/bf_enc_686.S" \ 13.113 + compile-with "${CC} -c -I$S/crypto/blowfish/arch/i386 ${ASM_CFLAGS} ${WERROR} ${.IMPSRC}" \ 13.114 + no-implicit-rule 13.115 +crypto/des/arch/i386/des_enc.S optional crypto 13.116 +crypto/des/des_ecb.c optional crypto 13.117 +crypto/des/des_setkey.c optional crypto 13.118 +dev/ar/if_ar.c optional ar 13.119 +dev/ar/if_ar_pci.c optional ar pci 13.120 +dev/cx/csigma.c optional cx 13.121 +dev/cx/cxddk.c optional cx 13.122 +dev/cx/if_cx.c optional cx 13.123 +dev/dgb/dgb.c count dgb 13.124 +dev/fb/fb.c optional fb 13.125 +dev/fb/fb.c optional vga 13.126 +dev/fb/splash.c optional splash 13.127 +dev/fb/vga.c optional vga 13.128 +dev/kbd/atkbd.c optional atkbd 13.129 +dev/kbd/atkbdc.c optional atkbdc 13.130 +dev/kbd/kbd.c optional atkbd 13.131 +dev/kbd/kbd.c optional kbd 13.132 +dev/kbd/kbd.c optional sc 13.133 +dev/kbd/kbd.c optional ukbd 13.134 +dev/kbd/kbd.c optional vt 13.135 +dev/mem/memutil.c standard 13.136 +dev/random/nehemiah.c standard 13.137 +dev/ppc/ppc.c optional ppc 13.138 +dev/ppc/ppc_puc.c optional ppc puc pci 13.139 +dev/sio/sio.c optional sio 13.140 +dev/sio/sio_isa.c optional sio isa 13.141 +dev/syscons/schistory.c optional sc 13.142 +dev/syscons/scmouse.c optional sc 13.143 +dev/syscons/scterm.c optional sc 13.144 +dev/syscons/scterm-dumb.c optional sc 13.145 +dev/syscons/scterm-sc.c optional sc 13.146 +dev/syscons/scvesactl.c optional sc vga vesa 13.147 +dev/syscons/scvgarndr.c optional sc vga 13.148 +dev/syscons/scvidctl.c optional sc 13.149 +dev/syscons/scvtb.c optional sc 13.150 +dev/syscons/syscons.c optional sc 13.151 +dev/syscons/sysmouse.c optional sc 13.152 +dev/uart/uart_cpu_i386.c optional uart 13.153 +geom/geom_bsd.c standard 13.154 +geom/geom_bsd_enc.c standard 13.155 +geom/geom_mbr.c standard 13.156 +geom/geom_mbr_enc.c standard 13.157 +i386/acpica/OsdEnvironment.c optional acpi 13.158 +i386/acpica/acpi_machdep.c optional acpi 13.159 +i386/acpica/acpi_wakeup.c optional acpi 13.160 +acpi_wakecode.h optional acpi \ 13.161 + dependency "$S/i386/acpica/acpi_wakecode.S" \ 13.162 + compile-with "${MAKE} -f $S/i386/acpica/Makefile MAKESRCPATH=$S/i386/acpica" \ 13.163 + no-obj no-implicit-rule before-depend \ 13.164 + clean "acpi_wakecode.h acpi_wakecode.o acpi_wakecode.bin" 13.165 +# 13.166 +i386/acpica/madt.c optional acpi apic 13.167 +i386/bios/mca_machdep.c optional mca 13.168 +i386/bios/smapi.c optional smapi 13.169 +i386/bios/smapi_bios.S optional smapi 13.170 +i386/bios/smbios.c optional smbios 13.171 +i386/bios/vpd.c optional vpd 13.172 +i386/i386/apic_vector.s optional apic 13.173 +i386/i386/atomic.c standard \ 13.174 + compile-with "${CC} -c ${CFLAGS} ${DEFINED_PROF:S/^$/-fomit-frame-pointer/} ${.IMPSRC}" 13.175 +i386/i386/autoconf.c standard 13.176 +i386/i386/busdma_machdep.c standard 13.177 +i386-xen/i386-xen/critical.c standard 13.178 +i386/i386/db_disasm.c optional ddb 13.179 +i386-xen/i386-xen/db_interface.c optional ddb 13.180 +i386/i386/db_trace.c optional ddb 13.181 +i386/i386/i386-gdbstub.c optional ddb 13.182 +i386/i386/dump_machdep.c standard 13.183 +i386/i386/elf_machdep.c standard 13.184 +i386-xen/i386-xen/exception.s standard 13.185 +i386-xen/i386-xen/i686_mem.c standard 13.186 +i386/i386/identcpu.c standard 13.187 +i386/i386/in_cksum.c optional inet 13.188 +i386-xen/i386-xen/initcpu.c standard 13.189 +i386-xen/i386-xen/intr_machdep.c standard 13.190 +i386-xen/i386-xen/io_apic.c optional apic 13.191 +i386/i386/legacy.c standard 13.192 +i386-xen/i386-xen/locore.s standard no-obj 13.193 +i386-xen/i386-xen/machdep.c standard 13.194 +i386/i386/mem.c standard 13.195 +i386-xen/i386-xen/mp_clock.c optional smp 13.196 +i386-xen/i386-xen/mp_machdep.c optional smp 13.197 +i386/i386/mpboot.s optional smp 13.198 +i386-xen/i386-xen/mptable.c optional apic 13.199 +i386-xen/i386-xen/local_apic.c optional apic 13.200 +i386/i386/mptable_pci.c optional apic pci 13.201 +i386/i386/nexus.c standard 13.202 +i386/i386/uio_machdep.c standard 13.203 +i386/i386/perfmon.c optional perfmon 13.204 +i386/i386/perfmon.c optional perfmon profiling-routine 13.205 +i386-xen/i386-xen/pmap.c standard 13.206 +i386-xen/i386-xen/support.s standard 13.207 +i386-xen/i386-xen/swtch.s standard 13.208 +i386-xen/i386-xen/sys_machdep.c standard 13.209 +i386-xen/i386-xen/trap.c standard 13.210 +i386/i386/tsc.c standard 13.211 +i386-xen/i386-xen/vm_machdep.c standard 13.212 +i386-xen/i386-xen/clock.c standard 13.213 + 13.214 +# xen specific arch-dep files 13.215 +i386-xen/i386-xen/hypervisor.c standard 13.216 +i386-xen/i386-xen/xen_machdep.c standard 13.217 +i386-xen/i386-xen/xen_bus.c standard 13.218 +i386-xen/i386-xen/evtchn.c standard 13.219 +i386-xen/i386-xen/ctrl_if.c standard 13.220 + 13.221 + 13.222 +i386/isa/asc.c count asc 13.223 +i386/isa/ctx.c optional ctx 13.224 +i386/isa/cy.c count cy 13.225 +i386/isa/elink.c optional ep 13.226 +i386/isa/elink.c optional ie 13.227 +i386/isa/gpib.c optional gp 13.228 +i386/isa/gsc.c count gsc 13.229 +i386/isa/istallion.c optional stli nowerror 13.230 +i386/isa/loran.c optional loran 13.231 +i386/isa/mse.c optional mse 13.232 +i386/isa/nmi.c standard 13.233 + 13.234 +# drivers 13.235 +i386-xen/xen/misc/npx.c optional npx 13.236 +i386-xen/xen/misc/evtchn_dev.c standard 13.237 +i386-xen/xen/char/console.c standard 13.238 +i386-xen/xen/netfront/xn_netfront.c standard 13.239 +i386-xen/xen/blkfront/xb_blkfront.c standard 13.240 + 13.241 + 13.242 + 13.243 +i386/isa/pcf.c optional pcf 13.244 +i386/isa/pcvt/pcvt_drv.c optional vt 13.245 +i386/isa/pcvt/pcvt_ext.c optional vt 13.246 +i386/isa/pcvt/pcvt_kbd.c optional vt 13.247 +i386/isa/pcvt/pcvt_out.c optional vt 13.248 +i386/isa/pcvt/pcvt_sup.c optional vt 13.249 +i386/isa/pcvt/pcvt_vtf.c optional vt 13.250 +i386/isa/pmtimer.c optional pmtimer 13.251 +i386/isa/prof_machdep.c optional profiling-routine 13.252 +i386/isa/spic.c optional spic 13.253 +i386/isa/spigot.c count spigot 13.254 +i386/isa/spkr.c optional speaker 13.255 +i386/isa/stallion.c optional stl nowerror 13.256 +i386/isa/vesa.c optional vga vesa 13.257 +i386/isa/wt.c count wt 13.258 +i386/linux/imgact_linux.c optional compat_linux 13.259 +i386/linux/linux_dummy.c optional compat_linux 13.260 +i386/linux/linux_locore.s optional compat_linux \ 13.261 + dependency "linux_assym.h" 13.262 +i386/linux/linux_machdep.c optional compat_linux 13.263 +i386/linux/linux_ptrace.c optional compat_linux 13.264 +i386/linux/linux_sysent.c optional compat_linux 13.265 +i386/linux/linux_sysvec.c optional compat_linux 13.266 +i386/pci/pci_cfgreg.c optional pci 13.267 +i386/pci/pci_bus.c optional pci 13.268 +i386/svr4/svr4_locore.s optional compat_svr4 \ 13.269 + dependency "svr4_assym.h" \ 13.270 + warning "COMPAT_SVR4 is broken and should be avoided" 13.271 +i386/svr4/svr4_machdep.c optional compat_svr4 13.272 +isa/atkbd_isa.c optional atkbd 13.273 +isa/atkbdc_isa.c optional atkbdc 13.274 +isa/fd.c optional fdc 13.275 +isa/psm.c optional psm 13.276 +isa/syscons_isa.c optional sc 13.277 +isa/vga_isa.c optional vga 13.278 +kern/imgact_aout.c optional compat_aout 13.279 +kern/imgact_gzip.c optional gzip 13.280 +libkern/divdi3.c standard 13.281 +libkern/moddi3.c standard 13.282 +libkern/qdivrem.c standard 13.283 +libkern/ucmpdi2.c standard 13.284 +libkern/udivdi3.c standard 13.285 +libkern/umoddi3.c standard 13.286 +libkern/flsl.c standard 13.287 +libkern/ffsl.c standard 13.288 + 13.289 +pci/cy_pci.c optional cy pci 13.290 +pci/agp_intel.c optional agp 13.291 +pci/agp_via.c optional agp 13.292 +pci/agp_sis.c optional agp 13.293 +pci/agp_ali.c optional agp 13.294 +pci/agp_amd.c optional agp 13.295 +pci/agp_i810.c optional agp 13.296 +pci/agp_nvidia.c optional agp 13.297 +
14.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 14.2 +++ b/freebsd-5.3-xen-sparse/conf/ldscript.i386-xen Thu Mar 24 22:52:13 2005 +0000 14.3 @@ -0,0 +1,134 @@ 14.4 +/* $FreeBSD: src/sys/conf/ldscript.i386,v 1.9 2003/12/03 07:40:03 phk Exp $ */ 14.5 +OUTPUT_FORMAT("elf32-i386-freebsd", "elf32-i386-freebsd", "elf32-i386-freebsd") 14.6 +OUTPUT_ARCH(i386) 14.7 +ENTRY(btext) 14.8 +SEARCH_DIR(/usr/lib); 14.9 +SECTIONS 14.10 +{ 14.11 + /* Read-only sections, merged into text segment: */ 14.12 + . = kernbase + SIZEOF_HEADERS; 14.13 + .interp : { *(.interp) } 14.14 + .hash : { *(.hash) } 14.15 + .dynsym : { *(.dynsym) } 14.16 + .dynstr : { *(.dynstr) } 14.17 + .gnu.version : { *(.gnu.version) } 14.18 + .gnu.version_d : { *(.gnu.version_d) } 14.19 + .gnu.version_r : { *(.gnu.version_r) } 14.20 + .rel.text : 14.21 + { *(.rel.text) *(.rel.gnu.linkonce.t*) } 14.22 + .rela.text : 14.23 + { *(.rela.text) *(.rela.gnu.linkonce.t*) } 14.24 + .rel.data : 14.25 + { *(.rel.data) *(.rel.gnu.linkonce.d*) } 14.26 + .rela.data : 14.27 + { *(.rela.data) *(.rela.gnu.linkonce.d*) } 14.28 + .rel.rodata : 14.29 + { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } 14.30 + .rela.rodata : 14.31 + { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } 14.32 + .rel.got : { *(.rel.got) } 14.33 + .rela.got : { *(.rela.got) } 14.34 + .rel.ctors : { *(.rel.ctors) } 14.35 + .rela.ctors : { *(.rela.ctors) } 14.36 + .rel.dtors : { *(.rel.dtors) } 14.37 + .rela.dtors : { *(.rela.dtors) } 14.38 + .rel.init : { *(.rel.init) } 14.39 + .rela.init : { *(.rela.init) } 14.40 + .rel.fini : { *(.rel.fini) } 14.41 + .rela.fini : { *(.rela.fini) } 14.42 + .rel.bss : { *(.rel.bss) } 14.43 + .rela.bss : { *(.rela.bss) } 14.44 + .rel.plt : { *(.rel.plt) } 14.45 + .rela.plt : { *(.rela.plt) } 14.46 + .init : { *(.init) } =0x9090 14.47 + .plt : { *(.plt) } 14.48 + .text : 14.49 + { 14.50 + *(.text) 14.51 + *(.stub) 14.52 + /* .gnu.warning sections are handled specially by elf32.em. */ 14.53 + *(.gnu.warning) 14.54 + *(.gnu.linkonce.t*) 14.55 + } =0x9090 14.56 + _etext = .; 14.57 + PROVIDE (etext = .); 14.58 + .fini : { *(.fini) } =0x9090 14.59 + .rodata : { *(.rodata) *(.gnu.linkonce.r*) } 14.60 + .rodata1 : { *(.rodata1) } 14.61 + /* Adjust the address for the data segment. We want to adjust up to 14.62 + the same address within the page on the next page up. */ 14.63 + . = ALIGN(0x1000) + (. & (0x1000 - 1)) ; 14.64 + .data : 14.65 + { 14.66 + *(.data) 14.67 + *(.gnu.linkonce.d*) 14.68 + CONSTRUCTORS 14.69 + } 14.70 + .data1 : { *(.data1) } 14.71 + . = ALIGN(32 / 8); 14.72 + _start_ctors = .; 14.73 + PROVIDE (start_ctors = .); 14.74 + .ctors : 14.75 + { 14.76 + *(.ctors) 14.77 + } 14.78 + _stop_ctors = .; 14.79 + PROVIDE (stop_ctors = .); 14.80 + .dtors : 14.81 + { 14.82 + *(.dtors) 14.83 + } 14.84 + .got : { *(.got.plt) *(.got) } 14.85 + .dynamic : { *(.dynamic) } 14.86 + /* We want the small data sections together, so single-instruction offsets 14.87 + can access them all, and initialized data all before uninitialized, so 14.88 + we can shorten the on-disk segment size. */ 14.89 + .sdata : { *(.sdata) } 14.90 + _edata = .; 14.91 + PROVIDE (edata = .); 14.92 + __bss_start = .; 14.93 + .sbss : { *(.sbss) *(.scommon) } 14.94 + .bss : 14.95 + { 14.96 + *(.dynbss) 14.97 + *(.bss) 14.98 + *(COMMON) 14.99 + } 14.100 + . = ALIGN(32 / 8); 14.101 + _end = . ; 14.102 + PROVIDE (end = .); 14.103 + /* Stabs debugging sections. */ 14.104 + .stab 0 : { *(.stab) } 14.105 + .stabstr 0 : { *(.stabstr) } 14.106 + .stab.excl 0 : { *(.stab.excl) } 14.107 + .stab.exclstr 0 : { *(.stab.exclstr) } 14.108 + .stab.index 0 : { *(.stab.index) } 14.109 + .stab.indexstr 0 : { *(.stab.indexstr) } 14.110 + .comment 0 : { *(.comment) } 14.111 + /* DWARF debug sections. 14.112 + Symbols in the DWARF debugging sections are relative to the beginning 14.113 + of the section so we begin them at 0. */ 14.114 + /* DWARF 1 */ 14.115 + .debug 0 : { *(.debug) } 14.116 + .line 0 : { *(.line) } 14.117 + /* GNU DWARF 1 extensions */ 14.118 + .debug_srcinfo 0 : { *(.debug_srcinfo) } 14.119 + .debug_sfnames 0 : { *(.debug_sfnames) } 14.120 + /* DWARF 1.1 and DWARF 2 */ 14.121 + .debug_aranges 0 : { *(.debug_aranges) } 14.122 + .debug_pubnames 0 : { *(.debug_pubnames) } 14.123 + /* DWARF 2 */ 14.124 + .debug_info 0 : { *(.debug_info) } 14.125 + .debug_abbrev 0 : { *(.debug_abbrev) } 14.126 + .debug_line 0 : { *(.debug_line) } 14.127 + .debug_frame 0 : { *(.debug_frame) } 14.128 + .debug_str 0 : { *(.debug_str) } 14.129 + .debug_loc 0 : { *(.debug_loc) } 14.130 + .debug_macinfo 0 : { *(.debug_macinfo) } 14.131 + /* SGI/MIPS DWARF 2 extensions */ 14.132 + .debug_weaknames 0 : { *(.debug_weaknames) } 14.133 + .debug_funcnames 0 : { *(.debug_funcnames) } 14.134 + .debug_typenames 0 : { *(.debug_typenames) } 14.135 + .debug_varnames 0 : { *(.debug_varnames) } 14.136 + /* These must appear regardless of . */ 14.137 +}
15.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 15.2 +++ b/freebsd-5.3-xen-sparse/conf/options.i386-xen Thu Mar 24 22:52:13 2005 +0000 15.3 @@ -0,0 +1,162 @@ 15.4 +# $FreeBSD: src/sys/conf/options.i386,v 1.204 2003/12/03 23:06:30 imp Exp $ 15.5 +# Options specific to the i386 platform kernels 15.6 + 15.7 +AUTO_EOI_1 opt_auto_eoi.h 15.8 +AUTO_EOI_2 opt_auto_eoi.h 15.9 +BROKEN_KEYBOARD_RESET opt_reset.h 15.10 +COMPAT_OLDISA 15.11 +I586_PMC_GUPROF opt_i586_guprof.h 15.12 +MAXMEM 15.13 +MPTABLE_FORCE_HTT 15.14 +NO_MIXED_MODE 15.15 +PERFMON 15.16 +DISABLE_PSE opt_pmap.h 15.17 +DISABLE_PG_G opt_pmap.h 15.18 +PMAP_SHPGPERPROC opt_pmap.h 15.19 +PPC_PROBE_CHIPSET opt_ppc.h 15.20 +PPC_DEBUG opt_ppc.h 15.21 +POWERFAIL_NMI opt_trap.h 15.22 +MP_WATCHDOG opt_mp_watchdog.h 15.23 + 15.24 + 15.25 + 15.26 +# Options for emulators. These should only be used at config time, so 15.27 +# they are handled like options for static filesystems 15.28 +# (see src/sys/conf/options), except for broken debugging options. 15.29 +COMPAT_AOUT opt_dontuse.h 15.30 +IBCS2 opt_dontuse.h 15.31 +COMPAT_LINUX opt_dontuse.h 15.32 +COMPAT_SVR4 opt_dontuse.h 15.33 +DEBUG_SVR4 opt_svr4.h 15.34 +PECOFF_SUPPORT opt_dontuse.h 15.35 +PECOFF_DEBUG opt_pecoff.h 15.36 + 15.37 +# Change KVM size. Changes things all over the kernel. 15.38 +KVA_PAGES opt_global.h 15.39 +XEN opt_global.h 15.40 +XENDEV opt_xen.h 15.41 +NOXENDEBUG opt_xen.h 15.42 +# Physical address extensions and support for >4G ram. As above. 15.43 +PAE opt_global.h 15.44 + 15.45 +CLK_CALIBRATION_LOOP opt_clock.h 15.46 +CLK_USE_I8254_CALIBRATION opt_clock.h 15.47 +CLK_USE_TSC_CALIBRATION opt_clock.h 15.48 +TIMER_FREQ opt_clock.h 15.49 + 15.50 +CPU_ATHLON_SSE_HACK opt_cpu.h 15.51 +CPU_BLUELIGHTNING_3X opt_cpu.h 15.52 +CPU_BLUELIGHTNING_FPU_OP_CACHE opt_cpu.h 15.53 +CPU_BTB_EN opt_cpu.h 15.54 +CPU_CYRIX_NO_LOCK opt_cpu.h 15.55 +CPU_DIRECT_MAPPED_CACHE opt_cpu.h 15.56 +CPU_DISABLE_5X86_LSSER opt_cpu.h 15.57 +CPU_DISABLE_CMPXCHG opt_global.h # XXX global, unlike other CPU_* 15.58 +CPU_DISABLE_SSE opt_cpu.h 15.59 +CPU_ELAN opt_cpu.h 15.60 +CPU_ELAN_XTAL opt_cpu.h 15.61 +CPU_ELAN_PPS opt_cpu.h 15.62 +CPU_ENABLE_SSE opt_cpu.h 15.63 +CPU_FASTER_5X86_FPU opt_cpu.h 15.64 +CPU_GEODE opt_cpu.h 15.65 +CPU_I486_ON_386 opt_cpu.h 15.66 +CPU_IORT opt_cpu.h 15.67 +CPU_L2_LATENCY opt_cpu.h 15.68 +CPU_LOOP_EN opt_cpu.h 15.69 +CPU_PPRO2CELERON opt_cpu.h 15.70 +CPU_RSTK_EN opt_cpu.h 15.71 +CPU_SOEKRIS opt_cpu.h 15.72 +CPU_SUSP_HLT opt_cpu.h 15.73 +CPU_UPGRADE_HW_CACHE opt_cpu.h 15.74 +CPU_WT_ALLOC opt_cpu.h 15.75 +CYRIX_CACHE_REALLY_WORKS opt_cpu.h 15.76 +CYRIX_CACHE_WORKS opt_cpu.h 15.77 +NO_F00F_HACK opt_cpu.h 15.78 +NO_MEMORY_HOLE opt_cpu.h 15.79 + 15.80 +# The CPU type affects the endian conversion functions all over the kernel. 15.81 +I386_CPU opt_global.h 15.82 +I486_CPU opt_global.h 15.83 +I586_CPU opt_global.h 15.84 +I686_CPU opt_global.h 15.85 + 15.86 +VGA_ALT_SEQACCESS opt_vga.h 15.87 +VGA_DEBUG opt_vga.h 15.88 +VGA_NO_FONT_LOADING opt_vga.h 15.89 +VGA_NO_MODE_CHANGE opt_vga.h 15.90 +VGA_SLOW_IOACCESS opt_vga.h 15.91 +VGA_WIDTH90 opt_vga.h 15.92 + 15.93 +VESA 15.94 +VESA_DEBUG opt_vesa.h 15.95 + 15.96 +PSM_HOOKRESUME opt_psm.h 15.97 +PSM_RESETAFTERSUSPEND opt_psm.h 15.98 +PSM_DEBUG opt_psm.h 15.99 + 15.100 +ATKBD_DFLT_KEYMAP opt_atkbd.h 15.101 + 15.102 +# pcvt(4) has a bunch of options 15.103 +FAT_CURSOR opt_pcvt.h 15.104 +XSERVER opt_pcvt.h 15.105 +PCVT_24LINESDEF opt_pcvt.h 15.106 +PCVT_CTRL_ALT_DEL opt_pcvt.h 15.107 +PCVT_META_ESC opt_pcvt.h 15.108 +PCVT_NSCREENS opt_pcvt.h 15.109 +PCVT_PRETTYSCRNS opt_pcvt.h 15.110 +PCVT_SCANSET opt_pcvt.h 15.111 +PCVT_SCREENSAVER opt_pcvt.h 15.112 +PCVT_USEKBDSEC opt_pcvt.h 15.113 +PCVT_VT220KEYB opt_pcvt.h 15.114 +PCVT_GREENSAVER opt_pcvt.h 15.115 + 15.116 +# Video spigot 15.117 +SPIGOT_UNSECURE opt_spigot.h 15.118 + 15.119 +# Enables NETGRAPH support for Cronyx adapters 15.120 +NETGRAPH_CRONYX opt_ng_cronyx.h 15.121 + 15.122 +# ------------------------------- 15.123 +# isdn4bsd: passive ISA cards 15.124 +# ------------------------------- 15.125 +TEL_S0_8 opt_i4b.h 15.126 +TEL_S0_16 opt_i4b.h 15.127 +TEL_S0_16_3 opt_i4b.h 15.128 +AVM_A1 opt_i4b.h 15.129 +USR_STI opt_i4b.h 15.130 +ITKIX1 opt_i4b.h 15.131 +ELSA_PCC16 opt_i4b.h 15.132 +# ------------------------------- 15.133 +# isdn4bsd: passive ISA PnP cards 15.134 +# ------------------------------- 15.135 +CRTX_S0_P opt_i4b.h 15.136 +DRN_NGO opt_i4b.h 15.137 +TEL_S0_16_3_P opt_i4b.h 15.138 +SEDLBAUER opt_i4b.h 15.139 +DYNALINK opt_i4b.h 15.140 +ASUSCOM_IPAC opt_i4b.h 15.141 +ELSA_QS1ISA opt_i4b.h 15.142 +SIEMENS_ISURF2 opt_i4b.h 15.143 +EICON_DIVA opt_i4b.h 15.144 +COMPAQ_M610 opt_i4b.h 15.145 +# ------------------------------- 15.146 +# isdn4bsd: passive PCI cards 15.147 +# ------------------------------- 15.148 +ELSA_QS1PCI opt_i4b.h 15.149 +# ------------------------------- 15.150 +# isdn4bsd: misc options 15.151 +# ------------------------------- 15.152 +# temporary workaround for SMP machines 15.153 +I4B_SMP_WORKAROUND opt_i4b.h 15.154 +# enable VJ compression code for ipr i/f 15.155 +IPR_VJ opt_i4b.h 15.156 +IPR_LOG opt_i4b.h 15.157 + 15.158 +# Device options 15.159 +DEV_ACPI opt_acpi.h 15.160 +DEV_APIC opt_apic.h 15.161 +DEV_NPX opt_npx.h 15.162 + 15.163 +# ------------------------------- 15.164 +# EOF 15.165 +# -------------------------------
16.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 16.2 +++ b/freebsd-5.3-xen-sparse/fbsdxensetup Thu Mar 24 22:52:13 2005 +0000 16.3 @@ -0,0 +1,39 @@ 16.4 +#!/bin/csh -f 16.5 + 16.6 +setenv XENROOT `bk root` 16.7 +rm -rf $XENROOT/fbsdtmp $XENROOT/freebsd-5.3-xenU 16.8 +mkdir -p $XENROOT/fbsdtmp 16.9 +cd $XENROOT/fbsdtmp 16.10 +echo "step 1" 16.11 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.aa 16.12 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ab 16.13 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ac 16.14 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ad 16.15 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ae 16.16 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.af 16.17 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ag 16.18 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ah 16.19 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ai 16.20 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.aj 16.21 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ak 16.22 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.al 16.23 +mkdir -p foo 16.24 +cat ssys.?? | tar --unlink -xpzf - -C foo/ 16.25 +mkdir -p $XENROOT/freebsd-5.3-xenU 16.26 +mv foo/sys/* $XENROOT/freebsd-5.3-xenU 16.27 +cd $XENROOT 16.28 +rm -rf $XENROOT/fbsdtmp 16.29 +echo "step 2" 16.30 +mkdir -p $XENROOT/freebsd-5.3-xenU/i386-xen/include 16.31 +cd $XENROOT/freebsd-5.3-xenU/i386-xen/include/ 16.32 +foreach file (../../i386/include/*) 16.33 + ln -s $file 16.34 +end 16.35 +echo "step 3" 16.36 +cd $XENROOT/freebsd-5.3-xen-sparse 16.37 +echo "step 4" 16.38 +./mkbuildtree ../freebsd-5.3-xenU 16.39 +echo "step 5" 16.40 +cd $XENROOT/freebsd-5.3-xenU/i386-xen/include 16.41 +ln -s $XENROOT/xen/include/public xen-public 16.42 +echo "done"
17.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 17.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/Makefile Thu Mar 24 22:52:13 2005 +0000 17.3 @@ -0,0 +1,40 @@ 17.4 +# $FreeBSD: src/sys/i386/Makefile,v 1.11 2002/06/21 06:18:02 mckusick Exp $ 17.5 +# @(#)Makefile 8.1 (Berkeley) 6/11/93 17.6 + 17.7 +# Makefile for i386 links, tags file 17.8 + 17.9 +# SYS is normally set in Make.tags.inc 17.10 +# SYS=/sys 17.11 +SYS=/nsys 17.12 + 17.13 +TAGDIR= i386 17.14 + 17.15 +.include "../kern/Make.tags.inc" 17.16 + 17.17 +all: 17.18 + @echo "make links or tags only" 17.19 + 17.20 +# Directories in which to place i386 tags links 17.21 +DI386= apm i386 ibcs2 include isa linux 17.22 + 17.23 +links:: 17.24 + -for i in ${COMMDIR1}; do \ 17.25 + (cd $$i && { rm -f tags; ln -s ../${TAGDIR}/tags tags; }) done 17.26 + -for i in ${COMMDIR2}; do \ 17.27 + (cd $$i && { rm -f tags; ln -s ../../${TAGDIR}/tags tags; }) done 17.28 + -for i in ${DI386}; do \ 17.29 + (cd $$i && { rm -f tags; ln -s ../tags tags; }) done 17.30 + 17.31 +SI386= ${SYS}/i386/apm/*.[ch] \ 17.32 + ${SYS}/i386/i386/*.[ch] ${SYS}/i386/ibcs2/*.[ch] \ 17.33 + ${SYS}/i386/include/*.[ch] ${SYS}/i386/isa/*.[ch] \ 17.34 + ${SYS}/i386/linux/*.[ch] 17.35 +AI386= ${SYS}/i386/i386/*.s 17.36 + 17.37 +tags:: 17.38 + -ctags -wdt ${COMM} ${SI386} 17.39 + egrep "^ENTRY(.*)|^ALTENTRY(.*)" ${AI386} | \ 17.40 + sed "s;\([^:]*\):\([^(]*\)(\([^, )]*\)\(.*\);\3 \1 /^\2(\3\4$$/;" \ 17.41 + >> tags 17.42 + sort -o tags tags 17.43 + chmod 444 tags
18.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 18.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/compile/.cvsignore Thu Mar 24 22:52:13 2005 +0000 18.3 @@ -0,0 +1,1 @@ 18.4 +[A-Za-z0-9]*
19.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 19.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/GENERIC Thu Mar 24 22:52:13 2005 +0000 19.3 @@ -0,0 +1,273 @@ 19.4 +# 19.5 +# GENERIC -- Generic kernel configuration file for FreeBSD/i386 19.6 +# 19.7 +# For more information on this file, please read the handbook section on 19.8 +# Kernel Configuration Files: 19.9 +# 19.10 +# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html 19.11 +# 19.12 +# The handbook is also available locally in /usr/share/doc/handbook 19.13 +# if you've installed the doc distribution, otherwise always see the 19.14 +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the 19.15 +# latest information. 19.16 +# 19.17 +# An exhaustive list of options and more detailed explanations of the 19.18 +# device lines is also present in the ../../conf/NOTES and NOTES files. 19.19 +# If you are in doubt as to the purpose or necessity of a line, check first 19.20 +# in NOTES. 19.21 +# 19.22 +# $FreeBSD: src/sys/i386/conf/GENERIC,v 1.394.2.3 2004/01/26 19:42:11 nectar Exp $ 19.23 + 19.24 +machine i386 19.25 +cpu I486_CPU 19.26 +cpu I586_CPU 19.27 +cpu I686_CPU 19.28 +ident GENERIC 19.29 + 19.30 +#To statically compile in device wiring instead of /boot/device.hints 19.31 +#hints "GENERIC.hints" #Default places to look for devices. 19.32 + 19.33 +#makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols 19.34 + 19.35 +options SCHED_4BSD #4BSD scheduler 19.36 +options INET #InterNETworking 19.37 +options INET6 #IPv6 communications protocols 19.38 +options FFS #Berkeley Fast Filesystem 19.39 +options SOFTUPDATES #Enable FFS soft updates support 19.40 +options UFS_ACL #Support for access control lists 19.41 +options UFS_DIRHASH #Improve performance on big directories 19.42 +options MD_ROOT #MD is a potential root device 19.43 +options NFSCLIENT #Network Filesystem Client 19.44 +options NFSSERVER #Network Filesystem Server 19.45 +options NFS_ROOT #NFS usable as /, requires NFSCLIENT 19.46 +options MSDOSFS #MSDOS Filesystem 19.47 +options CD9660 #ISO 9660 Filesystem 19.48 +options PROCFS #Process filesystem (requires PSEUDOFS) 19.49 +options PSEUDOFS #Pseudo-filesystem framework 19.50 +options COMPAT_43 #Compatible with BSD 4.3 [KEEP THIS!] 19.51 +options COMPAT_FREEBSD4 #Compatible with FreeBSD4 19.52 +options SCSI_DELAY=15000 #Delay (in ms) before probing SCSI 19.53 +options KTRACE #ktrace(1) support 19.54 +options SYSVSHM #SYSV-style shared memory 19.55 +options SYSVMSG #SYSV-style message queues 19.56 +options SYSVSEM #SYSV-style semaphores 19.57 +options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions 19.58 +options KBD_INSTALL_CDEV # install a CDEV entry in /dev 19.59 +options AHC_REG_PRETTY_PRINT # Print register bitfields in debug 19.60 + # output. Adds ~128k to driver. 19.61 +options AHD_REG_PRETTY_PRINT # Print register bitfields in debug 19.62 + # output. Adds ~215k to driver. 19.63 +options PFIL_HOOKS # pfil(9) framework 19.64 + 19.65 +# Debugging for use in -current 19.66 +#options DDB #Enable the kernel debugger 19.67 +#options INVARIANTS #Enable calls of extra sanity checking 19.68 +options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS 19.69 +#options WITNESS #Enable checks to detect deadlocks and cycles 19.70 +#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed 19.71 + 19.72 +# To make an SMP kernel, the next two are needed 19.73 +options SMP # Symmetric MultiProcessor Kernel 19.74 +device apic # I/O APIC 19.75 + 19.76 +device isa 19.77 +device eisa 19.78 +device pci 19.79 + 19.80 +# Floppy drives 19.81 +device fdc 19.82 + 19.83 +# ATA and ATAPI devices 19.84 +device ata 19.85 +device atadisk # ATA disk drives 19.86 +device ataraid # ATA RAID drives 19.87 +device atapicd # ATAPI CDROM drives 19.88 +device atapifd # ATAPI floppy drives 19.89 +device atapist # ATAPI tape drives 19.90 +options ATA_STATIC_ID #Static device numbering 19.91 + 19.92 +# SCSI Controllers 19.93 +device ahb # EISA AHA1742 family 19.94 +device ahc # AHA2940 and onboard AIC7xxx devices 19.95 +device ahd # AHA39320/29320 and onboard AIC79xx devices 19.96 +device amd # AMD 53C974 (Tekram DC-390(T)) 19.97 +device isp # Qlogic family 19.98 +device mpt # LSI-Logic MPT-Fusion 19.99 +#device ncr # NCR/Symbios Logic 19.100 +device sym # NCR/Symbios Logic (newer chipsets + those of `ncr') 19.101 +device trm # Tekram DC395U/UW/F DC315U adapters 19.102 + 19.103 +device adv # Advansys SCSI adapters 19.104 +device adw # Advansys wide SCSI adapters 19.105 +device aha # Adaptec 154x SCSI adapters 19.106 +device aic # Adaptec 15[012]x SCSI adapters, AIC-6[23]60. 19.107 +device bt # Buslogic/Mylex MultiMaster SCSI adapters 19.108 + 19.109 +device ncv # NCR 53C500 19.110 +device nsp # Workbit Ninja SCSI-3 19.111 +device stg # TMC 18C30/18C50 19.112 + 19.113 +# SCSI peripherals 19.114 +device scbus # SCSI bus (required for SCSI) 19.115 +device ch # SCSI media changers 19.116 +device da # Direct Access (disks) 19.117 +device sa # Sequential Access (tape etc) 19.118 +device cd # CD 19.119 +device pass # Passthrough device (direct SCSI access) 19.120 +device ses # SCSI Environmental Services (and SAF-TE) 19.121 + 19.122 +# RAID controllers interfaced to the SCSI subsystem 19.123 +device amr # AMI MegaRAID 19.124 +device asr # DPT SmartRAID V, VI and Adaptec SCSI RAID 19.125 +device ciss # Compaq Smart RAID 5* 19.126 +device dpt # DPT Smartcache III, IV - See NOTES for options 19.127 +device iir # Intel Integrated RAID 19.128 +device ips # IBM (Adaptec) ServeRAID 19.129 +device mly # Mylex AcceleRAID/eXtremeRAID 19.130 + 19.131 +# RAID controllers 19.132 +device aac # Adaptec FSA RAID 19.133 +device aacp # SCSI passthrough for aac (requires CAM) 19.134 +device ida # Compaq Smart RAID 19.135 +device mlx # Mylex DAC960 family 19.136 +device pst # Promise Supertrak SX6000 19.137 +device twe # 3ware ATA RAID 19.138 + 19.139 +# atkbdc0 controls both the keyboard and the PS/2 mouse 19.140 +device atkbdc # AT keyboard controller 19.141 +device atkbd # AT keyboard 19.142 +device psm # PS/2 mouse 19.143 + 19.144 +device vga # VGA video card driver 19.145 + 19.146 +device splash # Splash screen and screen saver support 19.147 + 19.148 +# syscons is the default console driver, resembling an SCO console 19.149 +device sc 19.150 + 19.151 +# Enable this for the pcvt (VT220 compatible) console driver 19.152 +#device vt 19.153 +#options XSERVER # support for X server on a vt console 19.154 +#options FAT_CURSOR # start with block cursor 19.155 + 19.156 +device agp # support several AGP chipsets 19.157 + 19.158 +# Floating point support - do not disable. 19.159 +device npx 19.160 + 19.161 +# Power management support (see NOTES for more options) 19.162 +#device apm 19.163 +# Add suspend/resume support for the i8254. 19.164 +device pmtimer 19.165 + 19.166 +# PCCARD (PCMCIA) support 19.167 +# Pcmcia and cardbus bridge support 19.168 +device cbb # cardbus (yenta) bridge 19.169 +#device pcic # ExCA ISA and PCI bridges 19.170 +device pccard # PC Card (16-bit) bus 19.171 +device cardbus # CardBus (32-bit) bus 19.172 + 19.173 +# Serial (COM) ports 19.174 +device sio # 8250, 16[45]50 based serial ports 19.175 + 19.176 +# Parallel port 19.177 +device ppc 19.178 +device ppbus # Parallel port bus (required) 19.179 +device lpt # Printer 19.180 +device plip # TCP/IP over parallel 19.181 +device ppi # Parallel port interface device 19.182 +#device vpo # Requires scbus and da 19.183 + 19.184 +# If you've got a "dumb" serial or parallel PCI card that is 19.185 +# supported by the puc(4) glue driver, uncomment the following 19.186 +# line to enable it (connects to the sio and/or ppc drivers): 19.187 +#device puc 19.188 + 19.189 +# PCI Ethernet NICs. 19.190 +device de # DEC/Intel DC21x4x (``Tulip'') 19.191 +device em # Intel PRO/1000 adapter Gigabit Ethernet Card 19.192 +device txp # 3Com 3cR990 (``Typhoon'') 19.193 +device vx # 3Com 3c590, 3c595 (``Vortex'') 19.194 + 19.195 +# PCI Ethernet NICs that use the common MII bus controller code. 19.196 +# NOTE: Be sure to keep the 'device miibus' line in order to use these NICs! 19.197 +device miibus # MII bus support 19.198 +device bfe # Broadcom BCM440x 10/100 ethernet 19.199 +device bge # Broadcom BCM570xx Gigabit Ethernet 19.200 +device dc # DEC/Intel 21143 and various workalikes 19.201 +device fxp # Intel EtherExpress PRO/100B (82557, 82558) 19.202 +device pcn # AMD Am79C97x PCI 10/100 (precedence over 'lnc') 19.203 +device re # RealTek 8139C+/8169/8169S/8110S 19.204 +device rl # RealTek 8129/8139 19.205 +device sf # Adaptec AIC-6915 (``Starfire'') 19.206 +device sis # Silicon Integrated Systems SiS 900/SiS 7016 19.207 +device sk # SysKonnect SK-984x and SK-982x gigabit ethernet 19.208 +device ste # Sundance ST201 (D-Link DFE-550TX) 19.209 +device ti # Alteon Networks Tigon I/II gigabit ethernet 19.210 +device tl # Texas Instruments ThunderLAN 19.211 +device tx # SMC EtherPower II (83c170 ``EPIC'') 19.212 +device vr # VIA Rhine, Rhine II 19.213 +device wb # Winbond W89C840F 19.214 +device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'') 19.215 + 19.216 +# ISA Ethernet NICs. pccard nics included. 19.217 +device cs # Crystal Semiconductor CS89x0 NIC 19.218 +# 'device ed' requires 'device miibus' 19.219 +device ed # NE[12]000, SMC Ultra, 3c503, DS8390 cards 19.220 +device ex # Intel EtherExpress Pro/10 and Pro/10+ 19.221 +device ep # Etherlink III based cards 19.222 +device fe # Fujitsu MB8696x based cards 19.223 +device ie # EtherExpress 8/16, 3C507, StarLAN 10 etc. 19.224 +device lnc # NE2100, NE32-VL Lance Ethernet cards 19.225 +device sn # SMC's 9000 series of ethernet chips 19.226 +device xe # Xircom pccard ethernet 19.227 + 19.228 +# ISA devices that use the old ISA shims 19.229 +#device le 19.230 + 19.231 +# Wireless NIC cards 19.232 +device wlan # 802.11 support 19.233 +device an # Aironet 4500/4800 802.11 wireless NICs. 19.234 +device awi # BayStack 660 and others 19.235 +device wi # WaveLAN/Intersil/Symbol 802.11 wireless NICs. 19.236 +#device wl # Older non 802.11 Wavelan wireless NIC. 19.237 + 19.238 +# Pseudo devices - the number indicates how many units to allocate. 19.239 +device random # Entropy device 19.240 +device loop # Network loopback 19.241 +device ether # Ethernet support 19.242 +device sl # Kernel SLIP 19.243 +device ppp # Kernel PPP 19.244 +device tun # Packet tunnel. 19.245 +device pty # Pseudo-ttys (telnet etc) 19.246 +device md # Memory "disks" 19.247 +device gif # IPv6 and IPv4 tunneling 19.248 +device faith # IPv6-to-IPv4 relaying (translation) 19.249 + 19.250 +# The `bpf' device enables the Berkeley Packet Filter. 19.251 +# Be aware of the administrative consequences of enabling this! 19.252 +device bpf # Berkeley packet filter 19.253 + 19.254 +# USB support 19.255 +device uhci # UHCI PCI->USB interface 19.256 +device ohci # OHCI PCI->USB interface 19.257 +device usb # USB Bus (required) 19.258 +#device udbp # USB Double Bulk Pipe devices 19.259 +device ugen # Generic 19.260 +device uhid # "Human Interface Devices" 19.261 +device ukbd # Keyboard 19.262 +device ulpt # Printer 19.263 +device umass # Disks/Mass storage - Requires scbus and da 19.264 +device ums # Mouse 19.265 +device urio # Diamond Rio 500 MP3 player 19.266 +device uscanner # Scanners 19.267 +# USB Ethernet, requires mii 19.268 +device aue # ADMtek USB ethernet 19.269 +device axe # ASIX Electronics USB ethernet 19.270 +device cue # CATC USB ethernet 19.271 +device kue # Kawasaki LSI USB ethernet 19.272 + 19.273 +# FireWire support 19.274 +device firewire # FireWire bus code 19.275 +device sbp # SCSI over FireWire (Requires scbus and da) 19.276 +device fwe # Ethernet over FireWire (non-standard!)
20.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 20.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/GENERIC.hints Thu Mar 24 22:52:13 2005 +0000 20.3 @@ -0,0 +1,93 @@ 20.4 +# $FreeBSD: src/sys/i386/conf/GENERIC.hints,v 1.11 2002/12/05 22:49:47 jhb Exp $ 20.5 +hint.fdc.0.at="isa" 20.6 +hint.fdc.0.port="0x3F0" 20.7 +hint.fdc.0.irq="6" 20.8 +hint.fdc.0.drq="2" 20.9 +hint.fd.0.at="fdc0" 20.10 +hint.fd.0.drive="0" 20.11 +hint.fd.1.at="fdc0" 20.12 +hint.fd.1.drive="1" 20.13 +hint.ata.0.at="isa" 20.14 +hint.ata.0.port="0x1F0" 20.15 +hint.ata.0.irq="14" 20.16 +hint.ata.1.at="isa" 20.17 +hint.ata.1.port="0x170" 20.18 +hint.ata.1.irq="15" 20.19 +hint.adv.0.at="isa" 20.20 +hint.adv.0.disabled="1" 20.21 +hint.bt.0.at="isa" 20.22 +hint.bt.0.disabled="1" 20.23 +hint.aha.0.at="isa" 20.24 +hint.aha.0.disabled="1" 20.25 +hint.aic.0.at="isa" 20.26 +hint.aic.0.disabled="1" 20.27 +hint.atkbdc.0.at="isa" 20.28 +hint.atkbdc.0.port="0x060" 20.29 +hint.atkbd.0.at="atkbdc" 20.30 +hint.atkbd.0.irq="1" 20.31 +hint.atkbd.0.flags="0x1" 20.32 +hint.psm.0.at="atkbdc" 20.33 +hint.psm.0.irq="12" 20.34 +hint.vga.0.at="isa" 20.35 +hint.sc.0.at="isa" 20.36 +hint.sc.0.flags="0x100" 20.37 +hint.vt.0.at="isa" 20.38 +hint.vt.0.disabled="1" 20.39 +hint.apm.0.disabled="1" 20.40 +hint.apm.0.flags="0x20" 20.41 +hint.pcic.0.at="isa" 20.42 +# hint.pcic.0.irq="10" # Default to polling 20.43 +hint.pcic.0.port="0x3e0" 20.44 +hint.pcic.0.maddr="0xd0000" 20.45 +hint.pcic.1.at="isa" 20.46 +hint.pcic.1.irq="11" 20.47 +hint.pcic.1.port="0x3e2" 20.48 +hint.pcic.1.maddr="0xd4000" 20.49 +hint.pcic.1.disabled="1" 20.50 +hint.sio.0.at="isa" 20.51 +hint.sio.0.port="0x3F8" 20.52 +hint.sio.0.flags="0x10" 20.53 +hint.sio.0.irq="4" 20.54 +hint.sio.1.at="isa" 20.55 +hint.sio.1.port="0x2F8" 20.56 +hint.sio.1.irq="3" 20.57 +hint.sio.2.at="isa" 20.58 +hint.sio.2.disabled="1" 20.59 +hint.sio.2.port="0x3E8" 20.60 +hint.sio.2.irq="5" 20.61 +hint.sio.3.at="isa" 20.62 +hint.sio.3.disabled="1" 20.63 +hint.sio.3.port="0x2E8" 20.64 +hint.sio.3.irq="9" 20.65 +hint.ppc.0.at="isa" 20.66 +hint.ppc.0.irq="7" 20.67 +hint.ed.0.at="isa" 20.68 +hint.ed.0.disabled="1" 20.69 +hint.ed.0.port="0x280" 20.70 +hint.ed.0.irq="10" 20.71 +hint.ed.0.maddr="0xd8000" 20.72 +hint.cs.0.at="isa" 20.73 +hint.cs.0.disabled="1" 20.74 +hint.cs.0.port="0x300" 20.75 +hint.sn.0.at="isa" 20.76 +hint.sn.0.disabled="1" 20.77 +hint.sn.0.port="0x300" 20.78 +hint.sn.0.irq="10" 20.79 +hint.ie.0.at="isa" 20.80 +hint.ie.0.disabled="1" 20.81 +hint.ie.0.port="0x300" 20.82 +hint.ie.0.irq="10" 20.83 +hint.ie.0.maddr="0xd0000" 20.84 +hint.fe.0.at="isa" 20.85 +hint.fe.0.disabled="1" 20.86 +hint.fe.0.port="0x300" 20.87 +hint.le.0.at="isa" 20.88 +hint.le.0.disabled="1" 20.89 +hint.le.0.port="0x300" 20.90 +hint.le.0.irq="5" 20.91 +hint.le.0.maddr="0xd0000" 20.92 +hint.lnc.0.at="isa" 20.93 +hint.lnc.0.disabled="1" 20.94 +hint.lnc.0.port="0x280" 20.95 +hint.lnc.0.irq="10" 20.96 +hint.lnc.0.drq="0"
21.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 21.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/Makefile Thu Mar 24 22:52:13 2005 +0000 21.3 @@ -0,0 +1,3 @@ 21.4 +# $FreeBSD: src/sys/i386/conf/Makefile,v 1.9 2003/02/26 23:36:58 ru Exp $ 21.5 + 21.6 +.include "${.CURDIR}/../../conf/makeLINT.mk"
22.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 22.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/NOTES Thu Mar 24 22:52:13 2005 +0000 22.3 @@ -0,0 +1,1115 @@ 22.4 +# 22.5 +# NOTES -- Lines that can be cut/pasted into kernel and hints configs. 22.6 +# 22.7 +# This file contains machine dependent kernel configuration notes. For 22.8 +# machine independent notes, look in /sys/conf/NOTES. 22.9 +# 22.10 +# $FreeBSD: src/sys/i386/conf/NOTES,v 1.1108 2003/12/04 19:57:56 phk Exp $ 22.11 +# 22.12 + 22.13 +# 22.14 +# This directive is mandatory; it defines the architecture to be 22.15 +# configured for; in this case, the 386 family based IBM-PC and 22.16 +# compatibles. 22.17 +# 22.18 +machine i386 22.19 + 22.20 +# 22.21 +# We want LINT to cover profiling as well 22.22 +profile 2 22.23 + 22.24 + 22.25 +##################################################################### 22.26 +# SMP OPTIONS: 22.27 +# 22.28 +# The apic device enables the use of the I/O APIC for interrupt delivery. 22.29 +# The apic device can be used in both UP and SMP kernels, but is required 22.30 +# for SMP kernels. Thus, the apic device is not strictly an SMP option, 22.31 +# but it is a prerequisite for SMP. 22.32 +# 22.33 +# Notes: 22.34 +# 22.35 +# Be sure to disable 'cpu I386_CPU' for SMP kernels. 22.36 +# 22.37 +# By default, mixed mode is used to route IRQ0 from the AT timer via 22.38 +# the 8259A master PIC through the ExtINT pin on the first I/O APIC. 22.39 +# This can be disabled via the NO_MIXED_MODE option. In that case, 22.40 +# IRQ0 will be routed via an intpin on the first I/O APIC. Not all 22.41 +# motherboards hook IRQ0 up to the first I/O APIC even though their 22.42 +# MP table or MADT may claim to do so. That is why mixed mode is 22.43 +# enabled by default. 22.44 +# 22.45 +# HTT CPUs should only be used if they are enabled in the BIOS. For 22.46 +# the ACPI case, ACPI only correctly tells us about any HTT CPUs if 22.47 +# they are enabled. However, most HTT systems do not list HTT CPUs 22.48 +# in the MP Table if they are enabled, thus we guess at the HTT CPUs 22.49 +# for the MP Table case. However, we shouldn't try to guess and use 22.50 +# these CPUs if HTTT is disabled. Thus, HTT guessing is only enabled 22.51 +# for the MP Table if the user explicitly asks for it via the 22.52 +# MPTABLE_FORCE_HTT option. Do NOT use this option if you have HTT 22.53 +# disabled in your BIOS. 22.54 +# 22.55 + 22.56 +# Mandatory: 22.57 +device apic # I/O apic 22.58 + 22.59 +# Optional: 22.60 +options MPTABLE_FORCE_HTT # Enable HTT CPUs with the MP Table 22.61 +options NO_MIXED_MODE # Disable use of mixed mode 22.62 + 22.63 + 22.64 +##################################################################### 22.65 +# CPU OPTIONS 22.66 + 22.67 +# 22.68 +# You must specify at least one CPU (the one you intend to run on); 22.69 +# deleting the specification for CPUs you don't need to use may make 22.70 +# parts of the system run faster. 22.71 +# I386_CPU is mutually exclusive with the other CPU types. 22.72 +# 22.73 +#cpu I386_CPU 22.74 +cpu I486_CPU 22.75 +cpu I586_CPU # aka Pentium(tm) 22.76 +cpu I686_CPU # aka Pentium Pro(tm) 22.77 + 22.78 +# 22.79 +# Options for CPU features. 22.80 +# 22.81 +# CPU_ATHLON_SSE_HACK tries to enable SSE instructions when the BIOS has 22.82 +# forgotten to enable them. 22.83 +# 22.84 +# CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM 22.85 +# BlueLightning CPU. It works only with Cyrix FPU, and this option 22.86 +# should not be used with Intel FPU. 22.87 +# 22.88 +# CPU_BLUELIGHTNING_3X enables triple-clock mode on IBM Blue Lightning 22.89 +# CPU if CPU supports it. The default is double-clock mode on 22.90 +# BlueLightning CPU box. 22.91 +# 22.92 +# CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1). 22.93 +# 22.94 +# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct 22.95 +# mapped mode. Default is 2-way set associative mode. 22.96 +# 22.97 +# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space 22.98 +# of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1. 22.99 +# Otherwise, the NO_LOCK bit of CCR1 is cleared. (NOTE 3) 22.100 +# 22.101 +# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables 22.102 +# reorder). This option should not be used if you use memory mapped 22.103 +# I/O device(s). 22.104 +# 22.105 +# CPU_ELAN enables support for AMDs ElanSC520 CPU. 22.106 +# CPU_ELAN_XTAL sets the clock crystal frequency in Hz 22.107 +# CPU_ELAN_PPS enables precision timestamp code. 22.108 +# 22.109 +# CPU_SOEKRIS enables support www.soekris.com hardware. 22.110 +# 22.111 +# CPU_ENABLE_SSE enables SSE/MMX2 instructions support. This is default 22.112 +# on I686_CPU and above. 22.113 +# CPU_DISABLE_SSE explicitly prevent I686_CPU from turning on SSE. 22.114 +# 22.115 +# CPU_FASTER_5X86_FPU enables faster FPU exception handler. 22.116 +# 22.117 +# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products 22.118 +# for i386 machines. 22.119 +# 22.120 +# CPU_IORT defines I/O clock delay time (NOTE 1). Default values of 22.121 +# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively 22.122 +# (no clock delay). 22.123 +# 22.124 +# CPU_L2_LATENCY specifed the L2 cache latency value. This option is used 22.125 +# only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected. 22.126 +# The default value is 5. 22.127 +# 22.128 +# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination 22.129 +# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE 22.130 +# 1). 22.131 +# 22.132 +# CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs. This option 22.133 +# is useful when you use Socket 8 to Socket 370 converter, because most Pentium 22.134 +# Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs. 22.135 +# 22.136 +# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1). 22.137 +# 22.138 +# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU 22.139 +# enters suspend mode following execution of HALT instruction. 22.140 +# 22.141 +# CPU_UPGRADE_HW_CACHE eliminates unneeded cache flush instruction(s). 22.142 +# 22.143 +# CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD 22.144 +# K5/K6/K6-2 cpus. 22.145 +# 22.146 +# CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache 22.147 +# flush at hold state. 22.148 +# 22.149 +# CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs 22.150 +# without cache flush at hold state, and (2) write-back CPU cache on 22.151 +# Cyrix 6x86 whose revision < 2.7 (NOTE 2). 22.152 +# 22.153 +# NO_F00F_HACK disables the hack that prevents Pentiums (and ONLY 22.154 +# Pentiums) from locking up when a LOCK CMPXCHG8B instruction is 22.155 +# executed. This option is only needed if I586_CPU is also defined, 22.156 +# and should be included for any non-Pentium CPU that defines it. 22.157 +# 22.158 +# NO_MEMORY_HOLE is an optimisation for systems with AMD K6 processors 22.159 +# which indicates that the 15-16MB range is *definitely* not being 22.160 +# occupied by an ISA memory hole. 22.161 +# 22.162 +# CPU_DISABLE_CMPXCHG disables the CMPXCHG instruction on > i386 IA32 22.163 +# machines. VmWare seems to emulate this instruction poorly, causing 22.164 +# the guest OS to run very slowly. Enabling this with a SMP kernel 22.165 +# will cause the kernel to be unusable. 22.166 +# 22.167 +# NOTE 1: The options, CPU_BTB_EN, CPU_LOOP_EN, CPU_IORT, 22.168 +# CPU_LOOP_EN and CPU_RSTK_EN should not be used because of CPU bugs. 22.169 +# These options may crash your system. 22.170 +# 22.171 +# NOTE 2: If CYRIX_CACHE_REALLY_WORKS is not set, CPU cache is enabled 22.172 +# in write-through mode when revision < 2.7. If revision of Cyrix 22.173 +# 6x86 >= 2.7, CPU cache is always enabled in write-back mode. 22.174 +# 22.175 +# NOTE 3: This option may cause failures for software that requires 22.176 +# locked cycles in order to operate correctly. 22.177 +# 22.178 +options CPU_ATHLON_SSE_HACK 22.179 +options CPU_BLUELIGHTNING_FPU_OP_CACHE 22.180 +options CPU_BLUELIGHTNING_3X 22.181 +options CPU_BTB_EN 22.182 +options CPU_DIRECT_MAPPED_CACHE 22.183 +options CPU_DISABLE_5X86_LSSER 22.184 +options CPU_ELAN 22.185 +options CPU_SOEKRIS 22.186 +options CPU_ELAN_XTAL=32768000 22.187 +options CPU_ELAN_PPS 22.188 +options CPU_ENABLE_SSE 22.189 +#options CPU_DISABLE_SSE 22.190 +options CPU_FASTER_5X86_FPU 22.191 +options CPU_I486_ON_386 22.192 +options CPU_IORT 22.193 +options CPU_L2_LATENCY=5 22.194 +options CPU_LOOP_EN 22.195 +options CPU_PPRO2CELERON 22.196 +options CPU_RSTK_EN 22.197 +options CPU_SUSP_HLT 22.198 +options CPU_UPGRADE_HW_CACHE 22.199 +options CPU_WT_ALLOC 22.200 +options CYRIX_CACHE_WORKS 22.201 +options CYRIX_CACHE_REALLY_WORKS 22.202 +#options NO_F00F_HACK 22.203 +options CPU_DISABLE_CMPXCHG 22.204 + 22.205 +# Debug options 22.206 +options NPX_DEBUG # enable npx debugging (FPU/math emu) 22.207 + #new math emulator 22.208 + 22.209 +# 22.210 +# PERFMON causes the driver for Pentium/Pentium Pro performance counters 22.211 +# to be compiled. See perfmon(4) for more information. 22.212 +# 22.213 +options PERFMON 22.214 + 22.215 + 22.216 +##################################################################### 22.217 +# NETWORKING OPTIONS 22.218 + 22.219 +# 22.220 +# DEVICE_POLLING adds support for mixed interrupt-polling handling 22.221 +# of network device drivers, which has significant benefits in terms 22.222 +# of robustness to overloads and responsivity, as well as permitting 22.223 +# accurate scheduling of the CPU time between kernel network processing 22.224 +# and other activities. The drawback is a moderate (up to 1/HZ seconds) 22.225 +# potential increase in response times. 22.226 +# It is strongly recommended to use HZ=1000 or 2000 with DEVICE_POLLING 22.227 +# to achieve smoother behaviour. 22.228 +# Additionally, you can enable/disable polling at runtime with the 22.229 +# sysctl variable kern.polling.enable (defaults off), and select 22.230 +# the CPU fraction reserved to userland with the sysctl variable 22.231 +# kern.polling.user_frac (default 50, range 0..100). 22.232 +# 22.233 +# Only the "dc" "fxp" and "sis" devices support this mode of operation at 22.234 +# the time of this writing. 22.235 + 22.236 +options DEVICE_POLLING 22.237 + 22.238 + 22.239 +##################################################################### 22.240 +# CLOCK OPTIONS 22.241 + 22.242 +# The following options are used for debugging clock behavior only, and 22.243 +# should not be used for production systems. 22.244 +# 22.245 +# CLK_CALIBRATION_LOOP will run the clock calibration loop at startup 22.246 +# until the user presses a key. 22.247 + 22.248 +options CLK_CALIBRATION_LOOP 22.249 + 22.250 +# The following two options measure the frequency of the corresponding 22.251 +# clock relative to the RTC (onboard mc146818a). 22.252 + 22.253 +options CLK_USE_I8254_CALIBRATION 22.254 +options CLK_USE_TSC_CALIBRATION 22.255 + 22.256 + 22.257 +##################################################################### 22.258 +# MISCELLANEOUS DEVICES AND OPTIONS 22.259 + 22.260 +device speaker #Play IBM BASIC-style noises out your speaker 22.261 +hint.speaker.0.at="isa" 22.262 +hint.speaker.0.port="0x61" 22.263 +device gzip #Exec gzipped a.out's. REQUIRES COMPAT_AOUT! 22.264 +device apm_saver # Requires APM 22.265 + 22.266 + 22.267 +##################################################################### 22.268 +# HARDWARE BUS CONFIGURATION 22.269 + 22.270 +# 22.271 +# ISA bus 22.272 +# 22.273 +device isa 22.274 + 22.275 +# 22.276 +# Options for `isa': 22.277 +# 22.278 +# AUTO_EOI_1 enables the `automatic EOI' feature for the master 8259A 22.279 +# interrupt controller. This saves about 0.7-1.25 usec for each interrupt. 22.280 +# This option breaks suspend/resume on some portables. 22.281 +# 22.282 +# AUTO_EOI_2 enables the `automatic EOI' feature for the slave 8259A 22.283 +# interrupt controller. This saves about 0.7-1.25 usec for each interrupt. 22.284 +# Automatic EOI is documented not to work for for the slave with the 22.285 +# original i8259A, but it works for some clones and some integrated 22.286 +# versions. 22.287 +# 22.288 +# MAXMEM specifies the amount of RAM on the machine; if this is not 22.289 +# specified, FreeBSD will first read the amount of memory from the CMOS 22.290 +# RAM, so the amount of memory will initially be limited to 64MB or 16MB 22.291 +# depending on the BIOS. If the BIOS reports 64MB, a memory probe will 22.292 +# then attempt to detect the installed amount of RAM. If this probe 22.293 +# fails to detect >64MB RAM you will have to use the MAXMEM option. 22.294 +# The amount is in kilobytes, so for a machine with 128MB of RAM, it would 22.295 +# be 131072 (128 * 1024). 22.296 +# 22.297 +# BROKEN_KEYBOARD_RESET disables the use of the keyboard controller to 22.298 +# reset the CPU for reboot. This is needed on some systems with broken 22.299 +# keyboard controllers. 22.300 + 22.301 +options COMPAT_OLDISA #Use ISA shims and glue for old drivers 22.302 +options AUTO_EOI_1 22.303 +#options AUTO_EOI_2 22.304 + 22.305 +options MAXMEM=(128*1024) 22.306 +#options BROKEN_KEYBOARD_RESET 22.307 + 22.308 +# 22.309 +# EISA bus 22.310 +# 22.311 +# The EISA bus device is `eisa'. It provides auto-detection and 22.312 +# configuration support for all devices on the EISA bus. 22.313 + 22.314 +device eisa 22.315 + 22.316 +# By default, only 10 EISA slots are probed, since the slot numbers 22.317 +# above clash with the configuration address space of the PCI subsystem, 22.318 +# and the EISA probe is not very smart about this. This is sufficient 22.319 +# for most machines, but in particular the HP NetServer LC series comes 22.320 +# with an onboard AIC7770 dual-channel SCSI controller on EISA slot #11, 22.321 +# thus you need to bump this figure to 12 for them. 22.322 +options EISA_SLOTS=12 22.323 + 22.324 +# 22.325 +# MCA bus: 22.326 +# 22.327 +# The MCA bus device is `mca'. It provides auto-detection and 22.328 +# configuration support for all devices on the MCA bus. 22.329 +# No hints are required for MCA. 22.330 + 22.331 +device mca 22.332 + 22.333 +# 22.334 +# PCI bus & PCI options: 22.335 +# 22.336 +device pci 22.337 + 22.338 +# 22.339 +# AGP GART support 22.340 +device agp 22.341 + 22.342 + 22.343 +##################################################################### 22.344 +# HARDWARE DEVICE CONFIGURATION 22.345 + 22.346 +# 22.347 +# Mandatory devices: 22.348 +# 22.349 + 22.350 +# To include support for VGA VESA video modes 22.351 +options VESA 22.352 + 22.353 +# Turn on extra debugging checks and output for VESA support. 22.354 +options VESA_DEBUG 22.355 + 22.356 +# The pcvt console driver (vt220 compatible). 22.357 +device vt 22.358 +hint.vt.0.at="isa" 22.359 +options XSERVER # support for running an X server on vt 22.360 +options FAT_CURSOR # start with block cursor 22.361 +# This PCVT option is for keyboards such as those used on really old ThinkPads 22.362 +options PCVT_SCANSET=2 22.363 +# Other PCVT options are documented in pcvt(4). 22.364 +options PCVT_24LINESDEF 22.365 +options PCVT_CTRL_ALT_DEL 22.366 +options PCVT_META_ESC 22.367 +options PCVT_NSCREENS=9 22.368 +options PCVT_PRETTYSCRNS 22.369 +options PCVT_SCREENSAVER 22.370 +options PCVT_USEKBDSEC 22.371 +options PCVT_VT220KEYB 22.372 +options PCVT_GREENSAVER 22.373 + 22.374 +# 22.375 +# The Numeric Processing eXtension driver. In addition to this, you 22.376 +# may configure a math emulator (see above). If your machine has a 22.377 +# hardware FPU and the kernel configuration includes the npx device 22.378 +# *and* a math emulator compiled into the kernel, the hardware FPU 22.379 +# will be used, unless it is found to be broken or unless "flags" to 22.380 +# npx0 includes "0x08", which requests preference for the emulator. 22.381 +device npx 22.382 +hint.npx.0.flags="0x0" 22.383 +hint.npx.0.irq="13" 22.384 + 22.385 +# 22.386 +# `flags' for npx0: 22.387 +# 0x01 don't use the npx registers to optimize bcopy. 22.388 +# 0x02 don't use the npx registers to optimize bzero. 22.389 +# 0x04 don't use the npx registers to optimize copyin or copyout. 22.390 +# 0x08 use emulator even if hardware FPU is available. 22.391 +# The npx registers are normally used to optimize copying and zeroing when 22.392 +# all of the following conditions are satisfied: 22.393 +# I586_CPU is an option 22.394 +# the cpu is an i586 (perhaps not a Pentium) 22.395 +# the probe for npx0 succeeds 22.396 +# INT 16 exception handling works. 22.397 +# Then copying and zeroing using the npx registers is normally 30-100% faster. 22.398 +# The flags can be used to control cases where it doesn't work or is slower. 22.399 +# Setting them at boot time using userconfig works right (the optimizations 22.400 +# are not used until later in the bootstrap when npx0 is attached). 22.401 +# Flag 0x08 automatically disables the i586 optimized routines. 22.402 +# 22.403 + 22.404 +# 22.405 +# Optional devices: 22.406 +# 22.407 + 22.408 +# 3Dfx Voodoo Graphics, Voodoo II /dev/3dfx CDEV support. This will create 22.409 +# the /dev/3dfx0 device to work with glide implementations. This should get 22.410 +# linked to /dev/3dfx and /dev/voodoo. Note that this is not the same as 22.411 +# the tdfx DRI module from XFree86 and is completely unrelated. 22.412 +# 22.413 +# To enable Linuxulator support, one must also include COMPAT_LINUX in the 22.414 +# config as well, or you will not have the dependencies. The other option 22.415 +# is to load both as modules. 22.416 + 22.417 +device tdfx # Enable 3Dfx Voodoo support 22.418 +options TDFX_LINUX # Enable Linuxulator support 22.419 + 22.420 +# 22.421 +# ACPI support using the Intel ACPI Component Architecture reference 22.422 +# implementation. 22.423 +# 22.424 +# ACPI_DEBUG enables the use of the debug.acpi.level and debug.acpi.layer 22.425 +# kernel environment variables to select initial debugging levels for the 22.426 +# Intel ACPICA code. (Note that the Intel code must also have USE_DEBUGGER 22.427 +# defined when it is built). 22.428 +# 22.429 +# ACPI_MAX_THREADS sets the number of task threads started. 22.430 +# 22.431 +# ACPI_NO_SEMAPHORES makes the AcpiOs*Semaphore routines a no-op. 22.432 +# 22.433 +# ACPICA_PEDANTIC enables strict checking of AML. Our default is to 22.434 +# relax these checks to allow code generated by the Microsoft compiler 22.435 +# to still execute. 22.436 +# 22.437 +# Note that building ACPI into the kernel is deprecated; the module is 22.438 +# normally loaded automatically by the loader. 22.439 +# 22.440 +device acpi 22.441 +options ACPI_DEBUG 22.442 +options ACPI_MAX_THREADS=1 22.443 +#!options ACPI_NO_SEMAPHORES 22.444 +#!options ACPICA_PEDANTIC 22.445 + 22.446 +# DRM options: 22.447 +# mgadrm: AGP Matrox G200, G400, G450, G550 22.448 +# r128drm: ATI Rage 128 22.449 +# radeondrm: ATI Radeon up to 9000/9100 22.450 +# sisdrm: SiS 300/305,540,630 22.451 +# tdfxdrm: 3dfx Voodoo 3/4/5 and Banshee 22.452 +# DRM_DEBUG: include debug printfs, very slow 22.453 +# 22.454 +# mga requires AGP in the kernel, and it is recommended 22.455 +# for AGP r128 and radeon cards. 22.456 + 22.457 +device mgadrm 22.458 +device "r128drm" 22.459 +device radeondrm 22.460 +device sisdrm 22.461 +device tdfxdrm 22.462 + 22.463 +options DRM_DEBUG 22.464 + 22.465 +# M-systems DiskOnchip products see src/sys/contrib/dev/fla/README 22.466 +device fla 22.467 +hint.fla.0.at="isa" 22.468 + 22.469 +# 22.470 +# mse: Logitech and ATI InPort bus mouse ports 22.471 + 22.472 +device mse 22.473 +hint.mse.0.at="isa" 22.474 +hint.mse.0.port="0x23c" 22.475 +hint.mse.0.irq="5" 22.476 + 22.477 +# 22.478 +# Network interfaces: 22.479 +# 22.480 + 22.481 +# ar: Arnet SYNC/570i hdlc sync 2/4 port V.35/X.21 serial driver 22.482 +# (requires sppp) 22.483 +# ath: Atheros a/b/g WiFi adapters (requires ath_hal and wlan) 22.484 +# cx: Cronyx/Sigma multiport sync/async (with Cisco or PPP framing) 22.485 +# ed: Western Digital and SMC 80xx; Novell NE1000 and NE2000; 3Com 3C503 22.486 +# HP PC Lan+, various PC Card devices (refer to etc/defauls/pccard.conf) 22.487 +# (requires miibus) 22.488 +# el: 3Com 3C501 (slow!) 22.489 +# ie: AT&T StarLAN 10 and EN100; 3Com 3C507; unknown NI5210; 22.490 +# Intel EtherExpress 22.491 +# le: Digital Equipment EtherWorks 2 and EtherWorks 3 (DEPCA, DE100, 22.492 +# DE101, DE200, DE201, DE202, DE203, DE204, DE205, DE422) 22.493 +# lnc: Lance/PCnet cards (Isolan, Novell NE2100, NE32-VL, AMD Am7990 and 22.494 +# Am79C960) 22.495 +# oltr: Olicom ISA token-ring adapters OC-3115, OC-3117, OC-3118 and OC-3133 22.496 +# (no hints needed). 22.497 +# Olicom PCI token-ring adapters OC-3136, OC-3137, OC-3139, OC-3140, 22.498 +# OC-3141, OC-3540, OC-3250 22.499 +# rdp: RealTek RTL 8002-based pocket ethernet adapters 22.500 +# sbni: Granch SBNI12-xx ISA and PCI adapters 22.501 +# sr: RISCom/N2 hdlc sync 1/2 port V.35/X.21 serial driver (requires sppp) 22.502 +# wl: Lucent Wavelan (ISA card only). 22.503 + 22.504 +# Order for ISA/EISA devices is important here 22.505 + 22.506 +device ar 22.507 +hint.ar.0.at="isa" 22.508 +hint.ar.0.port="0x300" 22.509 +hint.ar.0.irq="10" 22.510 +hint.ar.0.maddr="0xd0000" 22.511 +device cx 22.512 +hint.cx.0.at="isa" 22.513 +hint.cx.0.port="0x240" 22.514 +hint.cx.0.irq="15" 22.515 +hint.cx.0.drq="7" 22.516 +device ed 22.517 +#options ED_NO_MIIBUS # Disable ed miibus support 22.518 +hint.ed.0.at="isa" 22.519 +hint.ed.0.port="0x280" 22.520 +hint.ed.0.irq="5" 22.521 +hint.ed.0.maddr="0xd8000" 22.522 +device el 1 22.523 +hint.el.0.at="isa" 22.524 +hint.el.0.port="0x300" 22.525 +hint.el.0.irq="9" 22.526 +device ie # Hints only required for Starlan 22.527 +hint.ie.2.at="isa" 22.528 +hint.ie.2.port="0x300" 22.529 +hint.ie.2.irq="5" 22.530 +hint.ie.2.maddr="0xd0000" 22.531 +device le 1 22.532 +hint.le.0.at="isa" 22.533 +hint.le.0.port="0x300" 22.534 +hint.le.0.irq="5" 22.535 +hint.le.0.maddr="0xd0000" 22.536 +device lnc 22.537 +hint.lnc.0.at="isa" 22.538 +hint.lnc.0.port="0x280" 22.539 +hint.lnc.0.irq="10" 22.540 +hint.lnc.0.drq="0" 22.541 +device rdp 1 22.542 +hint.rdp.0.at="isa" 22.543 +hint.rdp.0.port="0x378" 22.544 +hint.rdp.0.irq="7" 22.545 +hint.rdp.0.flags="2" 22.546 +device sbni 22.547 +hint.sbni.0.at="isa" 22.548 +hint.sbni.0.port="0x210" 22.549 +hint.sbni.0.irq="0xefdead" 22.550 +hint.sbni.0.flags="0" 22.551 +device sr 22.552 +hint.sr.0.at="isa" 22.553 +hint.sr.0.port="0x300" 22.554 +hint.sr.0.irq="5" 22.555 +hint.sr.0.maddr="0xd0000" 22.556 +device oltr 22.557 +hint.oltr.0.at="isa" 22.558 +device wl 22.559 +hint.wl.0.at="isa" 22.560 +hint.wl.0.port="0x300" 22.561 +options WLCACHE # enables the signal-strength cache 22.562 +options WLDEBUG # enables verbose debugging output 22.563 + 22.564 +device ath 22.565 +device ath_hal # Atheros HAL (includes binary component) 22.566 +#device wlan # 802.11 layer 22.567 + 22.568 +# 22.569 +# ATA raid adapters 22.570 +# 22.571 +device pst 22.572 + 22.573 +# 22.574 +# SCSI host adapters: 22.575 +# 22.576 +# ncv: NCR 53C500 based SCSI host adapters. 22.577 +# nsp: Workbit Ninja SCSI-3 based PC Card SCSI host adapters. 22.578 +# stg: TMC 18C30, 18C50 based SCSI host adapters. 22.579 + 22.580 +device ncv 22.581 +device nsp 22.582 +device stg 22.583 +hint.stg.0.at="isa" 22.584 +hint.stg.0.port="0x140" 22.585 +hint.stg.0.port="11" 22.586 + 22.587 +# 22.588 +# Adaptec FSA RAID controllers, including integrated DELL controllers, 22.589 +# the Dell PERC 2/QC and the HP NetRAID-4M 22.590 +device aac 22.591 +device aacp # SCSI Passthrough interface (optional, CAM required) 22.592 + 22.593 +# 22.594 +# IBM (now Adaptec) ServeRAID controllers 22.595 +device ips 22.596 + 22.597 +# 22.598 +# SafeNet crypto driver: can be moved to the MI NOTES as soon as 22.599 +# it's tested on a big-endian machine 22.600 +# 22.601 +device safe # SafeNet 1141 22.602 +options SAFE_DEBUG # enable debugging support: hw.safe.debug 22.603 +options SAFE_RNDTEST # enable rndtest support 22.604 + 22.605 +##################################################################### 22.606 + 22.607 +# 22.608 +# Miscellaneous hardware: 22.609 +# 22.610 +# wt: Wangtek and Archive QIC-02/QIC-36 tape drives 22.611 +# ctx: Cortex-I frame grabber 22.612 +# apm: Laptop Advanced Power Management (experimental) 22.613 +# pmtimer: Timer device driver for power management events (APM or ACPI) 22.614 +# spigot: The Creative Labs Video Spigot video-acquisition board 22.615 +# dgb: Digiboard PC/Xi and PC/Xe series driver (ALPHA QUALITY!) 22.616 +# digi: Digiboard driver 22.617 +# gp: National Instruments AT-GPIB and AT-GPIB/TNT board, PCMCIA-GPIB 22.618 +# asc: GI1904-based hand scanners, e.g. the Trust Amiscan Grey 22.619 +# gsc: Genius GS-4500 hand scanner. 22.620 +# spic: Sony Programmable I/O controller (VAIO notebooks) 22.621 +# stl: Stallion EasyIO and EasyConnection 8/32 (cd1400 based) 22.622 +# stli: Stallion EasyConnection 8/64, ONboard, Brumby (intelligent) 22.623 + 22.624 +# Notes on APM 22.625 +# The flags takes the following meaning for apm0: 22.626 +# 0x0020 Statclock is broken. 22.627 +# If apm is omitted, some systems require sysctl kern.timecounter.method=1 22.628 +# for correct timekeeping. 22.629 + 22.630 +# Notes on the spigot: 22.631 +# The video spigot is at 0xad6. This port address can not be changed. 22.632 +# The irq values may only be 10, 11, or 15 22.633 +# I/O memory is an 8kb region. Possible values are: 22.634 +# 0a0000, 0a2000, ..., 0fffff, f00000, f02000, ..., ffffff 22.635 +# The start address must be on an even boundary. 22.636 +# Add the following option if you want to allow non-root users to be able 22.637 +# to access the spigot. This option is not secure because it allows users 22.638 +# direct access to the I/O page. 22.639 +# options SPIGOT_UNSECURE 22.640 + 22.641 +# Notes on the Specialix SI/XIO driver: 22.642 +# The host card is memory, not IO mapped. 22.643 +# The Rev 1 host cards use a 64K chunk, on a 32K boundary. 22.644 +# The Rev 2 host cards use a 32K chunk, on a 32K boundary. 22.645 +# The cards can use an IRQ of 11, 12 or 15. 22.646 + 22.647 +# Notes on the Sony Programmable I/O controller 22.648 +# This is a temporary driver that should someday be replaced by something 22.649 +# that hooks into the ACPI layer. The device is hooked to the PIIX4's 22.650 +# General Device 10 decoder, which means you have to fiddle with PCI 22.651 +# registers to map it in, even though it is otherwise treated here as 22.652 +# an ISA device. At the moment, the driver polls, although the device 22.653 +# is capable of generating interrupts. It largely undocumented. 22.654 +# The port location in the hint is where you WANT the device to be 22.655 +# mapped. 0x10a0 seems to be traditional. At the moment the jogdial 22.656 +# is the only thing truly supported, but aparently a fair percentage 22.657 +# of the Vaio extra features are controlled by this device. 22.658 + 22.659 +# Notes on the Stallion stl and stli drivers: 22.660 +# See src/i386/isa/README.stl for complete instructions. 22.661 +# This is version 0.0.5alpha, unsupported by Stallion. 22.662 +# The stl driver has a secondary IO port hard coded at 0x280. You need 22.663 +# to change src/i386/isa/stallion.c if you reconfigure this on the boards. 22.664 +# The "flags" and "msize" settings on the stli driver depend on the board: 22.665 +# EasyConnection 8/64 ISA: flags 23 msize 0x1000 22.666 +# EasyConnection 8/64 EISA: flags 24 msize 0x10000 22.667 +# EasyConnection 8/64 MCA: flags 25 msize 0x1000 22.668 +# ONboard ISA: flags 4 msize 0x10000 22.669 +# ONboard EISA: flags 7 msize 0x10000 22.670 +# ONboard MCA: flags 3 msize 0x10000 22.671 +# Brumby: flags 2 msize 0x4000 22.672 +# Stallion: flags 1 msize 0x10000 22.673 + 22.674 +# Notes on the Digiboard PC/Xi and PC/Xe series driver 22.675 +# 22.676 +# The NDGBPORTS option specifies the number of ports controlled by the 22.677 +# dgb(4) driver. The default value is 16 ports per device. 22.678 +# 22.679 +# The following flag values have special meanings in dgb: 22.680 +# 0x01 - alternate layout of pins 22.681 +# 0x02 - use the windowed PC/Xe in 64K mode 22.682 + 22.683 +device wt 1 22.684 +hint.wt.0.at="isa" 22.685 +hint.wt.0.port="0x300" 22.686 +hint.wt.0.irq="5" 22.687 +hint.wt.0.drq="1" 22.688 +device ctx 22.689 +hint.ctx.0.at="isa" 22.690 +hint.ctx.0.port="0x230" 22.691 +hint.ctx.0.maddr="0xd0000" 22.692 +device spigot 1 22.693 +hint.spigot.0.at="isa" 22.694 +hint.spigot.0.port="0xad6" 22.695 +hint.spigot.0.irq="15" 22.696 +hint.spigot.0.maddr="0xee000" 22.697 +device apm 22.698 +hint.apm.0.flags="0x20" 22.699 +device pmtimer # Adjust system timer at wakeup time 22.700 +device gp 22.701 +hint.gp.0.at="isa" 22.702 +hint.gp.0.port="0x2c0" 22.703 +device gsc 1 22.704 +hint.gsc.0.at="isa" 22.705 +hint.gsc.0.port="0x270" 22.706 +hint.gsc.0.drq="3" 22.707 +device dgb 1 22.708 +options NDGBPORTS=17 22.709 +hint.dgb.0.at="isa" 22.710 +hint.dgb.0.port="0x220" 22.711 +hint.dgb.0.maddr="0xfc000" 22.712 +device digi 22.713 +hint.digi.0.at="isa" 22.714 +hint.digi.0.port="0x104" 22.715 +hint.digi.0.maddr="0xd0000" 22.716 +# BIOS & FEP/OS components of device digi. 22.717 +device digi_CX 22.718 +device digi_CX_PCI 22.719 +device digi_EPCX 22.720 +device digi_EPCX_PCI 22.721 +device digi_Xe 22.722 +device digi_Xem 22.723 +device digi_Xr 22.724 +device asc 1 22.725 +hint.asc.0.at="isa" 22.726 +hint.asc.0.port="0x3EB" 22.727 +hint.asc.0.drq="3" 22.728 +hint.asc.0.irq="10" 22.729 +device spic 22.730 +hint.spic.0.at="isa" 22.731 +hint.spic.0.port="0x10a0" 22.732 +device stl 22.733 +hint.stl.0.at="isa" 22.734 +hint.stl.0.port="0x2a0" 22.735 +hint.stl.0.irq="10" 22.736 +device stli 22.737 +hint.stli.0.at="isa" 22.738 +hint.stli.0.port="0x2a0" 22.739 +hint.stli.0.maddr="0xcc000" 22.740 +hint.stli.0.flags="23" 22.741 +hint.stli.0.msize="0x1000" 22.742 +# You are unlikely to have the hardware for loran <phk@FreeBSD.org> 22.743 +device loran 22.744 +hint.loran.0.at="isa" 22.745 +hint.loran.0.irq="5" 22.746 +# HOT1 Xilinx 6200 card (http://www.vcc.com/) 22.747 +device xrpu 22.748 + 22.749 +# 22.750 +# Laptop/Notebook options: 22.751 +# 22.752 +# See also: 22.753 +# apm under `Miscellaneous hardware' 22.754 +# above. 22.755 + 22.756 +# For older notebooks that signal a powerfail condition (external 22.757 +# power supply dropped, or battery state low) by issuing an NMI: 22.758 + 22.759 +options POWERFAIL_NMI # make it beep instead of panicing 22.760 + 22.761 +# 22.762 +# I2C Bus 22.763 +# 22.764 +# Philips i2c bus support is provided by the `iicbus' device. 22.765 +# 22.766 +# Supported interfaces: 22.767 +# pcf Philips PCF8584 ISA-bus controller 22.768 +# 22.769 +device pcf 22.770 +hint.pcf.0.at="isa" 22.771 +hint.pcf.0.port="0x320" 22.772 +hint.pcf.0.irq="5" 22.773 + 22.774 +#--------------------------------------------------------------------------- 22.775 +# ISDN4BSD 22.776 +# 22.777 +# See /usr/share/examples/isdn/ROADMAP for an introduction to isdn4bsd. 22.778 +# 22.779 +# i4b passive ISDN cards support contains the following hardware drivers: 22.780 +# 22.781 +# isic - Siemens/Infineon ISDN ISAC/HSCX/IPAC chipset driver 22.782 +# iwic - Winbond W6692 PCI bus ISDN S/T interface controller 22.783 +# ifpi - AVM Fritz!Card PCI driver 22.784 +# ifpi2 - AVM Fritz!Card PCI version 2 driver 22.785 +# ihfc - Cologne Chip HFC ISA/ISA-PnP chipset driver 22.786 +# ifpnp - AVM Fritz!Card PnP driver 22.787 +# itjc - Siemens ISAC / TJNet Tiger300/320 chipset 22.788 +# 22.789 +# i4b active ISDN cards support contains the following hardware drivers: 22.790 +# 22.791 +# iavc - AVM B1 PCI, AVM B1 ISA, AVM T1 22.792 +# 22.793 +# Note that the ``options'' (if given) and ``device'' lines must BOTH 22.794 +# be uncommented to enable support for a given card ! 22.795 +# 22.796 +# In addition to a hardware driver (and probably an option) the mandatory 22.797 +# ISDN protocol stack devices and the mandatory support device must be 22.798 +# enabled as well as one or more devices from the optional devices section. 22.799 +# 22.800 +#--------------------------------------------------------------------------- 22.801 +# isic driver (Siemens/Infineon chipsets) 22.802 +# 22.803 +device isic 22.804 +# 22.805 +# ISA bus non-PnP Cards: 22.806 +# ---------------------- 22.807 +# 22.808 +# Teles S0/8 or Niccy 1008 22.809 +options TEL_S0_8 22.810 +hint.isic.0.at="isa" 22.811 +hint.isic.0.maddr="0xd0000" 22.812 +hint.isic.0.irq="5" 22.813 +hint.isic.0.flags="1" 22.814 +# 22.815 +# Teles S0/16 or Creatix ISDN-S0 or Niccy 1016 22.816 +options TEL_S0_16 22.817 +hint.isic.0.at="isa" 22.818 +hint.isic.0.port="0xd80" 22.819 +hint.isic.0.maddr="0xd0000" 22.820 +hint.isic.0.irq="5" 22.821 +hint.isic.0.flags="2" 22.822 +# 22.823 +# Teles S0/16.3 22.824 +options TEL_S0_16_3 22.825 +hint.isic.0.at="isa" 22.826 +hint.isic.0.port="0xd80" 22.827 +hint.isic.0.irq="5" 22.828 +hint.isic.0.flags="3" 22.829 +# 22.830 +# AVM A1 or AVM Fritz!Card 22.831 +options AVM_A1 22.832 +hint.isic.0.at="isa" 22.833 +hint.isic.0.port="0x340" 22.834 +hint.isic.0.irq="5" 22.835 +hint.isic.0.flags="4" 22.836 +# 22.837 +# USRobotics Sportster ISDN TA intern 22.838 +options USR_STI 22.839 +hint.isic.0.at="isa" 22.840 +hint.isic.0.port="0x268" 22.841 +hint.isic.0.irq="5" 22.842 +hint.isic.0.flags="7" 22.843 +# 22.844 +# ITK ix1 Micro ( < V.3, non-PnP version ) 22.845 +options ITKIX1 22.846 +hint.isic.0.at="isa" 22.847 +hint.isic.0.port="0x398" 22.848 +hint.isic.0.irq="10" 22.849 +hint.isic.0.flags="18" 22.850 +# 22.851 +# ELSA PCC-16 22.852 +options ELSA_PCC16 22.853 +hint.isic.0.at="isa" 22.854 +hint.isic.0.port="0x360" 22.855 +hint.isic.0.irq="10" 22.856 +hint.isic.0.flags="20" 22.857 +# 22.858 +# ISA bus PnP Cards: 22.859 +# ------------------ 22.860 +# 22.861 +# Teles S0/16.3 PnP 22.862 +options TEL_S0_16_3_P 22.863 +# 22.864 +# Creatix ISDN-S0 P&P 22.865 +options CRTX_S0_P 22.866 +# 22.867 +# Dr. Neuhaus Niccy Go@ 22.868 +options DRN_NGO 22.869 +# 22.870 +# Sedlbauer Win Speed 22.871 +options SEDLBAUER 22.872 +# 22.873 +# Dynalink IS64PH 22.874 +options DYNALINK 22.875 +# 22.876 +# ELSA QuickStep 1000pro ISA 22.877 +options ELSA_QS1ISA 22.878 +# 22.879 +# Siemens I-Surf 2.0 22.880 +options SIEMENS_ISURF2 22.881 +# 22.882 +# Asuscom ISDNlink 128K ISA 22.883 +options ASUSCOM_IPAC 22.884 +# 22.885 +# Eicon Diehl DIVA 2.0 and 2.02 22.886 +options EICON_DIVA 22.887 +# 22.888 +# Compaq Microcom 610 ISDN card (Compaq series PSB2222I) 22.889 +options COMPAQ_M610 22.890 +# 22.891 +# PCI bus Cards: 22.892 +# -------------- 22.893 +# 22.894 +# Cyclades Cyclom-Y PCI serial driver 22.895 +device cy 1 22.896 +options CY_PCI_FASTINTR # Use with cy_pci unless irq is shared 22.897 +hint.cy.0.at="isa" 22.898 +hint.cy.0.irq="10" 22.899 +hint.cy.0.maddr="0xd4000" 22.900 +hint.cy.0.msize="0x2000" 22.901 +# 22.902 +#--------------------------------------------------------------------------- 22.903 +# ELSA MicroLink ISDN/PCI (same as ELSA QuickStep 1000pro PCI) 22.904 +options ELSA_QS1PCI 22.905 +# 22.906 +# 22.907 +#--------------------------------------------------------------------------- 22.908 +# ifpnp driver for AVM Fritz!Card PnP 22.909 +# 22.910 +# AVM Fritz!Card PnP 22.911 +device ifpnp 22.912 +# 22.913 +#--------------------------------------------------------------------------- 22.914 +# ihfc driver for Cologne Chip ISA chipsets (experimental!) 22.915 +# 22.916 +# Teles 16.3c ISA PnP 22.917 +# AcerISDN P10 ISA PnP 22.918 +# TELEINT ISDN SPEED No.1 22.919 +device ihfc 22.920 +# 22.921 +#--------------------------------------------------------------------------- 22.922 +# ifpi driver for AVM Fritz!Card PCI 22.923 +# 22.924 +# AVM Fritz!Card PCI 22.925 +device ifpi 22.926 +# 22.927 +#--------------------------------------------------------------------------- 22.928 +# ifpi2 driver for AVM Fritz!Card PCI version 2 22.929 +# 22.930 +# AVM Fritz!Card PCI version 2 22.931 +device "ifpi2" 22.932 +# 22.933 +#--------------------------------------------------------------------------- 22.934 +# iwic driver for Winbond W6692 chipset 22.935 +# 22.936 +# ASUSCOM P-IN100-ST-D (and other Winbond W6692 based cards) 22.937 +device iwic 22.938 +# 22.939 +#--------------------------------------------------------------------------- 22.940 +# itjc driver for Simens ISAC / TJNet Tiger300/320 chipset 22.941 +# 22.942 +# Traverse Technologies NETjet-S 22.943 +# Teles PCI-TJ 22.944 +device itjc 22.945 +# 22.946 +#--------------------------------------------------------------------------- 22.947 +# iavc driver (AVM active cards, needs i4bcapi driver!) 22.948 +# 22.949 +device iavc 22.950 +# 22.951 +# AVM B1 ISA bus (PnP mode not supported!) 22.952 +# ---------------------------------------- 22.953 +hint.iavc.0.at="isa" 22.954 +hint.iavc.0.port="0x150" 22.955 +hint.iavc.0.irq="5" 22.956 +# 22.957 +#--------------------------------------------------------------------------- 22.958 +# ISDN Protocol Stack - mandatory for all hardware drivers 22.959 +# 22.960 +# Q.921 / layer 2 - i4b passive cards D channel handling 22.961 +device "i4bq921" 22.962 +# 22.963 +# Q.931 / layer 3 - i4b passive cards D channel handling 22.964 +device "i4bq931" 22.965 +# 22.966 +# layer 4 - i4b common passive and active card handling 22.967 +device "i4b" 22.968 +# 22.969 +#--------------------------------------------------------------------------- 22.970 +# ISDN devices - mandatory for all hardware drivers 22.971 +# 22.972 +# userland driver to do ISDN tracing (for passive cards only) 22.973 +device "i4btrc" 4 22.974 +# 22.975 +# userland driver to control the whole thing 22.976 +device "i4bctl" 22.977 +# 22.978 +#--------------------------------------------------------------------------- 22.979 +# ISDN devices - optional 22.980 +# 22.981 +# userland driver for access to raw B channel 22.982 +device "i4brbch" 4 22.983 +# 22.984 +# userland driver for telephony 22.985 +device "i4btel" 2 22.986 +# 22.987 +# network driver for IP over raw HDLC ISDN 22.988 +device "i4bipr" 4 22.989 +# enable VJ header compression detection for ipr i/f 22.990 +options IPR_VJ 22.991 +# enable logging of the first n IP packets to isdnd (n=32 here) 22.992 +options IPR_LOG=32 22.993 +# 22.994 +# network driver for sync PPP over ISDN; requires an equivalent 22.995 +# number of sppp device to be configured 22.996 +device "i4bisppp" 4 22.997 +# 22.998 +# B-channel interface to the netgraph subsystem 22.999 +device "i4bing" 2 22.1000 +# 22.1001 +# CAPI driver needed for active ISDN cards (see iavc driver above) 22.1002 +device "i4bcapi" 22.1003 +# 22.1004 +#--------------------------------------------------------------------------- 22.1005 + 22.1006 +# 22.1007 +# Set the number of PV entries per process. Increasing this can 22.1008 +# stop panics related to heavy use of shared memory. However, that can 22.1009 +# (combined with large amounts of physical memory) cause panics at 22.1010 +# boot time due the kernel running out of VM space. 22.1011 +# 22.1012 +# If you're tweaking this, you might also want to increase the sysctls 22.1013 +# "vm.v_free_min", "vm.v_free_reserved", and "vm.v_free_target". 22.1014 +# 22.1015 +# The value below is the one more than the default. 22.1016 +# 22.1017 +options PMAP_SHPGPERPROC=201 22.1018 + 22.1019 +# 22.1020 +# Change the size of the kernel virtual address space. Due to 22.1021 +# constraints in loader(8) on i386, this must be a multiple of 4. 22.1022 +# 256 = 1 GB of kernel address space. Increasing this also causes 22.1023 +# a reduction of the address space in user processes. 512 splits 22.1024 +# the 4GB cpu address space in half (2GB user, 2GB kernel). 22.1025 +# 22.1026 +options KVA_PAGES=260 22.1027 + 22.1028 + 22.1029 +##################################################################### 22.1030 +# ABI Emulation 22.1031 + 22.1032 +# Enable iBCS2 runtime support for SCO and ISC binaries 22.1033 +options IBCS2 22.1034 + 22.1035 +# Emulate spx device for client side of SVR3 local X interface 22.1036 +options SPX_HACK 22.1037 + 22.1038 +# Enable Linux ABI emulation 22.1039 +options COMPAT_LINUX 22.1040 + 22.1041 +# Enable i386 a.out binary support 22.1042 +options COMPAT_AOUT 22.1043 + 22.1044 +# Enable the linux-like proc filesystem support (requires COMPAT_LINUX 22.1045 +# and PSEUDOFS) 22.1046 +options LINPROCFS 22.1047 + 22.1048 +# 22.1049 +# SysVR4 ABI emulation 22.1050 +# 22.1051 +# The svr4 ABI emulator can be statically compiled into the kernel or loaded as 22.1052 +# a KLD module. 22.1053 +# The STREAMS network emulation code can also be compiled statically or as a 22.1054 +# module. If loaded as a module, it must be loaded before the svr4 module 22.1055 +# (the /usr/sbin/svr4 script does this for you). If compiling statically, 22.1056 +# the `streams' device must be configured into any kernel which also 22.1057 +# specifies COMPAT_SVR4. It is possible to have a statically-configured 22.1058 +# STREAMS device and a dynamically loadable svr4 emulator; the /usr/sbin/svr4 22.1059 +# script understands that it doesn't need to load the `streams' module under 22.1060 +# those circumstances. 22.1061 +# Caveat: At this time, `options KTRACE' is required for the svr4 emulator 22.1062 +# (whether static or dynamic). 22.1063 +# 22.1064 +options COMPAT_SVR4 # build emulator statically 22.1065 +options DEBUG_SVR4 # enable verbose debugging 22.1066 +device streams # STREAMS network driver (required for svr4). 22.1067 + 22.1068 + 22.1069 +##################################################################### 22.1070 +# VM OPTIONS 22.1071 + 22.1072 +# Disable the 4 MByte page PSE CPU feature. The PSE feature allows the 22.1073 +# kernel to use a 4 MByte pages to map the kernel instead of 4k pages. 22.1074 +# This saves on the amount of memory needed for page tables needed to 22.1075 +# map the kernel. You should only disable this feature as a temporary 22.1076 +# workaround if you are having problems with it enabled. 22.1077 +# 22.1078 +#options DISABLE_PSE 22.1079 + 22.1080 +# Disable the global pages PGE CPU feature. The PGE feature allows pages 22.1081 +# to be marked with the PG_G bit. TLB entries for these pages are not 22.1082 +# flushed from the cache when %cr3 is reloaded. This can make context 22.1083 +# switches less expensive. You should only disable this feature as a 22.1084 +# temporary workaround if you are having problems with it enabled. 22.1085 +# 22.1086 +#options DISABLE_PG_G 22.1087 + 22.1088 +# KSTACK_PAGES is the number of memory pages to assign to the kernel 22.1089 +# stack of each thread. 22.1090 + 22.1091 +options KSTACK_PAGES=3 22.1092 + 22.1093 +##################################################################### 22.1094 + 22.1095 +# More undocumented options for linting. 22.1096 +# Note that documenting these are not considered an affront. 22.1097 + 22.1098 +options FB_INSTALL_CDEV # install a CDEV entry in /dev 22.1099 + 22.1100 +# PECOFF module (Win32 Execution Format) 22.1101 +options PECOFF_SUPPORT 22.1102 +options PECOFF_DEBUG 22.1103 + 22.1104 +options ENABLE_ALART 22.1105 +options I4B_SMP_WORKAROUND 22.1106 +options I586_PMC_GUPROF=0x70000 22.1107 +options KBDIO_DEBUG=2 22.1108 +options KBD_MAXRETRY=4 22.1109 +options KBD_MAXWAIT=6 22.1110 +options KBD_RESETDELAY=201 22.1111 + 22.1112 +options PSM_DEBUG=1 22.1113 + 22.1114 +options TIMER_FREQ=((14318182+6)/12) 22.1115 + 22.1116 +options VM_KMEM_SIZE 22.1117 +options VM_KMEM_SIZE_MAX 22.1118 +options VM_KMEM_SIZE_SCALE
23.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 23.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/OLDCARD Thu Mar 24 22:52:13 2005 +0000 23.3 @@ -0,0 +1,17 @@ 23.4 +# 23.5 +# OLDCARD -- Generic kernel configuration file for FreeBSD/i386 23.6 +# using the OLDCARD pccard system. 23.7 +# 23.8 +# $FreeBSD: src/sys/i386/conf/OLDCARD,v 1.18 2003/02/15 02:39:13 ru Exp $ 23.9 + 23.10 +include GENERIC 23.11 + 23.12 +ident OLDCARD 23.13 + 23.14 +# PCCARD (PCMCIA) support 23.15 +nodevice cbb # cardbus (yenta) bridge 23.16 +#nodevice pcic # ExCA ISA and PCI bridges 23.17 +nodevice pccard # PC Card (16-bit) bus 23.18 +nodevice cardbus # CardBus (32-bit) bus 23.19 +device card 1 # pccard bus 23.20 +device pcic # PCMCIA bridge
24.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 24.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/PAE Thu Mar 24 22:52:13 2005 +0000 24.3 @@ -0,0 +1,99 @@ 24.4 +# 24.5 +# PAE -- Generic kernel configuration file for FreeBSD/i386 PAE 24.6 +# 24.7 +# $FreeBSD: src/sys/i386/conf/PAE,v 1.8 2003/11/03 22:49:19 jhb Exp $ 24.8 + 24.9 +include GENERIC 24.10 + 24.11 +ident PAE-GENERIC 24.12 + 24.13 +# To make a PAE kernel, the next option is needed 24.14 +options PAE # Physical Address Extensions Kernel 24.15 + 24.16 +# Compile acpi in statically since the module isn't built properly. Most 24.17 +# machines which support large amounts of memory require acpi. 24.18 +device acpi 24.19 + 24.20 +# Don't build modules with this kernel config, since they are not built with 24.21 +# the correct options headers. 24.22 +makeoptions NO_MODULES=yes 24.23 + 24.24 +# What follows is a list of drivers that are normally in GENERIC, but either 24.25 +# don't work or are untested with PAE. Be very careful before enabling any 24.26 +# of these drivers. Drivers which use DMA and don't handle 64 bit physical 24.27 +# address properly may cause data corruption when used in a machine with more 24.28 +# than 4 gigabytes of memory. 24.29 + 24.30 +nodevice ahb 24.31 +nodevice amd 24.32 +nodevice isp 24.33 +nodevice sym 24.34 +nodevice trm 24.35 + 24.36 +nodevice adv 24.37 +nodevice adw 24.38 +nodevice aha 24.39 +nodevice aic 24.40 +nodevice bt 24.41 + 24.42 +nodevice ncv 24.43 +nodevice nsp 24.44 +nodevice stg 24.45 + 24.46 +nodevice asr 24.47 +nodevice dpt 24.48 +nodevice iir 24.49 +nodevice mly 24.50 + 24.51 +nodevice amr 24.52 +nodevice ida 24.53 +nodevice mlx 24.54 +nodevice pst 24.55 + 24.56 +nodevice agp 24.57 + 24.58 +nodevice de 24.59 +nodevice txp 24.60 +nodevice vx 24.61 + 24.62 +nodevice dc 24.63 +nodevice pcn 24.64 +nodevice rl 24.65 +nodevice sf 24.66 +nodevice sis 24.67 +nodevice ste 24.68 +nodevice tl 24.69 +nodevice tx 24.70 +nodevice vr 24.71 +nodevice wb 24.72 + 24.73 +nodevice cs 24.74 +nodevice ed 24.75 +nodevice ex 24.76 +nodevice ep 24.77 +nodevice fe 24.78 +nodevice ie 24.79 +nodevice lnc 24.80 +nodevice sn 24.81 +nodevice xe 24.82 + 24.83 +nodevice wlan 24.84 +nodevice an 24.85 +nodevice awi 24.86 +nodevice wi 24.87 + 24.88 +nodevice uhci 24.89 +nodevice ohci 24.90 +nodevice usb 24.91 +nodevice ugen 24.92 +nodevice uhid 24.93 +nodevice ukbd 24.94 +nodevice ulpt 24.95 +nodevice umass 24.96 +nodevice ums 24.97 +nodevice urio 24.98 +nodevice uscanner 24.99 +nodevice aue 24.100 +nodevice axe 24.101 +nodevice cue 24.102 +nodevice kue
25.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 25.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/XENCONF Thu Mar 24 22:52:13 2005 +0000 25.3 @@ -0,0 +1,137 @@ 25.4 +# 25.5 +# GENERIC -- Generic kernel configuration file for FreeBSD/i386 25.6 +# 25.7 +# For more information on this file, please read the handbook section on 25.8 +# Kernel Configuration Files: 25.9 +# 25.10 +# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html 25.11 +# 25.12 +# The handbook is also available locally in /usr/share/doc/handbook 25.13 +# if you've installed the doc distribution, otherwise always see the 25.14 +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the 25.15 +# latest information. 25.16 +# 25.17 +# An exhaustive list of options and more detailed explanations of the 25.18 +# device lines is also present in the ../../conf/NOTES and NOTES files. 25.19 +# If you are in doubt as to the purpose or necessity of a line, check first 25.20 +# in NOTES. 25.21 +# 25.22 +# $FreeBSD: src/sys/i386/conf/GENERIC,v 1.394.2.3 2004/01/26 19:42:11 nectar Exp $ 25.23 + 25.24 +machine i386-xen 25.25 +cpu I686_CPU 25.26 +ident XEN 25.27 + 25.28 +#To statically compile in device wiring instead of /boot/device.hints 25.29 +#hints "GENERIC.hints" #Default places to look for devices. 25.30 + 25.31 +makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols 25.32 + 25.33 +options SCHED_4BSD #4BSD scheduler 25.34 +options INET #InterNETworking 25.35 +options INET6 #IPv6 communications protocols 25.36 +options FFS #Berkeley Fast Filesystem 25.37 +options SOFTUPDATES #Enable FFS soft updates support 25.38 +options UFS_ACL #Support for access control lists 25.39 +options UFS_DIRHASH #Improve performance on big directories 25.40 +options MD_ROOT #MD is a potential root device 25.41 +options NFSCLIENT #Network Filesystem Client 25.42 +options NFSSERVER #Network Filesystem Server 25.43 +# options NFS_ROOT #NFS usable as /, requires NFSCLIENT 25.44 +#options MSDOSFS #MSDOS Filesystem 25.45 +#options CD9660 #ISO 9660 Filesystem 25.46 +options PROCFS #Process filesystem (requires PSEUDOFS) 25.47 +options PSEUDOFS #Pseudo-filesystem framework 25.48 +options COMPAT_43 #Compatible with BSD 4.3 [KEEP THIS!] 25.49 +options COMPAT_FREEBSD4 #Compatible with FreeBSD4 25.50 +options SCSI_DELAY=15000 #Delay (in ms) before probing SCSI 25.51 +options KTRACE #ktrace(1) support 25.52 +options SYSVSHM #SYSV-style shared memory 25.53 +options SYSVMSG #SYSV-style message queues 25.54 +options SYSVSEM #SYSV-style semaphores 25.55 +options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions 25.56 +options KBD_INSTALL_CDEV # install a CDEV entry in /dev 25.57 +options CPU_DISABLE_SSE # don't turn on SSE framework with Xen 25.58 +#options PFIL_HOOKS # pfil(9) framework 25.59 + 25.60 +# Debugging for use in -current 25.61 +options KDB #Enable the kernel debugger 25.62 +options INVARIANTS #Enable calls of extra sanity checking 25.63 +options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS 25.64 +#options WITNESS #Enable checks to detect deadlocks and cycles 25.65 +#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed 25.66 + 25.67 +# To make an SMP kernel, the next two are needed 25.68 +#options SMP # Symmetric MultiProcessor Kernel 25.69 +#device apic # I/O APIC 25.70 + 25.71 +# SCSI peripherals 25.72 +device scbus # SCSI bus (required for SCSI) 25.73 +#device ch # SCSI media changers 25.74 +device da # Direct Access (disks) 25.75 +#device sa # Sequential Access (tape etc) 25.76 +#device cd # CD 25.77 +device pass # Passthrough device (direct SCSI access) 25.78 +#device ses # SCSI Environmental Services (and SAF-TE) 25.79 + 25.80 +# atkbdc0 controls both the keyboard and the PS/2 mouse 25.81 +#device atkbdc # AT keyboard controller 25.82 +#device atkbd # AT keyboard 25.83 +#device psm # PS/2 mouse 25.84 + 25.85 +# device vga # VGA video card driver 25.86 + 25.87 +#device splash # Splash screen and screen saver support 25.88 + 25.89 +# syscons is the default console driver, resembling an SCO console 25.90 +#device sc 25.91 + 25.92 +# Enable this for the pcvt (VT220 compatible) console driver 25.93 +#device vt 25.94 +#options XSERVER # support for X server on a vt console 25.95 +#options FAT_CURSOR # start with block cursor 25.96 + 25.97 +#device agp # support several AGP chipsets 25.98 + 25.99 +# Floating point support - do not disable. 25.100 +device npx 25.101 + 25.102 +# Serial (COM) ports 25.103 +#device sio # 8250, 16[45]50 based serial ports 25.104 + 25.105 +# Parallel port 25.106 +#device ppc 25.107 +#device ppbus # Parallel port bus (required) 25.108 +#device lpt # Printer 25.109 +#device plip # TCP/IP over parallel 25.110 +#device ppi # Parallel port interface device 25.111 +#device vpo # Requires scbus and da 25.112 + 25.113 +# If you've got a "dumb" serial or parallel PCI card that is 25.114 +# supported by the puc(4) glue driver, uncomment the following 25.115 +# line to enable it (connects to the sio and/or ppc drivers): 25.116 +#device puc 25.117 + 25.118 + 25.119 +# Pseudo devices - the number indicates how many units to allocate. 25.120 +device random # Entropy device 25.121 +device loop # Network loopback 25.122 +device ether # Ethernet support 25.123 +device tun # Packet tunnel. 25.124 +device pty # Pseudo-ttys (telnet etc) 25.125 +device md # Memory "disks" 25.126 +device gif # IPv6 and IPv4 tunneling 25.127 +device faith # IPv6-to-IPv4 relaying (translation) 25.128 + 25.129 +# The `bpf' device enables the Berkeley Packet Filter. 25.130 +# Be aware of the administrative consequences of enabling this! 25.131 +device bpf # Berkeley packet filter 25.132 + 25.133 +#options BOOTP 25.134 +options XEN 25.135 +options MCLSHIFT=12 # this has to be enabled for Xen as we can only have one cluster per page 25.136 +options MSIZE=256 25.137 +options DIAGNOSTIC 25.138 +options MAXMEM=(256*1024) 25.139 +options NOXENDEBUG=1 # Turn off Debugging printfs 25.140 +
26.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 26.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/gethints.awk Thu Mar 24 22:52:13 2005 +0000 26.3 @@ -0,0 +1,116 @@ 26.4 +#! /usr/bin/awk -f 26.5 +# 26.6 +# This is a transition aid. It extracts old-style configuration information 26.7 +# from a config file and writes an equivalent device.hints file to stdout. 26.8 +# You can use that with loader(8) or statically compile it in with the 26.9 +# 'hints' directive. See how GENERIC and GENERIC.hints fit together for 26.10 +# a static example. You should use loader(8) if at all possible. 26.11 +# 26.12 +# $FreeBSD: src/sys/i386/conf/gethints.awk,v 1.2 2002/07/26 03:52:30 peter Exp $ 26.13 + 26.14 +# skip commented lines, empty lines and not "device" lines 26.15 +/^[ \t]*#/ || /^[ \t]*$/ || !/[ \t]*device/ { next; } 26.16 + 26.17 +# input format : 26.18 +# device <name><unit> at <controler>[?] [key [val]]... 26.19 +# possible keys are : 26.20 +# disable, port #, irq #, drq #, drive #, iomem #, iosiz #, 26.21 +# flags #, bus #, target #, unit #. 26.22 +# output format : 26.23 +# hint.<name>.<unit>.<key>=<val> 26.24 +# mapped keys are : 26.25 +# iomem -> maddr, iosiz -> msize. 26.26 +{ 26.27 + gsub ("#.*", ""); # delete comments 26.28 + gsub ("\"", ""); # and double-quotes 26.29 + nameunit = $2; # <name><unit> 26.30 + at = $3; # at 26.31 + controler = $4; # <controler>[?] 26.32 + rest = 5; # optional keys begin at indice 5 26.33 + if (at != "at" || controler == "") 26.34 + next; # skip devices w/o controlers 26.35 + name = nameunit; 26.36 + sub ("[0-9]*$", "", name); # get the name 26.37 + unit = nameunit; 26.38 + sub ("^" name, "", unit); # and the unit 26.39 + sub ("\?$", "", controler); 26.40 + printf "hint.%s.%s.at=\"%s\"\n", name, unit, controler; 26.41 + # for each keys, if any ? 26.42 + for (key = $rest; rest <= NF; key = $(++rest)) { 26.43 + # skip auto-detect keys (the one w/ a ?) 26.44 + if (key == "port?" || key == "drq?" || key == "irq?" || \ 26.45 + key == "iomem?" || key == "iosiz?") 26.46 + continue; 26.47 + # disable has no value, so, give it one 26.48 + if (key == "disable") { 26.49 + printf "hint.%s.%s.disabled=\"1\"\n", name, unit; 26.50 + continue; 26.51 + } 26.52 + # recognized keys 26.53 + if (key == "port" || key == "irq" || key == "drq" || \ 26.54 + key == "drive" || key == "iomem" || key == "iosiz" || \ 26.55 + key == "flags" || key == "bus" || key == "target" || \ 26.56 + key == "unit") { 26.57 + val = $(++rest); 26.58 + if (val == "?") # has above 26.59 + continue; 26.60 + if (key == "port") { 26.61 + # map port macros to static values 26.62 + sub ("IO_AHA0", "0x330", val); 26.63 + sub ("IO_AHA1", "0x334", val); 26.64 + sub ("IO_ASC1", "0x3EB", val); 26.65 + sub ("IO_ASC2", "0x22B", val); 26.66 + sub ("IO_ASC3", "0x26B", val); 26.67 + sub ("IO_ASC4", "0x2AB", val); 26.68 + sub ("IO_ASC5", "0x2EB", val); 26.69 + sub ("IO_ASC6", "0x32B", val); 26.70 + sub ("IO_ASC7", "0x36B", val); 26.71 + sub ("IO_ASC8", "0x3AB", val); 26.72 + sub ("IO_BT0", "0x330", val); 26.73 + sub ("IO_BT1", "0x334", val); 26.74 + sub ("IO_CGA", "0x3D0", val); 26.75 + sub ("IO_COM1", "0x3F8", val); 26.76 + sub ("IO_COM2", "0x2F8", val); 26.77 + sub ("IO_COM3", "0x3E8", val); 26.78 + sub ("IO_COM4", "0x2E8", val); 26.79 + sub ("IO_DMA1", "0x000", val); 26.80 + sub ("IO_DMA2", "0x0C0", val); 26.81 + sub ("IO_DMAPG", "0x080", val); 26.82 + sub ("IO_FD1", "0x3F0", val); 26.83 + sub ("IO_FD2", "0x370", val); 26.84 + sub ("IO_GAME", "0x201", val); 26.85 + sub ("IO_GSC1", "0x270", val); 26.86 + sub ("IO_GSC2", "0x2E0", val); 26.87 + sub ("IO_GSC3", "0x370", val); 26.88 + sub ("IO_GSC4", "0x3E0", val); 26.89 + sub ("IO_ICU1", "0x020", val); 26.90 + sub ("IO_ICU2", "0x0A0", val); 26.91 + sub ("IO_KBD", "0x060", val); 26.92 + sub ("IO_LPT1", "0x378", val); 26.93 + sub ("IO_LPT2", "0x278", val); 26.94 + sub ("IO_LPT3", "0x3BC", val); 26.95 + sub ("IO_MDA", "0x3B0", val); 26.96 + sub ("IO_NMI", "0x070", val); 26.97 + sub ("IO_NPX", "0x0F0", val); 26.98 + sub ("IO_PMP1", "0x026", val); 26.99 + sub ("IO_PMP2", "0x178", val); 26.100 + sub ("IO_PPI", "0x061", val); 26.101 + sub ("IO_RTC", "0x070", val); 26.102 + sub ("IO_TIMER1", "0x040", val); 26.103 + sub ("IO_TIMER2", "0x048", val); 26.104 + sub ("IO_UHA0", "0x330", val); 26.105 + sub ("IO_VGA", "0x3C0", val); 26.106 + sub ("IO_WD1", "0x1F0", val); 26.107 + sub ("IO_WD2", "0x170", val); 26.108 + } else { 26.109 + # map key names 26.110 + sub ("iomem", "maddr", key); 26.111 + sub ("iosiz", "msize", key); 26.112 + } 26.113 + printf "hint.%s.%s.%s=\"%s\"\n", name, unit, key, val; 26.114 + continue; 26.115 + } 26.116 + printf ("unrecognized config token '%s:%s' on line %s\n", 26.117 + rest, key, NR); # > "/dev/stderr"; 26.118 + } 26.119 +}
27.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 27.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/clock.c Thu Mar 24 22:52:13 2005 +0000 27.3 @@ -0,0 +1,513 @@ 27.4 +/*- 27.5 + * Copyright (c) 1990 The Regents of the University of California. 27.6 + * All rights reserved. 27.7 + * 27.8 + * This code is derived from software contributed to Berkeley by 27.9 + * William Jolitz and Don Ahn. 27.10 + * 27.11 + * Redistribution and use in source and binary forms, with or without 27.12 + * modification, are permitted provided that the following conditions 27.13 + * are met: 27.14 + * 1. Redistributions of source code must retain the above copyright 27.15 + * notice, this list of conditions and the following disclaimer. 27.16 + * 2. Redistributions in binary form must reproduce the above copyright 27.17 + * notice, this list of conditions and the following disclaimer in the 27.18 + * documentation and/or other materials provided with the distribution. 27.19 + * 3. All advertising materials mentioning features or use of this software 27.20 + * must display the following acknowledgement: 27.21 + * This product includes software developed by the University of 27.22 + * California, Berkeley and its contributors. 27.23 + * 4. Neither the name of the University nor the names of its contributors 27.24 + * may be used to endorse or promote products derived from this software 27.25 + * without specific prior written permission. 27.26 + * 27.27 + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27.28 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27.29 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27.30 + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27.31 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27.32 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27.33 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27.34 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27.35 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27.36 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27.37 + * SUCH DAMAGE. 27.38 + * 27.39 + * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 27.40 + */ 27.41 + 27.42 +#include <sys/cdefs.h> 27.43 +__FBSDID("$FreeBSD: src/sys/i386/isa/clock.c,v 1.207 2003/11/13 10:02:12 phk Exp $"); 27.44 + 27.45 +/* #define DELAYDEBUG */ 27.46 +/* 27.47 + * Routines to handle clock hardware. 27.48 + */ 27.49 + 27.50 +/* 27.51 + * inittodr, settodr and support routines written 27.52 + * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 27.53 + * 27.54 + * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 27.55 + */ 27.56 + 27.57 +#include "opt_clock.h" 27.58 +#include "opt_isa.h" 27.59 +#include "opt_mca.h" 27.60 + 27.61 +#include <sys/param.h> 27.62 +#include <sys/systm.h> 27.63 +#include <sys/bus.h> 27.64 +#include <sys/lock.h> 27.65 +#include <sys/mutex.h> 27.66 +#include <sys/proc.h> 27.67 +#include <sys/time.h> 27.68 +#include <sys/timetc.h> 27.69 +#include <sys/kernel.h> 27.70 +#include <sys/limits.h> 27.71 +#include <sys/sysctl.h> 27.72 +#include <sys/cons.h> 27.73 +#include <sys/power.h> 27.74 + 27.75 +#include <machine/clock.h> 27.76 +#include <machine/cputypes.h> 27.77 +#include <machine/frame.h> 27.78 +#include <machine/intr_machdep.h> 27.79 +#include <machine/md_var.h> 27.80 +#include <machine/psl.h> 27.81 +#if defined(SMP) 27.82 +#include <machine/smp.h> 27.83 +#endif 27.84 +#include <machine/specialreg.h> 27.85 + 27.86 +#include <i386/isa/icu.h> 27.87 +#include <i386/isa/isa.h> 27.88 +#include <isa/rtc.h> 27.89 +#include <i386/isa/timerreg.h> 27.90 + 27.91 +/* XEN specific defines */ 27.92 +#include <machine/xen_intr.h> 27.93 + 27.94 +/* 27.95 + * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 27.96 + * can use a simple formula for leap years. 27.97 + */ 27.98 +#define LEAPYEAR(y) (((u_int)(y) % 4 == 0) ? 1 : 0) 27.99 +#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 27.100 + 27.101 +int adjkerntz; /* local offset from GMT in seconds */ 27.102 +int clkintr_pending; 27.103 +int disable_rtc_set = 1; /* disable resettodr() if != 0 */ 27.104 +int pscnt = 1; 27.105 +int psdiv = 1; 27.106 +int statclock_disable; 27.107 +#ifndef TIMER_FREQ 27.108 +#define TIMER_FREQ 1193182 27.109 +#endif 27.110 +u_int timer_freq = TIMER_FREQ; 27.111 +struct mtx clock_lock; 27.112 + 27.113 + 27.114 +static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 27.115 + 27.116 +/* Values for timerX_state: */ 27.117 +#define RELEASED 0 27.118 +#define RELEASE_PENDING 1 27.119 +#define ACQUIRED 2 27.120 +#define ACQUIRE_PENDING 3 27.121 + 27.122 +/* Cached *multiplier* to convert TSC counts to microseconds. 27.123 + * (see the equation below). 27.124 + * Equal to 2^32 * (1 / (clocks per usec) ). 27.125 + * Initialized in time_init. 27.126 + */ 27.127 +static unsigned long fast_gettimeoffset_quotient; 27.128 + 27.129 +/* These are peridically updated in shared_info, and then copied here. */ 27.130 +static uint32_t shadow_tsc_stamp; 27.131 +static uint64_t shadow_system_time; 27.132 +static uint32_t shadow_time_version; 27.133 +static struct timeval shadow_tv; 27.134 + 27.135 +static uint64_t processed_system_time;/* System time (ns) at last processing. */ 27.136 + 27.137 +#define NS_PER_TICK (1000000000ULL/hz) 27.138 + 27.139 +/* convert from cycles(64bits) => nanoseconds (64bits) 27.140 + * basic equation: 27.141 + * ns = cycles / (freq / ns_per_sec) 27.142 + * ns = cycles * (ns_per_sec / freq) 27.143 + * ns = cycles * (10^9 / (cpu_mhz * 10^6)) 27.144 + * ns = cycles * (10^3 / cpu_mhz) 27.145 + * 27.146 + * Then we use scaling math (suggested by george@mvista.com) to get: 27.147 + * ns = cycles * (10^3 * SC / cpu_mhz) / SC 27.148 + * ns = cycles * cyc2ns_scale / SC 27.149 + * 27.150 + * And since SC is a constant power of two, we can convert the div 27.151 + * into a shift. 27.152 + * -johnstul@us.ibm.com "math is hard, lets go shopping!" 27.153 + */ 27.154 +static unsigned long cyc2ns_scale; 27.155 +#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ 27.156 + 27.157 +static inline void set_cyc2ns_scale(unsigned long cpu_mhz) 27.158 +{ 27.159 + cyc2ns_scale = (1000 << CYC2NS_SCALE_FACTOR)/cpu_mhz; 27.160 +} 27.161 + 27.162 +static inline unsigned long long cycles_2_ns(unsigned long long cyc) 27.163 +{ 27.164 + return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR; 27.165 +} 27.166 + 27.167 +/* 27.168 + * Reads a consistent set of time-base values from Xen, into a shadow data 27.169 + * area. Must be called with the xtime_lock held for writing. 27.170 + */ 27.171 +static void __get_time_values_from_xen(void) 27.172 +{ 27.173 + shared_info_t *s = HYPERVISOR_shared_info; 27.174 + 27.175 + do { 27.176 + shadow_time_version = s->time_version2; 27.177 + rmb(); 27.178 + shadow_tv.tv_sec = s->wc_sec; 27.179 + shadow_tv.tv_usec = s->wc_usec; 27.180 + shadow_tsc_stamp = (uint32_t)s->tsc_timestamp; 27.181 + shadow_system_time = s->system_time; 27.182 + rmb(); 27.183 + } 27.184 + while (shadow_time_version != s->time_version1); 27.185 +} 27.186 + 27.187 +#define TIME_VALUES_UP_TO_DATE \ 27.188 + (shadow_time_version == HYPERVISOR_shared_info->time_version2) 27.189 + 27.190 +static void (*timer_func)(struct clockframe *frame) = hardclock; 27.191 + 27.192 +static unsigned xen_get_offset(void); 27.193 +static unsigned xen_get_timecount(struct timecounter *tc); 27.194 + 27.195 +static struct timecounter xen_timecounter = { 27.196 + xen_get_timecount, /* get_timecount */ 27.197 + 0, /* no poll_pps */ 27.198 + ~0u, /* counter_mask */ 27.199 + 0, /* frequency */ 27.200 + "ixen", /* name */ 27.201 + 0 /* quality */ 27.202 +}; 27.203 + 27.204 + 27.205 +static void 27.206 +clkintr(struct clockframe *frame) 27.207 +{ 27.208 + int64_t delta; 27.209 + long ticks = 0; 27.210 + 27.211 + 27.212 + do { 27.213 + __get_time_values_from_xen(); 27.214 + delta = (int64_t)(shadow_system_time + 27.215 + xen_get_offset() * 1000 - 27.216 + processed_system_time); 27.217 + } while (!TIME_VALUES_UP_TO_DATE); 27.218 + 27.219 + if (unlikely(delta < 0)) { 27.220 + printk("Timer ISR: Time went backwards: %lld\n", delta); 27.221 + return; 27.222 + } 27.223 + 27.224 + /* Process elapsed ticks since last call. */ 27.225 + while ( delta >= NS_PER_TICK ) 27.226 + { 27.227 + ticks++; 27.228 + delta -= NS_PER_TICK; 27.229 + processed_system_time += NS_PER_TICK; 27.230 + } 27.231 + 27.232 + if (ticks > 0) { 27.233 + if (frame) 27.234 + timer_func(frame); 27.235 +#ifdef SMP 27.236 + if (timer_func == hardclock && frame) 27.237 + forward_hardclock(); 27.238 +#endif 27.239 + } 27.240 +} 27.241 + 27.242 +#include "opt_ddb.h" 27.243 +static uint32_t 27.244 +getit(void) 27.245 +{ 27.246 + __get_time_values_from_xen(); 27.247 + return shadow_tsc_stamp; 27.248 +} 27.249 + 27.250 +/* 27.251 + * Wait "n" microseconds. 27.252 + * Relies on timer 1 counting down from (timer_freq / hz) 27.253 + * Note: timer had better have been programmed before this is first used! 27.254 + */ 27.255 +void 27.256 +DELAY(int n) 27.257 +{ 27.258 + int delta, ticks_left; 27.259 + uint32_t tick, prev_tick; 27.260 +#ifdef DELAYDEBUG 27.261 + int getit_calls = 1; 27.262 + int n1; 27.263 + static int state = 0; 27.264 + 27.265 + if (state == 0) { 27.266 + state = 1; 27.267 + for (n1 = 1; n1 <= 10000000; n1 *= 10) 27.268 + DELAY(n1); 27.269 + state = 2; 27.270 + } 27.271 + if (state == 1) 27.272 + printf("DELAY(%d)...", n); 27.273 +#endif 27.274 + /* 27.275 + * Read the counter first, so that the rest of the setup overhead is 27.276 + * counted. Guess the initial overhead is 20 usec (on most systems it 27.277 + * takes about 1.5 usec for each of the i/o's in getit(). The loop 27.278 + * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 27.279 + * multiplications and divisions to scale the count take a while). 27.280 + * 27.281 + * However, if ddb is active then use a fake counter since reading 27.282 + * the i8254 counter involves acquiring a lock. ddb must not go 27.283 + * locking for many reasons, but it calls here for at least atkbd 27.284 + * input. 27.285 + */ 27.286 + prev_tick = getit(); 27.287 + 27.288 + n -= 0; /* XXX actually guess no initial overhead */ 27.289 + /* 27.290 + * Calculate (n * (timer_freq / 1e6)) without using floating point 27.291 + * and without any avoidable overflows. 27.292 + */ 27.293 + if (n <= 0) 27.294 + ticks_left = 0; 27.295 + else if (n < 256) 27.296 + /* 27.297 + * Use fixed point to avoid a slow division by 1000000. 27.298 + * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 27.299 + * 2^15 is the first power of 2 that gives exact results 27.300 + * for n between 0 and 256. 27.301 + */ 27.302 + ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 27.303 + else 27.304 + /* 27.305 + * Don't bother using fixed point, although gcc-2.7.2 27.306 + * generates particularly poor code for the long long 27.307 + * division, since even the slow way will complete long 27.308 + * before the delay is up (unless we're interrupted). 27.309 + */ 27.310 + ticks_left = ((u_int)n * (long long)timer_freq + 999999) 27.311 + / 1000000; 27.312 + 27.313 + while (ticks_left > 0) { 27.314 + tick = getit(); 27.315 +#ifdef DELAYDEBUG 27.316 + ++getit_calls; 27.317 +#endif 27.318 + delta = tick - prev_tick; 27.319 + prev_tick = tick; 27.320 + if (delta < 0) { 27.321 + /* 27.322 + * Guard against timer0_max_count being wrong. 27.323 + * This shouldn't happen in normal operation, 27.324 + * but it may happen if set_timer_freq() is 27.325 + * traced. 27.326 + */ 27.327 + /* delta += timer0_max_count; ??? */ 27.328 + if (delta < 0) 27.329 + delta = 0; 27.330 + } 27.331 + ticks_left -= delta; 27.332 + } 27.333 +#ifdef DELAYDEBUG 27.334 + if (state == 1) 27.335 + printf(" %d calls to getit() at %d usec each\n", 27.336 + getit_calls, (n + 5) / getit_calls); 27.337 +#endif 27.338 +} 27.339 + 27.340 + 27.341 +int 27.342 +sysbeep(int pitch, int period) 27.343 +{ 27.344 + return (0); 27.345 +} 27.346 + 27.347 +/* 27.348 + * Restore all the timers non-atomically (XXX: should be atomically). 27.349 + * 27.350 + * This function is called from pmtimer_resume() to restore all the timers. 27.351 + * This should not be necessary, but there are broken laptops that do not 27.352 + * restore all the timers on resume. 27.353 + */ 27.354 +void 27.355 +timer_restore(void) 27.356 +{ 27.357 + /* Get timebases for new environment. */ 27.358 + __get_time_values_from_xen(); 27.359 + 27.360 + /* Reset our own concept of passage of system time. */ 27.361 + processed_system_time = shadow_system_time; 27.362 +} 27.363 + 27.364 +void 27.365 +startrtclock() 27.366 +{ 27.367 + unsigned long long alarm; 27.368 + uint64_t __cpu_khz; 27.369 + uint32_t cpu_khz; 27.370 + 27.371 + __cpu_khz = HYPERVISOR_shared_info->cpu_freq; 27.372 + __cpu_khz /= 1000; 27.373 + cpu_khz = (uint32_t)__cpu_khz; 27.374 + printk("Xen reported: %lu.%03lu MHz processor.\n", 27.375 + cpu_khz / 1000, cpu_khz % 1000); 27.376 + 27.377 + /* (10^6 * 2^32) / cpu_hz = (10^3 * 2^32) / cpu_khz = 27.378 + (2^32 * 1 / (clocks/us)) */ 27.379 + { 27.380 + unsigned long eax=0, edx=1000; 27.381 + __asm__("divl %2" 27.382 + :"=a" (fast_gettimeoffset_quotient), "=d" (edx) 27.383 + :"r" (cpu_khz), 27.384 + "0" (eax), "1" (edx)); 27.385 + } 27.386 + 27.387 + set_cyc2ns_scale(cpu_khz/1000); 27.388 + timer_freq = tsc_freq = xen_timecounter.tc_frequency = cpu_khz * 1000; 27.389 + tc_init(&xen_timecounter); 27.390 + 27.391 + 27.392 + rdtscll(alarm); 27.393 +} 27.394 + 27.395 +/* 27.396 + * Initialize the time of day register, based on the time base which is, e.g. 27.397 + * from a filesystem. 27.398 + */ 27.399 +void 27.400 +inittodr(time_t base) 27.401 +{ 27.402 + int s, y; 27.403 + struct timespec ts; 27.404 + 27.405 + s = splclock(); 27.406 + if (base) { 27.407 + ts.tv_sec = base; 27.408 + ts.tv_nsec = 0; 27.409 + tc_setclock(&ts); 27.410 + } 27.411 + 27.412 + y = time_second - shadow_tv.tv_sec; 27.413 + if (y <= -2 || y >= 2) { 27.414 + /* badly off, adjust it */ 27.415 + ts.tv_sec = shadow_tv.tv_sec; 27.416 + ts.tv_nsec = shadow_tv.tv_usec * 1000; 27.417 + tc_setclock(&ts); 27.418 + } 27.419 + splx(s); 27.420 +} 27.421 + 27.422 +/* 27.423 + * Write system time back to RTC. Not supported for guest domains. 27.424 + */ 27.425 +void 27.426 +resettodr() 27.427 +{ 27.428 +} 27.429 + 27.430 + 27.431 +/* 27.432 + * Start clocks running. 27.433 + */ 27.434 +void 27.435 +cpu_initclocks() 27.436 +{ 27.437 + int diag; 27.438 + int time_irq = bind_virq_to_irq(VIRQ_TIMER); 27.439 + 27.440 + if ((diag = intr_add_handler("clk", time_irq, 27.441 + (driver_intr_t *)clkintr, NULL, 27.442 + INTR_TYPE_CLK | INTR_FAST, NULL))) { 27.443 + panic("failed to register clock interrupt: %d\n", diag); 27.444 + } 27.445 + 27.446 + /* should fast clock be enabled ? */ 27.447 + 27.448 + /* initialize xen values */ 27.449 + __get_time_values_from_xen(); 27.450 + processed_system_time = shadow_system_time; 27.451 +} 27.452 + 27.453 +void 27.454 +cpu_startprofclock(void) 27.455 +{ 27.456 + 27.457 + printf("cpu_startprofclock: profiling clock is not supported\n"); 27.458 +} 27.459 + 27.460 +void 27.461 +cpu_stopprofclock(void) 27.462 +{ 27.463 + 27.464 + printf("cpu_stopprofclock: profiling clock is not supported\n"); 27.465 +} 27.466 + 27.467 +static uint32_t 27.468 +xen_get_timecount(struct timecounter *tc) 27.469 +{ 27.470 + __get_time_values_from_xen(); 27.471 + return shadow_tsc_stamp; 27.472 +} 27.473 + 27.474 +/* 27.475 + * Track behavior of cur_timer->get_offset() functionality in timer_tsc.c 27.476 + */ 27.477 +#undef rdtsc 27.478 +#define rdtsc(low,high) \ 27.479 + __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)) 27.480 + 27.481 +static uint32_t 27.482 +xen_get_offset(void) 27.483 +{ 27.484 + register unsigned long eax, edx; 27.485 + 27.486 + /* Read the Time Stamp Counter */ 27.487 + 27.488 + rdtsc(eax,edx); 27.489 + 27.490 + /* .. relative to previous jiffy (32 bits is enough) */ 27.491 + eax -= shadow_tsc_stamp; 27.492 + 27.493 + /* 27.494 + * Time offset = (tsc_low delta) * fast_gettimeoffset_quotient 27.495 + * = (tsc_low delta) * (usecs_per_clock) 27.496 + * = (tsc_low delta) * (usecs_per_jiffy / clocks_per_jiffy) 27.497 + * 27.498 + * Using a mull instead of a divl saves up to 31 clock cycles 27.499 + * in the critical path. 27.500 + */ 27.501 + 27.502 + __asm__("mull %2" 27.503 + :"=a" (eax), "=d" (edx) 27.504 + :"rm" (fast_gettimeoffset_quotient), 27.505 + "0" (eax)); 27.506 + 27.507 + /* our adjusted time offset in microseconds */ 27.508 + return edx; 27.509 +} 27.510 + 27.511 +void 27.512 +idle_block(void) 27.513 +{ 27.514 + if (HYPERVISOR_set_timer_op(processed_system_time + NS_PER_TICK) == 0) 27.515 + HYPERVISOR_block(); 27.516 +}
28.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 28.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/critical.c Thu Mar 24 22:52:13 2005 +0000 28.3 @@ -0,0 +1,46 @@ 28.4 +/*- 28.5 + * Copyright (c) 2002 Matthew Dillon. All Rights Reserved. 28.6 + * Redistribution and use in source and binary forms, with or without 28.7 + * modification, are permitted provided that the following conditions 28.8 + * are met: 28.9 + * 1. Redistributions of source code must retain the above copyright 28.10 + * notice, this list of conditions and the following disclaimer. 28.11 + * 2. Redistributions in binary form must reproduce the above copyright 28.12 + * notice, this list of conditions and the following disclaimer in the 28.13 + * documentation and/or other materials provided with the distribution. 28.14 + * 4. Neither the name of the University nor the names of its contributors 28.15 + * may be used to endorse or promote products derived from this software 28.16 + * without specific prior written permission. 28.17 + * 28.18 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 28.19 + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28.20 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28.21 + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 28.22 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28.23 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28.24 + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28.25 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28.26 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28.27 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28.28 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28.29 + */ 28.30 + 28.31 +#include <sys/cdefs.h> 28.32 +__FBSDID("$FreeBSD: src/sys/i386/i386/critical.c,v 1.12 2003/11/03 21:06:54 jhb Exp $"); 28.33 + 28.34 +#include <sys/param.h> 28.35 +#include <sys/systm.h> 28.36 +#include <sys/proc.h> 28.37 +#include <machine/critical.h> 28.38 +#include <machine/psl.h> 28.39 + 28.40 +/* 28.41 + * cpu_critical_fork_exit() - cleanup after fork 28.42 + * 28.43 + * Enable interrupts in the saved copy of eflags. 28.44 + */ 28.45 +void 28.46 +cpu_critical_fork_exit(void) 28.47 +{ 28.48 + curthread->td_md.md_savecrit = 0; 28.49 +}
29.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 29.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/ctrl_if.c Thu Mar 24 22:52:13 2005 +0000 29.3 @@ -0,0 +1,533 @@ 29.4 +/****************************************************************************** 29.5 + * ctrl_if.c 29.6 + * 29.7 + * Management functions for special interface to the domain controller. 29.8 + * 29.9 + * Copyright (c) 2004, K A Fraser 29.10 + * Copyright (c) 2004, K M Macy 29.11 + */ 29.12 + 29.13 +#include <sys/param.h> 29.14 +#include <sys/systm.h> 29.15 +#include <sys/uio.h> 29.16 +#include <sys/bus.h> 29.17 +#include <sys/malloc.h> 29.18 +#include <sys/kernel.h> 29.19 +#include <sys/lock.h> 29.20 +#include <sys/mutex.h> 29.21 +#include <sys/selinfo.h> 29.22 +#include <sys/poll.h> 29.23 +#include <sys/conf.h> 29.24 +#include <sys/fcntl.h> 29.25 +#include <sys/ioccom.h> 29.26 +#include <sys/taskqueue.h> 29.27 + 29.28 + 29.29 +#include <machine/cpufunc.h> 29.30 +#include <machine/intr_machdep.h> 29.31 +#include <machine/xen-os.h> 29.32 +#include <machine/xen_intr.h> 29.33 +#include <machine/bus.h> 29.34 +#include <sys/rman.h> 29.35 +#include <machine/resource.h> 29.36 +#include <machine/synch_bitops.h> 29.37 + 29.38 + 29.39 +#include <machine/hypervisor-ifs.h> 29.40 + 29.41 +#include <machine/ctrl_if.h> 29.42 +#include <machine/evtchn.h> 29.43 + 29.44 +/* 29.45 + * Extra ring macros to sync a consumer index up to the public producer index. 29.46 + * Generally UNSAFE, but we use it for recovery and shutdown in some cases. 29.47 + */ 29.48 +#define RING_DROP_PENDING_REQUESTS(_r) \ 29.49 + do { \ 29.50 + (_r)->req_cons = (_r)->sring->req_prod; \ 29.51 + } while (0) 29.52 +#define RING_DROP_PENDING_RESPONSES(_r) \ 29.53 + do { \ 29.54 + (_r)->rsp_cons = (_r)->sring->rsp_prod; \ 29.55 + } while (0) 29.56 +/* 29.57 + * Only used by initial domain which must create its own control-interface 29.58 + * event channel. This value is picked up by the user-space domain controller 29.59 + * via an ioctl. 29.60 + */ 29.61 +int initdom_ctrlif_domcontroller_port = -1; 29.62 + 29.63 +static int ctrl_if_evtchn; 29.64 +static int ctrl_if_irq; 29.65 +static struct mtx ctrl_if_lock; 29.66 +static int * ctrl_if_wchan = &ctrl_if_evtchn; 29.67 + 29.68 + 29.69 +static ctrl_front_ring_t ctrl_if_tx_ring; 29.70 +static ctrl_back_ring_t ctrl_if_rx_ring; 29.71 + 29.72 +/* Incoming message requests. */ 29.73 + /* Primary message type -> message handler. */ 29.74 +static ctrl_msg_handler_t ctrl_if_rxmsg_handler[256]; 29.75 + /* Primary message type -> callback in process context? */ 29.76 +static unsigned long ctrl_if_rxmsg_blocking_context[256/sizeof(unsigned long)]; 29.77 + /* Queue up messages to be handled in process context. */ 29.78 +static ctrl_msg_t ctrl_if_rxmsg_deferred[CONTROL_RING_SIZE]; 29.79 +static CONTROL_RING_IDX ctrl_if_rxmsg_deferred_prod; 29.80 +static CONTROL_RING_IDX ctrl_if_rxmsg_deferred_cons; 29.81 + 29.82 +/* Incoming message responses: message identifier -> message handler/id. */ 29.83 +static struct { 29.84 + ctrl_msg_handler_t fn; 29.85 + unsigned long id; 29.86 +} ctrl_if_txmsg_id_mapping[CONTROL_RING_SIZE]; 29.87 + 29.88 +/* 29.89 + * FreeBSD task queues don't allow you to requeue an already executing task. 29.90 + * Since ctrl_if_interrupt clears the TX_FULL condition and schedules any 29.91 + * waiting tasks, which themselves may need to schedule a new task 29.92 + * (due to new a TX_FULL condition), we ping-pong between these A/B task queues. 29.93 + * The interrupt runs anything on the current queue and moves the index so that 29.94 + * future schedulings occur on the next queue. We should never get into a 29.95 + * situation where there is a task scheduleded on both the A & B queues. 29.96 + */ 29.97 +TASKQUEUE_DECLARE(ctrl_if_txA); 29.98 +TASKQUEUE_DEFINE(ctrl_if_txA, NULL, NULL, {}); 29.99 +TASKQUEUE_DECLARE(ctrl_if_txB); 29.100 +TASKQUEUE_DEFINE(ctrl_if_txB, NULL, NULL, {}); 29.101 +struct taskqueue **taskqueue_ctrl_if_tx[2] = { &taskqueue_ctrl_if_txA, 29.102 + &taskqueue_ctrl_if_txB }; 29.103 +static int ctrl_if_idx = 0; 29.104 + 29.105 +static struct task ctrl_if_rx_tasklet; 29.106 +static struct task ctrl_if_tx_tasklet; 29.107 + /* Passed to schedule_task(). */ 29.108 +static struct task ctrl_if_rxmsg_deferred_task; 29.109 + 29.110 + 29.111 + 29.112 +#define get_ctrl_if() ((control_if_t *)((char *)HYPERVISOR_shared_info + 2048)) 29.113 + 29.114 +static void 29.115 +ctrl_if_notify_controller(void) 29.116 +{ 29.117 + notify_via_evtchn(ctrl_if_evtchn); 29.118 +} 29.119 + 29.120 +static void 29.121 +ctrl_if_rxmsg_default_handler(ctrl_msg_t *msg, unsigned long id) 29.122 +{ 29.123 + msg->length = 0; 29.124 + ctrl_if_send_response(msg); 29.125 +} 29.126 + 29.127 +static void 29.128 +__ctrl_if_tx_tasklet(void *context __unused, int pending __unused) 29.129 +{ 29.130 + ctrl_msg_t *msg; 29.131 + int was_full = RING_FULL(&ctrl_if_tx_ring); 29.132 + RING_IDX i, rp; 29.133 + 29.134 + i = ctrl_if_tx_ring.rsp_cons; 29.135 + rp = ctrl_if_tx_ring.sring->rsp_prod; 29.136 + rmb(); /* Ensure we see all requests up to 'rp'. */ 29.137 + 29.138 + for ( ; i != rp; i++ ) 29.139 + { 29.140 + msg = RING_GET_RESPONSE(&ctrl_if_tx_ring, i); 29.141 + 29.142 + /* Execute the callback handler, if one was specified. */ 29.143 + if ( msg->id != 0xFF ) 29.144 + { 29.145 + (*ctrl_if_txmsg_id_mapping[msg->id].fn)( 29.146 + msg, ctrl_if_txmsg_id_mapping[msg->id].id); 29.147 + smp_mb(); /* Execute, /then/ free. */ 29.148 + ctrl_if_txmsg_id_mapping[msg->id].fn = NULL; 29.149 + } 29.150 + 29.151 + } 29.152 + 29.153 + /* 29.154 + * Step over the message in the ring /after/ finishing reading it. As 29.155 + * soon as the index is updated then the message may get blown away. 29.156 + */ 29.157 + smp_mb(); 29.158 + ctrl_if_tx_ring.rsp_cons = i; 29.159 + 29.160 + if ( was_full && !RING_FULL(&ctrl_if_tx_ring) ) 29.161 + { 29.162 + wakeup(ctrl_if_wchan); 29.163 + 29.164 + /* bump idx so future enqueues will occur on the next taskq 29.165 + * process any currently pending tasks 29.166 + */ 29.167 + ctrl_if_idx++; 29.168 + taskqueue_run(*taskqueue_ctrl_if_tx[(ctrl_if_idx-1) & 1]); 29.169 + } 29.170 + 29.171 +} 29.172 + 29.173 +static void 29.174 +__ctrl_if_rxmsg_deferred_task(void *context __unused, int pending __unused) 29.175 +{ 29.176 + ctrl_msg_t *msg; 29.177 + CONTROL_RING_IDX dp; 29.178 + 29.179 + dp = ctrl_if_rxmsg_deferred_prod; 29.180 + rmb(); /* Ensure we see all deferred requests up to 'dp'. */ 29.181 + 29.182 + while ( ctrl_if_rxmsg_deferred_cons != dp ) 29.183 + { 29.184 + msg = &ctrl_if_rxmsg_deferred[MASK_CONTROL_IDX( 29.185 + ctrl_if_rxmsg_deferred_cons++)]; 29.186 + (*ctrl_if_rxmsg_handler[msg->type])(msg, 0); 29.187 + } 29.188 + 29.189 +} 29.190 + 29.191 +static void 29.192 +__ctrl_if_rx_tasklet(void *context __unused, int pending __unused) 29.193 +{ 29.194 + ctrl_msg_t msg, *pmsg; 29.195 + CONTROL_RING_IDX dp; 29.196 + RING_IDX rp, i; 29.197 + 29.198 + i = ctrl_if_rx_ring.req_cons; 29.199 + rp = ctrl_if_rx_ring.sring->req_prod; 29.200 + dp = ctrl_if_rxmsg_deferred_prod; 29.201 + 29.202 + rmb(); /* Ensure we see all requests up to 'rp'. */ 29.203 + 29.204 + for ( ; i != rp; i++) 29.205 + { 29.206 + pmsg = RING_GET_REQUEST(&ctrl_if_rx_ring, i); 29.207 + memcpy(&msg, pmsg, offsetof(ctrl_msg_t, msg)); 29.208 + 29.209 + if ( msg.length > sizeof(msg.msg)) 29.210 + msg.length = sizeof(msg.msg); 29.211 + if ( msg.length != 0 ) 29.212 + memcpy(msg.msg, pmsg->msg, msg.length); 29.213 + if ( test_bit(msg.type, &ctrl_if_rxmsg_blocking_context) ) 29.214 + { 29.215 + memcpy(&ctrl_if_rxmsg_deferred[MASK_CONTROL_IDX(dp++)], 29.216 + &msg, offsetof(ctrl_msg_t, msg) + msg.length); 29.217 + } 29.218 + else 29.219 + { 29.220 + (*ctrl_if_rxmsg_handler[msg.type])(&msg, 0); 29.221 + } 29.222 + } 29.223 + ctrl_if_rx_ring.req_cons = i; 29.224 + 29.225 + if ( dp != ctrl_if_rxmsg_deferred_prod ) 29.226 + { 29.227 + wmb(); 29.228 + ctrl_if_rxmsg_deferred_prod = dp; 29.229 + taskqueue_enqueue(taskqueue_thread, &ctrl_if_rxmsg_deferred_task); 29.230 + } 29.231 + 29.232 +} 29.233 + 29.234 +static void 29.235 +ctrl_if_interrupt(void *ctrl_sc) 29.236 +/* (int irq, void *dev_id, struct pt_regs *regs) */ 29.237 +{ 29.238 + 29.239 + 29.240 + if ( RING_HAS_UNCONSUMED_RESPONSES(&ctrl_if_tx_ring) ) 29.241 + taskqueue_enqueue(taskqueue_swi, &ctrl_if_tx_tasklet); 29.242 + 29.243 + 29.244 + if ( RING_HAS_UNCONSUMED_REQUESTS(&ctrl_if_rx_ring) ) 29.245 + taskqueue_enqueue(taskqueue_swi, &ctrl_if_rx_tasklet); 29.246 + 29.247 +} 29.248 + 29.249 +int 29.250 +ctrl_if_send_message_noblock( 29.251 + ctrl_msg_t *msg, 29.252 + ctrl_msg_handler_t hnd, 29.253 + unsigned long id) 29.254 +{ 29.255 + unsigned long flags; 29.256 + ctrl_msg_t *dmsg; 29.257 + int i; 29.258 + 29.259 + mtx_lock_irqsave(&ctrl_if_lock, flags); 29.260 + 29.261 + if ( RING_FULL(&ctrl_if_tx_ring) ) 29.262 + { 29.263 + mtx_unlock_irqrestore(&ctrl_if_lock, flags); 29.264 + return EAGAIN; 29.265 + } 29.266 + 29.267 + msg->id = 0xFF; 29.268 + if ( hnd != NULL ) 29.269 + { 29.270 + for ( i = 0; ctrl_if_txmsg_id_mapping[i].fn != NULL; i++ ) 29.271 + continue; 29.272 + ctrl_if_txmsg_id_mapping[i].fn = hnd; 29.273 + ctrl_if_txmsg_id_mapping[i].id = id; 29.274 + msg->id = i; 29.275 + } 29.276 + 29.277 + dmsg = RING_GET_REQUEST(&ctrl_if_tx_ring, 29.278 + ctrl_if_tx_ring.req_prod_pvt); 29.279 + memcpy(dmsg, msg, sizeof(*msg)); 29.280 + ctrl_if_tx_ring.req_prod_pvt++; 29.281 + RING_PUSH_REQUESTS(&ctrl_if_tx_ring); 29.282 + 29.283 + mtx_unlock_irqrestore(&ctrl_if_lock, flags); 29.284 + 29.285 + ctrl_if_notify_controller(); 29.286 + 29.287 + return 0; 29.288 +} 29.289 + 29.290 +int 29.291 +ctrl_if_send_message_block( 29.292 + ctrl_msg_t *msg, 29.293 + ctrl_msg_handler_t hnd, 29.294 + unsigned long id, 29.295 + long wait_state) 29.296 +{ 29.297 + int rc, sst = 0; 29.298 + 29.299 + /* Fast path. */ 29.300 + if ( (rc = ctrl_if_send_message_noblock(msg, hnd, id)) != EAGAIN ) 29.301 + goto done; 29.302 + 29.303 + for ( ; ; ) 29.304 + { 29.305 + 29.306 + if ( (rc = ctrl_if_send_message_noblock(msg, hnd, id)) != EAGAIN ) 29.307 + break; 29.308 + 29.309 + if ( sst != 0) { 29.310 + rc = EINTR; 29.311 + goto done; 29.312 + } 29.313 + 29.314 + sst = tsleep(ctrl_if_wchan, PWAIT|PCATCH, "ctlrwt", 10); 29.315 + } 29.316 + done: 29.317 + 29.318 + return rc; 29.319 +} 29.320 + 29.321 +int 29.322 +ctrl_if_enqueue_space_callback(struct task *task) 29.323 +{ 29.324 + 29.325 + /* Fast path. */ 29.326 + if ( !RING_FULL(&ctrl_if_tx_ring) ) 29.327 + return 0; 29.328 + 29.329 + (void)taskqueue_enqueue(*taskqueue_ctrl_if_tx[(ctrl_if_idx & 1)], task); 29.330 + 29.331 + /* 29.332 + * We may race execution of the task queue, so return re-checked status. If 29.333 + * the task is not executed despite the ring being non-full then we will 29.334 + * certainly return 'not full'. 29.335 + */ 29.336 + smp_mb(); 29.337 + return RING_FULL(&ctrl_if_tx_ring); 29.338 +} 29.339 + 29.340 +void 29.341 +ctrl_if_send_response(ctrl_msg_t *msg) 29.342 +{ 29.343 + unsigned long flags; 29.344 + ctrl_msg_t *dmsg; 29.345 + 29.346 + /* 29.347 + * NB. The response may the original request message, modified in-place. 29.348 + * In this situation we may have src==dst, so no copying is required. 29.349 + */ 29.350 + mtx_lock_irqsave(&ctrl_if_lock, flags); 29.351 + dmsg = RING_GET_RESPONSE(&ctrl_if_rx_ring, 29.352 + ctrl_if_rx_ring.rsp_prod_pvt); 29.353 + if ( dmsg != msg ) 29.354 + memcpy(dmsg, msg, sizeof(*msg)); 29.355 + 29.356 + ctrl_if_rx_ring.rsp_prod_pvt++; 29.357 + RING_PUSH_RESPONSES(&ctrl_if_rx_ring); 29.358 + 29.359 + mtx_unlock_irqrestore(&ctrl_if_lock, flags); 29.360 + 29.361 + ctrl_if_notify_controller(); 29.362 +} 29.363 + 29.364 +int 29.365 +ctrl_if_register_receiver( 29.366 + uint8_t type, 29.367 + ctrl_msg_handler_t hnd, 29.368 + unsigned int flags) 29.369 +{ 29.370 + unsigned long _flags; 29.371 + int inuse; 29.372 + 29.373 + mtx_lock_irqsave(&ctrl_if_lock, _flags); 29.374 + 29.375 + inuse = (ctrl_if_rxmsg_handler[type] != ctrl_if_rxmsg_default_handler); 29.376 + 29.377 + if ( inuse ) 29.378 + { 29.379 + printk("Receiver %p already established for control " 29.380 + "messages of type %d.\n", ctrl_if_rxmsg_handler[type], type); 29.381 + } 29.382 + else 29.383 + { 29.384 + ctrl_if_rxmsg_handler[type] = hnd; 29.385 + clear_bit(type, &ctrl_if_rxmsg_blocking_context); 29.386 + if ( flags == CALLBACK_IN_BLOCKING_CONTEXT ) 29.387 + { 29.388 + set_bit(type, &ctrl_if_rxmsg_blocking_context); 29.389 + } 29.390 + } 29.391 + 29.392 + mtx_unlock_irqrestore(&ctrl_if_lock, _flags); 29.393 + 29.394 + return !inuse; 29.395 +} 29.396 + 29.397 +void 29.398 +ctrl_if_unregister_receiver(uint8_t type, ctrl_msg_handler_t hnd) 29.399 +{ 29.400 + unsigned long flags; 29.401 + 29.402 + mtx_lock_irqsave(&ctrl_if_lock, flags); 29.403 + 29.404 + if ( ctrl_if_rxmsg_handler[type] != hnd ) 29.405 + printk("Receiver %p is not registered for control " 29.406 + "messages of type %d.\n", hnd, type); 29.407 + else 29.408 + ctrl_if_rxmsg_handler[type] = ctrl_if_rxmsg_default_handler; 29.409 + 29.410 + mtx_unlock_irqrestore(&ctrl_if_lock, flags); 29.411 + 29.412 + /* Ensure that @hnd will not be executed after this function returns. */ 29.413 + /* XXX need rx_tasklet_lock -- can cheat for now?*/ 29.414 +#ifdef notyet 29.415 + tasklet_unlock_wait(&ctrl_if_rx_tasklet); 29.416 +#endif 29.417 +} 29.418 + 29.419 +void 29.420 +ctrl_if_suspend(void) 29.421 +{ 29.422 + /* I'm not sure what the equivalent is - we aren't going to support suspend 29.423 + * yet anyway 29.424 + */ 29.425 +#ifdef notyet 29.426 + free_irq(ctrl_if_irq, NULL); 29.427 +#endif 29.428 + unbind_evtchn_from_irq(ctrl_if_evtchn); 29.429 +} 29.430 + 29.431 +#if 0 29.432 +/** Reset the control interface progress pointers. 29.433 + * Marks the queues empty if 'clear' non-zero. 29.434 + */ 29.435 +static void 29.436 +ctrl_if_reset(int clear) 29.437 +{ 29.438 + control_if_t *ctrl_if = get_ctrl_if(); 29.439 + 29.440 + if (clear) { 29.441 + *ctrl_if = (control_if_t){}; 29.442 + } 29.443 + 29.444 + ctrl_if_tx_resp_cons = ctrl_if->tx_resp_prod; 29.445 + ctrl_if_rx_req_cons = ctrl_if->rx_resp_prod; 29.446 +} 29.447 + 29.448 +#endif 29.449 +void 29.450 +ctrl_if_resume(void) 29.451 +{ 29.452 + control_if_t *ctrl_if = get_ctrl_if(); 29.453 + 29.454 + TRACE_ENTER; 29.455 + if ( xen_start_info->flags & SIF_INITDOMAIN ) 29.456 + { 29.457 + /* 29.458 + * The initial domain must create its own domain-controller link. 29.459 + * The controller is probably not running at this point, but will 29.460 + * pick up its end of the event channel from 29.461 + */ 29.462 + evtchn_op_t op; 29.463 + op.cmd = EVTCHNOP_bind_interdomain; 29.464 + op.u.bind_interdomain.dom1 = DOMID_SELF; 29.465 + op.u.bind_interdomain.dom2 = DOMID_SELF; 29.466 + op.u.bind_interdomain.port1 = 0; 29.467 + op.u.bind_interdomain.port2 = 0; 29.468 + if ( HYPERVISOR_event_channel_op(&op) != 0 ) 29.469 + panic("event_channel_op failed\n"); 29.470 + xen_start_info->domain_controller_evtchn = op.u.bind_interdomain.port1; 29.471 + initdom_ctrlif_domcontroller_port = op.u.bind_interdomain.port2; 29.472 + } 29.473 + 29.474 + 29.475 + /* Sync up with shared indexes. */ 29.476 + FRONT_RING_ATTACH(&ctrl_if_tx_ring, &ctrl_if->tx_ring); 29.477 + BACK_RING_ATTACH(&ctrl_if_rx_ring, &ctrl_if->rx_ring); 29.478 + 29.479 + ctrl_if_evtchn = xen_start_info->domain_controller_evtchn; 29.480 + ctrl_if_irq = bind_evtchn_to_irq(ctrl_if_evtchn); 29.481 + 29.482 + /* 29.483 + * I have not taken the time to determine what the interrupt thread priorities 29.484 + * correspond to - this interface is used for network and disk, network would 29.485 + * seem higher priority, hence I'm using it 29.486 + */ 29.487 + 29.488 + intr_add_handler("ctrl-if", ctrl_if_irq, (driver_intr_t*)ctrl_if_interrupt, 29.489 + NULL, INTR_TYPE_NET, NULL); 29.490 + TRACE_EXIT; 29.491 + /* XXX currently assuming not MPSAFE */ 29.492 +} 29.493 + 29.494 +static void 29.495 +ctrl_if_init(void *dummy __unused) 29.496 +{ 29.497 + control_if_t *ctrl_if = get_ctrl_if(); 29.498 + 29.499 + int i; 29.500 + 29.501 + for ( i = 0; i < 256; i++ ) 29.502 + ctrl_if_rxmsg_handler[i] = ctrl_if_rxmsg_default_handler; 29.503 + 29.504 + FRONT_RING_ATTACH(&ctrl_if_tx_ring, &ctrl_if->tx_ring); 29.505 + BACK_RING_ATTACH(&ctrl_if_rx_ring, &ctrl_if->rx_ring); 29.506 + 29.507 + mtx_init(&ctrl_if_lock, "ctrlif", NULL, MTX_SPIN | MTX_NOWITNESS); 29.508 + 29.509 + TASK_INIT(&ctrl_if_tx_tasklet, 0, __ctrl_if_tx_tasklet, NULL); 29.510 + 29.511 + TASK_INIT(&ctrl_if_rx_tasklet, 0, __ctrl_if_rx_tasklet, NULL); 29.512 + 29.513 + TASK_INIT(&ctrl_if_rxmsg_deferred_task, 0, __ctrl_if_rxmsg_deferred_task, NULL); 29.514 + 29.515 + 29.516 + ctrl_if_resume(); 29.517 +} 29.518 + 29.519 +/* 29.520 + * !! The following are DANGEROUS FUNCTIONS !! 29.521 + * Use with care [for example, see xencons_force_flush()]. 29.522 + */ 29.523 + 29.524 +int 29.525 +ctrl_if_transmitter_empty(void) 29.526 +{ 29.527 + return (ctrl_if_tx_ring.sring->req_prod == ctrl_if_tx_ring.rsp_cons); 29.528 +} 29.529 + 29.530 +void 29.531 +ctrl_if_discard_responses(void) 29.532 +{ 29.533 + RING_DROP_PENDING_RESPONSES(&ctrl_if_tx_ring); 29.534 +} 29.535 + 29.536 +SYSINIT(ctrl_if_init, SI_SUB_DRIVERS, SI_ORDER_FIRST, ctrl_if_init, NULL);
30.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 30.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/db_interface.c Thu Mar 24 22:52:13 2005 +0000 30.3 @@ -0,0 +1,209 @@ 30.4 +/* 30.5 + * Mach Operating System 30.6 + * Copyright (c) 1991,1990 Carnegie Mellon University 30.7 + * All Rights Reserved. 30.8 + * 30.9 + * Permission to use, copy, modify and distribute this software and its 30.10 + * documentation is hereby granted, provided that both the copyright 30.11 + * notice and this permission notice appear in all copies of the 30.12 + * software, derivative works or modified versions, and any portions 30.13 + * thereof, and that both notices appear in supporting documentation. 30.14 + * 30.15 + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS 30.16 + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 30.17 + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 30.18 + * 30.19 + * Carnegie Mellon requests users of this software to return to 30.20 + * 30.21 + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 30.22 + * School of Computer Science 30.23 + * Carnegie Mellon University 30.24 + * Pittsburgh PA 15213-3890 30.25 + * 30.26 + * any improvements or extensions that they make and grant Carnegie the 30.27 + * rights to redistribute these changes. 30.28 + */ 30.29 + 30.30 +#include <sys/cdefs.h> 30.31 +__FBSDID("$FreeBSD: src/sys/i386/i386/db_interface.c,v 1.77 2003/11/08 03:01:26 alc Exp $"); 30.32 + 30.33 +/* 30.34 + * Interface to new debugger. 30.35 + */ 30.36 +#include <sys/param.h> 30.37 +#include <sys/systm.h> 30.38 +#include <sys/reboot.h> 30.39 +#include <sys/cons.h> 30.40 +#include <sys/pcpu.h> 30.41 +#include <sys/proc.h> 30.42 +#include <sys/smp.h> 30.43 + 30.44 +#include <machine/cpu.h> 30.45 +#ifdef SMP 30.46 +#include <machine/smptests.h> /** CPUSTOP_ON_DDBBREAK */ 30.47 +#endif 30.48 + 30.49 +#include <vm/vm.h> 30.50 +#include <vm/pmap.h> 30.51 + 30.52 +#include <ddb/ddb.h> 30.53 + 30.54 +#include <machine/setjmp.h> 30.55 +#include <machine/xenfunc.h> 30.56 + 30.57 + 30.58 +static jmp_buf *db_nofault = 0; 30.59 +extern jmp_buf db_jmpbuf; 30.60 + 30.61 +extern void gdb_handle_exception(db_regs_t *, int, int); 30.62 + 30.63 +int db_active; 30.64 +db_regs_t ddb_regs; 30.65 + 30.66 +static __inline u_short 30.67 +rss(void) 30.68 +{ 30.69 + u_short ss; 30.70 +#ifdef __GNUC__ 30.71 + __asm __volatile("mov %%ss,%0" : "=r" (ss)); 30.72 +#else 30.73 + ss = 0; /* XXXX Fix for other compilers. */ 30.74 +#endif 30.75 + return ss; 30.76 +} 30.77 + 30.78 +/* 30.79 + * kdb_trap - field a TRACE or BPT trap 30.80 + */ 30.81 +int 30.82 +kdb_trap(int type, int code, struct i386_saved_state *regs) 30.83 +{ 30.84 + volatile int ddb_mode = !(boothowto & RB_GDB); 30.85 + 30.86 + disable_intr(); 30.87 + 30.88 + if (ddb_mode) { 30.89 + /* we can't do much as a guest domain except print a 30.90 + * backtrace and die gracefuly. The reason is that we 30.91 + * can't get character input to make this work. 30.92 + */ 30.93 + db_active = 1; 30.94 + db_print_backtrace(); 30.95 + db_printf("************ Domain shutting down ************\n"); 30.96 + HYPERVISOR_shutdown(); 30.97 + } else { 30.98 + Debugger("kdb_trap"); 30.99 + } 30.100 + return (1); 30.101 +} 30.102 + 30.103 +/* 30.104 + * Read bytes from kernel address space for debugger. 30.105 + */ 30.106 +void 30.107 +db_read_bytes(vm_offset_t addr, size_t size, char *data) 30.108 +{ 30.109 + char *src; 30.110 + 30.111 + db_nofault = &db_jmpbuf; 30.112 + 30.113 + src = (char *)addr; 30.114 + while (size-- > 0) 30.115 + *data++ = *src++; 30.116 + 30.117 + db_nofault = 0; 30.118 +} 30.119 + 30.120 +/* 30.121 + * Write bytes to kernel address space for debugger. 30.122 + */ 30.123 +void 30.124 +db_write_bytes(vm_offset_t addr, size_t size, char *data) 30.125 +{ 30.126 + char *dst; 30.127 + 30.128 + pt_entry_t *ptep0 = NULL; 30.129 + pt_entry_t oldmap0 = 0; 30.130 + vm_offset_t addr1; 30.131 + pt_entry_t *ptep1 = NULL; 30.132 + pt_entry_t oldmap1 = 0; 30.133 + 30.134 + db_nofault = &db_jmpbuf; 30.135 + 30.136 + if (addr > trunc_page((vm_offset_t)btext) - size && 30.137 + addr < round_page((vm_offset_t)etext)) { 30.138 + 30.139 + ptep0 = pmap_pte(kernel_pmap, addr); 30.140 + oldmap0 = *ptep0; 30.141 + *ptep0 |= PG_RW; 30.142 + 30.143 + /* Map another page if the data crosses a page boundary. */ 30.144 + if ((*ptep0 & PG_PS) == 0) { 30.145 + addr1 = trunc_page(addr + size - 1); 30.146 + if (trunc_page(addr) != addr1) { 30.147 + ptep1 = pmap_pte(kernel_pmap, addr1); 30.148 + oldmap1 = *ptep1; 30.149 + *ptep1 |= PG_RW; 30.150 + } 30.151 + } else { 30.152 + addr1 = trunc_4mpage(addr + size - 1); 30.153 + if (trunc_4mpage(addr) != addr1) { 30.154 + ptep1 = pmap_pte(kernel_pmap, addr1); 30.155 + oldmap1 = *ptep1; 30.156 + *ptep1 |= PG_RW; 30.157 + } 30.158 + } 30.159 + 30.160 + invltlb(); 30.161 + } 30.162 + 30.163 + dst = (char *)addr; 30.164 + 30.165 + while (size-- > 0) 30.166 + *dst++ = *data++; 30.167 + 30.168 + db_nofault = 0; 30.169 + 30.170 + if (ptep0) { 30.171 + *ptep0 = oldmap0; 30.172 + 30.173 + if (ptep1) 30.174 + *ptep1 = oldmap1; 30.175 + 30.176 + invltlb(); 30.177 + } 30.178 +} 30.179 + 30.180 +/* 30.181 + * XXX 30.182 + * Move this to machdep.c and allow it to be called if any debugger is 30.183 + * installed. 30.184 + */ 30.185 +void 30.186 +Debugger(const char *msg) 30.187 +{ 30.188 + static volatile u_int in_Debugger; 30.189 + 30.190 + /* 30.191 + * XXX 30.192 + * Do nothing if the console is in graphics mode. This is 30.193 + * OK if the call is for the debugger hotkey but not if the call 30.194 + * is a weak form of panicing. 30.195 + */ 30.196 + if (cons_unavail && !(boothowto & RB_GDB)) 30.197 + return; 30.198 + 30.199 + if (atomic_cmpset_acq_int(&in_Debugger, 0, 1)) { 30.200 + db_printf("Debugger(\"%s\")\n", msg); 30.201 + breakpoint(); 30.202 + atomic_store_rel_int(&in_Debugger, 0); 30.203 + } 30.204 +} 30.205 + 30.206 +void 30.207 +db_show_mdpcpu(struct pcpu *pc) 30.208 +{ 30.209 + 30.210 + db_printf("APIC ID = %d\n", pc->pc_apic_id); 30.211 + db_printf("currentldt = 0x%x\n", pc->pc_currentldt); 30.212 +}
31.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 31.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/evtchn.c Thu Mar 24 22:52:13 2005 +0000 31.3 @@ -0,0 +1,579 @@ 31.4 +/****************************************************************************** 31.5 + * evtchn.c 31.6 + * 31.7 + * Communication via Xen event channels. 31.8 + * 31.9 + * Copyright (c) 2002-2004, K A Fraser 31.10 + */ 31.11 +#include <sys/param.h> 31.12 +#include <sys/systm.h> 31.13 +#include <sys/bus.h> 31.14 +#include <sys/malloc.h> 31.15 +#include <sys/kernel.h> 31.16 +#include <sys/lock.h> 31.17 +#include <sys/mutex.h> 31.18 + 31.19 +#include <machine/cpufunc.h> 31.20 +#include <machine/intr_machdep.h> 31.21 +#include <machine/xen-os.h> 31.22 +#include <machine/xen_intr.h> 31.23 +#include <machine/synch_bitops.h> 31.24 +#include <machine/evtchn.h> 31.25 +#include <machine/hypervisor.h> 31.26 +#include <machine/hypervisor-ifs.h> 31.27 + 31.28 + 31.29 +static struct mtx irq_mapping_update_lock; 31.30 + 31.31 +#define TODO printf("%s: not implemented!\n", __func__) 31.32 + 31.33 +/* IRQ <-> event-channel mappings. */ 31.34 +static int evtchn_to_irq[NR_EVENT_CHANNELS]; 31.35 +static int irq_to_evtchn[NR_IRQS]; 31.36 + 31.37 +/* IRQ <-> VIRQ mapping. */ 31.38 +static int virq_to_irq[NR_VIRQS]; 31.39 + 31.40 +/* Reference counts for bindings to IRQs. */ 31.41 +static int irq_bindcount[NR_IRQS]; 31.42 + 31.43 +#define VALID_EVTCHN(_chn) ((_chn) != -1) 31.44 + 31.45 +/* 31.46 + * Force a proper event-channel callback from Xen after clearing the 31.47 + * callback mask. We do this in a very simple manner, by making a call 31.48 + * down into Xen. The pending flag will be checked by Xen on return. 31.49 + */ 31.50 +void force_evtchn_callback(void) 31.51 +{ 31.52 + (void)HYPERVISOR_xen_version(0); 31.53 +} 31.54 + 31.55 +void 31.56 +evtchn_do_upcall(struct intrframe *frame) 31.57 +{ 31.58 + unsigned long l1, l2; 31.59 + unsigned int l1i, l2i, port; 31.60 + int irq; 31.61 + unsigned long flags; 31.62 + shared_info_t *s = HYPERVISOR_shared_info; 31.63 + vcpu_info_t *vcpu_info = &s->vcpu_data[smp_processor_id()]; 31.64 + 31.65 + local_irq_save(flags); 31.66 + 31.67 + while ( s->vcpu_data[0].evtchn_upcall_pending ) 31.68 + { 31.69 + s->vcpu_data[0].evtchn_upcall_pending = 0; 31.70 + /* NB. No need for a barrier here -- XCHG is a barrier on x86. */ 31.71 + l1 = xen_xchg(&vcpu_info->evtchn_pending_sel, 0); 31.72 + while ( (l1i = ffs(l1)) != 0 ) 31.73 + { 31.74 + l1i--; 31.75 + l1 &= ~(1 << l1i); 31.76 + 31.77 + l2 = s->evtchn_pending[l1i] & ~s->evtchn_mask[l1i]; 31.78 + while ( (l2i = ffs(l2)) != 0 ) 31.79 + { 31.80 + l2i--; 31.81 + l2 &= ~(1 << l2i); 31.82 + 31.83 + port = (l1i << 5) + l2i; 31.84 + if ( (irq = evtchn_to_irq[port]) != -1 ) { 31.85 + struct intsrc *isrc = intr_lookup_source(irq); 31.86 + intr_execute_handlers(isrc, frame); 31.87 + } else { 31.88 + evtchn_device_upcall(port); 31.89 + } 31.90 + } 31.91 + } 31.92 + } 31.93 + 31.94 + local_irq_restore(flags); 31.95 + 31.96 +} 31.97 + 31.98 + 31.99 +static int 31.100 +find_unbound_irq(void) 31.101 +{ 31.102 + int irq; 31.103 + 31.104 + for ( irq = 0; irq < NR_IRQS; irq++ ) 31.105 + if ( irq_bindcount[irq] == 0 ) 31.106 + break; 31.107 + 31.108 + if ( irq == NR_IRQS ) 31.109 + panic("No available IRQ to bind to: increase NR_IRQS!\n"); 31.110 + 31.111 + return irq; 31.112 +} 31.113 + 31.114 +int 31.115 +bind_virq_to_irq(int virq) 31.116 +{ 31.117 + evtchn_op_t op; 31.118 + int evtchn, irq; 31.119 + 31.120 + mtx_lock(&irq_mapping_update_lock); 31.121 + 31.122 + if ( (irq = virq_to_irq[virq]) == -1 ) 31.123 + { 31.124 + op.cmd = EVTCHNOP_bind_virq; 31.125 + op.u.bind_virq.virq = virq; 31.126 + if ( HYPERVISOR_event_channel_op(&op) != 0 ) 31.127 + panic("Failed to bind virtual IRQ %d\n", virq); 31.128 + evtchn = op.u.bind_virq.port; 31.129 + 31.130 + irq = find_unbound_irq(); 31.131 + evtchn_to_irq[evtchn] = irq; 31.132 + irq_to_evtchn[irq] = evtchn; 31.133 + 31.134 + virq_to_irq[virq] = irq; 31.135 + } 31.136 + 31.137 + irq_bindcount[irq]++; 31.138 + 31.139 + mtx_unlock(&irq_mapping_update_lock); 31.140 + 31.141 + return irq; 31.142 +} 31.143 + 31.144 +void 31.145 +unbind_virq_from_irq(int virq) 31.146 +{ 31.147 + evtchn_op_t op; 31.148 + int irq = virq_to_irq[virq]; 31.149 + int evtchn = irq_to_evtchn[irq]; 31.150 + 31.151 + mtx_lock(&irq_mapping_update_lock); 31.152 + 31.153 + if ( --irq_bindcount[irq] == 0 ) 31.154 + { 31.155 + op.cmd = EVTCHNOP_close; 31.156 + op.u.close.dom = DOMID_SELF; 31.157 + op.u.close.port = evtchn; 31.158 + if ( HYPERVISOR_event_channel_op(&op) != 0 ) 31.159 + panic("Failed to unbind virtual IRQ %d\n", virq); 31.160 + 31.161 + evtchn_to_irq[evtchn] = -1; 31.162 + irq_to_evtchn[irq] = -1; 31.163 + virq_to_irq[virq] = -1; 31.164 + } 31.165 + 31.166 + mtx_unlock(&irq_mapping_update_lock); 31.167 +} 31.168 + 31.169 +int 31.170 +bind_evtchn_to_irq(int evtchn) 31.171 +{ 31.172 + int irq; 31.173 + 31.174 + mtx_lock(&irq_mapping_update_lock); 31.175 + 31.176 + if ( (irq = evtchn_to_irq[evtchn]) == -1 ) 31.177 + { 31.178 + irq = find_unbound_irq(); 31.179 + evtchn_to_irq[evtchn] = irq; 31.180 + irq_to_evtchn[irq] = evtchn; 31.181 + } 31.182 + 31.183 + irq_bindcount[irq]++; 31.184 + 31.185 + mtx_unlock(&irq_mapping_update_lock); 31.186 + 31.187 + return irq; 31.188 +} 31.189 + 31.190 +void 31.191 +unbind_evtchn_from_irq(int evtchn) 31.192 +{ 31.193 + int irq = evtchn_to_irq[evtchn]; 31.194 + 31.195 + mtx_lock(&irq_mapping_update_lock); 31.196 + 31.197 + if ( --irq_bindcount[irq] == 0 ) 31.198 + { 31.199 + evtchn_to_irq[evtchn] = -1; 31.200 + irq_to_evtchn[irq] = -1; 31.201 + } 31.202 + 31.203 + mtx_unlock(&irq_mapping_update_lock); 31.204 +} 31.205 + 31.206 + 31.207 +/* 31.208 + * Interface to generic handling in intr_machdep.c 31.209 + */ 31.210 + 31.211 + 31.212 +/*------------ interrupt handling --------------------------------------*/ 31.213 +#define TODO printf("%s: not implemented!\n", __func__) 31.214 + 31.215 + struct mtx xenpic_lock; 31.216 + 31.217 +struct xenpic_intsrc { 31.218 + struct intsrc xp_intsrc; 31.219 + uint8_t xp_vector; 31.220 + boolean_t xp_masked; 31.221 +}; 31.222 + 31.223 +struct xenpic { 31.224 + struct pic xp_pic; /* this MUST be first */ 31.225 + uint16_t xp_numintr; 31.226 + struct xenpic_intsrc xp_pins[0]; 31.227 +}; 31.228 + 31.229 +static void xenpic_enable_dynirq_source(struct intsrc *isrc); 31.230 +static void xenpic_disable_dynirq_source(struct intsrc *isrc, int); 31.231 +static void xenpic_eoi_source(struct intsrc *isrc); 31.232 +static void xenpic_enable_dynirq_intr(struct intsrc *isrc); 31.233 +static int xenpic_vector(struct intsrc *isrc); 31.234 +static int xenpic_source_pending(struct intsrc *isrc); 31.235 +static void xenpic_suspend(struct intsrc *isrc); 31.236 +static void xenpic_resume(struct intsrc *isrc); 31.237 + 31.238 + 31.239 +struct pic xenpic_template = { 31.240 + xenpic_enable_dynirq_source, 31.241 + xenpic_disable_dynirq_source, 31.242 + xenpic_eoi_source, 31.243 + xenpic_enable_dynirq_intr, 31.244 + xenpic_vector, 31.245 + xenpic_source_pending, 31.246 + xenpic_suspend, 31.247 + xenpic_resume 31.248 +}; 31.249 + 31.250 + 31.251 +void 31.252 +xenpic_enable_dynirq_source(struct intsrc *isrc) 31.253 +{ 31.254 + unsigned int irq; 31.255 + struct xenpic_intsrc *xp; 31.256 + 31.257 + xp = (struct xenpic_intsrc *)isrc; 31.258 + 31.259 + if (xp->xp_masked) { 31.260 + irq = xenpic_vector(isrc); 31.261 + unmask_evtchn(irq_to_evtchn[irq]); 31.262 + xp->xp_masked = FALSE; 31.263 + } 31.264 +} 31.265 + 31.266 +static void 31.267 +xenpic_disable_dynirq_source(struct intsrc *isrc, int foo) 31.268 +{ 31.269 + unsigned int irq; 31.270 + struct xenpic_intsrc *xp; 31.271 + 31.272 + xp = (struct xenpic_intsrc *)isrc; 31.273 + 31.274 + if (!xp->xp_masked) { 31.275 + irq = xenpic_vector(isrc); 31.276 + mask_evtchn(irq_to_evtchn[irq]); 31.277 + xp->xp_masked = TRUE; 31.278 + } 31.279 + 31.280 +} 31.281 + 31.282 +static void 31.283 +xenpic_enable_dynirq_intr(struct intsrc *isrc) 31.284 +{ 31.285 + unsigned int irq; 31.286 + 31.287 + irq = xenpic_vector(isrc); 31.288 + unmask_evtchn(irq_to_evtchn[irq]); 31.289 +} 31.290 + 31.291 +static void 31.292 +xenpic_eoi_source(struct intsrc *isrc) 31.293 +{ 31.294 + unsigned int irq = xenpic_vector(isrc); 31.295 + clear_evtchn(irq_to_evtchn[irq]); 31.296 +} 31.297 + 31.298 +static int 31.299 +xenpic_vector(struct intsrc *isrc) 31.300 +{ 31.301 + struct xenpic_intsrc *pin = (struct xenpic_intsrc *)isrc; 31.302 + return (pin->xp_vector); 31.303 +} 31.304 + 31.305 +static int 31.306 +xenpic_source_pending(struct intsrc *isrc) 31.307 +{ 31.308 + TODO; 31.309 + return 0; 31.310 +} 31.311 + 31.312 +static void 31.313 +xenpic_suspend(struct intsrc *isrc) 31.314 +{ 31.315 + TODO; 31.316 +} 31.317 + 31.318 +static void 31.319 +xenpic_resume(struct intsrc *isrc) 31.320 +{ 31.321 + TODO; 31.322 +} 31.323 + 31.324 +#ifdef CONFIG_PHYSDEV 31.325 +/* required for support of physical devices */ 31.326 +static inline void 31.327 +pirq_unmask_notify(int pirq) 31.328 +{ 31.329 + physdev_op_t op; 31.330 + if ( unlikely(test_bit(pirq, &pirq_needs_unmask_notify[0])) ) 31.331 + { 31.332 + op.cmd = PHYSDEVOP_IRQ_UNMASK_NOTIFY; 31.333 + (void)HYPERVISOR_physdev_op(&op); 31.334 + } 31.335 +} 31.336 + 31.337 +static inline void 31.338 +pirq_query_unmask(int pirq) 31.339 +{ 31.340 + physdev_op_t op; 31.341 + op.cmd = PHYSDEVOP_IRQ_STATUS_QUERY; 31.342 + op.u.irq_status_query.irq = pirq; 31.343 + (void)HYPERVISOR_physdev_op(&op); 31.344 + clear_bit(pirq, &pirq_needs_unmask_notify[0]); 31.345 + if ( op.u.irq_status_query.flags & PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY ) 31.346 + set_bit(pirq, &pirq_needs_unmask_notify[0]); 31.347 +} 31.348 + 31.349 +/* 31.350 + * On startup, if there is no action associated with the IRQ then we are 31.351 + * probing. In this case we should not share with others as it will confuse us. 31.352 + */ 31.353 +#define probing_irq(_irq) (irq_desc[(_irq)].action == NULL) 31.354 + 31.355 +static unsigned int startup_pirq(unsigned int irq) 31.356 +{ 31.357 + evtchn_op_t op; 31.358 + int evtchn; 31.359 + 31.360 + op.cmd = EVTCHNOP_bind_pirq; 31.361 + op.u.bind_pirq.pirq = irq; 31.362 + /* NB. We are happy to share unless we are probing. */ 31.363 + op.u.bind_pirq.flags = probing_irq(irq) ? 0 : BIND_PIRQ__WILL_SHARE; 31.364 + if ( HYPERVISOR_event_channel_op(&op) != 0 ) 31.365 + { 31.366 + if ( !probing_irq(irq) ) /* Some failures are expected when probing. */ 31.367 + printk(KERN_INFO "Failed to obtain physical IRQ %d\n", irq); 31.368 + return 0; 31.369 + } 31.370 + evtchn = op.u.bind_pirq.port; 31.371 + 31.372 + pirq_query_unmask(irq_to_pirq(irq)); 31.373 + 31.374 + evtchn_to_irq[evtchn] = irq; 31.375 + irq_to_evtchn[irq] = evtchn; 31.376 + 31.377 + unmask_evtchn(evtchn); 31.378 + pirq_unmask_notify(irq_to_pirq(irq)); 31.379 + 31.380 + return 0; 31.381 +} 31.382 + 31.383 +static void shutdown_pirq(unsigned int irq) 31.384 +{ 31.385 + evtchn_op_t op; 31.386 + int evtchn = irq_to_evtchn[irq]; 31.387 + 31.388 + if ( !VALID_EVTCHN(evtchn) ) 31.389 + return; 31.390 + 31.391 + mask_evtchn(evtchn); 31.392 + 31.393 + op.cmd = EVTCHNOP_close; 31.394 + op.u.close.dom = DOMID_SELF; 31.395 + op.u.close.port = evtchn; 31.396 + if ( HYPERVISOR_event_channel_op(&op) != 0 ) 31.397 + panic("Failed to unbind physical IRQ %d\n", irq); 31.398 + 31.399 + evtchn_to_irq[evtchn] = -1; 31.400 + irq_to_evtchn[irq] = -1; 31.401 +} 31.402 + 31.403 +static void enable_pirq(unsigned int irq) 31.404 +{ 31.405 + int evtchn = irq_to_evtchn[irq]; 31.406 + if ( !VALID_EVTCHN(evtchn) ) 31.407 + return; 31.408 + unmask_evtchn(evtchn); 31.409 + pirq_unmask_notify(irq_to_pirq(irq)); 31.410 +} 31.411 + 31.412 +static void disable_pirq(unsigned int irq) 31.413 +{ 31.414 + int evtchn = irq_to_evtchn[irq]; 31.415 + if ( !VALID_EVTCHN(evtchn) ) 31.416 + return; 31.417 + mask_evtchn(evtchn); 31.418 +} 31.419 + 31.420 +static void ack_pirq(unsigned int irq) 31.421 +{ 31.422 + int evtchn = irq_to_evtchn[irq]; 31.423 + if ( !VALID_EVTCHN(evtchn) ) 31.424 + return; 31.425 + mask_evtchn(evtchn); 31.426 + clear_evtchn(evtchn); 31.427 +} 31.428 + 31.429 +static void end_pirq(unsigned int irq) 31.430 +{ 31.431 + int evtchn = irq_to_evtchn[irq]; 31.432 + if ( !VALID_EVTCHN(evtchn) ) 31.433 + return; 31.434 + if ( !(irq_desc[irq].status & IRQ_DISABLED) ) 31.435 + { 31.436 + unmask_evtchn(evtchn); 31.437 + pirq_unmask_notify(irq_to_pirq(irq)); 31.438 + } 31.439 +} 31.440 + 31.441 +static struct hw_interrupt_type pirq_type = { 31.442 + "Phys-irq", 31.443 + startup_pirq, 31.444 + shutdown_pirq, 31.445 + enable_pirq, 31.446 + disable_pirq, 31.447 + ack_pirq, 31.448 + end_pirq, 31.449 + NULL 31.450 +}; 31.451 +#endif 31.452 + 31.453 +#if 0 31.454 +static void 31.455 +misdirect_interrupt(void *sc) 31.456 +{ 31.457 +} 31.458 +#endif 31.459 +void irq_suspend(void) 31.460 +{ 31.461 + int virq, irq, evtchn; 31.462 + 31.463 + /* Unbind VIRQs from event channels. */ 31.464 + for ( virq = 0; virq < NR_VIRQS; virq++ ) 31.465 + { 31.466 + if ( (irq = virq_to_irq[virq]) == -1 ) 31.467 + continue; 31.468 + evtchn = irq_to_evtchn[irq]; 31.469 + 31.470 + /* Mark the event channel as unused in our table. */ 31.471 + evtchn_to_irq[evtchn] = -1; 31.472 + irq_to_evtchn[irq] = -1; 31.473 + } 31.474 + 31.475 + /* 31.476 + * We should now be unbound from all event channels. Stale bindings to 31.477 + * PIRQs and/or inter-domain event channels will cause us to barf here. 31.478 + */ 31.479 + for ( evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++ ) 31.480 + if ( evtchn_to_irq[evtchn] != -1 ) 31.481 + panic("Suspend attempted while bound to evtchn %d.\n", evtchn); 31.482 +} 31.483 + 31.484 + 31.485 +void irq_resume(void) 31.486 +{ 31.487 + evtchn_op_t op; 31.488 + int virq, irq, evtchn; 31.489 + 31.490 + for ( evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++ ) 31.491 + mask_evtchn(evtchn); /* New event-channel space is not 'live' yet. */ 31.492 + 31.493 + for ( virq = 0; virq < NR_VIRQS; virq++ ) 31.494 + { 31.495 + if ( (irq = virq_to_irq[virq]) == -1 ) 31.496 + continue; 31.497 + 31.498 + /* Get a new binding from Xen. */ 31.499 + op.cmd = EVTCHNOP_bind_virq; 31.500 + op.u.bind_virq.virq = virq; 31.501 + if ( HYPERVISOR_event_channel_op(&op) != 0 ) 31.502 + panic("Failed to bind virtual IRQ %d\n", virq); 31.503 + evtchn = op.u.bind_virq.port; 31.504 + 31.505 + /* Record the new mapping. */ 31.506 + evtchn_to_irq[evtchn] = irq; 31.507 + irq_to_evtchn[irq] = evtchn; 31.508 + 31.509 + /* Ready for use. */ 31.510 + unmask_evtchn(evtchn); 31.511 + } 31.512 +} 31.513 + 31.514 +static void 31.515 +evtchn_init(void *dummy __unused) 31.516 +{ 31.517 + int i; 31.518 + struct xenpic *xp; 31.519 + struct xenpic_intsrc *pin; 31.520 + 31.521 + /* 31.522 + * xenpic_lock: in order to allow an interrupt to occur in a critical 31.523 + * section, to set pcpu->ipending (etc...) properly, we 31.524 + * must be able to get the icu lock, so it can't be 31.525 + * under witness. 31.526 + */ 31.527 + mtx_init(&irq_mapping_update_lock, "xp", NULL, MTX_DEF); 31.528 + 31.529 + /* No VIRQ -> IRQ mappings. */ 31.530 + for ( i = 0; i < NR_VIRQS; i++ ) 31.531 + virq_to_irq[i] = -1; 31.532 + 31.533 + /* No event-channel -> IRQ mappings. */ 31.534 + for ( i = 0; i < NR_EVENT_CHANNELS; i++ ) 31.535 + { 31.536 + evtchn_to_irq[i] = -1; 31.537 + mask_evtchn(i); /* No event channels are 'live' right now. */ 31.538 + } 31.539 + 31.540 + /* No IRQ -> event-channel mappings. */ 31.541 + for ( i = 0; i < NR_IRQS; i++ ) 31.542 + irq_to_evtchn[i] = -1; 31.543 + 31.544 + xp = malloc(sizeof(struct xenpic) + NR_DYNIRQS*sizeof(struct xenpic_intsrc), M_DEVBUF, M_WAITOK); 31.545 + xp->xp_pic = xenpic_template; 31.546 + xp->xp_numintr = NR_DYNIRQS; 31.547 + bzero(xp->xp_pins, sizeof(struct xenpic_intsrc) * NR_DYNIRQS); 31.548 + 31.549 + for ( i = 0, pin = xp->xp_pins; i < NR_DYNIRQS; i++, pin++ ) 31.550 + { 31.551 + /* Dynamic IRQ space is currently unbound. Zero the refcnts. */ 31.552 + irq_bindcount[dynirq_to_irq(i)] = 0; 31.553 + 31.554 + pin->xp_intsrc.is_pic = (struct pic *)xp; 31.555 + pin->xp_vector = i; 31.556 + intr_register_source(&pin->xp_intsrc); 31.557 + } 31.558 + /* We don't currently have any support for physical devices in XenoFreeBSD 31.559 + * so leaving this out for the moment for the sake of expediency. 31.560 + */ 31.561 +#ifdef notyet 31.562 + for ( i = 0; i < NR_PIRQS; i++ ) 31.563 + { 31.564 + /* Phys IRQ space is statically bound (1:1 mapping). Nail refcnts. */ 31.565 + irq_bindcount[pirq_to_irq(i)] = 1; 31.566 + 31.567 + irq_desc[pirq_to_irq(i)].status = IRQ_DISABLED; 31.568 + irq_desc[pirq_to_irq(i)].action = 0; 31.569 + irq_desc[pirq_to_irq(i)].depth = 1; 31.570 + irq_desc[pirq_to_irq(i)].handler = &pirq_type; 31.571 + } 31.572 + 31.573 +#endif 31.574 +#if 0 31.575 + (void) intr_add_handler("xb_mis", bind_virq_to_irq(VIRQ_MISDIRECT), 31.576 + (driver_intr_t *)misdirect_interrupt, 31.577 + NULL, INTR_TYPE_MISC, NULL); 31.578 + 31.579 +#endif 31.580 +} 31.581 + 31.582 +SYSINIT(evtchn_init, SI_SUB_INTR, SI_ORDER_ANY, evtchn_init, NULL);
32.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 32.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/exception.s Thu Mar 24 22:52:13 2005 +0000 32.3 @@ -0,0 +1,428 @@ 32.4 +/*- 32.5 + * Copyright (c) 1989, 1990 William F. Jolitz. 32.6 + * Copyright (c) 1990 The Regents of the University of California. 32.7 + * All rights reserved. 32.8 + * 32.9 + * Redistribution and use in source and binary forms, with or without 32.10 + * modification, are permitted provided that the following conditions 32.11 + * are met: 32.12 + * 1. Redistributions of source code must retain the above copyright 32.13 + * notice, this list of conditions and the following disclaimer. 32.14 + * 2. Redistributions in binary form must reproduce the above copyright 32.15 + * notice, this list of conditions and the following disclaimer in the 32.16 + * documentation and/or other materials provided with the distribution. 32.17 + * 4. Neither the name of the University nor the names of its contributors 32.18 + * may be used to endorse or promote products derived from this software 32.19 + * without specific prior written permission. 32.20 + * 32.21 + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32.22 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32.23 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32.24 + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32.25 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32.26 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32.27 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32.28 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32.29 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32.30 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32.31 + * SUCH DAMAGE. 32.32 + * 32.33 + * $FreeBSD: src/sys/i386/i386/exception.s,v 1.106 2003/11/03 22:08:52 jhb Exp $ 32.34 + */ 32.35 + 32.36 +#include "opt_npx.h" 32.37 + 32.38 +#include <machine/asmacros.h> 32.39 +#include <machine/psl.h> 32.40 +#include <machine/trap.h> 32.41 + 32.42 +#include "assym.s" 32.43 + 32.44 +#define SEL_RPL_MASK 0x0002 32.45 +/* Offsets into shared_info_t. */ 32.46 +#define evtchn_upcall_pending /* 0 */ 32.47 +#define evtchn_upcall_mask 1 32.48 +#define XEN_BLOCK_EVENTS(reg) movb $1,evtchn_upcall_mask(reg) 32.49 +#define XEN_UNBLOCK_EVENTS(reg) movb $0,evtchn_upcall_mask(reg) 32.50 +#define XEN_TEST_PENDING(reg) testb $0x1,evtchn_upcall_pending(reg) 32.51 + 32.52 + 32.53 +#define POPA \ 32.54 + popl %edi; \ 32.55 + popl %esi; \ 32.56 + popl %ebp; \ 32.57 + popl %ebx; \ 32.58 + popl %ebx; \ 32.59 + popl %edx; \ 32.60 + popl %ecx; \ 32.61 + popl %eax; 32.62 + 32.63 + .text 32.64 + 32.65 +/*****************************************************************************/ 32.66 +/* Trap handling */ 32.67 +/*****************************************************************************/ 32.68 +/* 32.69 + * Trap and fault vector routines. 32.70 + * 32.71 + * Most traps are 'trap gates', SDT_SYS386TGT. A trap gate pushes state on 32.72 + * the stack that mostly looks like an interrupt, but does not disable 32.73 + * interrupts. A few of the traps we are use are interrupt gates, 32.74 + * SDT_SYS386IGT, which are nearly the same thing except interrupts are 32.75 + * disabled on entry. 32.76 + * 32.77 + * The cpu will push a certain amount of state onto the kernel stack for 32.78 + * the current process. The amount of state depends on the type of trap 32.79 + * and whether the trap crossed rings or not. See i386/include/frame.h. 32.80 + * At the very least the current EFLAGS (status register, which includes 32.81 + * the interrupt disable state prior to the trap), the code segment register, 32.82 + * and the return instruction pointer are pushed by the cpu. The cpu 32.83 + * will also push an 'error' code for certain traps. We push a dummy 32.84 + * error code for those traps where the cpu doesn't in order to maintain 32.85 + * a consistent frame. We also push a contrived 'trap number'. 32.86 + * 32.87 + * The cpu does not push the general registers, we must do that, and we 32.88 + * must restore them prior to calling 'iret'. The cpu adjusts the %cs and 32.89 + * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we 32.90 + * must load them with appropriate values for supervisor mode operation. 32.91 + */ 32.92 + 32.93 +MCOUNT_LABEL(user) 32.94 +MCOUNT_LABEL(btrap) 32.95 + 32.96 +IDTVEC(div) 32.97 + pushl $0; pushl $0; TRAP(T_DIVIDE) 32.98 +IDTVEC(dbg) 32.99 + pushl $0; pushl $0; TRAP(T_TRCTRAP) 32.100 +IDTVEC(nmi) 32.101 + pushl $0; pushl $0; TRAP(T_NMI) 32.102 +IDTVEC(bpt) 32.103 + pushl $0; pushl $0; TRAP(T_BPTFLT) 32.104 +IDTVEC(ofl) 32.105 + pushl $0; pushl $0; TRAP(T_OFLOW) 32.106 +IDTVEC(bnd) 32.107 + pushl $0; pushl $0; TRAP(T_BOUND) 32.108 +IDTVEC(ill) 32.109 + pushl $0; pushl $0; TRAP(T_PRIVINFLT) 32.110 +IDTVEC(dna) 32.111 + pushl $0; pushl $0; TRAP(T_DNA) 32.112 +IDTVEC(fpusegm) 32.113 + pushl $0; pushl $0; TRAP(T_FPOPFLT) 32.114 +IDTVEC(tss) 32.115 + pushl $0; TRAP(T_TSSFLT) 32.116 +IDTVEC(missing) 32.117 + pushl $0; TRAP(T_SEGNPFLT) 32.118 +IDTVEC(stk) 32.119 + pushl $0; TRAP(T_STKFLT) 32.120 +IDTVEC(prot) 32.121 + pushl $0; TRAP(T_PROTFLT) 32.122 +IDTVEC(page) 32.123 + TRAP(T_PAGEFLT) 32.124 +IDTVEC(mchk) 32.125 + pushl $0; pushl $0; TRAP(T_MCHK) 32.126 +IDTVEC(rsvd) 32.127 + pushl $0; pushl $0; TRAP(T_RESERVED) 32.128 +IDTVEC(fpu) 32.129 + pushl $0; pushl $0; TRAP(T_ARITHTRAP) 32.130 +IDTVEC(align) 32.131 + pushl $0; TRAP(T_ALIGNFLT) 32.132 + 32.133 +IDTVEC(xmm) 32.134 + pushl $0; pushl $0; TRAP(T_XMMFLT) 32.135 + 32.136 +IDTVEC(hypervisor_callback) 32.137 + pushl $T_HYPCALLBACK; pushl %eax; TRAP(T_HYPCALLBACK) 32.138 + 32.139 +hypervisor_callback_pending: 32.140 + movl $T_HYPCALLBACK,TF_TRAPNO(%esp) 32.141 + movl $T_HYPCALLBACK,TF_ERR(%esp) 32.142 + jmp 11f 32.143 + 32.144 + /* 32.145 + * alltraps entry point. Interrupts are enabled if this was a trap 32.146 + * gate (TGT), else disabled if this was an interrupt gate (IGT). 32.147 + * Note that int0x80_syscall is a trap gate. Only page faults 32.148 + * use an interrupt gate. 32.149 + */ 32.150 + 32.151 + SUPERALIGN_TEXT 32.152 + .globl alltraps 32.153 + .type alltraps,@function 32.154 +alltraps: 32.155 + cld 32.156 + pushal 32.157 + pushl %ds 32.158 + pushl %es 32.159 + pushl %fs 32.160 +alltraps_with_regs_pushed: 32.161 + movl $KDSEL,%eax 32.162 + movl %eax,%ds 32.163 + movl %eax,%es 32.164 + movl $KPSEL,%eax 32.165 + movl %eax,%fs 32.166 + FAKE_MCOUNT(TF_EIP(%esp)) 32.167 +calltrap: 32.168 + movl TF_EIP(%esp),%eax 32.169 + cmpl $scrit,%eax 32.170 + jb 11f 32.171 + cmpl $ecrit,%eax 32.172 + jb critical_region_fixup 32.173 +11: call trap 32.174 + 32.175 + /* 32.176 + * Return via doreti to handle ASTs. 32.177 + */ 32.178 + MEXITCOUNT 32.179 + jmp doreti 32.180 + 32.181 +/* 32.182 + * SYSCALL CALL GATE (old entry point for a.out binaries) 32.183 + * 32.184 + * The intersegment call has been set up to specify one dummy parameter. 32.185 + * 32.186 + * This leaves a place to put eflags so that the call frame can be 32.187 + * converted to a trap frame. Note that the eflags is (semi-)bogusly 32.188 + * pushed into (what will be) tf_err and then copied later into the 32.189 + * final spot. It has to be done this way because esp can't be just 32.190 + * temporarily altered for the pushfl - an interrupt might come in 32.191 + * and clobber the saved cs/eip. 32.192 + */ 32.193 + SUPERALIGN_TEXT 32.194 +IDTVEC(lcall_syscall) 32.195 + pushfl /* save eflags */ 32.196 + popl 8(%esp) /* shuffle into tf_eflags */ 32.197 + pushl $7 /* sizeof "lcall 7,0" */ 32.198 + subl $4,%esp /* skip over tf_trapno */ 32.199 + pushal 32.200 + pushl %ds 32.201 + pushl %es 32.202 + pushl %fs 32.203 + movl $KDSEL,%eax /* switch to kernel segments */ 32.204 + movl %eax,%ds 32.205 + movl %eax,%es 32.206 + movl $KPSEL,%eax 32.207 + movl %eax,%fs 32.208 + FAKE_MCOUNT(TF_EIP(%esp)) 32.209 + call syscall 32.210 + MEXITCOUNT 32.211 + jmp doreti 32.212 + 32.213 +/* 32.214 + * Call gate entry for FreeBSD ELF and Linux/NetBSD syscall (int 0x80) 32.215 + * 32.216 + * Even though the name says 'int0x80', this is actually a TGT (trap gate) 32.217 + * rather then an IGT (interrupt gate). Thus interrupts are enabled on 32.218 + * entry just as they are for a normal syscall. 32.219 + */ 32.220 + SUPERALIGN_TEXT 32.221 +IDTVEC(int0x80_syscall) 32.222 + pushl $2 /* sizeof "int 0x80" */ 32.223 + pushl $0xCAFE 32.224 + pushl $0xDEAD 32.225 + pushal 32.226 + pushl %ds 32.227 + pushl %es 32.228 + pushl %fs 32.229 + movl $KDSEL,%eax /* switch to kernel segments */ 32.230 + movl %eax,%ds 32.231 + movl %eax,%es 32.232 + movl $KPSEL,%eax 32.233 + movl %eax,%fs 32.234 + FAKE_MCOUNT(TF_EIP(%esp)) 32.235 + call syscall 32.236 + MEXITCOUNT 32.237 + jmp doreti 32.238 + 32.239 +ENTRY(fork_trampoline) 32.240 + pushl %esp /* trapframe pointer */ 32.241 + pushl %ebx /* arg1 */ 32.242 + pushl %esi /* function */ 32.243 + call fork_exit 32.244 + addl $12,%esp 32.245 + /* cut from syscall */ 32.246 + 32.247 + /* 32.248 + * Return via doreti to handle ASTs. 32.249 + */ 32.250 + MEXITCOUNT 32.251 + jmp doreti 32.252 + 32.253 + 32.254 +/* 32.255 +# A note on the "critical region" in our callback handler. 32.256 +# We want to avoid stacking callback handlers due to events occurring 32.257 +# during handling of the last event. To do this, we keep events disabled 32.258 +# until weve done all processing. HOWEVER, we must enable events before 32.259 +# popping the stack frame (cant be done atomically) and so it would still 32.260 +# be possible to get enough handler activations to overflow the stack. 32.261 +# Although unlikely, bugs of that kind are hard to track down, so wed 32.262 +# like to avoid the possibility. 32.263 +# So, on entry to the handler we detect whether we interrupted an 32.264 +# existing activation in its critical region -- if so, we pop the current 32.265 +# activation and restart the handler using the previous one. 32.266 +*/ 32.267 + 32.268 + 32.269 +/* 32.270 + * void doreti(struct trapframe) 32.271 + * 32.272 + * Handle return from interrupts, traps and syscalls. 32.273 + */ 32.274 + .text 32.275 + SUPERALIGN_TEXT 32.276 + .globl doreti 32.277 + .type doreti,@function 32.278 +doreti: 32.279 + FAKE_MCOUNT(bintr) /* init "from" bintr -> doreti */ 32.280 +doreti_next: 32.281 + testb $SEL_RPL_MASK,TF_CS(%esp) /* are we returning to user mode? */ 32.282 + jz doreti_exit /* #can't handle ASTs now if not */ 32.283 + 32.284 +doreti_ast: 32.285 + /* 32.286 + * Check for ASTs atomically with returning. Disabling CPU 32.287 + * interrupts provides sufficient locking even in the SMP case, 32.288 + * since we will be informed of any new ASTs by an IPI. 32.289 + */ 32.290 + 32.291 + movl HYPERVISOR_shared_info,%esi 32.292 + XEN_BLOCK_EVENTS(%esi) 32.293 + movl PCPU(CURTHREAD),%eax 32.294 + testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%eax) 32.295 + je doreti_exit 32.296 + XEN_UNBLOCK_EVENTS(%esi) 32.297 + pushl %esp /* pass a pointer to the trapframe */ 32.298 + call ast 32.299 + add $4,%esp 32.300 + jmp doreti_ast 32.301 + 32.302 +doreti_exit: 32.303 + /* 32.304 + * doreti_exit: pop registers, iret. 32.305 + * 32.306 + * The segment register pop is a special case, since it may 32.307 + * fault if (for example) a sigreturn specifies bad segment 32.308 + * registers. The fault is handled in trap.c. 32.309 + */ 32.310 + 32.311 + movl HYPERVISOR_shared_info,%esi 32.312 + XEN_UNBLOCK_EVENTS(%esi) # reenable event callbacks (sti) 32.313 + 32.314 + .globl scrit 32.315 +scrit: 32.316 + XEN_TEST_PENDING(%esi) 32.317 + jnz hypervisor_callback_pending /* More to go */ 32.318 + MEXITCOUNT 32.319 + 32.320 + .globl doreti_popl_fs 32.321 +doreti_popl_fs: 32.322 + popl %fs 32.323 + .globl doreti_popl_es 32.324 +doreti_popl_es: 32.325 + popl %es 32.326 + .globl doreti_popl_ds 32.327 +doreti_popl_ds: 32.328 + popl %ds 32.329 + POPA 32.330 + addl $12,%esp 32.331 + .globl doreti_iret 32.332 +doreti_iret: 32.333 + iret 32.334 + .globl ecrit 32.335 +ecrit: 32.336 + 32.337 + /* 32.338 + * doreti_iret_fault and friends. Alternative return code for 32.339 + * the case where we get a fault in the doreti_exit code 32.340 + * above. trap() (i386/i386/trap.c) catches this specific 32.341 + * case, sends the process a signal and continues in the 32.342 + * corresponding place in the code below. 32.343 + */ 32.344 + ALIGN_TEXT 32.345 + .globl doreti_iret_fault 32.346 +doreti_iret_fault: 32.347 + subl $12,%esp 32.348 + pushal 32.349 + pushl %ds 32.350 + .globl doreti_popl_ds_fault 32.351 +doreti_popl_ds_fault: 32.352 + pushl %es 32.353 + .globl doreti_popl_es_fault 32.354 +doreti_popl_es_fault: 32.355 + pushl %fs 32.356 + .globl doreti_popl_fs_fault 32.357 +doreti_popl_fs_fault: 32.358 + movl $0,TF_ERR(%esp) /* XXX should be the error code */ 32.359 + movl $T_PROTFLT,TF_TRAPNO(%esp) 32.360 + jmp alltraps_with_regs_pushed 32.361 + 32.362 + 32.363 + 32.364 + 32.365 +/* 32.366 +# [How we do the fixup]. We want to merge the current stack frame with the 32.367 +# just-interrupted frame. How we do this depends on where in the critical 32.368 +# region the interrupted handler was executing, and so how many saved 32.369 +# registers are in each frame. We do this quickly using the lookup table 32.370 +# 'critical_fixup_table'. For each byte offset in the critical region, it 32.371 +# provides the number of bytes which have already been popped from the 32.372 +# interrupted stack frame. 32.373 +*/ 32.374 + 32.375 +.globl critical_region_fixup 32.376 +critical_region_fixup: 32.377 + addl $critical_fixup_table-scrit,%eax 32.378 + movzbl (%eax),%eax # %eax contains num bytes popped 32.379 + movl %esp,%esi 32.380 + add %eax,%esi # %esi points at end of src region 32.381 + movl %esp,%edi 32.382 + add $0x44,%edi # %edi points at end of dst region 32.383 + movl %eax,%ecx 32.384 + shr $2,%ecx # convert bytes to words 32.385 + je 16f # skip loop if nothing to copy 32.386 +15: subl $4,%esi # pre-decrementing copy loop 32.387 + subl $4,%edi 32.388 + movl (%esi),%eax 32.389 + movl %eax,(%edi) 32.390 + loop 15b 32.391 +16: movl %edi,%esp # final %edi is top of merged stack 32.392 + jmp hypervisor_callback_pending 32.393 + 32.394 + 32.395 +critical_fixup_table: 32.396 +.byte 0x0,0x0,0x0 #testb $0x1,(%esi) 32.397 +.byte 0x0,0x0,0x0,0x0,0x0,0x0 #jne ea 32.398 +.byte 0x0,0x0 #pop %fs 32.399 +.byte 0x04 #pop %es 32.400 +.byte 0x08 #pop %ds 32.401 +.byte 0x0c #pop %edi 32.402 +.byte 0x10 #pop %esi 32.403 +.byte 0x14 #pop %ebp 32.404 +.byte 0x18 #pop %ebx 32.405 +.byte 0x1c #pop %ebx 32.406 +.byte 0x20 #pop %edx 32.407 +.byte 0x24 #pop %ecx 32.408 +.byte 0x28 #pop %eax 32.409 +.byte 0x2c,0x2c,0x2c #add $0xc,%esp 32.410 +.byte 0x38 #iret 32.411 + 32.412 + 32.413 +/* # Hypervisor uses this for application faults while it executes.*/ 32.414 +ENTRY(failsafe_callback) 32.415 + pushal 32.416 + call xen_failsafe_handler 32.417 +/*# call install_safe_pf_handler */ 32.418 + movl 32(%esp),%ebx 32.419 +1: movl %ebx,%ds 32.420 + movl 36(%esp),%ebx 32.421 +2: movl %ebx,%es 32.422 + movl 40(%esp),%ebx 32.423 +3: movl %ebx,%fs 32.424 + movl 44(%esp),%ebx 32.425 +4: movl %ebx,%gs 32.426 +/*# call install_normal_pf_handler */ 32.427 + popal 32.428 + addl $16,%esp 32.429 + iret 32.430 + 32.431 +
33.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 33.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/genassym.c Thu Mar 24 22:52:13 2005 +0000 33.3 @@ -0,0 +1,234 @@ 33.4 +/*- 33.5 + * Copyright (c) 1982, 1990 The Regents of the University of California. 33.6 + * All rights reserved. 33.7 + * 33.8 + * This code is derived from software contributed to Berkeley by 33.9 + * William Jolitz. 33.10 + * 33.11 + * Redistribution and use in source and binary forms, with or without 33.12 + * modification, are permitted provided that the following conditions 33.13 + * are met: 33.14 + * 1. Redistributions of source code must retain the above copyright 33.15 + * notice, this list of conditions and the following disclaimer. 33.16 + * 2. Redistributions in binary form must reproduce the above copyright 33.17 + * notice, this list of conditions and the following disclaimer in the 33.18 + * documentation and/or other materials provided with the distribution. 33.19 + * 3. All advertising materials mentioning features or use of this software 33.20 + * must display the following acknowledgement: 33.21 + * This product includes software developed by the University of 33.22 + * California, Berkeley and its contributors. 33.23 + * 4. Neither the name of the University nor the names of its contributors 33.24 + * may be used to endorse or promote products derived from this software 33.25 + * without specific prior written permission. 33.26 + * 33.27 + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33.28 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33.29 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33.30 + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33.31 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33.32 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33.33 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33.34 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33.35 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33.36 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33.37 + * SUCH DAMAGE. 33.38 + * 33.39 + * from: @(#)genassym.c 5.11 (Berkeley) 5/10/91 33.40 + */ 33.41 + 33.42 +#include <sys/cdefs.h> 33.43 +__FBSDID("$FreeBSD: src/sys/i386/i386/genassym.c,v 1.146 2003/11/12 18:14:34 jhb Exp $"); 33.44 + 33.45 +#include "opt_apic.h" 33.46 +#include "opt_compat.h" 33.47 +#include "opt_kstack_pages.h" 33.48 + 33.49 +#include <sys/param.h> 33.50 +#include <sys/systm.h> 33.51 +#include <sys/assym.h> 33.52 +#include <sys/bio.h> 33.53 +#include <sys/buf.h> 33.54 +#include <sys/proc.h> 33.55 +#include <sys/errno.h> 33.56 +#include <sys/mount.h> 33.57 +#include <sys/mutex.h> 33.58 +#include <sys/socket.h> 33.59 +#include <sys/resourcevar.h> 33.60 +#include <sys/ucontext.h> 33.61 +#include <sys/user.h> 33.62 +#include <machine/bootinfo.h> 33.63 +#include <machine/tss.h> 33.64 +#include <sys/vmmeter.h> 33.65 +#include <vm/vm.h> 33.66 +#include <vm/vm_param.h> 33.67 +#include <vm/pmap.h> 33.68 +#include <vm/vm_map.h> 33.69 +#include <sys/user.h> 33.70 +#include <sys/proc.h> 33.71 +#include <net/if.h> 33.72 +#include <netinet/in.h> 33.73 +#include <nfs/nfsproto.h> 33.74 +#include <nfs/rpcv2.h> 33.75 +#include <nfsclient/nfs.h> 33.76 +#include <nfsclient/nfsdiskless.h> 33.77 +#ifdef DEV_APIC 33.78 +#include <machine/apicreg.h> 33.79 +#endif 33.80 +#include <machine/cpu.h> 33.81 +#include <machine/sigframe.h> 33.82 +#include <machine/proc.h> 33.83 + 33.84 +ASSYM(P_VMSPACE, offsetof(struct proc, p_vmspace)); 33.85 +ASSYM(VM_PMAP, offsetof(struct vmspace, vm_pmap)); 33.86 +ASSYM(PM_ACTIVE, offsetof(struct pmap, pm_active)); 33.87 +ASSYM(P_SFLAG, offsetof(struct proc, p_sflag)); 33.88 +ASSYM(P_UAREA, offsetof(struct proc, p_uarea)); 33.89 + 33.90 +ASSYM(TD_FLAGS, offsetof(struct thread, td_flags)); 33.91 +ASSYM(TD_PCB, offsetof(struct thread, td_pcb)); 33.92 +ASSYM(TD_PROC, offsetof(struct thread, td_proc)); 33.93 +ASSYM(TD_MD, offsetof(struct thread, td_md)); 33.94 + 33.95 +ASSYM(P_MD, offsetof(struct proc, p_md)); 33.96 +ASSYM(MD_LDT, offsetof(struct mdproc, md_ldt)); 33.97 + 33.98 +ASSYM(TDF_ASTPENDING, TDF_ASTPENDING); 33.99 +ASSYM(TDF_NEEDRESCHED, TDF_NEEDRESCHED); 33.100 + 33.101 +ASSYM(V_TRAP, offsetof(struct vmmeter, v_trap)); 33.102 +ASSYM(V_SYSCALL, offsetof(struct vmmeter, v_syscall)); 33.103 +ASSYM(V_INTR, offsetof(struct vmmeter, v_intr)); 33.104 +/* ASSYM(UPAGES, UPAGES);*/ 33.105 +ASSYM(UAREA_PAGES, UAREA_PAGES); 33.106 +ASSYM(KSTACK_PAGES, KSTACK_PAGES); 33.107 +ASSYM(PAGE_SIZE, PAGE_SIZE); 33.108 +ASSYM(NPTEPG, NPTEPG); 33.109 +ASSYM(NPDEPG, NPDEPG); 33.110 +ASSYM(NPDEPTD, NPDEPTD); 33.111 +ASSYM(NPGPTD, NPGPTD); 33.112 +ASSYM(PDESIZE, sizeof(pd_entry_t)); 33.113 +ASSYM(PTESIZE, sizeof(pt_entry_t)); 33.114 +ASSYM(PDESHIFT, PDESHIFT); 33.115 +ASSYM(PTESHIFT, PTESHIFT); 33.116 +ASSYM(PAGE_SHIFT, PAGE_SHIFT); 33.117 +ASSYM(PAGE_MASK, PAGE_MASK); 33.118 +ASSYM(PDRSHIFT, PDRSHIFT); 33.119 +ASSYM(PDRMASK, PDRMASK); 33.120 +ASSYM(USRSTACK, USRSTACK); 33.121 +ASSYM(VM_MAXUSER_ADDRESS, VM_MAXUSER_ADDRESS); 33.122 +ASSYM(KERNBASE, KERNBASE); 33.123 +ASSYM(KERNLOAD, KERNLOAD); 33.124 +ASSYM(MCLBYTES, MCLBYTES); 33.125 +ASSYM(PCB_CR3, offsetof(struct pcb, pcb_cr3)); 33.126 +ASSYM(PCB_EDI, offsetof(struct pcb, pcb_edi)); 33.127 +ASSYM(PCB_ESI, offsetof(struct pcb, pcb_esi)); 33.128 +ASSYM(PCB_EBP, offsetof(struct pcb, pcb_ebp)); 33.129 +ASSYM(PCB_ESP, offsetof(struct pcb, pcb_esp)); 33.130 +ASSYM(PCB_EBX, offsetof(struct pcb, pcb_ebx)); 33.131 +ASSYM(PCB_EIP, offsetof(struct pcb, pcb_eip)); 33.132 +ASSYM(TSS_ESP0, offsetof(struct i386tss, tss_esp0)); 33.133 + 33.134 +ASSYM(PCB_GS, offsetof(struct pcb, pcb_gs)); 33.135 +ASSYM(PCB_DR0, offsetof(struct pcb, pcb_dr0)); 33.136 +ASSYM(PCB_DR1, offsetof(struct pcb, pcb_dr1)); 33.137 +ASSYM(PCB_DR2, offsetof(struct pcb, pcb_dr2)); 33.138 +ASSYM(PCB_DR3, offsetof(struct pcb, pcb_dr3)); 33.139 +ASSYM(PCB_DR6, offsetof(struct pcb, pcb_dr6)); 33.140 +ASSYM(PCB_DR7, offsetof(struct pcb, pcb_dr7)); 33.141 +ASSYM(PCB_PSL, offsetof(struct pcb, pcb_psl)); 33.142 +ASSYM(PCB_DBREGS, PCB_DBREGS); 33.143 +ASSYM(PCB_EXT, offsetof(struct pcb, pcb_ext)); 33.144 + 33.145 +ASSYM(PCB_SPARE, offsetof(struct pcb, __pcb_spare)); 33.146 +ASSYM(PCB_FLAGS, offsetof(struct pcb, pcb_flags)); 33.147 +ASSYM(PCB_SAVEFPU, offsetof(struct pcb, pcb_save)); 33.148 +ASSYM(PCB_SAVEFPU_SIZE, sizeof(union savefpu)); 33.149 +ASSYM(PCB_ONFAULT, offsetof(struct pcb, pcb_onfault)); 33.150 +ASSYM(PCB_SWITCHOUT, offsetof(struct pcb, pcb_switchout)); 33.151 + 33.152 +ASSYM(PCB_SIZE, sizeof(struct pcb)); 33.153 + 33.154 +ASSYM(TF_TRAPNO, offsetof(struct trapframe, tf_trapno)); 33.155 +ASSYM(TF_ERR, offsetof(struct trapframe, tf_err)); 33.156 +ASSYM(TF_CS, offsetof(struct trapframe, tf_cs)); 33.157 +ASSYM(TF_EFLAGS, offsetof(struct trapframe, tf_eflags)); 33.158 +ASSYM(TF_EIP, offsetof(struct trapframe, tf_eip)); 33.159 +ASSYM(SIGF_HANDLER, offsetof(struct sigframe, sf_ahu.sf_handler)); 33.160 +#ifdef COMPAT_43 33.161 +ASSYM(SIGF_SC, offsetof(struct osigframe, sf_siginfo.si_sc)); 33.162 +#endif 33.163 +ASSYM(SIGF_UC, offsetof(struct sigframe, sf_uc)); 33.164 +#ifdef COMPAT_FREEBSD4 33.165 +ASSYM(SIGF_UC4, offsetof(struct sigframe4, sf_uc)); 33.166 +#endif 33.167 +#ifdef COMPAT_43 33.168 +ASSYM(SC_PS, offsetof(struct osigcontext, sc_ps)); 33.169 +ASSYM(SC_FS, offsetof(struct osigcontext, sc_fs)); 33.170 +ASSYM(SC_GS, offsetof(struct osigcontext, sc_gs)); 33.171 +ASSYM(SC_TRAPNO, offsetof(struct osigcontext, sc_trapno)); 33.172 +#endif 33.173 +#ifdef COMPAT_FREEBSD4 33.174 +ASSYM(UC4_EFLAGS, offsetof(struct ucontext4, uc_mcontext.mc_eflags)); 33.175 +ASSYM(UC4_GS, offsetof(struct ucontext4, uc_mcontext.mc_gs)); 33.176 +#endif 33.177 +ASSYM(UC_EFLAGS, offsetof(ucontext_t, uc_mcontext.mc_eflags)); 33.178 +ASSYM(UC_GS, offsetof(ucontext_t, uc_mcontext.mc_gs)); 33.179 +ASSYM(ENOENT, ENOENT); 33.180 +ASSYM(EFAULT, EFAULT); 33.181 +ASSYM(ENAMETOOLONG, ENAMETOOLONG); 33.182 +ASSYM(MAXCOMLEN, MAXCOMLEN); 33.183 +ASSYM(MAXPATHLEN, MAXPATHLEN); 33.184 +ASSYM(BOOTINFO_SIZE, sizeof(struct bootinfo)); 33.185 +ASSYM(BI_VERSION, offsetof(struct bootinfo, bi_version)); 33.186 +ASSYM(BI_KERNELNAME, offsetof(struct bootinfo, bi_kernelname)); 33.187 +ASSYM(BI_NFS_DISKLESS, offsetof(struct bootinfo, bi_nfs_diskless)); 33.188 +ASSYM(BI_ENDCOMMON, offsetof(struct bootinfo, bi_endcommon)); 33.189 +ASSYM(NFSDISKLESS_SIZE, sizeof(struct nfs_diskless)); 33.190 +ASSYM(BI_SIZE, offsetof(struct bootinfo, bi_size)); 33.191 +ASSYM(BI_SYMTAB, offsetof(struct bootinfo, bi_symtab)); 33.192 +ASSYM(BI_ESYMTAB, offsetof(struct bootinfo, bi_esymtab)); 33.193 +ASSYM(BI_KERNEND, offsetof(struct bootinfo, bi_kernend)); 33.194 +ASSYM(PC_SIZEOF, sizeof(struct pcpu)); 33.195 +ASSYM(PC_PRVSPACE, offsetof(struct pcpu, pc_prvspace)); 33.196 +ASSYM(PC_CURTHREAD, offsetof(struct pcpu, pc_curthread)); 33.197 +ASSYM(PC_FPCURTHREAD, offsetof(struct pcpu, pc_fpcurthread)); 33.198 +ASSYM(PC_IDLETHREAD, offsetof(struct pcpu, pc_idlethread)); 33.199 +ASSYM(PC_CURPCB, offsetof(struct pcpu, pc_curpcb)); 33.200 +ASSYM(PC_COMMON_TSS, offsetof(struct pcpu, pc_common_tss)); 33.201 +ASSYM(PC_COMMON_TSSD, offsetof(struct pcpu, pc_common_tssd)); 33.202 +ASSYM(PC_TSS_GDT, offsetof(struct pcpu, pc_tss_gdt)); 33.203 +ASSYM(PC_CURRENTLDT, offsetof(struct pcpu, pc_currentldt)); 33.204 +ASSYM(PC_CPUID, offsetof(struct pcpu, pc_cpuid)); 33.205 +ASSYM(PC_CURPMAP, offsetof(struct pcpu, pc_curpmap)); 33.206 +ASSYM(PC_TRAP_NESTING, offsetof(struct pcpu, pc_trap_nesting)); 33.207 + 33.208 +ASSYM(PC_CR3, offsetof(struct pcpu, pc_pdir)); 33.209 + 33.210 +#ifdef DEV_APIC 33.211 +ASSYM(LA_VER, offsetof(struct LAPIC, version)); 33.212 +ASSYM(LA_TPR, offsetof(struct LAPIC, tpr)); 33.213 +ASSYM(LA_EOI, offsetof(struct LAPIC, eoi)); 33.214 +ASSYM(LA_SVR, offsetof(struct LAPIC, svr)); 33.215 +ASSYM(LA_ICR_LO, offsetof(struct LAPIC, icr_lo)); 33.216 +ASSYM(LA_ICR_HI, offsetof(struct LAPIC, icr_hi)); 33.217 +ASSYM(LA_ISR, offsetof(struct LAPIC, isr0)); 33.218 +#endif 33.219 + 33.220 +ASSYM(KCSEL, GSEL(GCODE_SEL, SEL_KPL)); 33.221 +ASSYM(KDSEL, GSEL(GDATA_SEL, SEL_KPL)); 33.222 +ASSYM(KPSEL, GSEL(GPRIV_SEL, SEL_KPL)); 33.223 + 33.224 +ASSYM(BC32SEL, GSEL(GBIOSCODE32_SEL, SEL_KPL)); 33.225 +ASSYM(GPROC0_SEL, GPROC0_SEL); 33.226 + 33.227 +ASSYM(MTX_LOCK, offsetof(struct mtx, mtx_lock)); 33.228 +ASSYM(MTX_RECURSECNT, offsetof(struct mtx, mtx_recurse)); 33.229 + 33.230 +#ifdef PC98 33.231 +#include <machine/bus.h> 33.232 + 33.233 +ASSYM(BUS_SPACE_HANDLE_BASE, offsetof(struct bus_space_handle, bsh_base)); 33.234 +ASSYM(BUS_SPACE_HANDLE_IAT, offsetof(struct bus_space_handle, bsh_iat)); 33.235 +#endif 33.236 + 33.237 +ASSYM(HYPERVISOR_STACK_SWITCH, __HYPERVISOR_stack_switch);
34.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 34.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/hypervisor.c Thu Mar 24 22:52:13 2005 +0000 34.3 @@ -0,0 +1,107 @@ 34.4 +/****************************************************************************** 34.5 + * hypervisor.c 34.6 + * 34.7 + * Communication to/from hypervisor. 34.8 + * 34.9 + * Copyright (c) 2002-2003, K A Fraser 34.10 + * 34.11 + * Permission is hereby granted, free of charge, to any person obtaining a copy 34.12 + * of this software and associated documentation files (the "Software"), to 34.13 + * deal in the Software without restriction, including without limitation the 34.14 + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 34.15 + * sell copies of the Software, and to permit persons to whom the Software is 34.16 + * furnished to do so, subject to the following conditions: 34.17 + * 34.18 + * The above copyright notice and this permission notice shall be included in 34.19 + * all copies or substantial portions of the Software. 34.20 + * 34.21 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 34.22 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIEAS OF MERCHANTABILITY, 34.23 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 34.24 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 34.25 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 34.26 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 34.27 + * DEALINGS IN THE SOFTWARE. 34.28 + */ 34.29 + 34.30 +#include <machine/xen-os.h> 34.31 +#include <machine/hypervisor.h> 34.32 +#include <machine/xenvar.h> 34.33 +#include <machine/multicall.h> 34.34 + 34.35 +/* XXX need to verify what the caller save registers are on x86 KMM */ 34.36 +#define CALLER_SAVE __asm__("pushal; ") 34.37 +#define CALLER_RESTORE __asm__("popal;") 34.38 + 34.39 + 34.40 +/* ni == non-inline - these are only intended for use from assembler 34.41 + * no reason to have them in a header - 34.42 + * 34.43 + */ 34.44 +void ni_queue_multicall0(unsigned long op); 34.45 +void ni_queue_multicall1(unsigned long op, unsigned long arg1); 34.46 +void ni_queue_multicall2(unsigned long op, unsigned long arg1, 34.47 + unsigned long arg2); 34.48 +void ni_queue_multicall3(unsigned long op, unsigned long arg1, 34.49 + unsigned long arg2, unsigned long arg3); 34.50 +void ni_queue_multicall4(unsigned long op, unsigned long arg1, 34.51 + unsigned long arg2, unsigned long arg4, 34.52 + unsigned long arg5); 34.53 + 34.54 +void ni_execute_multicall_list(void); 34.55 + 34.56 +multicall_entry_t multicall_list[MAX_MULTICALL_ENTS]; 34.57 +int nr_multicall_ents = 0; 34.58 + 34.59 + 34.60 +void 34.61 +ni_queue_multicall0(unsigned long op) 34.62 +{ 34.63 + CALLER_SAVE; 34.64 + queue_multicall0(op); 34.65 + CALLER_RESTORE; 34.66 +} 34.67 + 34.68 +void 34.69 +ni_queue_multicall1(unsigned long op, unsigned long arg1) 34.70 +{ 34.71 + CALLER_SAVE; 34.72 + queue_multicall1(op, arg1); 34.73 + CALLER_RESTORE; 34.74 +} 34.75 + 34.76 +void 34.77 +ni_queue_multicall2(unsigned long op, unsigned long arg1, 34.78 + unsigned long arg2) 34.79 +{ 34.80 + CALLER_SAVE; 34.81 + queue_multicall2(op, arg1, arg2); 34.82 + CALLER_RESTORE; 34.83 +} 34.84 + 34.85 +void 34.86 +ni_queue_multicall3(unsigned long op, unsigned long arg1, 34.87 + unsigned long arg2, unsigned long arg3) 34.88 +{ 34.89 + CALLER_SAVE; 34.90 + queue_multicall3(op, arg1, arg2, arg3); 34.91 + CALLER_RESTORE; 34.92 +} 34.93 + 34.94 +void 34.95 +ni_queue_multicall4(unsigned long op, unsigned long arg1, 34.96 + unsigned long arg2, unsigned long arg3, 34.97 + unsigned long arg4) 34.98 +{ 34.99 + CALLER_SAVE; 34.100 + queue_multicall4(op, arg1, arg2, arg3, arg4); 34.101 + CALLER_RESTORE; 34.102 +} 34.103 + 34.104 +void 34.105 +ni_execute_multicall_list(void) 34.106 +{ 34.107 + CALLER_SAVE; 34.108 + execute_multicall_list(); 34.109 + CALLER_RESTORE; 34.110 +}
35.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 35.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/i686_mem.c Thu Mar 24 22:52:13 2005 +0000 35.3 @@ -0,0 +1,626 @@ 35.4 +/*- 35.5 + * Copyright (c) 1999 Michael Smith <msmith@freebsd.org> 35.6 + * All rights reserved. 35.7 + * 35.8 + * Redistribution and use in source and binary forms, with or without 35.9 + * modification, are permitted provided that the following conditions 35.10 + * are met: 35.11 + * 1. Redistributions of source code must retain the above copyright 35.12 + * notice, this list of conditions and the following disclaimer. 35.13 + * 2. Redistributions in binary form must reproduce the above copyright 35.14 + * notice, this list of conditions and the following disclaimer in the 35.15 + * documentation and/or other materials provided with the distribution. 35.16 + * 35.17 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 35.18 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35.19 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35.20 + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 35.21 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35.22 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35.23 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35.24 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35.25 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35.26 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35.27 + * SUCH DAMAGE. 35.28 + */ 35.29 + 35.30 +#include <sys/cdefs.h> 35.31 +__FBSDID("$FreeBSD: src/sys/i386/i386/i686_mem.c,v 1.23 2003/10/21 18:28:34 silby Exp $"); 35.32 + 35.33 +#include <sys/param.h> 35.34 +#include <sys/kernel.h> 35.35 +#include <sys/systm.h> 35.36 +#include <sys/malloc.h> 35.37 +#include <sys/memrange.h> 35.38 +#include <sys/smp.h> 35.39 +#include <sys/sysctl.h> 35.40 + 35.41 +#include <machine/md_var.h> 35.42 +#include <machine/specialreg.h> 35.43 + 35.44 +/* 35.45 + * i686 memory range operations 35.46 + * 35.47 + * This code will probably be impenetrable without reference to the 35.48 + * Intel Pentium Pro documentation. 35.49 + */ 35.50 + 35.51 +static char *mem_owner_bios = "BIOS"; 35.52 + 35.53 +#define MR686_FIXMTRR (1<<0) 35.54 + 35.55 +#define mrwithin(mr, a) \ 35.56 + (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len))) 35.57 +#define mroverlap(mra, mrb) \ 35.58 + (mrwithin(mra, mrb->mr_base) || mrwithin(mrb, mra->mr_base)) 35.59 + 35.60 +#define mrvalid(base, len) \ 35.61 + ((!(base & ((1 << 12) - 1))) && /* base is multiple of 4k */ \ 35.62 + ((len) >= (1 << 12)) && /* length is >= 4k */ \ 35.63 + powerof2((len)) && /* ... and power of two */ \ 35.64 + !((base) & ((len) - 1))) /* range is not discontiuous */ 35.65 + 35.66 +#define mrcopyflags(curr, new) (((curr) & ~MDF_ATTRMASK) | ((new) & MDF_ATTRMASK)) 35.67 + 35.68 +static int mtrrs_disabled; 35.69 +TUNABLE_INT("machdep.disable_mtrrs", &mtrrs_disabled); 35.70 +SYSCTL_INT(_machdep, OID_AUTO, disable_mtrrs, CTLFLAG_RDTUN, 35.71 + &mtrrs_disabled, 0, "Disable i686 MTRRs."); 35.72 + 35.73 +static void i686_mrinit(struct mem_range_softc *sc); 35.74 +static int i686_mrset(struct mem_range_softc *sc, 35.75 + struct mem_range_desc *mrd, 35.76 + int *arg); 35.77 +static void i686_mrAPinit(struct mem_range_softc *sc); 35.78 + 35.79 +static struct mem_range_ops i686_mrops = { 35.80 + i686_mrinit, 35.81 + i686_mrset, 35.82 + i686_mrAPinit 35.83 +}; 35.84 + 35.85 +/* XXX for AP startup hook */ 35.86 +static u_int64_t mtrrcap, mtrrdef; 35.87 + 35.88 +static struct mem_range_desc *mem_range_match(struct mem_range_softc *sc, 35.89 + struct mem_range_desc *mrd); 35.90 +static void i686_mrfetch(struct mem_range_softc *sc); 35.91 +static int i686_mtrrtype(int flags); 35.92 +#if 0 35.93 +static int i686_mrt2mtrr(int flags, int oldval); 35.94 +#endif 35.95 +static int i686_mtrrconflict(int flag1, int flag2); 35.96 +static void i686_mrstore(struct mem_range_softc *sc); 35.97 +static void i686_mrstoreone(void *arg); 35.98 +static struct mem_range_desc *i686_mtrrfixsearch(struct mem_range_softc *sc, 35.99 + u_int64_t addr); 35.100 +static int i686_mrsetlow(struct mem_range_softc *sc, 35.101 + struct mem_range_desc *mrd, 35.102 + int *arg); 35.103 +static int i686_mrsetvariable(struct mem_range_softc *sc, 35.104 + struct mem_range_desc *mrd, 35.105 + int *arg); 35.106 + 35.107 +/* i686 MTRR type to memory range type conversion */ 35.108 +static int i686_mtrrtomrt[] = { 35.109 + MDF_UNCACHEABLE, 35.110 + MDF_WRITECOMBINE, 35.111 + MDF_UNKNOWN, 35.112 + MDF_UNKNOWN, 35.113 + MDF_WRITETHROUGH, 35.114 + MDF_WRITEPROTECT, 35.115 + MDF_WRITEBACK 35.116 +}; 35.117 + 35.118 +#define MTRRTOMRTLEN (sizeof(i686_mtrrtomrt) / sizeof(i686_mtrrtomrt[0])) 35.119 + 35.120 +static int 35.121 +i686_mtrr2mrt(int val) { 35.122 + if (val < 0 || val >= MTRRTOMRTLEN) 35.123 + return MDF_UNKNOWN; 35.124 + return i686_mtrrtomrt[val]; 35.125 +} 35.126 + 35.127 +/* 35.128 + * i686 MTRR conflicts. Writeback and uncachable may overlap. 35.129 + */ 35.130 +static int 35.131 +i686_mtrrconflict(int flag1, int flag2) { 35.132 + flag1 &= MDF_ATTRMASK; 35.133 + flag2 &= MDF_ATTRMASK; 35.134 + if (flag1 == flag2 || 35.135 + (flag1 == MDF_WRITEBACK && flag2 == MDF_UNCACHEABLE) || 35.136 + (flag2 == MDF_WRITEBACK && flag1 == MDF_UNCACHEABLE)) 35.137 + return 0; 35.138 + return 1; 35.139 +} 35.140 + 35.141 +/* 35.142 + * Look for an exactly-matching range. 35.143 + */ 35.144 +static struct mem_range_desc * 35.145 +mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd) 35.146 +{ 35.147 + struct mem_range_desc *cand; 35.148 + int i; 35.149 + 35.150 + for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++) 35.151 + if ((cand->mr_base == mrd->mr_base) && 35.152 + (cand->mr_len == mrd->mr_len)) 35.153 + return(cand); 35.154 + return(NULL); 35.155 +} 35.156 + 35.157 +/* 35.158 + * Fetch the current mtrr settings from the current CPU (assumed to all 35.159 + * be in sync in the SMP case). Note that if we are here, we assume 35.160 + * that MTRRs are enabled, and we may or may not have fixed MTRRs. 35.161 + */ 35.162 +static void 35.163 +i686_mrfetch(struct mem_range_softc *sc) 35.164 +{ 35.165 + struct mem_range_desc *mrd; 35.166 + u_int64_t msrv; 35.167 + int i, j, msr; 35.168 + 35.169 + mrd = sc->mr_desc; 35.170 + 35.171 + /* Get fixed-range MTRRs */ 35.172 + if (sc->mr_cap & MR686_FIXMTRR) { 35.173 + msr = MSR_MTRR64kBase; 35.174 + for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { 35.175 + msrv = rdmsr(msr); 35.176 + for (j = 0; j < 8; j++, mrd++) { 35.177 + mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | 35.178 + i686_mtrr2mrt(msrv & 0xff) | 35.179 + MDF_ACTIVE; 35.180 + if (mrd->mr_owner[0] == 0) 35.181 + strcpy(mrd->mr_owner, mem_owner_bios); 35.182 + msrv = msrv >> 8; 35.183 + } 35.184 + } 35.185 + msr = MSR_MTRR16kBase; 35.186 + for (i = 0; i < (MTRR_N16K / 8); i++, msr++) { 35.187 + msrv = rdmsr(msr); 35.188 + for (j = 0; j < 8; j++, mrd++) { 35.189 + mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | 35.190 + i686_mtrr2mrt(msrv & 0xff) | 35.191 + MDF_ACTIVE; 35.192 + if (mrd->mr_owner[0] == 0) 35.193 + strcpy(mrd->mr_owner, mem_owner_bios); 35.194 + msrv = msrv >> 8; 35.195 + } 35.196 + } 35.197 + msr = MSR_MTRR4kBase; 35.198 + for (i = 0; i < (MTRR_N4K / 8); i++, msr++) { 35.199 + msrv = rdmsr(msr); 35.200 + for (j = 0; j < 8; j++, mrd++) { 35.201 + mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | 35.202 + i686_mtrr2mrt(msrv & 0xff) | 35.203 + MDF_ACTIVE; 35.204 + if (mrd->mr_owner[0] == 0) 35.205 + strcpy(mrd->mr_owner, mem_owner_bios); 35.206 + msrv = msrv >> 8; 35.207 + } 35.208 + } 35.209 + } 35.210 + 35.211 + /* Get remainder which must be variable MTRRs */ 35.212 + msr = MSR_MTRRVarBase; 35.213 + for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) { 35.214 + msrv = rdmsr(msr); 35.215 + mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | 35.216 + i686_mtrr2mrt(msrv & 0xff); 35.217 + mrd->mr_base = msrv & 0x0000000ffffff000LL; 35.218 + msrv = rdmsr(msr + 1); 35.219 + mrd->mr_flags = (msrv & 0x800) ? 35.220 + (mrd->mr_flags | MDF_ACTIVE) : 35.221 + (mrd->mr_flags & ~MDF_ACTIVE); 35.222 + /* Compute the range from the mask. Ick. */ 35.223 + mrd->mr_len = (~(msrv & 0x0000000ffffff000LL) & 0x0000000fffffffffLL) + 1; 35.224 + if (!mrvalid(mrd->mr_base, mrd->mr_len)) 35.225 + mrd->mr_flags |= MDF_BOGUS; 35.226 + /* If unclaimed and active, must be the BIOS */ 35.227 + if ((mrd->mr_flags & MDF_ACTIVE) && (mrd->mr_owner[0] == 0)) 35.228 + strcpy(mrd->mr_owner, mem_owner_bios); 35.229 + } 35.230 +} 35.231 + 35.232 +/* 35.233 + * Return the MTRR memory type matching a region's flags 35.234 + */ 35.235 +static int 35.236 +i686_mtrrtype(int flags) 35.237 +{ 35.238 + int i; 35.239 + 35.240 + flags &= MDF_ATTRMASK; 35.241 + 35.242 + for (i = 0; i < MTRRTOMRTLEN; i++) { 35.243 + if (i686_mtrrtomrt[i] == MDF_UNKNOWN) 35.244 + continue; 35.245 + if (flags == i686_mtrrtomrt[i]) 35.246 + return(i); 35.247 + } 35.248 + return(-1); 35.249 +} 35.250 +#if 0 35.251 +static int 35.252 +i686_mrt2mtrr(int flags, int oldval) 35.253 +{ 35.254 + int val; 35.255 + 35.256 + if ((val = i686_mtrrtype(flags)) == -1) 35.257 + return oldval & 0xff; 35.258 + return val & 0xff; 35.259 +} 35.260 +#endif 35.261 +/* 35.262 + * Update running CPU(s) MTRRs to match the ranges in the descriptor 35.263 + * list. 35.264 + * 35.265 + * XXX Must be called with interrupts enabled. 35.266 + */ 35.267 +static void 35.268 +i686_mrstore(struct mem_range_softc *sc) 35.269 +{ 35.270 +#ifdef SMP 35.271 + /* 35.272 + * We should use ipi_all_but_self() to call other CPUs into a 35.273 + * locking gate, then call a target function to do this work. 35.274 + * The "proper" solution involves a generalised locking gate 35.275 + * implementation, not ready yet. 35.276 + */ 35.277 + smp_rendezvous(NULL, i686_mrstoreone, NULL, (void *)sc); 35.278 +#else 35.279 + disable_intr(); /* disable interrupts */ 35.280 + i686_mrstoreone((void *)sc); 35.281 + enable_intr(); 35.282 +#endif 35.283 +} 35.284 + 35.285 +/* 35.286 + * Update the current CPU's MTRRs with those represented in the 35.287 + * descriptor list. Note that we do this wholesale rather than 35.288 + * just stuffing one entry; this is simpler (but slower, of course). 35.289 + */ 35.290 +static void 35.291 +i686_mrstoreone(void *arg) 35.292 +{ 35.293 +#if 0 35.294 + struct mem_range_softc *sc = (struct mem_range_softc *)arg; 35.295 + struct mem_range_desc *mrd; 35.296 + u_int64_t omsrv, msrv; 35.297 + int i, j, msr; 35.298 + u_int cr4save; 35.299 + 35.300 + mrd = sc->mr_desc; 35.301 + 35.302 + cr4save = rcr4(); /* save cr4 */ 35.303 + if (cr4save & CR4_PGE) 35.304 + load_cr4(cr4save & ~CR4_PGE); 35.305 + load_cr0((rcr0() & ~CR0_NW) | CR0_CD); /* disable caches (CD = 1, NW = 0) */ 35.306 + wbinvd(); /* flush caches, TLBs */ 35.307 + wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~0x800); /* disable MTRRs (E = 0) */ 35.308 + 35.309 + /* Set fixed-range MTRRs */ 35.310 + if (sc->mr_cap & MR686_FIXMTRR) { 35.311 + msr = MSR_MTRR64kBase; 35.312 + for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { 35.313 + msrv = 0; 35.314 + omsrv = rdmsr(msr); 35.315 + for (j = 7; j >= 0; j--) { 35.316 + msrv = msrv << 8; 35.317 + msrv |= i686_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8)); 35.318 + } 35.319 + wrmsr(msr, msrv); 35.320 + mrd += 8; 35.321 + } 35.322 + msr = MSR_MTRR16kBase; 35.323 + for (i = 0; i < (MTRR_N16K / 8); i++, msr++) { 35.324 + msrv = 0; 35.325 + omsrv = rdmsr(msr); 35.326 + for (j = 7; j >= 0; j--) { 35.327 + msrv = msrv << 8; 35.328 + msrv |= i686_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8)); 35.329 + } 35.330 + wrmsr(msr, msrv); 35.331 + mrd += 8; 35.332 + } 35.333 + msr = MSR_MTRR4kBase; 35.334 + for (i = 0; i < (MTRR_N4K / 8); i++, msr++) { 35.335 + msrv = 0; 35.336 + omsrv = rdmsr(msr); 35.337 + for (j = 7; j >= 0; j--) { 35.338 + msrv = msrv << 8; 35.339 + msrv |= i686_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8)); 35.340 + } 35.341 + wrmsr(msr, msrv); 35.342 + mrd += 8; 35.343 + } 35.344 + } 35.345 + 35.346 + /* Set remainder which must be variable MTRRs */ 35.347 + msr = MSR_MTRRVarBase; 35.348 + for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) { 35.349 + /* base/type register */ 35.350 + omsrv = rdmsr(msr); 35.351 + if (mrd->mr_flags & MDF_ACTIVE) { 35.352 + msrv = mrd->mr_base & 0x0000000ffffff000LL; 35.353 + msrv |= i686_mrt2mtrr(mrd->mr_flags, omsrv); 35.354 + } else { 35.355 + msrv = 0; 35.356 + } 35.357 + wrmsr(msr, msrv); 35.358 + 35.359 + /* mask/active register */ 35.360 + if (mrd->mr_flags & MDF_ACTIVE) { 35.361 + msrv = 0x800 | (~(mrd->mr_len - 1) & 0x0000000ffffff000LL); 35.362 + } else { 35.363 + msrv = 0; 35.364 + } 35.365 + wrmsr(msr + 1, msrv); 35.366 + } 35.367 + wbinvd(); /* flush caches, TLBs */ 35.368 + wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | 0x800); /* restore MTRR state */ 35.369 + load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* enable caches CD = 0 and NW = 0 */ 35.370 + load_cr4(cr4save); /* restore cr4 */ 35.371 +#endif 35.372 +} 35.373 + 35.374 +/* 35.375 + * Hunt for the fixed MTRR referencing (addr) 35.376 + */ 35.377 +static struct mem_range_desc * 35.378 +i686_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr) 35.379 +{ 35.380 + struct mem_range_desc *mrd; 35.381 + int i; 35.382 + 35.383 + for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K); i++, mrd++) 35.384 + if ((addr >= mrd->mr_base) && (addr < (mrd->mr_base + mrd->mr_len))) 35.385 + return(mrd); 35.386 + return(NULL); 35.387 +} 35.388 + 35.389 +/* 35.390 + * Try to satisfy the given range request by manipulating the fixed MTRRs that 35.391 + * cover low memory. 35.392 + * 35.393 + * Note that we try to be generous here; we'll bloat the range out to the 35.394 + * next higher/lower boundary to avoid the consumer having to know too much 35.395 + * about the mechanisms here. 35.396 + * 35.397 + * XXX note that this will have to be updated when we start supporting "busy" ranges. 35.398 + */ 35.399 +static int 35.400 +i686_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg) 35.401 +{ 35.402 + struct mem_range_desc *first_md, *last_md, *curr_md; 35.403 + 35.404 + /* range check */ 35.405 + if (((first_md = i686_mtrrfixsearch(sc, mrd->mr_base)) == NULL) || 35.406 + ((last_md = i686_mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL)) 35.407 + return(EINVAL); 35.408 + 35.409 + /* check we aren't doing something risky */ 35.410 + if (!(mrd->mr_flags & MDF_FORCE)) 35.411 + for (curr_md = first_md; curr_md <= last_md; curr_md++) { 35.412 + if ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN) 35.413 + return (EACCES); 35.414 + } 35.415 + 35.416 + /* set flags, clear set-by-firmware flag */ 35.417 + for (curr_md = first_md; curr_md <= last_md; curr_md++) { 35.418 + curr_md->mr_flags = mrcopyflags(curr_md->mr_flags & ~MDF_FIRMWARE, mrd->mr_flags); 35.419 + bcopy(mrd->mr_owner, curr_md->mr_owner, sizeof(mrd->mr_owner)); 35.420 + } 35.421 + 35.422 + return(0); 35.423 +} 35.424 + 35.425 + 35.426 +/* 35.427 + * Modify/add a variable MTRR to satisfy the request. 35.428 + * 35.429 + * XXX needs to be updated to properly support "busy" ranges. 35.430 + */ 35.431 +static int 35.432 +i686_mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg) 35.433 +{ 35.434 + struct mem_range_desc *curr_md, *free_md; 35.435 + int i; 35.436 + 35.437 + /* 35.438 + * Scan the currently active variable descriptors, look for 35.439 + * one we exactly match (straight takeover) and for possible 35.440 + * accidental overlaps. 35.441 + * Keep track of the first empty variable descriptor in case we 35.442 + * can't perform a takeover. 35.443 + */ 35.444 + i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0; 35.445 + curr_md = sc->mr_desc + i; 35.446 + free_md = NULL; 35.447 + for (; i < sc->mr_ndesc; i++, curr_md++) { 35.448 + if (curr_md->mr_flags & MDF_ACTIVE) { 35.449 + /* exact match? */ 35.450 + if ((curr_md->mr_base == mrd->mr_base) && 35.451 + (curr_md->mr_len == mrd->mr_len)) { 35.452 + /* whoops, owned by someone */ 35.453 + if (curr_md->mr_flags & MDF_BUSY) 35.454 + return(EBUSY); 35.455 + /* check we aren't doing something risky */ 35.456 + if (!(mrd->mr_flags & MDF_FORCE) && 35.457 + ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN)) 35.458 + return (EACCES); 35.459 + /* Ok, just hijack this entry */ 35.460 + free_md = curr_md; 35.461 + break; 35.462 + } 35.463 + /* non-exact overlap ? */ 35.464 + if (mroverlap(curr_md, mrd)) { 35.465 + /* between conflicting region types? */ 35.466 + if (i686_mtrrconflict(curr_md->mr_flags, mrd->mr_flags)) 35.467 + return(EINVAL); 35.468 + } 35.469 + } else if (free_md == NULL) { 35.470 + free_md = curr_md; 35.471 + } 35.472 + } 35.473 + /* got somewhere to put it? */ 35.474 + if (free_md == NULL) 35.475 + return(ENOSPC); 35.476 + 35.477 + /* Set up new descriptor */ 35.478 + free_md->mr_base = mrd->mr_base; 35.479 + free_md->mr_len = mrd->mr_len; 35.480 + free_md->mr_flags = mrcopyflags(MDF_ACTIVE, mrd->mr_flags); 35.481 + bcopy(mrd->mr_owner, free_md->mr_owner, sizeof(mrd->mr_owner)); 35.482 + return(0); 35.483 +} 35.484 + 35.485 +/* 35.486 + * Handle requests to set memory range attributes by manipulating MTRRs. 35.487 + * 35.488 + */ 35.489 +static int 35.490 +i686_mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg) 35.491 +{ 35.492 + struct mem_range_desc *targ; 35.493 + int error = 0; 35.494 + 35.495 + switch(*arg) { 35.496 + case MEMRANGE_SET_UPDATE: 35.497 + /* make sure that what's being asked for is even possible at all */ 35.498 + if (!mrvalid(mrd->mr_base, mrd->mr_len) || 35.499 + i686_mtrrtype(mrd->mr_flags) == -1) 35.500 + return(EINVAL); 35.501 + 35.502 +#define FIXTOP ((MTRR_N64K * 0x10000) + (MTRR_N16K * 0x4000) + (MTRR_N4K * 0x1000)) 35.503 + 35.504 + /* are the "low memory" conditions applicable? */ 35.505 + if ((sc->mr_cap & MR686_FIXMTRR) && 35.506 + ((mrd->mr_base + mrd->mr_len) <= FIXTOP)) { 35.507 + if ((error = i686_mrsetlow(sc, mrd, arg)) != 0) 35.508 + return(error); 35.509 + } else { 35.510 + /* it's time to play with variable MTRRs */ 35.511 + if ((error = i686_mrsetvariable(sc, mrd, arg)) != 0) 35.512 + return(error); 35.513 + } 35.514 + break; 35.515 + 35.516 + case MEMRANGE_SET_REMOVE: 35.517 + if ((targ = mem_range_match(sc, mrd)) == NULL) 35.518 + return(ENOENT); 35.519 + if (targ->mr_flags & MDF_FIXACTIVE) 35.520 + return(EPERM); 35.521 + if (targ->mr_flags & MDF_BUSY) 35.522 + return(EBUSY); 35.523 + targ->mr_flags &= ~MDF_ACTIVE; 35.524 + targ->mr_owner[0] = 0; 35.525 + break; 35.526 + 35.527 + default: 35.528 + return(EOPNOTSUPP); 35.529 + } 35.530 + 35.531 + /* update the hardware */ 35.532 + i686_mrstore(sc); 35.533 + i686_mrfetch(sc); /* refetch to see where we're at */ 35.534 + return(0); 35.535 +} 35.536 + 35.537 +/* 35.538 + * Work out how many ranges we support, initialise storage for them, 35.539 + * fetch the initial settings. 35.540 + */ 35.541 +static void 35.542 +i686_mrinit(struct mem_range_softc *sc) 35.543 +{ 35.544 + struct mem_range_desc *mrd; 35.545 + int nmdesc = 0; 35.546 + int i; 35.547 + 35.548 + /* XXX */ 35.549 + return; 35.550 + 35.551 + mtrrcap = rdmsr(MSR_MTRRcap); 35.552 + mtrrdef = rdmsr(MSR_MTRRdefType); 35.553 + 35.554 + /* For now, bail out if MTRRs are not enabled */ 35.555 + if (!(mtrrdef & 0x800)) { 35.556 + if (bootverbose) 35.557 + printf("CPU supports MTRRs but not enabled\n"); 35.558 + return; 35.559 + } 35.560 + nmdesc = mtrrcap & 0xff; 35.561 + printf("Pentium Pro MTRR support enabled\n"); 35.562 + 35.563 + /* If fixed MTRRs supported and enabled */ 35.564 + if ((mtrrcap & 0x100) && (mtrrdef & 0x400)) { 35.565 + sc->mr_cap = MR686_FIXMTRR; 35.566 + nmdesc += MTRR_N64K + MTRR_N16K + MTRR_N4K; 35.567 + } 35.568 + 35.569 + sc->mr_desc = 35.570 + (struct mem_range_desc *)malloc(nmdesc * sizeof(struct mem_range_desc), 35.571 + M_MEMDESC, M_WAITOK | M_ZERO); 35.572 + sc->mr_ndesc = nmdesc; 35.573 + 35.574 + mrd = sc->mr_desc; 35.575 + 35.576 + /* Populate the fixed MTRR entries' base/length */ 35.577 + if (sc->mr_cap & MR686_FIXMTRR) { 35.578 + for (i = 0; i < MTRR_N64K; i++, mrd++) { 35.579 + mrd->mr_base = i * 0x10000; 35.580 + mrd->mr_len = 0x10000; 35.581 + mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE; 35.582 + } 35.583 + for (i = 0; i < MTRR_N16K; i++, mrd++) { 35.584 + mrd->mr_base = i * 0x4000 + 0x80000; 35.585 + mrd->mr_len = 0x4000; 35.586 + mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE; 35.587 + } 35.588 + for (i = 0; i < MTRR_N4K; i++, mrd++) { 35.589 + mrd->mr_base = i * 0x1000 + 0xc0000; 35.590 + mrd->mr_len = 0x1000; 35.591 + mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE; 35.592 + } 35.593 + } 35.594 + 35.595 + /* 35.596 + * Get current settings, anything set now is considered to have 35.597 + * been set by the firmware. (XXX has something already played here?) 35.598 + */ 35.599 + i686_mrfetch(sc); 35.600 + mrd = sc->mr_desc; 35.601 + for (i = 0; i < sc->mr_ndesc; i++, mrd++) { 35.602 + if (mrd->mr_flags & MDF_ACTIVE) 35.603 + mrd->mr_flags |= MDF_FIRMWARE; 35.604 + } 35.605 +} 35.606 + 35.607 +/* 35.608 + * Initialise MTRRs on an AP after the BSP has run the init code. 35.609 + */ 35.610 +static void 35.611 +i686_mrAPinit(struct mem_range_softc *sc) 35.612 +{ 35.613 + i686_mrstoreone((void *)sc); /* set MTRRs to match BSP */ 35.614 + wrmsr(MSR_MTRRdefType, mtrrdef); /* set MTRR behaviour to match BSP */ 35.615 +} 35.616 + 35.617 +static void 35.618 +i686_mem_drvinit(void *unused) 35.619 +{ 35.620 + /* Try for i686 MTRRs */ 35.621 + if (!mtrrs_disabled && (cpu_feature & CPUID_MTRR) && 35.622 + ((cpu_id & 0xf00) == 0x600 || (cpu_id & 0xf00) == 0xf00) && 35.623 + ((strcmp(cpu_vendor, "GenuineIntel") == 0) || 35.624 + (strcmp(cpu_vendor, "AuthenticAMD") == 0))) { 35.625 + mem_range_softc.mr_op = &i686_mrops; 35.626 + } 35.627 +} 35.628 + 35.629 +SYSINIT(i686memdev,SI_SUB_DRIVERS,SI_ORDER_FIRST,i686_mem_drvinit,NULL)
36.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 36.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/initcpu.c Thu Mar 24 22:52:13 2005 +0000 36.3 @@ -0,0 +1,889 @@ 36.4 +/*- 36.5 + * Copyright (c) KATO Takenori, 1997, 1998. 36.6 + * 36.7 + * All rights reserved. Unpublished rights reserved under the copyright 36.8 + * laws of Japan. 36.9 + * 36.10 + * Redistribution and use in source and binary forms, with or without 36.11 + * modification, are permitted provided that the following conditions 36.12 + * are met: 36.13 + * 36.14 + * 1. Redistributions of source code must retain the above copyright 36.15 + * notice, this list of conditions and the following disclaimer as 36.16 + * the first lines of this file unmodified. 36.17 + * 2. Redistributions in binary form must reproduce the above copyright 36.18 + * notice, this list of conditions and the following disclaimer in the 36.19 + * documentation and/or other materials provided with the distribution. 36.20 + * 36.21 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 36.22 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 36.23 + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36.24 + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 36.25 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36.26 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36.27 + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36.28 + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36.29 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36.30 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36.31 + */ 36.32 + 36.33 +#include <sys/cdefs.h> 36.34 +__FBSDID("$FreeBSD: src/sys/i386/i386/initcpu.c,v 1.49 2003/11/10 15:48:30 jhb Exp $"); 36.35 + 36.36 +#include "opt_cpu.h" 36.37 + 36.38 +#include <sys/param.h> 36.39 +#include <sys/kernel.h> 36.40 +#include <sys/systm.h> 36.41 +#include <sys/sysctl.h> 36.42 + 36.43 +#include <machine/cputypes.h> 36.44 +#include <machine/md_var.h> 36.45 +#include <machine/specialreg.h> 36.46 + 36.47 +#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU) 36.48 +#define CPU_ENABLE_SSE 36.49 +#endif 36.50 +#if defined(CPU_DISABLE_SSE) 36.51 +#undef CPU_ENABLE_SSE 36.52 +#endif 36.53 + 36.54 +void initializecpu(void); 36.55 +#if defined(I586_CPU) && defined(CPU_WT_ALLOC) 36.56 +void enable_K5_wt_alloc(void); 36.57 +void enable_K6_wt_alloc(void); 36.58 +void enable_K6_2_wt_alloc(void); 36.59 +#endif 36.60 + 36.61 +#ifdef I486_CPU 36.62 +static void init_5x86(void); 36.63 +static void init_bluelightning(void); 36.64 +static void init_486dlc(void); 36.65 +static void init_cy486dx(void); 36.66 +#ifdef CPU_I486_ON_386 36.67 +static void init_i486_on_386(void); 36.68 +#endif 36.69 +static void init_6x86(void); 36.70 +#endif /* I486_CPU */ 36.71 + 36.72 +#ifdef I686_CPU 36.73 +static void init_6x86MX(void); 36.74 +static void init_ppro(void); 36.75 +static void init_mendocino(void); 36.76 +#endif 36.77 + 36.78 +static int hw_instruction_sse; 36.79 +SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 36.80 + &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 36.81 + 36.82 +/* Must *NOT* be BSS or locore will bzero these after setting them */ 36.83 +int cpu = 0; /* Are we 386, 386sx, 486, etc? */ 36.84 +u_int cpu_feature = 0; /* Feature flags */ 36.85 +u_int cpu_high = 0; /* Highest arg to CPUID */ 36.86 +u_int cpu_id = 0; /* Stepping ID */ 36.87 +u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */ 36.88 +char cpu_vendor[20] = ""; /* CPU Origin code */ 36.89 + 36.90 +#ifdef CPU_ENABLE_SSE 36.91 +u_int cpu_fxsr; /* SSE enabled */ 36.92 +#endif 36.93 + 36.94 +#ifdef I486_CPU 36.95 +/* 36.96 + * IBM Blue Lightning 36.97 + */ 36.98 +static void 36.99 +init_bluelightning(void) 36.100 +{ 36.101 +#if 0 36.102 + u_long eflags; 36.103 + 36.104 +#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 36.105 + need_post_dma_flush = 1; 36.106 +#endif 36.107 + 36.108 + eflags = read_eflags(); 36.109 + disable_intr(); 36.110 + 36.111 + load_cr0(rcr0() | CR0_CD | CR0_NW); 36.112 + invd(); 36.113 + 36.114 +#ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE 36.115 + wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ 36.116 +#else 36.117 + wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ 36.118 +#endif 36.119 + /* Enables 13MB and 0-640KB cache. */ 36.120 + wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); 36.121 +#ifdef CPU_BLUELIGHTNING_3X 36.122 + wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ 36.123 +#else 36.124 + wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ 36.125 +#endif 36.126 + 36.127 + /* Enable caching in CR0. */ 36.128 + load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 36.129 + invd(); 36.130 + write_eflags(eflags); 36.131 +#endif 36.132 +} 36.133 + 36.134 +/* 36.135 + * Cyrix 486SLC/DLC/SR/DR series 36.136 + */ 36.137 +static void 36.138 +init_486dlc(void) 36.139 +{ 36.140 + u_long eflags; 36.141 + u_char ccr0; 36.142 + 36.143 + eflags = read_eflags(); 36.144 + disable_intr(); 36.145 + invd(); 36.146 + 36.147 + ccr0 = read_cyrix_reg(CCR0); 36.148 +#ifndef CYRIX_CACHE_WORKS 36.149 + ccr0 |= CCR0_NC1 | CCR0_BARB; 36.150 + write_cyrix_reg(CCR0, ccr0); 36.151 + invd(); 36.152 +#else 36.153 + ccr0 &= ~CCR0_NC0; 36.154 +#ifndef CYRIX_CACHE_REALLY_WORKS 36.155 + ccr0 |= CCR0_NC1 | CCR0_BARB; 36.156 +#else 36.157 + ccr0 |= CCR0_NC1; 36.158 +#endif 36.159 +#ifdef CPU_DIRECT_MAPPED_CACHE 36.160 + ccr0 |= CCR0_CO; /* Direct mapped mode. */ 36.161 +#endif 36.162 + write_cyrix_reg(CCR0, ccr0); 36.163 + 36.164 + /* Clear non-cacheable region. */ 36.165 + write_cyrix_reg(NCR1+2, NCR_SIZE_0K); 36.166 + write_cyrix_reg(NCR2+2, NCR_SIZE_0K); 36.167 + write_cyrix_reg(NCR3+2, NCR_SIZE_0K); 36.168 + write_cyrix_reg(NCR4+2, NCR_SIZE_0K); 36.169 + 36.170 + write_cyrix_reg(0, 0); /* dummy write */ 36.171 + 36.172 + /* Enable caching in CR0. */ 36.173 + load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 36.174 + invd(); 36.175 +#endif /* !CYRIX_CACHE_WORKS */ 36.176 + write_eflags(eflags); 36.177 +} 36.178 + 36.179 + 36.180 +/* 36.181 + * Cyrix 486S/DX series 36.182 + */ 36.183 +static void 36.184 +init_cy486dx(void) 36.185 +{ 36.186 + u_long eflags; 36.187 + u_char ccr2; 36.188 + 36.189 + eflags = read_eflags(); 36.190 + disable_intr(); 36.191 + invd(); 36.192 + 36.193 + ccr2 = read_cyrix_reg(CCR2); 36.194 +#ifdef CPU_SUSP_HLT 36.195 + ccr2 |= CCR2_SUSP_HLT; 36.196 +#endif 36.197 + 36.198 +#ifdef PC98 36.199 + /* Enables WB cache interface pin and Lock NW bit in CR0. */ 36.200 + ccr2 |= CCR2_WB | CCR2_LOCK_NW; 36.201 + /* Unlock NW bit in CR0. */ 36.202 + write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW); 36.203 + load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 36.204 +#endif 36.205 + 36.206 + write_cyrix_reg(CCR2, ccr2); 36.207 + write_eflags(eflags); 36.208 +} 36.209 + 36.210 + 36.211 +/* 36.212 + * Cyrix 5x86 36.213 + */ 36.214 +static void 36.215 +init_5x86(void) 36.216 +{ 36.217 + u_long eflags; 36.218 + u_char ccr2, ccr3, ccr4, pcr0; 36.219 + 36.220 + eflags = read_eflags(); 36.221 + disable_intr(); 36.222 + 36.223 + load_cr0(rcr0() | CR0_CD | CR0_NW); 36.224 + wbinvd(); 36.225 + 36.226 + (void)read_cyrix_reg(CCR3); /* dummy */ 36.227 + 36.228 + /* Initialize CCR2. */ 36.229 + ccr2 = read_cyrix_reg(CCR2); 36.230 + ccr2 |= CCR2_WB; 36.231 +#ifdef CPU_SUSP_HLT 36.232 + ccr2 |= CCR2_SUSP_HLT; 36.233 +#else 36.234 + ccr2 &= ~CCR2_SUSP_HLT; 36.235 +#endif 36.236 + ccr2 |= CCR2_WT1; 36.237 + write_cyrix_reg(CCR2, ccr2); 36.238 + 36.239 + /* Initialize CCR4. */ 36.240 + ccr3 = read_cyrix_reg(CCR3); 36.241 + write_cyrix_reg(CCR3, CCR3_MAPEN0); 36.242 + 36.243 + ccr4 = read_cyrix_reg(CCR4); 36.244 + ccr4 |= CCR4_DTE; 36.245 + ccr4 |= CCR4_MEM; 36.246 +#ifdef CPU_FASTER_5X86_FPU 36.247 + ccr4 |= CCR4_FASTFPE; 36.248 +#else 36.249 + ccr4 &= ~CCR4_FASTFPE; 36.250 +#endif 36.251 + ccr4 &= ~CCR4_IOMASK; 36.252 + /******************************************************************** 36.253 + * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time 36.254 + * should be 0 for errata fix. 36.255 + ********************************************************************/ 36.256 +#ifdef CPU_IORT 36.257 + ccr4 |= CPU_IORT & CCR4_IOMASK; 36.258 +#endif 36.259 + write_cyrix_reg(CCR4, ccr4); 36.260 + 36.261 + /* Initialize PCR0. */ 36.262 + /**************************************************************** 36.263 + * WARNING: RSTK_EN and LOOP_EN could make your system unstable. 36.264 + * BTB_EN might make your system unstable. 36.265 + ****************************************************************/ 36.266 + pcr0 = read_cyrix_reg(PCR0); 36.267 +#ifdef CPU_RSTK_EN 36.268 + pcr0 |= PCR0_RSTK; 36.269 +#else 36.270 + pcr0 &= ~PCR0_RSTK; 36.271 +#endif 36.272 +#ifdef CPU_BTB_EN 36.273 + pcr0 |= PCR0_BTB; 36.274 +#else 36.275 + pcr0 &= ~PCR0_BTB; 36.276 +#endif 36.277 +#ifdef CPU_LOOP_EN 36.278 + pcr0 |= PCR0_LOOP; 36.279 +#else 36.280 + pcr0 &= ~PCR0_LOOP; 36.281 +#endif 36.282 + 36.283 + /**************************************************************** 36.284 + * WARNING: if you use a memory mapped I/O device, don't use 36.285 + * DISABLE_5X86_LSSER option, which may reorder memory mapped 36.286 + * I/O access. 36.287 + * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER. 36.288 + ****************************************************************/ 36.289 +#ifdef CPU_DISABLE_5X86_LSSER 36.290 + pcr0 &= ~PCR0_LSSER; 36.291 +#else 36.292 + pcr0 |= PCR0_LSSER; 36.293 +#endif 36.294 + write_cyrix_reg(PCR0, pcr0); 36.295 + 36.296 + /* Restore CCR3. */ 36.297 + write_cyrix_reg(CCR3, ccr3); 36.298 + 36.299 + (void)read_cyrix_reg(0x80); /* dummy */ 36.300 + 36.301 + /* Unlock NW bit in CR0. */ 36.302 + write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 36.303 + load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 36.304 + /* Lock NW bit in CR0. */ 36.305 + write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 36.306 + 36.307 + write_eflags(eflags); 36.308 +} 36.309 + 36.310 +#ifdef CPU_I486_ON_386 36.311 +/* 36.312 + * There are i486 based upgrade products for i386 machines. 36.313 + * In this case, BIOS doesn't enables CPU cache. 36.314 + */ 36.315 +static void 36.316 +init_i486_on_386(void) 36.317 +{ 36.318 + u_long eflags; 36.319 + 36.320 +#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 36.321 + need_post_dma_flush = 1; 36.322 +#endif 36.323 + 36.324 + eflags = read_eflags(); 36.325 + disable_intr(); 36.326 + 36.327 + load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */ 36.328 + 36.329 + write_eflags(eflags); 36.330 +} 36.331 +#endif 36.332 + 36.333 +/* 36.334 + * Cyrix 6x86 36.335 + * 36.336 + * XXX - What should I do here? Please let me know. 36.337 + */ 36.338 +static void 36.339 +init_6x86(void) 36.340 +{ 36.341 + u_long eflags; 36.342 + u_char ccr3, ccr4; 36.343 + 36.344 + eflags = read_eflags(); 36.345 + disable_intr(); 36.346 + 36.347 + load_cr0(rcr0() | CR0_CD | CR0_NW); 36.348 + wbinvd(); 36.349 + 36.350 + /* Initialize CCR0. */ 36.351 + write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 36.352 + 36.353 + /* Initialize CCR1. */ 36.354 +#ifdef CPU_CYRIX_NO_LOCK 36.355 + write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 36.356 +#else 36.357 + write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 36.358 +#endif 36.359 + 36.360 + /* Initialize CCR2. */ 36.361 +#ifdef CPU_SUSP_HLT 36.362 + write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 36.363 +#else 36.364 + write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 36.365 +#endif 36.366 + 36.367 + ccr3 = read_cyrix_reg(CCR3); 36.368 + write_cyrix_reg(CCR3, CCR3_MAPEN0); 36.369 + 36.370 + /* Initialize CCR4. */ 36.371 + ccr4 = read_cyrix_reg(CCR4); 36.372 + ccr4 |= CCR4_DTE; 36.373 + ccr4 &= ~CCR4_IOMASK; 36.374 +#ifdef CPU_IORT 36.375 + write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 36.376 +#else 36.377 + write_cyrix_reg(CCR4, ccr4 | 7); 36.378 +#endif 36.379 + 36.380 + /* Initialize CCR5. */ 36.381 +#ifdef CPU_WT_ALLOC 36.382 + write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 36.383 +#endif 36.384 + 36.385 + /* Restore CCR3. */ 36.386 + write_cyrix_reg(CCR3, ccr3); 36.387 + 36.388 + /* Unlock NW bit in CR0. */ 36.389 + write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 36.390 + 36.391 + /* 36.392 + * Earlier revision of the 6x86 CPU could crash the system if 36.393 + * L1 cache is in write-back mode. 36.394 + */ 36.395 + if ((cyrix_did & 0xff00) > 0x1600) 36.396 + load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 36.397 + else { 36.398 + /* Revision 2.6 and lower. */ 36.399 +#ifdef CYRIX_CACHE_REALLY_WORKS 36.400 + load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 36.401 +#else 36.402 + load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */ 36.403 +#endif 36.404 + } 36.405 + 36.406 + /* Lock NW bit in CR0. */ 36.407 + write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 36.408 + 36.409 + write_eflags(eflags); 36.410 +} 36.411 +#endif /* I486_CPU */ 36.412 + 36.413 +#ifdef I686_CPU 36.414 +/* 36.415 + * Cyrix 6x86MX (code-named M2) 36.416 + * 36.417 + * XXX - What should I do here? Please let me know. 36.418 + */ 36.419 +static void 36.420 +init_6x86MX(void) 36.421 +{ 36.422 +#if 0 36.423 + u_long eflags; 36.424 + u_char ccr3, ccr4; 36.425 + 36.426 + eflags = read_eflags(); 36.427 + disable_intr(); 36.428 + 36.429 + load_cr0(rcr0() | CR0_CD | CR0_NW); 36.430 + wbinvd(); 36.431 + 36.432 + /* Initialize CCR0. */ 36.433 + write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 36.434 + 36.435 + /* Initialize CCR1. */ 36.436 +#ifdef CPU_CYRIX_NO_LOCK 36.437 + write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 36.438 +#else 36.439 + write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 36.440 +#endif 36.441 + 36.442 + /* Initialize CCR2. */ 36.443 +#ifdef CPU_SUSP_HLT 36.444 + write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 36.445 +#else 36.446 + write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 36.447 +#endif 36.448 + 36.449 + ccr3 = read_cyrix_reg(CCR3); 36.450 + write_cyrix_reg(CCR3, CCR3_MAPEN0); 36.451 + 36.452 + /* Initialize CCR4. */ 36.453 + ccr4 = read_cyrix_reg(CCR4); 36.454 + ccr4 &= ~CCR4_IOMASK; 36.455 +#ifdef CPU_IORT 36.456 + write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 36.457 +#else 36.458 + write_cyrix_reg(CCR4, ccr4 | 7); 36.459 +#endif 36.460 + 36.461 + /* Initialize CCR5. */ 36.462 +#ifdef CPU_WT_ALLOC 36.463 + write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 36.464 +#endif 36.465 + 36.466 + /* Restore CCR3. */ 36.467 + write_cyrix_reg(CCR3, ccr3); 36.468 + 36.469 + /* Unlock NW bit in CR0. */ 36.470 + write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 36.471 + 36.472 + load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 36.473 + 36.474 + /* Lock NW bit in CR0. */ 36.475 + write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 36.476 + 36.477 + write_eflags(eflags); 36.478 +#endif 36.479 +} 36.480 + 36.481 +static void 36.482 +init_ppro(void) 36.483 +{ 36.484 + u_int64_t apicbase; 36.485 + 36.486 + /* 36.487 + * Local APIC should be disabled if it is not going to be used. 36.488 + */ 36.489 + apicbase = rdmsr(MSR_APICBASE); 36.490 + apicbase &= ~APICBASE_ENABLED; 36.491 + wrmsr(MSR_APICBASE, apicbase); 36.492 +} 36.493 + 36.494 +/* 36.495 + * Initialize BBL_CR_CTL3 (Control register 3: used to configure the 36.496 + * L2 cache). 36.497 + */ 36.498 +static void 36.499 +init_mendocino(void) 36.500 +{ 36.501 +#ifdef CPU_PPRO2CELERON 36.502 + u_long eflags; 36.503 + u_int64_t bbl_cr_ctl3; 36.504 + 36.505 + eflags = read_eflags(); 36.506 + disable_intr(); 36.507 + 36.508 + load_cr0(rcr0() | CR0_CD | CR0_NW); 36.509 + wbinvd(); 36.510 + 36.511 + bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); 36.512 + 36.513 + /* If the L2 cache is configured, do nothing. */ 36.514 + if (!(bbl_cr_ctl3 & 1)) { 36.515 + bbl_cr_ctl3 = 0x134052bLL; 36.516 + 36.517 + /* Set L2 Cache Latency (Default: 5). */ 36.518 +#ifdef CPU_CELERON_L2_LATENCY 36.519 +#if CPU_L2_LATENCY > 15 36.520 +#error invalid CPU_L2_LATENCY. 36.521 +#endif 36.522 + bbl_cr_ctl3 |= CPU_L2_LATENCY << 1; 36.523 +#else 36.524 + bbl_cr_ctl3 |= 5 << 1; 36.525 +#endif 36.526 + wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3); 36.527 + } 36.528 + 36.529 + load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); 36.530 + write_eflags(eflags); 36.531 +#endif /* CPU_PPRO2CELERON */ 36.532 +} 36.533 + 36.534 +#endif /* I686_CPU */ 36.535 + 36.536 +/* 36.537 + * Initialize CR4 (Control register 4) to enable SSE instructions. 36.538 + */ 36.539 +void 36.540 +enable_sse(void) 36.541 +{ 36.542 +#ifdef XEN 36.543 + return; 36.544 +#endif 36.545 +#if defined(CPU_ENABLE_SSE) 36.546 + if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 36.547 + load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 36.548 + cpu_fxsr = hw_instruction_sse = 1; 36.549 + } 36.550 +#endif 36.551 +} 36.552 + 36.553 +void 36.554 +initializecpu(void) 36.555 +{ 36.556 + 36.557 + switch (cpu) { 36.558 +#ifdef I486_CPU 36.559 + case CPU_BLUE: 36.560 + init_bluelightning(); 36.561 + break; 36.562 + case CPU_486DLC: 36.563 + init_486dlc(); 36.564 + break; 36.565 + case CPU_CY486DX: 36.566 + init_cy486dx(); 36.567 + break; 36.568 + case CPU_M1SC: 36.569 + init_5x86(); 36.570 + break; 36.571 +#ifdef CPU_I486_ON_386 36.572 + case CPU_486: 36.573 + init_i486_on_386(); 36.574 + break; 36.575 +#endif 36.576 + case CPU_M1: 36.577 + init_6x86(); 36.578 + break; 36.579 +#endif /* I486_CPU */ 36.580 +#ifdef I686_CPU 36.581 + case CPU_M2: 36.582 + init_6x86MX(); 36.583 + break; 36.584 + case CPU_686: 36.585 + if (strcmp(cpu_vendor, "GenuineIntel") == 0) { 36.586 + switch (cpu_id & 0xff0) { 36.587 + case 0x610: 36.588 + init_ppro(); 36.589 + break; 36.590 + case 0x660: 36.591 + init_mendocino(); 36.592 + break; 36.593 + } 36.594 + } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 36.595 +#if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK) 36.596 + /* 36.597 + * Sometimes the BIOS doesn't enable SSE instructions. 36.598 + * According to AMD document 20734, the mobile 36.599 + * Duron, the (mobile) Athlon 4 and the Athlon MP 36.600 + * support SSE. These correspond to cpu_id 0x66X 36.601 + * or 0x67X. 36.602 + */ 36.603 + if ((cpu_feature & CPUID_XMM) == 0 && 36.604 + ((cpu_id & ~0xf) == 0x660 || 36.605 + (cpu_id & ~0xf) == 0x670 || 36.606 + (cpu_id & ~0xf) == 0x680)) { 36.607 + u_int regs[4]; 36.608 + wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000); 36.609 + do_cpuid(1, regs); 36.610 + cpu_feature = regs[3]; 36.611 + } 36.612 +#endif 36.613 + } 36.614 + break; 36.615 +#endif 36.616 + default: 36.617 + break; 36.618 + } 36.619 + enable_sse(); 36.620 + 36.621 +#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 36.622 + /* 36.623 + * OS should flush L1 cache by itself because no PC-98 supports 36.624 + * non-Intel CPUs. Use wbinvd instruction before DMA transfer 36.625 + * when need_pre_dma_flush = 1, use invd instruction after DMA 36.626 + * transfer when need_post_dma_flush = 1. If your CPU upgrade 36.627 + * product supports hardware cache control, you can add the 36.628 + * CPU_UPGRADE_HW_CACHE option in your kernel configuration file. 36.629 + * This option eliminates unneeded cache flush instruction(s). 36.630 + */ 36.631 + if (strcmp(cpu_vendor, "CyrixInstead") == 0) { 36.632 + switch (cpu) { 36.633 +#ifdef I486_CPU 36.634 + case CPU_486DLC: 36.635 + need_post_dma_flush = 1; 36.636 + break; 36.637 + case CPU_M1SC: 36.638 + need_pre_dma_flush = 1; 36.639 + break; 36.640 + case CPU_CY486DX: 36.641 + need_pre_dma_flush = 1; 36.642 +#ifdef CPU_I486_ON_386 36.643 + need_post_dma_flush = 1; 36.644 +#endif 36.645 + break; 36.646 +#endif 36.647 + default: 36.648 + break; 36.649 + } 36.650 + } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 36.651 + switch (cpu_id & 0xFF0) { 36.652 + case 0x470: /* Enhanced Am486DX2 WB */ 36.653 + case 0x490: /* Enhanced Am486DX4 WB */ 36.654 + case 0x4F0: /* Am5x86 WB */ 36.655 + need_pre_dma_flush = 1; 36.656 + break; 36.657 + } 36.658 + } else if (strcmp(cpu_vendor, "IBM") == 0) { 36.659 + need_post_dma_flush = 1; 36.660 + } else { 36.661 +#ifdef CPU_I486_ON_386 36.662 + need_pre_dma_flush = 1; 36.663 +#endif 36.664 + } 36.665 +#endif /* PC98 && !CPU_UPGRADE_HW_CACHE */ 36.666 +} 36.667 + 36.668 +#if defined(I586_CPU) && defined(CPU_WT_ALLOC) 36.669 +/* 36.670 + * Enable write allocate feature of AMD processors. 36.671 + * Following two functions require the Maxmem variable being set. 36.672 + */ 36.673 +void 36.674 +enable_K5_wt_alloc(void) 36.675 +{ 36.676 + u_int64_t msr; 36.677 + register_t savecrit; 36.678 + 36.679 + /* 36.680 + * Write allocate is supported only on models 1, 2, and 3, with 36.681 + * a stepping of 4 or greater. 36.682 + */ 36.683 + if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) { 36.684 + savecrit = intr_disable(); 36.685 + msr = rdmsr(0x83); /* HWCR */ 36.686 + wrmsr(0x83, msr & !(0x10)); 36.687 + 36.688 + /* 36.689 + * We have to tell the chip where the top of memory is, 36.690 + * since video cards could have frame bufferes there, 36.691 + * memory-mapped I/O could be there, etc. 36.692 + */ 36.693 + if(Maxmem > 0) 36.694 + msr = Maxmem / 16; 36.695 + else 36.696 + msr = 0; 36.697 + msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; 36.698 +#ifdef PC98 36.699 + if (!(inb(0x43b) & 4)) { 36.700 + wrmsr(0x86, 0x0ff00f0); 36.701 + msr |= AMD_WT_ALLOC_PRE; 36.702 + } 36.703 +#else 36.704 + /* 36.705 + * There is no way to know wheter 15-16M hole exists or not. 36.706 + * Therefore, we disable write allocate for this range. 36.707 + */ 36.708 + wrmsr(0x86, 0x0ff00f0); 36.709 + msr |= AMD_WT_ALLOC_PRE; 36.710 +#endif 36.711 + wrmsr(0x85, msr); 36.712 + 36.713 + msr=rdmsr(0x83); 36.714 + wrmsr(0x83, msr|0x10); /* enable write allocate */ 36.715 + intr_restore(savecrit); 36.716 + } 36.717 +} 36.718 + 36.719 +void 36.720 +enable_K6_wt_alloc(void) 36.721 +{ 36.722 + quad_t size; 36.723 + u_int64_t whcr; 36.724 + u_long eflags; 36.725 + 36.726 + eflags = read_eflags(); 36.727 + disable_intr(); 36.728 + wbinvd(); 36.729 + 36.730 +#ifdef CPU_DISABLE_CACHE 36.731 + /* 36.732 + * Certain K6-2 box becomes unstable when write allocation is 36.733 + * enabled. 36.734 + */ 36.735 + /* 36.736 + * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 36.737 + * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 36.738 + * All other bits in TR12 have no effect on the processer's operation. 36.739 + * The I/O Trap Restart function (bit 9 of TR12) is always enabled 36.740 + * on the AMD-K6. 36.741 + */ 36.742 + wrmsr(0x0000000e, (u_int64_t)0x0008); 36.743 +#endif 36.744 + /* Don't assume that memory size is aligned with 4M. */ 36.745 + if (Maxmem > 0) 36.746 + size = ((Maxmem >> 8) + 3) >> 2; 36.747 + else 36.748 + size = 0; 36.749 + 36.750 + /* Limit is 508M bytes. */ 36.751 + if (size > 0x7f) 36.752 + size = 0x7f; 36.753 + whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1); 36.754 + 36.755 +#if defined(PC98) || defined(NO_MEMORY_HOLE) 36.756 + if (whcr & (0x7fLL << 1)) { 36.757 +#ifdef PC98 36.758 + /* 36.759 + * If bit 2 of port 0x43b is 0, disable wrte allocate for the 36.760 + * 15-16M range. 36.761 + */ 36.762 + if (!(inb(0x43b) & 4)) 36.763 + whcr &= ~0x0001LL; 36.764 + else 36.765 +#endif 36.766 + whcr |= 0x0001LL; 36.767 + } 36.768 +#else 36.769 + /* 36.770 + * There is no way to know wheter 15-16M hole exists or not. 36.771 + * Therefore, we disable write allocate for this range. 36.772 + */ 36.773 + whcr &= ~0x0001LL; 36.774 +#endif 36.775 + wrmsr(0x0c0000082, whcr); 36.776 + 36.777 + write_eflags(eflags); 36.778 +} 36.779 + 36.780 +void 36.781 +enable_K6_2_wt_alloc(void) 36.782 +{ 36.783 + quad_t size; 36.784 + u_int64_t whcr; 36.785 + u_long eflags; 36.786 + 36.787 + eflags = read_eflags(); 36.788 + disable_intr(); 36.789 + wbinvd(); 36.790 + 36.791 +#ifdef CPU_DISABLE_CACHE 36.792 + /* 36.793 + * Certain K6-2 box becomes unstable when write allocation is 36.794 + * enabled. 36.795 + */ 36.796 + /* 36.797 + * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 36.798 + * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 36.799 + * All other bits in TR12 have no effect on the processer's operation. 36.800 + * The I/O Trap Restart function (bit 9 of TR12) is always enabled 36.801 + * on the AMD-K6. 36.802 + */ 36.803 + wrmsr(0x0000000e, (u_int64_t)0x0008); 36.804 +#endif 36.805 + /* Don't assume that memory size is aligned with 4M. */ 36.806 + if (Maxmem > 0) 36.807 + size = ((Maxmem >> 8) + 3) >> 2; 36.808 + else 36.809 + size = 0; 36.810 + 36.811 + /* Limit is 4092M bytes. */ 36.812 + if (size > 0x3fff) 36.813 + size = 0x3ff; 36.814 + whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22); 36.815 + 36.816 +#if defined(PC98) || defined(NO_MEMORY_HOLE) 36.817 + if (whcr & (0x3ffLL << 22)) { 36.818 +#ifdef PC98 36.819 + /* 36.820 + * If bit 2 of port 0x43b is 0, disable wrte allocate for the 36.821 + * 15-16M range. 36.822 + */ 36.823 + if (!(inb(0x43b) & 4)) 36.824 + whcr &= ~(1LL << 16); 36.825 + else 36.826 +#endif 36.827 + whcr |= 1LL << 16; 36.828 + } 36.829 +#else 36.830 + /* 36.831 + * There is no way to know wheter 15-16M hole exists or not. 36.832 + * Therefore, we disable write allocate for this range. 36.833 + */ 36.834 + whcr &= ~(1LL << 16); 36.835 +#endif 36.836 + wrmsr(0x0c0000082, whcr); 36.837 + 36.838 + write_eflags(eflags); 36.839 +} 36.840 +#endif /* I585_CPU && CPU_WT_ALLOC */ 36.841 + 36.842 +#include "opt_ddb.h" 36.843 +#ifdef DDB 36.844 +#include <ddb/ddb.h> 36.845 +#if 0 36.846 +DB_SHOW_COMMAND(cyrixreg, cyrixreg) 36.847 +{ 36.848 + u_long eflags; 36.849 + u_int cr0; 36.850 + u_char ccr1, ccr2, ccr3; 36.851 + u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0; 36.852 + 36.853 + cr0 = rcr0(); 36.854 + if (strcmp(cpu_vendor,"CyrixInstead") == 0) { 36.855 + eflags = read_eflags(); 36.856 + disable_intr(); 36.857 + 36.858 + 36.859 + if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) { 36.860 + ccr0 = read_cyrix_reg(CCR0); 36.861 + } 36.862 + ccr1 = read_cyrix_reg(CCR1); 36.863 + ccr2 = read_cyrix_reg(CCR2); 36.864 + ccr3 = read_cyrix_reg(CCR3); 36.865 + if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 36.866 + write_cyrix_reg(CCR3, CCR3_MAPEN0); 36.867 + ccr4 = read_cyrix_reg(CCR4); 36.868 + if ((cpu == CPU_M1) || (cpu == CPU_M2)) 36.869 + ccr5 = read_cyrix_reg(CCR5); 36.870 + else 36.871 + pcr0 = read_cyrix_reg(PCR0); 36.872 + write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */ 36.873 + } 36.874 + write_eflags(eflags); 36.875 + 36.876 + if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) 36.877 + printf("CCR0=%x, ", (u_int)ccr0); 36.878 + 36.879 + printf("CCR1=%x, CCR2=%x, CCR3=%x", 36.880 + (u_int)ccr1, (u_int)ccr2, (u_int)ccr3); 36.881 + if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 36.882 + printf(", CCR4=%x, ", (u_int)ccr4); 36.883 + if (cpu == CPU_M1SC) 36.884 + printf("PCR0=%x\n", pcr0); 36.885 + else 36.886 + printf("CCR5=%x\n", ccr5); 36.887 + } 36.888 + } 36.889 + printf("CR0=%x\n", cr0); 36.890 +} 36.891 +#endif 36.892 +#endif /* DDB */
37.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 37.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/intr_machdep.c Thu Mar 24 22:52:13 2005 +0000 37.3 @@ -0,0 +1,326 @@ 37.4 +/*- 37.5 + * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 37.6 + * All rights reserved. 37.7 + * 37.8 + * Redistribution and use in source and binary forms, with or without 37.9 + * modification, are permitted provided that the following conditions 37.10 + * are met: 37.11 + * 1. Redistributions of source code must retain the above copyright 37.12 + * notice, this list of conditions and the following disclaimer. 37.13 + * 2. Redistributions in binary form must reproduce the above copyright 37.14 + * notice, this list of conditions and the following disclaimer in the 37.15 + * documentation and/or other materials provided with the distribution. 37.16 + * 3. Neither the name of the author nor the names of any co-contributors 37.17 + * may be used to endorse or promote products derived from this software 37.18 + * without specific prior written permission. 37.19 + * 37.20 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 37.21 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37.22 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 37.23 + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 37.24 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37.25 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37.26 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37.27 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37.28 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37.29 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37.30 + * SUCH DAMAGE. 37.31 + * 37.32 + * $FreeBSD: src/sys/i386/i386/intr_machdep.c,v 1.4 2003/11/17 06:10:14 peter Exp $ 37.33 + */ 37.34 + 37.35 +/* 37.36 + * Machine dependent interrupt code for i386. For the i386, we have to 37.37 + * deal with different PICs. Thus, we use the passed in vector to lookup 37.38 + * an interrupt source associated with that vector. The interrupt source 37.39 + * describes which PIC the source belongs to and includes methods to handle 37.40 + * that source. 37.41 + */ 37.42 + 37.43 +#include "opt_ddb.h" 37.44 + 37.45 +#include <sys/param.h> 37.46 +#include <sys/bus.h> 37.47 +#include <sys/interrupt.h> 37.48 +#include <sys/lock.h> 37.49 +#include <sys/ktr.h> 37.50 +#include <sys/kernel.h> 37.51 +#include <sys/mutex.h> 37.52 +#include <sys/proc.h> 37.53 +#include <sys/syslog.h> 37.54 +#include <sys/systm.h> 37.55 +#include <machine/clock.h> 37.56 +#include <machine/intr_machdep.h> 37.57 +#ifdef DDB 37.58 +#include <ddb/ddb.h> 37.59 +#endif 37.60 + 37.61 +#define MAX_STRAY_LOG 5 37.62 + 37.63 +typedef void (*mask_fn)(uintptr_t vector); 37.64 + 37.65 +static int intrcnt_index; 37.66 +static struct intsrc *interrupt_sources[NUM_IO_INTS]; 37.67 +static struct mtx intr_table_lock; 37.68 + 37.69 +static void intr_init(void *__dummy); 37.70 +static void intrcnt_setname(const char *name, int index); 37.71 +static void intrcnt_updatename(struct intsrc *is); 37.72 +static void intrcnt_register(struct intsrc *is); 37.73 + 37.74 +/* 37.75 + * Register a new interrupt source with the global interrupt system. 37.76 + * The global interrupts need to be disabled when this function is 37.77 + * called. 37.78 + */ 37.79 +int 37.80 +intr_register_source(struct intsrc *isrc) 37.81 +{ 37.82 + int error, vector; 37.83 + 37.84 + vector = isrc->is_pic->pic_vector(isrc); 37.85 + if (interrupt_sources[vector] != NULL) 37.86 + return (EEXIST); 37.87 + error = ithread_create(&isrc->is_ithread, (uintptr_t)isrc, 0, 37.88 + (mask_fn)isrc->is_pic->pic_disable_source, 37.89 + (mask_fn)isrc->is_pic->pic_enable_source, "irq%d:", vector); 37.90 + if (error) 37.91 + return (error); 37.92 + mtx_lock_spin(&intr_table_lock); 37.93 + if (interrupt_sources[vector] != NULL) { 37.94 + mtx_unlock_spin(&intr_table_lock); 37.95 + ithread_destroy(isrc->is_ithread); 37.96 + return (EEXIST); 37.97 + } 37.98 + intrcnt_register(isrc); 37.99 + interrupt_sources[vector] = isrc; 37.100 + mtx_unlock_spin(&intr_table_lock); 37.101 + return (0); 37.102 +} 37.103 + 37.104 +struct intsrc * 37.105 +intr_lookup_source(int vector) 37.106 +{ 37.107 + 37.108 + return (interrupt_sources[vector]); 37.109 +} 37.110 + 37.111 +int 37.112 +intr_add_handler(const char *name, int vector, driver_intr_t handler, 37.113 + void *arg, enum intr_type flags, void **cookiep) 37.114 +{ 37.115 + struct intsrc *isrc; 37.116 + int error; 37.117 + 37.118 + isrc = intr_lookup_source(vector); 37.119 + if (isrc == NULL) 37.120 + return (EINVAL); 37.121 + 37.122 + error = ithread_add_handler(isrc->is_ithread, name, handler, arg, 37.123 + ithread_priority(flags), flags, cookiep); 37.124 + if (error == 0) { 37.125 + intrcnt_updatename(isrc); 37.126 + isrc->is_pic->pic_enable_intr(isrc); 37.127 + isrc->is_pic->pic_enable_source(isrc); 37.128 + } 37.129 + return (error); 37.130 +} 37.131 + 37.132 +int 37.133 +intr_remove_handler(void *cookie) 37.134 +{ 37.135 + int error; 37.136 + 37.137 + error = ithread_remove_handler(cookie); 37.138 +#ifdef XXX 37.139 + if (error == 0) 37.140 + intrcnt_updatename(/* XXX */); 37.141 +#endif 37.142 + return (error); 37.143 +} 37.144 + 37.145 +int 37.146 +intr_config_intr(int vector, enum intr_trigger trig, enum intr_polarity pol) 37.147 +{ 37.148 + struct intsrc *isrc; 37.149 + 37.150 + isrc = intr_lookup_source(vector); 37.151 + if (isrc == NULL) 37.152 + return (EINVAL); 37.153 + return (isrc->is_pic->pic_config_intr(isrc, trig, pol)); 37.154 +} 37.155 + 37.156 +void 37.157 +intr_execute_handlers(struct intsrc *isrc, struct intrframe *iframe) 37.158 +{ 37.159 + struct thread *td; 37.160 + struct ithd *it; 37.161 + struct intrhand *ih; 37.162 + int error, vector; 37.163 + 37.164 + td = curthread; 37.165 + td->td_intr_nesting_level++; 37.166 + 37.167 + /* 37.168 + * We count software interrupts when we process them. The 37.169 + * code here follows previous practice, but there's an 37.170 + * argument for counting hardware interrupts when they're 37.171 + * processed too. 37.172 + */ 37.173 + atomic_add_long(isrc->is_count, 1); 37.174 + atomic_add_int(&cnt.v_intr, 1); 37.175 + 37.176 + it = isrc->is_ithread; 37.177 + if (it == NULL) 37.178 + ih = NULL; 37.179 + else 37.180 + ih = TAILQ_FIRST(&it->it_handlers); 37.181 + 37.182 + /* 37.183 + * XXX: We assume that IRQ 0 is only used for the ISA timer 37.184 + * device (clk). 37.185 + */ 37.186 + vector = isrc->is_pic->pic_vector(isrc); 37.187 + if (vector == 0) 37.188 + clkintr_pending = 1; 37.189 + 37.190 + 37.191 + if (ih != NULL && ih->ih_flags & IH_FAST) { 37.192 + /* 37.193 + * Execute fast interrupt handlers directly. 37.194 + * To support clock handlers, if a handler registers 37.195 + * with a NULL argument, then we pass it a pointer to 37.196 + * a trapframe as its argument. 37.197 + */ 37.198 + critical_enter(); 37.199 + TAILQ_FOREACH(ih, &it->it_handlers, ih_next) { 37.200 + MPASS(ih->ih_flags & IH_FAST); 37.201 + CTR3(KTR_INTR, "%s: executing handler %p(%p)", 37.202 + __func__, ih->ih_handler, 37.203 + ih->ih_argument == NULL ? iframe : 37.204 + ih->ih_argument); 37.205 + if (ih->ih_argument == NULL) 37.206 + ih->ih_handler(iframe); 37.207 + else 37.208 + ih->ih_handler(ih->ih_argument); 37.209 + } 37.210 + isrc->is_pic->pic_eoi_source(isrc); 37.211 + error = 0; 37.212 + /* XXX */ 37.213 + td->td_pflags &= ~TDP_OWEPREEMPT; 37.214 + critical_exit(); 37.215 + } else { 37.216 + /* 37.217 + * For stray and threaded interrupts, we mask and EOI the 37.218 + * source. 37.219 + */ 37.220 + isrc->is_pic->pic_disable_source(isrc, PIC_EOI); 37.221 + if (ih == NULL) 37.222 + error = EINVAL; 37.223 + else 37.224 + error = ithread_schedule(it); 37.225 + isrc->is_pic->pic_eoi_source(isrc); 37.226 + } 37.227 + 37.228 + if (error == EINVAL) { 37.229 + atomic_add_long(isrc->is_straycount, 1); 37.230 + if (*isrc->is_straycount < MAX_STRAY_LOG) 37.231 + log(LOG_ERR, "stray irq%d\n", vector); 37.232 + else if (*isrc->is_straycount == MAX_STRAY_LOG) 37.233 + log(LOG_CRIT, 37.234 + "too many stray irq %d's: not logging anymore\n", 37.235 + vector); 37.236 + } 37.237 + td->td_intr_nesting_level--; 37.238 + 37.239 +} 37.240 + 37.241 +void 37.242 +intr_resume(void) 37.243 +{ 37.244 + struct intsrc **isrc; 37.245 + int i; 37.246 + 37.247 + mtx_lock_spin(&intr_table_lock); 37.248 + for (i = 0, isrc = interrupt_sources; i < NUM_IO_INTS; i++, isrc++) 37.249 + if (*isrc != NULL && (*isrc)->is_pic->pic_resume != NULL) 37.250 + (*isrc)->is_pic->pic_resume(*isrc); 37.251 + mtx_unlock_spin(&intr_table_lock); 37.252 +} 37.253 + 37.254 +void 37.255 +intr_suspend(void) 37.256 +{ 37.257 + struct intsrc **isrc; 37.258 + int i; 37.259 + 37.260 + mtx_lock_spin(&intr_table_lock); 37.261 + for (i = 0, isrc = interrupt_sources; i < NUM_IO_INTS; i++, isrc++) 37.262 + if (*isrc != NULL && (*isrc)->is_pic->pic_suspend != NULL) 37.263 + (*isrc)->is_pic->pic_suspend(*isrc); 37.264 + mtx_unlock_spin(&intr_table_lock); 37.265 +} 37.266 + 37.267 +static void 37.268 +intrcnt_setname(const char *name, int index) 37.269 +{ 37.270 + 37.271 + snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s", 37.272 + MAXCOMLEN, name); 37.273 +} 37.274 + 37.275 +static void 37.276 +intrcnt_updatename(struct intsrc *is) 37.277 +{ 37.278 + 37.279 + intrcnt_setname(is->is_ithread->it_td->td_proc->p_comm, is->is_index); 37.280 +} 37.281 + 37.282 +static void 37.283 +intrcnt_register(struct intsrc *is) 37.284 +{ 37.285 + char straystr[MAXCOMLEN + 1]; 37.286 + 37.287 + /* mtx_assert(&intr_table_lock, MA_OWNED); */ 37.288 + KASSERT(is->is_ithread != NULL, ("%s: isrc with no ithread", __func__)); 37.289 + is->is_index = intrcnt_index; 37.290 + intrcnt_index += 2; 37.291 + snprintf(straystr, MAXCOMLEN + 1, "stray irq%d", 37.292 + is->is_pic->pic_vector(is)); 37.293 + intrcnt_updatename(is); 37.294 + is->is_count = &intrcnt[is->is_index]; 37.295 + intrcnt_setname(straystr, is->is_index + 1); 37.296 + is->is_straycount = &intrcnt[is->is_index + 1]; 37.297 +} 37.298 + 37.299 +static void 37.300 +intr_init(void *dummy __unused) 37.301 +{ 37.302 + 37.303 + intrcnt_setname("???", 0); 37.304 + intrcnt_index = 1; 37.305 + mtx_init(&intr_table_lock, "intr table", NULL, MTX_SPIN); 37.306 +} 37.307 +SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL) 37.308 + 37.309 +#ifdef DDB 37.310 +/* 37.311 + * Dump data about interrupt handlers 37.312 + */ 37.313 +DB_SHOW_COMMAND(irqs, db_show_irqs) 37.314 +{ 37.315 + struct intsrc **isrc; 37.316 + int i, quit, verbose; 37.317 + 37.318 + quit = 0; 37.319 + if (strcmp(modif, "v") == 0) 37.320 + verbose = 1; 37.321 + else 37.322 + verbose = 0; 37.323 + isrc = interrupt_sources; 37.324 + db_setup_paging(db_simple_pager, &quit, DB_LINES_PER_PAGE); 37.325 + for (i = 0; i < NUM_IO_INTS && !quit; i++, isrc++) 37.326 + if (*isrc != NULL) 37.327 + db_dump_ithread((*isrc)->is_ithread, verbose); 37.328 +} 37.329 +#endif
38.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 38.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/io_apic.c Thu Mar 24 22:52:13 2005 +0000 38.3 @@ -0,0 +1,850 @@ 38.4 +/*- 38.5 + * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 38.6 + * All rights reserved. 38.7 + * 38.8 + * Redistribution and use in source and binary forms, with or without 38.9 + * modification, are permitted provided that the following conditions 38.10 + * are met: 38.11 + * 1. Redistributions of source code must retain the above copyright 38.12 + * notice, this list of conditions and the following disclaimer. 38.13 + * 2. Redistributions in binary form must reproduce the above copyright 38.14 + * notice, this list of conditions and the following disclaimer in the 38.15 + * documentation and/or other materials provided with the distribution. 38.16 + * 3. Neither the name of the author nor the names of any co-contributors 38.17 + * may be used to endorse or promote products derived from this software 38.18 + * without specific prior written permission. 38.19 + * 38.20 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 38.21 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 38.22 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 38.23 + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 38.24 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38.25 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38.26 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38.27 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38.28 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38.29 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38.30 + * SUCH DAMAGE. 38.31 + */ 38.32 + 38.33 +#include <sys/cdefs.h> 38.34 +__FBSDID("$FreeBSD: src/sys/i386/i386/io_apic.c,v 1.14 2004/08/02 15:31:10 scottl Exp $"); 38.35 + 38.36 +#include "opt_isa.h" 38.37 +#include "opt_no_mixed_mode.h" 38.38 + 38.39 +#include <sys/param.h> 38.40 +#include <sys/systm.h> 38.41 +#include <sys/bus.h> 38.42 +#include <sys/kernel.h> 38.43 +#include <sys/malloc.h> 38.44 +#include <sys/lock.h> 38.45 +#include <sys/mutex.h> 38.46 + 38.47 +#include <vm/vm.h> 38.48 +#include <vm/pmap.h> 38.49 + 38.50 +#include <machine/apicreg.h> 38.51 +#include <machine/frame.h> 38.52 +#include <machine/intr_machdep.h> 38.53 +#include <machine/apicvar.h> 38.54 +#include <machine/segments.h> 38.55 + 38.56 +#define IOAPIC_ISA_INTS 16 38.57 +#define IOAPIC_MEM_REGION 32 38.58 +#define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2) 38.59 +#define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1) 38.60 + 38.61 +#define VECTOR_EXTINT 252 38.62 +#define VECTOR_NMI 253 38.63 +#define VECTOR_SMI 254 38.64 +#define VECTOR_DISABLED 255 38.65 + 38.66 +#define DEST_NONE -1 38.67 +#define DEST_EXTINT -2 38.68 + 38.69 +#define TODO printf("%s: not implemented!\n", __func__) 38.70 + 38.71 +MALLOC_DEFINE(M_IOAPIC, "I/O APIC", "I/O APIC structures"); 38.72 + 38.73 +/* 38.74 + * New interrupt support code.. 38.75 + * 38.76 + * XXX: we really should have the interrupt cookie passed up from new-bus 38.77 + * just be a int pin, and not map 1:1 to interrupt vector number but should 38.78 + * use INTR_TYPE_FOO to set priority bands for device classes and do all the 38.79 + * magic remapping of intpin to vector in here. For now we just cheat as on 38.80 + * ia64 and map intpin X to vector NRSVIDT + X. Note that we assume that the 38.81 + * first IO APIC has ISA interrupts on pins 1-15. Not sure how you are 38.82 + * really supposed to figure out which IO APIC in a system with multiple IO 38.83 + * APIC's actually has the ISA interrupts routed to it. As far as interrupt 38.84 + * pin numbers, we use the ACPI System Interrupt number model where each 38.85 + * IO APIC has a contiguous chunk of the System Interrupt address space. 38.86 + */ 38.87 + 38.88 +/* 38.89 + * Direct the ExtINT pin on the first I/O APIC to a logical cluster of 38.90 + * CPUs rather than a physical destination of just the BSP. 38.91 + * 38.92 + * Note: This is disabled by default as test systems seem to croak with it 38.93 + * enabled. 38.94 +#define ENABLE_EXTINT_LOGICAL_DESTINATION 38.95 + */ 38.96 + 38.97 +struct ioapic_intsrc { 38.98 + struct intsrc io_intsrc; 38.99 + u_int io_intpin:8; 38.100 + u_int io_vector:8; 38.101 + u_int io_activehi:1; 38.102 + u_int io_edgetrigger:1; 38.103 + u_int io_masked:1; 38.104 + int io_dest:5; 38.105 + int io_bus:4; 38.106 +}; 38.107 + 38.108 +struct ioapic { 38.109 + struct pic io_pic; 38.110 + u_int io_id:8; /* logical ID */ 38.111 + u_int io_apic_id:4; 38.112 + u_int io_intbase:8; /* System Interrupt base */ 38.113 + u_int io_numintr:8; 38.114 + volatile ioapic_t *io_addr; /* XXX: should use bus_space */ 38.115 + STAILQ_ENTRY(ioapic) io_next; 38.116 + struct ioapic_intsrc io_pins[0]; 38.117 +}; 38.118 + 38.119 +static u_int ioapic_read(volatile ioapic_t *apic, int reg); 38.120 +static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val); 38.121 +static const char *ioapic_bus_string(int bus_type); 38.122 +static void ioapic_print_vector(struct ioapic_intsrc *intpin); 38.123 +static void ioapic_enable_source(struct intsrc *isrc); 38.124 +static void ioapic_disable_source(struct intsrc *isrc, int eoi); 38.125 +static void ioapic_eoi_source(struct intsrc *isrc); 38.126 +static void ioapic_enable_intr(struct intsrc *isrc); 38.127 +static int ioapic_vector(struct intsrc *isrc); 38.128 +static int ioapic_source_pending(struct intsrc *isrc); 38.129 +static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 38.130 + enum intr_polarity pol); 38.131 +static void ioapic_suspend(struct intsrc *isrc); 38.132 +static void ioapic_resume(struct intsrc *isrc); 38.133 +static void ioapic_program_destination(struct ioapic_intsrc *intpin); 38.134 +static void ioapic_program_intpin(struct ioapic_intsrc *intpin); 38.135 +static void ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin); 38.136 + 38.137 +static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list); 38.138 +struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source, 38.139 + ioapic_eoi_source, ioapic_enable_intr, 38.140 + ioapic_vector, ioapic_source_pending, 38.141 + ioapic_suspend, ioapic_resume, 38.142 + ioapic_config_intr }; 38.143 + 38.144 +static int bsp_id, current_cluster, logical_clusters, next_ioapic_base; 38.145 +static u_int mixed_mode_enabled, next_id, program_logical_dest; 38.146 +#ifdef NO_MIXED_MODE 38.147 +static int mixed_mode_active = 0; 38.148 +#else 38.149 +static int mixed_mode_active = 1; 38.150 +#endif 38.151 +TUNABLE_INT("hw.apic.mixed_mode", &mixed_mode_active); 38.152 + 38.153 +static __inline void 38.154 +_ioapic_eoi_source(struct intsrc *isrc) 38.155 +{ 38.156 + lapic_eoi(); 38.157 +} 38.158 + 38.159 +static u_int 38.160 +ioapic_read(volatile ioapic_t *apic, int reg) 38.161 +{ 38.162 + 38.163 + mtx_assert(&icu_lock, MA_OWNED); 38.164 + apic->ioregsel = reg; 38.165 + return (apic->iowin); 38.166 +} 38.167 + 38.168 +static void 38.169 +ioapic_write(volatile ioapic_t *apic, int reg, u_int val) 38.170 +{ 38.171 + 38.172 + mtx_assert(&icu_lock, MA_OWNED); 38.173 + apic->ioregsel = reg; 38.174 + apic->iowin = val; 38.175 +} 38.176 + 38.177 +static const char * 38.178 +ioapic_bus_string(int bus_type) 38.179 +{ 38.180 + 38.181 + switch (bus_type) { 38.182 + case APIC_BUS_ISA: 38.183 + return ("ISA"); 38.184 + case APIC_BUS_EISA: 38.185 + return ("EISA"); 38.186 + case APIC_BUS_PCI: 38.187 + return ("PCI"); 38.188 + default: 38.189 + return ("unknown"); 38.190 + } 38.191 +} 38.192 + 38.193 +static void 38.194 +ioapic_print_vector(struct ioapic_intsrc *intpin) 38.195 +{ 38.196 + 38.197 + switch (intpin->io_vector) { 38.198 + case VECTOR_DISABLED: 38.199 + printf("disabled"); 38.200 + break; 38.201 + case VECTOR_EXTINT: 38.202 + printf("ExtINT"); 38.203 + break; 38.204 + case VECTOR_NMI: 38.205 + printf("NMI"); 38.206 + break; 38.207 + case VECTOR_SMI: 38.208 + printf("SMI"); 38.209 + break; 38.210 + default: 38.211 + printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus), 38.212 + intpin->io_vector); 38.213 + } 38.214 +} 38.215 + 38.216 +static void 38.217 +ioapic_enable_source(struct intsrc *isrc) 38.218 +{ 38.219 + struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 38.220 + struct ioapic *io = (struct ioapic *)isrc->is_pic; 38.221 + uint32_t flags; 38.222 + 38.223 + mtx_lock_spin(&icu_lock); 38.224 + if (intpin->io_masked) { 38.225 + flags = ioapic_read(io->io_addr, 38.226 + IOAPIC_REDTBL_LO(intpin->io_intpin)); 38.227 + flags &= ~(IOART_INTMASK); 38.228 + ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 38.229 + flags); 38.230 + intpin->io_masked = 0; 38.231 + } 38.232 + mtx_unlock_spin(&icu_lock); 38.233 +} 38.234 + 38.235 +static void 38.236 +ioapic_disable_source(struct intsrc *isrc, int eoi) 38.237 +{ 38.238 + struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 38.239 + struct ioapic *io = (struct ioapic *)isrc->is_pic; 38.240 + uint32_t flags; 38.241 + 38.242 + mtx_lock_spin(&icu_lock); 38.243 + if (!intpin->io_masked && !intpin->io_edgetrigger) { 38.244 + flags = ioapic_read(io->io_addr, 38.245 + IOAPIC_REDTBL_LO(intpin->io_intpin)); 38.246 + flags |= IOART_INTMSET; 38.247 + ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 38.248 + flags); 38.249 + intpin->io_masked = 1; 38.250 + } 38.251 + 38.252 + if (eoi == PIC_EOI) 38.253 + _ioapic_eoi_source(isrc); 38.254 + 38.255 + mtx_unlock_spin(&icu_lock); 38.256 +} 38.257 + 38.258 +static void 38.259 +ioapic_eoi_source(struct intsrc *isrc) 38.260 +{ 38.261 + 38.262 + _ioapic_eoi_source(isrc); 38.263 +} 38.264 + 38.265 +/* 38.266 + * Completely program an intpin based on the data in its interrupt source 38.267 + * structure. 38.268 + */ 38.269 +static void 38.270 +ioapic_program_intpin(struct ioapic_intsrc *intpin) 38.271 +{ 38.272 + struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic; 38.273 + uint32_t low, high, value; 38.274 + 38.275 + /* 38.276 + * For pins routed via mixed mode or disabled, just ensure that 38.277 + * they are masked. 38.278 + */ 38.279 + if (intpin->io_dest == DEST_EXTINT || 38.280 + intpin->io_vector == VECTOR_DISABLED) { 38.281 + low = ioapic_read(io->io_addr, 38.282 + IOAPIC_REDTBL_LO(intpin->io_intpin)); 38.283 + if ((low & IOART_INTMASK) == IOART_INTMCLR) 38.284 + ioapic_write(io->io_addr, 38.285 + IOAPIC_REDTBL_LO(intpin->io_intpin), 38.286 + low | IOART_INTMSET); 38.287 + return; 38.288 + } 38.289 + 38.290 + /* Set the destination. */ 38.291 + if (intpin->io_dest == DEST_NONE) { 38.292 + low = IOART_DESTPHY; 38.293 + high = bsp_id << APIC_ID_SHIFT; 38.294 + } else { 38.295 + low = IOART_DESTLOG; 38.296 + high = (intpin->io_dest << APIC_ID_CLUSTER_SHIFT | 38.297 + APIC_ID_CLUSTER_ID) << APIC_ID_SHIFT; 38.298 + } 38.299 + 38.300 + /* Program the rest of the low word. */ 38.301 + if (intpin->io_edgetrigger) 38.302 + low |= IOART_TRGREDG; 38.303 + else 38.304 + low |= IOART_TRGRLVL; 38.305 + if (intpin->io_activehi) 38.306 + low |= IOART_INTAHI; 38.307 + else 38.308 + low |= IOART_INTALO; 38.309 + if (intpin->io_masked) 38.310 + low |= IOART_INTMSET; 38.311 + switch (intpin->io_vector) { 38.312 + case VECTOR_EXTINT: 38.313 + KASSERT(intpin->io_edgetrigger, 38.314 + ("EXTINT not edge triggered")); 38.315 + low |= IOART_DELEXINT; 38.316 + break; 38.317 + case VECTOR_NMI: 38.318 + KASSERT(intpin->io_edgetrigger, 38.319 + ("NMI not edge triggered")); 38.320 + low |= IOART_DELNMI; 38.321 + break; 38.322 + case VECTOR_SMI: 38.323 + KASSERT(intpin->io_edgetrigger, 38.324 + ("SMI not edge triggered")); 38.325 + low |= IOART_DELSMI; 38.326 + break; 38.327 + default: 38.328 + low |= IOART_DELLOPRI | apic_irq_to_idt(intpin->io_vector); 38.329 + } 38.330 + 38.331 + /* Write the values to the APIC. */ 38.332 + mtx_lock_spin(&icu_lock); 38.333 + ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low); 38.334 + value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin)); 38.335 + value &= ~IOART_DEST; 38.336 + value |= high; 38.337 + ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value); 38.338 + mtx_unlock_spin(&icu_lock); 38.339 +} 38.340 + 38.341 +/* 38.342 + * Program an individual intpin's logical destination. 38.343 + */ 38.344 +static void 38.345 +ioapic_program_destination(struct ioapic_intsrc *intpin) 38.346 +{ 38.347 + struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic; 38.348 + 38.349 + KASSERT(intpin->io_dest != DEST_NONE, 38.350 + ("intpin not assigned to a cluster")); 38.351 + KASSERT(intpin->io_dest != DEST_EXTINT, 38.352 + ("intpin routed via ExtINT")); 38.353 + if (bootverbose) { 38.354 + printf("ioapic%u: routing intpin %u (", io->io_id, 38.355 + intpin->io_intpin); 38.356 + ioapic_print_vector(intpin); 38.357 + printf(") to cluster %u\n", intpin->io_dest); 38.358 + } 38.359 + ioapic_program_intpin(intpin); 38.360 +} 38.361 + 38.362 +static void 38.363 +ioapic_assign_cluster(struct ioapic_intsrc *intpin) 38.364 +{ 38.365 + 38.366 + /* 38.367 + * Assign this intpin to a logical APIC cluster in a 38.368 + * round-robin fashion. We don't actually use the logical 38.369 + * destination for this intpin until after all the CPU's 38.370 + * have been started so that we don't end up with interrupts 38.371 + * that don't go anywhere. Another alternative might be to 38.372 + * start up the CPU's earlier so that they can handle interrupts 38.373 + * sooner. 38.374 + */ 38.375 + intpin->io_dest = current_cluster; 38.376 + current_cluster++; 38.377 + if (current_cluster >= logical_clusters) 38.378 + current_cluster = 0; 38.379 + if (program_logical_dest) 38.380 + ioapic_program_destination(intpin); 38.381 +} 38.382 + 38.383 +static void 38.384 +ioapic_enable_intr(struct intsrc *isrc) 38.385 +{ 38.386 + struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 38.387 + 38.388 + KASSERT(intpin->io_dest != DEST_EXTINT, 38.389 + ("ExtINT pin trying to use ioapic enable_intr method")); 38.390 + if (intpin->io_dest == DEST_NONE) { 38.391 + ioapic_assign_cluster(intpin); 38.392 + lapic_enable_intr(intpin->io_vector); 38.393 + } 38.394 +} 38.395 + 38.396 +static int 38.397 +ioapic_vector(struct intsrc *isrc) 38.398 +{ 38.399 + struct ioapic_intsrc *pin; 38.400 + 38.401 + pin = (struct ioapic_intsrc *)isrc; 38.402 + return (pin->io_vector); 38.403 +} 38.404 + 38.405 +static int 38.406 +ioapic_source_pending(struct intsrc *isrc) 38.407 +{ 38.408 + struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 38.409 + 38.410 + return (lapic_intr_pending(intpin->io_vector)); 38.411 +} 38.412 + 38.413 +static int 38.414 +ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 38.415 + enum intr_polarity pol) 38.416 +{ 38.417 + struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 38.418 + struct ioapic *io = (struct ioapic *)isrc->is_pic; 38.419 + int changed; 38.420 + 38.421 + KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM), 38.422 + ("%s: Conforming trigger or polarity\n", __func__)); 38.423 + 38.424 + /* 38.425 + * EISA interrupts always use active high polarity, so don't allow 38.426 + * them to be set to active low. 38.427 + * 38.428 + * XXX: Should we write to the ELCR if the trigger mode changes for 38.429 + * an EISA IRQ? 38.430 + */ 38.431 + if (intpin->io_bus == APIC_BUS_EISA) 38.432 + pol = INTR_POLARITY_HIGH; 38.433 + changed = 0; 38.434 + if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) { 38.435 + if (bootverbose) 38.436 + printf("ioapic%u: Changing trigger for pin %u to %s\n", 38.437 + io->io_id, intpin->io_intpin, 38.438 + trig == INTR_TRIGGER_EDGE ? "edge" : "level"); 38.439 + intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE); 38.440 + changed++; 38.441 + } 38.442 + if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) { 38.443 + if (bootverbose) 38.444 + printf("ioapic%u: Changing polarity for pin %u to %s\n", 38.445 + io->io_id, intpin->io_intpin, 38.446 + pol == INTR_POLARITY_HIGH ? "high" : "low"); 38.447 + intpin->io_activehi = (pol == INTR_POLARITY_HIGH); 38.448 + changed++; 38.449 + } 38.450 + if (changed) 38.451 + ioapic_program_intpin(intpin); 38.452 + return (0); 38.453 +} 38.454 + 38.455 +static void 38.456 +ioapic_suspend(struct intsrc *isrc) 38.457 +{ 38.458 + 38.459 + TODO; 38.460 +} 38.461 + 38.462 +static void 38.463 +ioapic_resume(struct intsrc *isrc) 38.464 +{ 38.465 + 38.466 + ioapic_program_intpin((struct ioapic_intsrc *)isrc); 38.467 +} 38.468 + 38.469 +/* 38.470 + * APIC enumerators call this function to indicate that the 8259A AT PICs 38.471 + * are available and that mixed mode can be used. 38.472 + */ 38.473 +void 38.474 +ioapic_enable_mixed_mode(void) 38.475 +{ 38.476 + 38.477 + mixed_mode_enabled = 1; 38.478 +} 38.479 + 38.480 +/* 38.481 + * Allocate and return a logical cluster ID. Note that the first time 38.482 + * this is called, it returns cluster 0. ioapic_enable_intr() treats 38.483 + * the two cases of logical_clusters == 0 and logical_clusters == 1 the 38.484 + * same: one cluster of ID 0 exists. The logical_clusters == 0 case is 38.485 + * for UP kernels, which should never call this function. 38.486 + */ 38.487 +int 38.488 +ioapic_next_logical_cluster(void) 38.489 +{ 38.490 + 38.491 + if (logical_clusters >= APIC_MAX_CLUSTER) 38.492 + panic("WARNING: Local APIC cluster IDs exhausted!"); 38.493 + return (logical_clusters++); 38.494 +} 38.495 + 38.496 +/* 38.497 + * Create a plain I/O APIC object. 38.498 + */ 38.499 +void * 38.500 +ioapic_create(uintptr_t addr, int32_t apic_id, int intbase) 38.501 +{ 38.502 + struct ioapic *io; 38.503 + struct ioapic_intsrc *intpin; 38.504 + volatile ioapic_t *apic; 38.505 + u_int numintr, i; 38.506 + uint32_t value; 38.507 + 38.508 + apic = (ioapic_t *)pmap_mapdev(addr, IOAPIC_MEM_REGION); 38.509 + mtx_lock_spin(&icu_lock); 38.510 + numintr = ((ioapic_read(apic, IOAPIC_VER) & IOART_VER_MAXREDIR) >> 38.511 + MAXREDIRSHIFT) + 1; 38.512 + mtx_unlock_spin(&icu_lock); 38.513 + io = malloc(sizeof(struct ioapic) + 38.514 + numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK); 38.515 + io->io_pic = ioapic_template; 38.516 + mtx_lock_spin(&icu_lock); 38.517 + io->io_id = next_id++; 38.518 + io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT; 38.519 + if (apic_id != -1 && io->io_apic_id != apic_id) { 38.520 + ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT); 38.521 + mtx_unlock_spin(&icu_lock); 38.522 + io->io_apic_id = apic_id; 38.523 + printf("ioapic%u: Changing APIC ID to %d\n", io->io_id, 38.524 + apic_id); 38.525 + } else 38.526 + mtx_unlock_spin(&icu_lock); 38.527 + if (intbase == -1) { 38.528 + intbase = next_ioapic_base; 38.529 + printf("ioapic%u: Assuming intbase of %d\n", io->io_id, 38.530 + intbase); 38.531 + } else if (intbase != next_ioapic_base) 38.532 + printf("ioapic%u: WARNING: intbase %d != expected base %d\n", 38.533 + io->io_id, intbase, next_ioapic_base); 38.534 + io->io_intbase = intbase; 38.535 + next_ioapic_base = intbase + numintr; 38.536 + io->io_numintr = numintr; 38.537 + io->io_addr = apic; 38.538 + 38.539 + /* 38.540 + * Initialize pins. Start off with interrupts disabled. Default 38.541 + * to active-hi and edge-triggered for ISA interrupts and active-lo 38.542 + * and level-triggered for all others. 38.543 + */ 38.544 + bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr); 38.545 + mtx_lock_spin(&icu_lock); 38.546 + for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) { 38.547 + intpin->io_intsrc.is_pic = (struct pic *)io; 38.548 + intpin->io_intpin = i; 38.549 + intpin->io_vector = intbase + i; 38.550 + 38.551 + /* 38.552 + * Assume that pin 0 on the first I/O APIC is an ExtINT pin 38.553 + * and that pins 1-15 are ISA interrupts. Assume that all 38.554 + * other pins are PCI interrupts. 38.555 + */ 38.556 + if (intpin->io_vector == 0) 38.557 + ioapic_set_extint(io, i); 38.558 + else if (intpin->io_vector < IOAPIC_ISA_INTS) { 38.559 + intpin->io_bus = APIC_BUS_ISA; 38.560 + intpin->io_activehi = 1; 38.561 + intpin->io_edgetrigger = 1; 38.562 + intpin->io_masked = 1; 38.563 + } else { 38.564 + intpin->io_bus = APIC_BUS_PCI; 38.565 + intpin->io_activehi = 0; 38.566 + intpin->io_edgetrigger = 0; 38.567 + intpin->io_masked = 1; 38.568 + } 38.569 + 38.570 + /* 38.571 + * Route interrupts to the BSP by default using physical 38.572 + * addressing. Vectored interrupts get readdressed using 38.573 + * logical IDs to CPU clusters when they are enabled. 38.574 + */ 38.575 + intpin->io_dest = DEST_NONE; 38.576 + if (bootverbose && intpin->io_vector != VECTOR_DISABLED) { 38.577 + printf("ioapic%u: intpin %d -> ", io->io_id, i); 38.578 + ioapic_print_vector(intpin); 38.579 + printf(" (%s, %s)\n", intpin->io_edgetrigger ? 38.580 + "edge" : "level", intpin->io_activehi ? "high" : 38.581 + "low"); 38.582 + } 38.583 + value = ioapic_read(apic, IOAPIC_REDTBL_LO(i)); 38.584 + ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET); 38.585 + } 38.586 + mtx_unlock_spin(&icu_lock); 38.587 + 38.588 + return (io); 38.589 +} 38.590 + 38.591 +int 38.592 +ioapic_get_vector(void *cookie, u_int pin) 38.593 +{ 38.594 + struct ioapic *io; 38.595 + 38.596 + io = (struct ioapic *)cookie; 38.597 + if (pin >= io->io_numintr) 38.598 + return (-1); 38.599 + return (io->io_pins[pin].io_vector); 38.600 +} 38.601 + 38.602 +int 38.603 +ioapic_disable_pin(void *cookie, u_int pin) 38.604 +{ 38.605 + struct ioapic *io; 38.606 + 38.607 + io = (struct ioapic *)cookie; 38.608 + if (pin >= io->io_numintr) 38.609 + return (EINVAL); 38.610 + if (io->io_pins[pin].io_vector == VECTOR_DISABLED) 38.611 + return (EINVAL); 38.612 + io->io_pins[pin].io_vector = VECTOR_DISABLED; 38.613 + if (bootverbose) 38.614 + printf("ioapic%u: intpin %d disabled\n", io->io_id, pin); 38.615 + return (0); 38.616 +} 38.617 + 38.618 +int 38.619 +ioapic_remap_vector(void *cookie, u_int pin, int vector) 38.620 +{ 38.621 + struct ioapic *io; 38.622 + 38.623 + io = (struct ioapic *)cookie; 38.624 + if (pin >= io->io_numintr || vector < 0) 38.625 + return (EINVAL); 38.626 + if (io->io_pins[pin].io_vector >= NUM_IO_INTS) 38.627 + return (EINVAL); 38.628 + io->io_pins[pin].io_vector = vector; 38.629 + if (bootverbose) 38.630 + printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id, 38.631 + vector, pin); 38.632 + return (0); 38.633 +} 38.634 + 38.635 +int 38.636 +ioapic_set_bus(void *cookie, u_int pin, int bus_type) 38.637 +{ 38.638 + struct ioapic *io; 38.639 + 38.640 + if (bus_type < 0 || bus_type > APIC_BUS_MAX) 38.641 + return (EINVAL); 38.642 + io = (struct ioapic *)cookie; 38.643 + if (pin >= io->io_numintr) 38.644 + return (EINVAL); 38.645 + if (io->io_pins[pin].io_vector >= NUM_IO_INTS) 38.646 + return (EINVAL); 38.647 + io->io_pins[pin].io_bus = bus_type; 38.648 + if (bootverbose) 38.649 + printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin, 38.650 + ioapic_bus_string(bus_type)); 38.651 + return (0); 38.652 +} 38.653 + 38.654 +int 38.655 +ioapic_set_nmi(void *cookie, u_int pin) 38.656 +{ 38.657 + struct ioapic *io; 38.658 + 38.659 + io = (struct ioapic *)cookie; 38.660 + if (pin >= io->io_numintr) 38.661 + return (EINVAL); 38.662 + if (io->io_pins[pin].io_vector == VECTOR_NMI) 38.663 + return (0); 38.664 + if (io->io_pins[pin].io_vector >= NUM_IO_INTS) 38.665 + return (EINVAL); 38.666 + io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 38.667 + io->io_pins[pin].io_vector = VECTOR_NMI; 38.668 + io->io_pins[pin].io_masked = 0; 38.669 + io->io_pins[pin].io_edgetrigger = 1; 38.670 + io->io_pins[pin].io_activehi = 1; 38.671 + if (bootverbose) 38.672 + printf("ioapic%u: Routing NMI -> intpin %d\n", 38.673 + io->io_id, pin); 38.674 + return (0); 38.675 +} 38.676 + 38.677 +int 38.678 +ioapic_set_smi(void *cookie, u_int pin) 38.679 +{ 38.680 + struct ioapic *io; 38.681 + 38.682 + io = (struct ioapic *)cookie; 38.683 + if (pin >= io->io_numintr) 38.684 + return (EINVAL); 38.685 + if (io->io_pins[pin].io_vector == VECTOR_SMI) 38.686 + return (0); 38.687 + if (io->io_pins[pin].io_vector >= NUM_IO_INTS) 38.688 + return (EINVAL); 38.689 + io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 38.690 + io->io_pins[pin].io_vector = VECTOR_SMI; 38.691 + io->io_pins[pin].io_masked = 0; 38.692 + io->io_pins[pin].io_edgetrigger = 1; 38.693 + io->io_pins[pin].io_activehi = 1; 38.694 + if (bootverbose) 38.695 + printf("ioapic%u: Routing SMI -> intpin %d\n", 38.696 + io->io_id, pin); 38.697 + return (0); 38.698 +} 38.699 + 38.700 +int 38.701 +ioapic_set_extint(void *cookie, u_int pin) 38.702 +{ 38.703 + struct ioapic *io; 38.704 + 38.705 + io = (struct ioapic *)cookie; 38.706 + if (pin >= io->io_numintr) 38.707 + return (EINVAL); 38.708 + if (io->io_pins[pin].io_vector == VECTOR_EXTINT) 38.709 + return (0); 38.710 + if (io->io_pins[pin].io_vector >= NUM_IO_INTS) 38.711 + return (EINVAL); 38.712 + io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 38.713 + io->io_pins[pin].io_vector = VECTOR_EXTINT; 38.714 + 38.715 + /* Enable this pin if mixed mode is available and active. */ 38.716 + if (mixed_mode_enabled && mixed_mode_active) 38.717 + io->io_pins[pin].io_masked = 0; 38.718 + else 38.719 + io->io_pins[pin].io_masked = 1; 38.720 + io->io_pins[pin].io_edgetrigger = 1; 38.721 + io->io_pins[pin].io_activehi = 1; 38.722 + if (bootverbose) 38.723 + printf("ioapic%u: Routing external 8259A's -> intpin %d\n", 38.724 + io->io_id, pin); 38.725 + return (0); 38.726 +} 38.727 + 38.728 +int 38.729 +ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol) 38.730 +{ 38.731 + struct ioapic *io; 38.732 + 38.733 + io = (struct ioapic *)cookie; 38.734 + if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM) 38.735 + return (EINVAL); 38.736 + if (io->io_pins[pin].io_vector >= NUM_IO_INTS) 38.737 + return (EINVAL); 38.738 + io->io_pins[pin].io_activehi = (pol == INTR_POLARITY_HIGH); 38.739 + if (bootverbose) 38.740 + printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin, 38.741 + pol == INTR_POLARITY_HIGH ? "high" : "low"); 38.742 + return (0); 38.743 +} 38.744 + 38.745 +int 38.746 +ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger) 38.747 +{ 38.748 + struct ioapic *io; 38.749 + 38.750 + io = (struct ioapic *)cookie; 38.751 + if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM) 38.752 + return (EINVAL); 38.753 + if (io->io_pins[pin].io_vector >= NUM_IO_INTS) 38.754 + return (EINVAL); 38.755 + io->io_pins[pin].io_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 38.756 + if (bootverbose) 38.757 + printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin, 38.758 + trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 38.759 + return (0); 38.760 +} 38.761 + 38.762 +/* 38.763 + * Register a complete I/O APIC object with the interrupt subsystem. 38.764 + */ 38.765 +void 38.766 +ioapic_register(void *cookie) 38.767 +{ 38.768 + struct ioapic_intsrc *pin; 38.769 + struct ioapic *io; 38.770 + volatile ioapic_t *apic; 38.771 + uint32_t flags; 38.772 + int i; 38.773 + 38.774 + io = (struct ioapic *)cookie; 38.775 + apic = io->io_addr; 38.776 + mtx_lock_spin(&icu_lock); 38.777 + flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION; 38.778 + STAILQ_INSERT_TAIL(&ioapic_list, io, io_next); 38.779 + mtx_unlock_spin(&icu_lock); 38.780 + printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n", 38.781 + io->io_id, flags >> 4, flags & 0xf, io->io_intbase, 38.782 + io->io_intbase + io->io_numintr - 1); 38.783 + bsp_id = PCPU_GET(apic_id); 38.784 + for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) { 38.785 + /* 38.786 + * Finish initializing the pins by programming the vectors 38.787 + * and delivery mode. 38.788 + */ 38.789 + if (pin->io_vector == VECTOR_DISABLED) 38.790 + continue; 38.791 + ioapic_program_intpin(pin); 38.792 + if (pin->io_vector >= NUM_IO_INTS) 38.793 + continue; 38.794 + /* 38.795 + * Route IRQ0 via the 8259A using mixed mode if mixed mode 38.796 + * is available and turned on. 38.797 + */ 38.798 + if (pin->io_vector == 0 && mixed_mode_active && 38.799 + mixed_mode_enabled) 38.800 + ioapic_setup_mixed_mode(pin); 38.801 + else 38.802 + intr_register_source(&pin->io_intsrc); 38.803 + } 38.804 +} 38.805 + 38.806 +/* 38.807 + * Program all the intpins to use logical destinations once the AP's 38.808 + * have been launched. 38.809 + */ 38.810 +static void 38.811 +ioapic_set_logical_destinations(void *arg __unused) 38.812 +{ 38.813 + struct ioapic *io; 38.814 + int i; 38.815 + 38.816 + program_logical_dest = 1; 38.817 + STAILQ_FOREACH(io, &ioapic_list, io_next) 38.818 + for (i = 0; i < io->io_numintr; i++) 38.819 + if (io->io_pins[i].io_dest != DEST_NONE && 38.820 + io->io_pins[i].io_dest != DEST_EXTINT) 38.821 + ioapic_program_destination(&io->io_pins[i]); 38.822 +} 38.823 +SYSINIT(ioapic_destinations, SI_SUB_SMP, SI_ORDER_SECOND, 38.824 + ioapic_set_logical_destinations, NULL) 38.825 + 38.826 +/* 38.827 + * Support for mixed-mode interrupt sources. These sources route an ISA 38.828 + * IRQ through the 8259A's via the ExtINT on pin 0 of the I/O APIC that 38.829 + * routes the ISA interrupts. We just ignore the intpins that use this 38.830 + * mode and allow the atpic driver to register its interrupt source for 38.831 + * that IRQ instead. 38.832 + */ 38.833 + 38.834 +static void 38.835 +ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin) 38.836 +{ 38.837 + struct ioapic_intsrc *extint; 38.838 + struct ioapic *io; 38.839 + 38.840 + /* 38.841 + * Mark the associated I/O APIC intpin as being delivered via 38.842 + * ExtINT and enable the ExtINT pin on the I/O APIC if needed. 38.843 + */ 38.844 + intpin->io_dest = DEST_EXTINT; 38.845 + io = (struct ioapic *)intpin->io_intsrc.is_pic; 38.846 + extint = &io->io_pins[0]; 38.847 + if (extint->io_vector != VECTOR_EXTINT) 38.848 + panic("Can't find ExtINT pin to route through!"); 38.849 +#ifdef ENABLE_EXTINT_LOGICAL_DESTINATION 38.850 + if (extint->io_dest == DEST_NONE) 38.851 + ioapic_assign_cluster(extint); 38.852 +#endif 38.853 +}
39.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 39.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/local_apic.c Thu Mar 24 22:52:13 2005 +0000 39.3 @@ -0,0 +1,762 @@ 39.4 +/*- 39.5 + * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 39.6 + * Copyright (c) 1996, by Steve Passe 39.7 + * All rights reserved. 39.8 + * 39.9 + * Redistribution and use in source and binary forms, with or without 39.10 + * modification, are permitted provided that the following conditions 39.11 + * are met: 39.12 + * 1. Redistributions of source code must retain the above copyright 39.13 + * notice, this list of conditions and the following disclaimer. 39.14 + * 2. The name of the developer may NOT be used to endorse or promote products 39.15 + * derived from this software without specific prior written permission. 39.16 + * 3. Neither the name of the author nor the names of any co-contributors 39.17 + * may be used to endorse or promote products derived from this software 39.18 + * without specific prior written permission. 39.19 + * 39.20 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 39.21 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 39.22 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 39.23 + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 39.24 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 39.25 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39.26 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39.27 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39.28 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39.29 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39.30 + * SUCH DAMAGE. 39.31 + */ 39.32 + 39.33 +/* 39.34 + * Local APIC support on Pentium and later processors. 39.35 + */ 39.36 + 39.37 +#include <sys/cdefs.h> 39.38 +__FBSDID("$FreeBSD: src/sys/i386/i386/local_apic.c,v 1.9 2004/07/14 18:12:15 jhb Exp $"); 39.39 + 39.40 +#include <sys/param.h> 39.41 +#include <sys/systm.h> 39.42 +#include <sys/bus.h> 39.43 +#include <sys/kernel.h> 39.44 +#include <sys/pcpu.h> 39.45 + 39.46 +#include <vm/vm.h> 39.47 +#include <vm/pmap.h> 39.48 + 39.49 +#include <machine/apicreg.h> 39.50 +#include <machine/cputypes.h> 39.51 +#include <machine/frame.h> 39.52 +#include <machine/intr_machdep.h> 39.53 +#include <machine/apicvar.h> 39.54 +#include <machine/md_var.h> 39.55 +#include <machine/smp.h> 39.56 +#include <machine/specialreg.h> 39.57 + 39.58 +/* 39.59 + * We can handle up to 60 APICs via our logical cluster IDs, but currently 39.60 + * the physical IDs on Intel processors up to the Pentium 4 are limited to 39.61 + * 16. 39.62 + */ 39.63 +#define MAX_APICID 16 39.64 + 39.65 +/* Sanity checks on IDT vectors. */ 39.66 +CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS <= APIC_LOCAL_INTS); 39.67 +CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 39.68 + 39.69 +/* 39.70 + * Support for local APICs. Local APICs manage interrupts on each 39.71 + * individual processor as opposed to I/O APICs which receive interrupts 39.72 + * from I/O devices and then forward them on to the local APICs. 39.73 + * 39.74 + * Local APICs can also send interrupts to each other thus providing the 39.75 + * mechanism for IPIs. 39.76 + */ 39.77 + 39.78 +struct lvt { 39.79 + u_int lvt_edgetrigger:1; 39.80 + u_int lvt_activehi:1; 39.81 + u_int lvt_masked:1; 39.82 + u_int lvt_active:1; 39.83 + u_int lvt_mode:16; 39.84 + u_int lvt_vector:8; 39.85 +}; 39.86 + 39.87 +struct lapic { 39.88 + struct lvt la_lvts[LVT_MAX + 1]; 39.89 + u_int la_id:8; 39.90 + u_int la_cluster:4; 39.91 + u_int la_cluster_id:2; 39.92 + u_int la_present:1; 39.93 +} static lapics[MAX_APICID]; 39.94 + 39.95 +/* XXX: should thermal be an NMI? */ 39.96 + 39.97 +/* Global defaults for local APIC LVT entries. */ 39.98 +static struct lvt lvts[LVT_MAX + 1] = { 39.99 + { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 39.100 + { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 39.101 + { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 }, /* Timer: needs a vector */ 39.102 + { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 }, /* Error: needs a vector */ 39.103 + { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 }, /* PMC */ 39.104 + { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 }, /* Thermal: needs a vector */ 39.105 +}; 39.106 + 39.107 +static inthand_t *ioint_handlers[] = { 39.108 + NULL, /* 0 - 31 */ 39.109 + IDTVEC(apic_isr1), /* 32 - 63 */ 39.110 + IDTVEC(apic_isr2), /* 64 - 95 */ 39.111 + IDTVEC(apic_isr3), /* 96 - 127 */ 39.112 + IDTVEC(apic_isr4), /* 128 - 159 */ 39.113 + IDTVEC(apic_isr5), /* 160 - 191 */ 39.114 + IDTVEC(apic_isr6), /* 192 - 223 */ 39.115 + IDTVEC(apic_isr7), /* 224 - 255 */ 39.116 +}; 39.117 + 39.118 +volatile lapic_t *lapic; 39.119 + 39.120 +static uint32_t 39.121 +lvt_mode(struct lapic *la, u_int pin, uint32_t value) 39.122 +{ 39.123 + struct lvt *lvt; 39.124 + 39.125 + KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 39.126 + if (la->la_lvts[pin].lvt_active) 39.127 + lvt = &la->la_lvts[pin]; 39.128 + else 39.129 + lvt = &lvts[pin]; 39.130 + 39.131 + value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 39.132 + APIC_LVT_VECTOR); 39.133 + if (lvt->lvt_edgetrigger == 0) 39.134 + value |= APIC_LVT_TM; 39.135 + if (lvt->lvt_activehi == 0) 39.136 + value |= APIC_LVT_IIPP_INTALO; 39.137 + if (lvt->lvt_masked) 39.138 + value |= APIC_LVT_M; 39.139 + value |= lvt->lvt_mode; 39.140 + switch (lvt->lvt_mode) { 39.141 + case APIC_LVT_DM_NMI: 39.142 + case APIC_LVT_DM_SMI: 39.143 + case APIC_LVT_DM_INIT: 39.144 + case APIC_LVT_DM_EXTINT: 39.145 + if (!lvt->lvt_edgetrigger) { 39.146 + printf("lapic%u: Forcing LINT%u to edge trigger\n", 39.147 + la->la_id, pin); 39.148 + value |= APIC_LVT_TM; 39.149 + } 39.150 + /* Use a vector of 0. */ 39.151 + break; 39.152 + case APIC_LVT_DM_FIXED: 39.153 +#if 0 39.154 + value |= lvt->lvt_vector; 39.155 +#else 39.156 + panic("Fixed LINT pins not supported"); 39.157 +#endif 39.158 + break; 39.159 + default: 39.160 + panic("bad APIC LVT delivery mode: %#x\n", value); 39.161 + } 39.162 + return (value); 39.163 +} 39.164 + 39.165 +/* 39.166 + * Map the local APIC and setup necessary interrupt vectors. 39.167 + */ 39.168 +void 39.169 +lapic_init(uintptr_t addr) 39.170 +{ 39.171 + u_int32_t value; 39.172 + 39.173 + /* Map the local APIC and setup the spurious interrupt handler. */ 39.174 + KASSERT(trunc_page(addr) == addr, 39.175 + ("local APIC not aligned on a page boundary")); 39.176 + lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t)); 39.177 + setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL, 39.178 + GSEL(GCODE_SEL, SEL_KPL)); 39.179 + 39.180 + /* Perform basic initialization of the BSP's local APIC. */ 39.181 + value = lapic->svr; 39.182 + value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 39.183 + value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 39.184 + lapic->svr = value; 39.185 + 39.186 + /* Set BSP's per-CPU local APIC ID. */ 39.187 + PCPU_SET(apic_id, lapic_id()); 39.188 + 39.189 + /* XXX: timer/error/thermal interrupts */ 39.190 +} 39.191 + 39.192 +/* 39.193 + * Create a local APIC instance. 39.194 + */ 39.195 +void 39.196 +lapic_create(u_int apic_id, int boot_cpu) 39.197 +{ 39.198 + int i; 39.199 + 39.200 + if (apic_id >= MAX_APICID) { 39.201 + printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 39.202 + if (boot_cpu) 39.203 + panic("Can't ignore BSP"); 39.204 + return; 39.205 + } 39.206 + KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 39.207 + apic_id)); 39.208 + 39.209 + /* 39.210 + * Assume no local LVT overrides and a cluster of 0 and 39.211 + * intra-cluster ID of 0. 39.212 + */ 39.213 + lapics[apic_id].la_present = 1; 39.214 + lapics[apic_id].la_id = apic_id; 39.215 + for (i = 0; i < LVT_MAX; i++) { 39.216 + lapics[apic_id].la_lvts[i] = lvts[i]; 39.217 + lapics[apic_id].la_lvts[i].lvt_active = 0; 39.218 + } 39.219 + 39.220 +#ifdef SMP 39.221 + cpu_add(apic_id, boot_cpu); 39.222 +#endif 39.223 +} 39.224 + 39.225 +/* 39.226 + * Dump contents of local APIC registers 39.227 + */ 39.228 +void 39.229 +lapic_dump(const char* str) 39.230 +{ 39.231 + 39.232 + printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 39.233 + printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 39.234 + lapic->id, lapic->version, lapic->ldr, lapic->dfr); 39.235 + printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 39.236 + lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 39.237 +} 39.238 + 39.239 +void 39.240 +lapic_enable_intr(u_int irq) 39.241 +{ 39.242 + u_int vector; 39.243 + 39.244 + vector = apic_irq_to_idt(irq); 39.245 + KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 39.246 + KASSERT(ioint_handlers[vector / 32] != NULL, 39.247 + ("No ISR handler for IRQ %u", irq)); 39.248 + setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL, 39.249 + GSEL(GCODE_SEL, SEL_KPL)); 39.250 +} 39.251 + 39.252 +void 39.253 +lapic_setup(void) 39.254 +{ 39.255 + struct lapic *la; 39.256 + u_int32_t value, maxlvt; 39.257 + register_t eflags; 39.258 + 39.259 + la = &lapics[lapic_id()]; 39.260 + KASSERT(la->la_present, ("missing APIC structure")); 39.261 + eflags = intr_disable(); 39.262 + maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 39.263 + 39.264 + /* Program LINT[01] LVT entries. */ 39.265 + lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 39.266 + lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 39.267 + 39.268 + /* XXX: more LVT entries */ 39.269 + 39.270 + /* Clear the TPR. */ 39.271 + value = lapic->tpr; 39.272 + value &= ~APIC_TPR_PRIO; 39.273 + lapic->tpr = value; 39.274 + 39.275 + /* Use the cluster model for logical IDs. */ 39.276 + value = lapic->dfr; 39.277 + value &= ~APIC_DFR_MODEL_MASK; 39.278 + value |= APIC_DFR_MODEL_CLUSTER; 39.279 + lapic->dfr = value; 39.280 + 39.281 + /* Set this APIC's logical ID. */ 39.282 + value = lapic->ldr; 39.283 + value &= ~APIC_ID_MASK; 39.284 + value |= (la->la_cluster << APIC_ID_CLUSTER_SHIFT | 39.285 + 1 << la->la_cluster_id) << APIC_ID_SHIFT; 39.286 + lapic->ldr = value; 39.287