ia64/xen-unstable

changeset 16018:9fbbba4c23fb

[IA64] Fix + more cr regs for vcpu_get_context

Do not hard code number of TRs in vcpucontext.
Correctly fill rr7 and add more cr registers for get_vcpu_context.

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author Alex Williamson <alex.williamson@hp.com>
date Tue Oct 02 09:18:38 2007 -0600 (2007-10-02)
parents f71b7d6ad5d8
children 669347b873fa
files xen/arch/ia64/xen/domain.c
line diff
     1.1 --- a/xen/arch/ia64/xen/domain.c	Mon Oct 01 13:59:37 2007 -0600
     1.2 +++ b/xen/arch/ia64/xen/domain.c	Tue Oct 02 09:18:38 2007 -0600
     1.3 @@ -721,17 +721,21 @@ void arch_get_info_guest(struct vcpu *v,
     1.4  		vcpu_get_ibr(v, i, &c.nat->regs.ibr[i]);
     1.5  	}
     1.6  
     1.7 -	for (i = 0; i < 7; i++)
     1.8 +	for (i = 0; i < 8; i++)
     1.9  		vcpu_get_rr(v, (unsigned long)i << 61, &c.nat->regs.rr[i]);
    1.10  
    1.11  	/* Fill extra regs.  */
    1.12 -	for (i = 0; i < 8; i++) {
    1.13 +	for (i = 0;
    1.14 +	     (i < sizeof(tr->itrs) / sizeof(tr->itrs[0])) && i < NITRS;
    1.15 +	     i++) {
    1.16  		tr->itrs[i].pte = v->arch.itrs[i].pte.val;
    1.17  		tr->itrs[i].itir = v->arch.itrs[i].itir;
    1.18  		tr->itrs[i].vadr = v->arch.itrs[i].vadr;
    1.19  		tr->itrs[i].rid = v->arch.itrs[i].rid;
    1.20  	}
    1.21 -	for (i = 0; i < 8; i++) {
    1.22 +	for (i = 0;
    1.23 +	     (i < sizeof(tr->dtrs) / sizeof(tr->dtrs[0])) && i < NDTRS;
    1.24 +	     i++) {
    1.25  		tr->dtrs[i].pte = v->arch.dtrs[i].pte.val;
    1.26  		tr->dtrs[i].itir = v->arch.dtrs[i].itir;
    1.27  		tr->dtrs[i].vadr = v->arch.dtrs[i].vadr;
    1.28 @@ -754,7 +758,10 @@ void arch_get_info_guest(struct vcpu *v,
    1.29  	vcpu_get_isr(v, &c.nat->regs.cr.isr);
    1.30  	vcpu_get_iip(v, &c.nat->regs.cr.iip);
    1.31  	vcpu_get_ifa(v, &c.nat->regs.cr.ifa);
    1.32 +	vcpu_get_itir(v, &c.nat->regs.cr.itir);
    1.33 +	vcpu_get_iha(v, &c.nat->regs.cr.iha);
    1.34  	vcpu_get_ivr(v, &c.nat->regs.cr.ivr);
    1.35 +	vcpu_get_iim(v, &c.nat->regs.cr.iim);
    1.36  
    1.37  	vcpu_get_tpr(v, &c.nat->regs.cr.tpr);
    1.38  	vcpu_get_irr0(v, &c.nat->regs.cr.irr[0]);
    1.39 @@ -886,13 +893,17 @@ int arch_set_info_guest(struct vcpu *v, 
    1.40  	if (c.nat->flags & VGCF_EXTRA_REGS) {
    1.41  		struct vcpu_tr_regs *tr = &c.nat->regs.tr;
    1.42  
    1.43 -		for (i = 0; i < 8; i++) {
    1.44 +		for (i = 0;
    1.45 +		     (i < sizeof(tr->itrs) / sizeof(tr->itrs[0])) && i < NITRS;
    1.46 +		     i++) {
    1.47  			vcpu_set_itr(v, i, tr->itrs[i].pte,
    1.48  			             tr->itrs[i].itir,
    1.49  			             tr->itrs[i].vadr,
    1.50  			             tr->itrs[i].rid);
    1.51  		}
    1.52 -		for (i = 0; i < 8; i++) {
    1.53 +		for (i = 0;
    1.54 +		     (i < sizeof(tr->dtrs) / sizeof(tr->dtrs[0])) && i < NDTRS;
    1.55 +		     i++) {
    1.56  			vcpu_set_dtr(v, i,
    1.57  			             tr->dtrs[i].pte,
    1.58  			             tr->dtrs[i].itir,