ia64/xen-unstable

changeset 8765:9eb1a1a6e16d

No C1-Clock Ramp disabling on AMD processors. The tiny drift
caused by the ramping changes should not cause TSCs to become
noticeably out of sync on Xen systems.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Mon Feb 06 16:51:06 2006 +0100 (2006-02-06)
parents d3547993be94
children 40c152531072
files xen/arch/x86/cpu/amd.c xen/arch/x86/mpparse.c xen/include/asm-x86/mpspec.h
line diff
     1.1 --- a/xen/arch/x86/cpu/amd.c	Mon Feb 06 15:41:26 2006 +0000
     1.2 +++ b/xen/arch/x86/cpu/amd.c	Mon Feb 06 16:51:06 2006 +0100
     1.3 @@ -3,20 +3,13 @@
     1.4  #include <xen/bitops.h>
     1.5  #include <xen/mm.h>
     1.6  #include <xen/smp.h>
     1.7 -#include <xen/sched.h>
     1.8  #include <asm/io.h>
     1.9  #include <asm/msr.h>
    1.10  #include <asm/processor.h>
    1.11 -#include <asm/hvm/vcpu.h>
    1.12  #include <asm/hvm/support.h>
    1.13  
    1.14 -
    1.15  #include "cpu.h"
    1.16  
    1.17 -
    1.18 -#define		AMD_C1_CLOCK_RAMP			0x80000084
    1.19 -#define		AMD_ADVPM_TSC_INVARIANT		0x80000007
    1.20 -
    1.21  /*
    1.22   * amd_flush_filter={on,off}. Forcibly Enable or disable the TLB flush
    1.23   * filter on AMD 64-bit processors.
    1.24 @@ -49,99 +42,6 @@ custom_param("amd_flush_filter", flush_f
    1.25  extern void vide(void);
    1.26  __asm__(".text\n.align 4\nvide: ret");
    1.27  
    1.28 -
    1.29 -/*
    1.30 - *	Check if C1-Clock ramping enabled in  PMM7.CpuLowPwrEnh
    1.31 - *	On 8th-Generation cores only. Assume BIOS has setup
    1.32 - *	all Northbridges equivalently.
    1.33 - */
    1.34 -
    1.35 -static int c1_ramp_8gen(void) 
    1.36 -{
    1.37 -	u32 l;
    1.38 -
    1.39 -	/*	Read dev=0x18, function = 3, offset=0x87  */
    1.40 -	l = AMD_C1_CLOCK_RAMP;
    1.41 -	/*	fill in dev (18) + function (3) */
    1.42 -	/*	direct cfc/cf8 should be safe here */
    1.43 -	l += (((0x18) << 3) + 0x3) << 8; 
    1.44 -	outl(l, 0xcf8);
    1.45 -	return (1 & (inl(0xcfc) >> 24));
    1.46 -}
    1.47 -
    1.48 -/*
    1.49 - * returns TRUE if ok to use TSC
    1.50 - */
    1.51 -
    1.52 -static int use_amd_tsc(struct cpuinfo_x86 *c) 
    1.53 -{ 
    1.54 -	if (c->x86 < 0xf) {
    1.55 -		/*
    1.56 -		 *	TSC drift doesn't exist on 7th Gen or less
    1.57 -		 *	However, OS still needs to consider effects
    1.58 -		 *	of P-state changes on TSC
    1.59 -		*/
    1.60 -		return 1;
    1.61 -	} else if ( cpuid_edx(AMD_ADVPM_TSC_INVARIANT) & 0x100 ) {
    1.62 -		/*
    1.63 -		 *	CPUID.AdvPowerMgmtInfo.TscInvariant
    1.64 -		 *	EDX bit 8, 8000_0007
    1.65 -		 *	Invariant TSC on 8th Gen or newer, use it
    1.66 -		 *	(assume all cores have invariant TSC)
    1.67 -		*/
    1.68 -		return 1;
    1.69 -	} else if ((mp_get_num_processors() == 1) && (c->x86_num_cores == 1)) {
    1.70 -		/*
    1.71 -		 *	OK to use TSC on uni-processor-uni-core
    1.72 -		 *	However, OS still needs to consider effects
    1.73 -		 *	of P-state changes on TSC
    1.74 -		*/
    1.75 -		return 1;
    1.76 -	} else if ( (mp_get_num_processors() == 1) && (c->x86 == 0x0f) 
    1.77 -				&& !c1_ramp_8gen()) {
    1.78 -		/*
    1.79 -		 *	Use TSC on 8th Gen uni-proc with C1_ramp off 
    1.80 -		 *	However, OS still needs to consider effects
    1.81 -		 *	of P-state changes on TSC
    1.82 -		*/
    1.83 -		return 1;
    1.84 -	} else { 
    1.85 -		return 0;
    1.86 -	}
    1.87 -}
    1.88 -
    1.89 -/*
    1.90 - *	Disable C1-Clock ramping if enabled in PMM7.CpuLowPwrEnh
    1.91 - *	On 8th-Generation cores only. Assume BIOS has setup
    1.92 - *	all Northbridges equivalently.
    1.93 - */
    1.94 -
    1.95 -static void amd_disable_c1_ramping(void) 
    1.96 -{
    1.97 -	u32 l, h;
    1.98 -	int i;
    1.99 -
   1.100 -	for (i=0; i < NR_CPUS;i++) {
   1.101 -		/* Read from the Northbridge for Node x. until we get invalid data */
   1.102 -		/* fill in dev (18 + cpu#) + function (3) */
   1.103 -		l = AMD_C1_CLOCK_RAMP + ((((0x18 + i) << 3) + 0x3) << 8);
   1.104 -		/*	direct cfc/cf8 should be safe here */
   1.105 -		outl(l, 0xcf8);
   1.106 -		h = inl(0xcfc);
   1.107 -		if (h != 0xFFFFFFFF) {
   1.108 -			h &= 0xFCFFFFFF; /* clears pmm7[1:0]  */
   1.109 -			outl(l, 0xcf8);
   1.110 -			outl(h, 0xcfc);
   1.111 -			printk ("AMD: Disabling C1 Clock Ramping Node #%x\n",i);
   1.112 -		}
   1.113 -		else {
   1.114 -			i = NR_CPUS;
   1.115 -		}
   1.116 -			
   1.117 -	}
   1.118 -	return;
   1.119 -}
   1.120 -
   1.121  static void __init init_amd(struct cpuinfo_x86 *c)
   1.122  {
   1.123  	u32 l, h;
   1.124 @@ -347,14 +247,6 @@ static void __init init_amd(struct cpuin
   1.125  		       cpu, c->x86_num_cores, cpu_core_id[cpu]);
   1.126  	}
   1.127  #endif
   1.128 -	/*
   1.129 -	 * Prevent TSC drift in non single-processor, single-core platforms
   1.130 -	 */
   1.131 -	if ( !use_amd_tsc(c) && (c->x86 == 0x0f) && c1_ramp_8gen() && 
   1.132 -			(smp_processor_id() == 0)) {
   1.133 -		/* Disable c1 Clock Ramping on all cores */
   1.134 -		amd_disable_c1_ramping();
   1.135 -	}
   1.136  
   1.137  #ifdef CONFIG_SVM
   1.138  	start_svm();
     2.1 --- a/xen/arch/x86/mpparse.c	Mon Feb 06 15:41:26 2006 +0000
     2.2 +++ b/xen/arch/x86/mpparse.c	Mon Feb 06 16:51:06 2006 +0100
     2.3 @@ -730,11 +730,6 @@ void __init get_smp_config (void)
     2.4  	 */
     2.5  }
     2.6  
     2.7 -int __init mp_get_num_processors(void)
     2.8 -{
     2.9 -    return num_processors;
    2.10 -}
    2.11 -
    2.12  static int __init smp_scan_config (unsigned long base, unsigned long length)
    2.13  {
    2.14  	unsigned int *bp = maddr_to_virt(base);
     3.1 --- a/xen/include/asm-x86/mpspec.h	Mon Feb 06 15:41:26 2006 +0000
     3.2 +++ b/xen/include/asm-x86/mpspec.h	Mon Feb 06 16:51:06 2006 +0100
     3.3 @@ -35,7 +35,6 @@ extern void mp_register_ioapic (u8 id, u
     3.4  extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 gsi);
     3.5  extern void mp_config_acpi_legacy_irqs (void);
     3.6  extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low);
     3.7 -extern int mp_get_num_processors(void);
     3.8  #endif /*CONFIG_ACPI_BOOT*/
     3.9  
    3.10  #define PHYSID_ARRAY_SIZE	BITS_TO_LONGS(MAX_APICS)