ia64/xen-unstable

changeset 11932:9e9d8696fb55

[IA64] Support multiple page sizes in VHPT

Enable VHPT support for multiple page sizes.

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Tue Oct 24 09:49:31 2006 -0600 (2006-10-24)
parents 901083dace1d
children aa8ca06d209e
files xen/arch/ia64/vmx/vmmu.c xen/arch/ia64/vmx/vmx_ivt.S xen/arch/ia64/vmx/vmx_phy_mode.c xen/arch/ia64/vmx/vmx_process.c xen/arch/ia64/vmx/vtlb.c xen/include/asm-ia64/mm.h xen/include/asm-ia64/vmmu.h xen/include/asm-ia64/vmx_phy_mode.h
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmmu.c	Tue Oct 24 09:22:56 2006 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmmu.c	Tue Oct 24 09:49:31 2006 -0600
     1.3 @@ -341,9 +341,9 @@ fetch_code(VCPU *vcpu, u64 gip, IA64_BUN
     1.4              ia64_ptcl(gip, ARCH_PAGE_SHIFT << 2);
     1.5              return IA64_RETRY;
     1.6          }
     1.7 -        mfn = tlb->ppn >> (PAGE_SHIFT - ARCH_PAGE_SHIFT);
     1.8          maddr = (tlb->ppn >> (tlb->ps - 12) << tlb->ps) |
     1.9                  (gip & (PSIZE(tlb->ps) - 1));
    1.10 +        mfn = maddr >> PAGE_SHIFT;
    1.11      }
    1.12  
    1.13      page = mfn_to_page(mfn);
    1.14 @@ -637,7 +637,7 @@ IA64FAULT vmx_vcpu_tpa(VCPU *vcpu, u64 v
    1.15      thash_data_t *data;
    1.16      ISR visr,pt_isr;
    1.17      REGS *regs;
    1.18 -    u64 vhpt_adr;
    1.19 +    u64 vhpt_adr, madr;
    1.20      IA64_PSR vpsr;
    1.21      regs=vcpu_regs(vcpu);
    1.22      pt_isr.val=VMX(vcpu,cr_isr);
    1.23 @@ -673,7 +673,9 @@ IA64FAULT vmx_vcpu_tpa(VCPU *vcpu, u64 v
    1.24              dnat_page_consumption(vcpu, vadr);
    1.25              return IA64_FAULT;
    1.26          }else{
    1.27 -            *padr = (get_gpfn_from_mfn(arch_to_xen_ppn(data->ppn)) << PAGE_SHIFT) | (vadr & (PAGE_SIZE - 1));
    1.28 +            madr = (data->ppn >> (data->ps - 12) << data->ps) |
    1.29 +                   (vadr & (PSIZE(data->ps) - 1));
    1.30 +            *padr = __mpa_to_gpa(madr);
    1.31              return IA64_NO_FAULT;
    1.32          }
    1.33      }
     2.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Tue Oct 24 09:22:56 2006 -0600
     2.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Tue Oct 24 09:49:31 2006 -0600
     2.3 @@ -172,13 +172,17 @@ vmx_itlb_loop:
     2.4      ld8 r27 = [r18]
     2.5      ld8 r29 = [r28]
     2.6      ;;
     2.7 -    st8 [r16] = r29
     2.8 -    st8 [r28] = r22
     2.9 +    st8 [r16] = r29, VLE_ITIR_OFFSET - VLE_TITAG_OFFSET
    2.10 +    st8 [r28] = r22, VLE_ITIR_OFFSET - VLE_TITAG_OFFSET
    2.11      extr.u r19 = r27, 56, 4
    2.12      ;;
    2.13 +    ld8 r29 = [r16]
    2.14 +    ld8 r22 = [r28]
    2.15      dep r27 = r0, r27, 56, 4
    2.16      dep r25 = r19, r25, 56, 4
    2.17      ;;
    2.18 +    st8 [r16] = r22
    2.19 +    st8 [r28] = r29
    2.20      st8 [r18] = r25
    2.21      st8 [r17] = r27
    2.22      ;;
    2.23 @@ -246,13 +250,17 @@ vmx_dtlb_loop:
    2.24      ld8 r27 = [r18]
    2.25      ld8 r29 = [r28]
    2.26      ;;
    2.27 -    st8 [r16] = r29
    2.28 -    st8 [r28] = r22
    2.29 +    st8 [r16] = r29, VLE_ITIR_OFFSET - VLE_TITAG_OFFSET
    2.30 +    st8 [r28] = r22, VLE_ITIR_OFFSET - VLE_TITAG_OFFSET
    2.31      extr.u r19 = r27, 56, 4
    2.32      ;;
    2.33 +    ld8 r29 = [r16]
    2.34 +    ld8 r22 = [r28]
    2.35      dep r27 = r0, r27, 56, 4
    2.36      dep r25 = r19, r25, 56, 4
    2.37      ;;
    2.38 +    st8 [r16] = r22
    2.39 +    st8 [r28] = r29
    2.40      st8 [r18] = r25
    2.41      st8 [r17] = r27
    2.42      ;;    
     3.1 --- a/xen/arch/ia64/vmx/vmx_phy_mode.c	Tue Oct 24 09:22:56 2006 -0600
     3.2 +++ b/xen/arch/ia64/vmx/vmx_phy_mode.c	Tue Oct 24 09:49:31 2006 -0600
     3.3 @@ -107,7 +107,7 @@ physical_mode_init(VCPU *vcpu)
     3.4  extern void vmx_switch_rr7(unsigned long ,shared_info_t*,void *,void *,void *);
     3.5  
     3.6  void
     3.7 -physical_tlb_miss(VCPU *vcpu, u64 vadr)
     3.8 +physical_tlb_miss(VCPU *vcpu, u64 vadr, int type)
     3.9  {
    3.10      u64 pte;
    3.11      ia64_rr rr;
    3.12 @@ -117,7 +117,7 @@ physical_tlb_miss(VCPU *vcpu, u64 vadr)
    3.13          pte = pte | PHY_PAGE_UC;
    3.14      else
    3.15          pte = pte | PHY_PAGE_WB;
    3.16 -    thash_vhpt_insert(vcpu, pte, (rr.ps << 2), vadr);
    3.17 +    thash_vhpt_insert(vcpu, pte, (rr.ps << 2), vadr, type);
    3.18      return;
    3.19  }
    3.20  
     4.1 --- a/xen/arch/ia64/vmx/vmx_process.c	Tue Oct 24 09:22:56 2006 -0600
     4.2 +++ b/xen/arch/ia64/vmx/vmx_process.c	Tue Oct 24 09:49:31 2006 -0600
     4.3 @@ -288,7 +288,7 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
     4.4                  return IA64_FAULT;
     4.5              }
     4.6          }
     4.7 -        physical_tlb_miss(v, vadr);
     4.8 +        physical_tlb_miss(v, vadr, type);
     4.9          return IA64_FAULT;
    4.10      }
    4.11  
    4.12 @@ -306,7 +306,7 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
    4.13                  return IA64_FAULT;
    4.14              }
    4.15          }
    4.16 -        thash_vhpt_insert(v,data->page_flags, data->itir ,vadr);
    4.17 +        thash_vhpt_insert(v, data->page_flags, data->itir, vadr, type);
    4.18  
    4.19      }else if(type == DSIDE_TLB){
    4.20      
     5.1 --- a/xen/arch/ia64/vmx/vtlb.c	Tue Oct 24 09:22:56 2006 -0600
     5.2 +++ b/xen/arch/ia64/vmx/vtlb.c	Tue Oct 24 09:49:31 2006 -0600
     5.3 @@ -178,11 +178,23 @@ static void vmx_vhpt_insert(thash_cb_t *
     5.4      return;
     5.5  }
     5.6  
     5.7 -void thash_vhpt_insert(VCPU *v, u64 pte, u64 itir, u64 va)
     5.8 +void thash_vhpt_insert(VCPU *v, u64 pte, u64 itir, u64 va, int type)
     5.9  {
    5.10 -    u64 phy_pte;
    5.11 +    u64 phy_pte, psr;
    5.12 +    ia64_rr mrr;
    5.13 +
    5.14 +    mrr.rrval = ia64_get_rr(va);
    5.15      phy_pte=translate_phy_pte(v, &pte, itir, va);
    5.16 -    vmx_vhpt_insert(vcpu_get_vhpt(v), phy_pte, itir, va);
    5.17 +
    5.18 +    if (itir_ps(itir) >= mrr.ps) {
    5.19 +        vmx_vhpt_insert(vcpu_get_vhpt(v), phy_pte, itir, va);
    5.20 +    } else {
    5.21 +        phy_pte  &= ~PAGE_FLAGS_RV_MASK;
    5.22 +        psr = ia64_clear_ic();
    5.23 +        ia64_itc(type + 1, va, phy_pte, itir_ps(itir));
    5.24 +        ia64_set_psr(psr);
    5.25 +        ia64_srlz_i();
    5.26 +    }
    5.27  }
    5.28  /*
    5.29   *   vhpt lookup
    5.30 @@ -191,7 +203,7 @@ void thash_vhpt_insert(VCPU *v, u64 pte,
    5.31  thash_data_t * vhpt_lookup(u64 va)
    5.32  {
    5.33      thash_data_t *hash, *head;
    5.34 -    u64 tag, pte;
    5.35 +    u64 tag, pte, itir;
    5.36      head = (thash_data_t *)ia64_thash(va);
    5.37      hash=head;
    5.38      tag = ia64_ttag(va);
    5.39 @@ -207,6 +219,9 @@ thash_data_t * vhpt_lookup(u64 va)
    5.40          tag = hash->etag;
    5.41          hash->etag = head->etag;
    5.42          head->etag = tag;
    5.43 +        itir = hash->itir;
    5.44 +        hash->itir = head->itir;
    5.45 +        head->itir = itir;
    5.46          head->len = hash->len;
    5.47          hash->len=0;
    5.48          return head;
    5.49 @@ -223,7 +238,8 @@ u64 guest_vhpt_lookup(u64 iha, u64 *pte)
    5.50      if (data == NULL) {
    5.51          data = vtlb_lookup(current, iha, DSIDE_TLB);
    5.52          if (data != NULL)
    5.53 -            thash_vhpt_insert(current, data->page_flags, data->itir ,iha);
    5.54 +            thash_vhpt_insert(current, data->page_flags, data->itir,
    5.55 +                              iha, DSIDE_TLB);
    5.56      }
    5.57  
    5.58      asm volatile ("rsm psr.ic|psr.i;;"
    5.59 @@ -607,7 +623,8 @@ void thash_init(thash_cb_t *hcb, u64 sz)
    5.60      head=hcb->hash;
    5.61      num = (hcb->hash_sz/sizeof(thash_data_t));
    5.62      do{
    5.63 -        head->itir = PAGE_SHIFT<<2;
    5.64 +        head->page_flags = 0;
    5.65 +        head->itir = 0;
    5.66          head->etag = 1UL<<63;
    5.67          head->next = 0;
    5.68          head++;
    5.69 @@ -617,11 +634,12 @@ void thash_init(thash_cb_t *hcb, u64 sz)
    5.70      hcb->cch_freelist = p = hcb->cch_buf;
    5.71      num = (hcb->cch_sz/sizeof(thash_data_t))-1;
    5.72      do{
    5.73 -        p->itir = PAGE_SHIFT<<2;
    5.74 +        p->page_flags = 0;
    5.75 +        p->itir = 0;
    5.76          p->next =p+1;
    5.77          p++;
    5.78          num--;
    5.79      }while(num);
    5.80 -    p->itir = PAGE_SHIFT<<2;
    5.81 +    p->itir = 0;
    5.82      p->next = NULL;
    5.83  }
     6.1 --- a/xen/include/asm-ia64/mm.h	Tue Oct 24 09:22:56 2006 -0600
     6.2 +++ b/xen/include/asm-ia64/mm.h	Tue Oct 24 09:49:31 2006 -0600
     6.3 @@ -497,6 +497,10 @@ extern u64 translate_domain_pte(u64 ptev
     6.4  #define __gpa_to_mpa(_d, gpa)   \
     6.5      ((gmfn_to_mfn((_d),(gpa)>>PAGE_SHIFT)<<PAGE_SHIFT)|((gpa)&~PAGE_MASK))
     6.6  
     6.7 +#define __mpa_to_gpa(madr) \
     6.8 +    ((get_gpfn_from_mfn((madr) >> PAGE_SHIFT) << PAGE_SHIFT) | \
     6.9 +    ((madr) & ~PAGE_MASK))
    6.10 +
    6.11  /* Arch-specific portion of memory_op hypercall. */
    6.12  long arch_memory_op(int op, XEN_GUEST_HANDLE(void) arg);
    6.13  
     7.1 --- a/xen/include/asm-ia64/vmmu.h	Tue Oct 24 09:22:56 2006 -0600
     7.2 +++ b/xen/include/asm-ia64/vmmu.h	Tue Oct 24 09:49:31 2006 -0600
     7.3 @@ -305,7 +305,8 @@ extern void emulate_io_inst(struct vcpu 
     7.4  extern int vhpt_enabled(struct vcpu *vcpu, uint64_t vadr, vhpt_ref_t ref);
     7.5  extern void vtlb_insert(struct vcpu *vcpu, u64 pte, u64 itir, u64 va);
     7.6  extern u64 translate_phy_pte(struct vcpu *v, u64 *pte, u64 itir, u64 va);
     7.7 -extern void thash_vhpt_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa);
     7.8 +extern void thash_vhpt_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa,
     7.9 +                              int type);
    7.10  extern u64 guest_vhpt_lookup(u64 iha, u64 *pte);
    7.11  
    7.12  static inline void vmx_vcpu_set_tr (thash_data_t *trp, u64 pte, u64 itir, u64 va, u64 rid)
     8.1 --- a/xen/include/asm-ia64/vmx_phy_mode.h	Tue Oct 24 09:22:56 2006 -0600
     8.2 +++ b/xen/include/asm-ia64/vmx_phy_mode.h	Tue Oct 24 09:49:31 2006 -0600
     8.3 @@ -96,7 +96,7 @@ extern void prepare_if_physical_mode(VCP
     8.4  extern void recover_if_physical_mode(VCPU *vcpu);
     8.5  extern void vmx_init_all_rr(VCPU *vcpu);
     8.6  extern void vmx_load_all_rr(VCPU *vcpu);
     8.7 -extern void physical_tlb_miss(VCPU *vcpu, u64 vadr);
     8.8 +extern void physical_tlb_miss(VCPU *vcpu, u64 vadr, int type);
     8.9  /*
    8.10   * No sanity check here, since all psr changes have been
    8.11   * checked in switch_mm_mode().