ia64/xen-unstable

changeset 17964:9cf72db44ee9

ioemu: Support more Capability Structures (including MSI/MSI-X)
and Device Specific Registers for pt device.

I implemented following Capability Structures and Device Specific
Registers.
* Configuration Header Type 0
-> emulation.
"emulation" does not mean no accessing real I/O device.
Access real I/O device, but guest value and real value
might be different.
* MSI Capability Structure
-> emulation.
Behavior is not changed from existed implementation in
pt-msi.c, although code is changed.
* MSI-X Capability Structure
-> emulation.
Behavior is not changed from existed implementation in
pt-msi.c, although code is changed.
* PCI Express Capability Structure
-> emulation.
* PCI Power Management Capability Structure
-> emulation.
* Vital Product Data Capability Structure
-> emulation.
Emulated register is only Next Capability Pointer
Register.
All other registers are passthrough.
* Vendor Specific Capability Structure
-> emulation
Emulated register is only Next Capability Pointer
Register.
All other registers are passthrough.
* Device Specific Register (exclude capability structures)
-> passthrough.
The device drivers in guest domain are allowed to access
Device Specific Register. So various I/O device will work.

I assigned following device to guest domain, and they worked fine.
- PCIe NIC (MSI)
- PCI NIC (MSI)
- UHCI (INTx interrupt)
- IDE Controller (INTx interrupt)

Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jul 04 11:54:21 2008 +0100 (2008-07-04)
parents 1db0b09b290e
children 14fd83fe71c3
files tools/ioemu/hw/pass-through.c tools/ioemu/hw/pass-through.h tools/ioemu/hw/pci.c tools/ioemu/hw/pt-msi.c tools/ioemu/hw/pt-msi.h tools/ioemu/vl.h
line diff
     1.1 --- a/tools/ioemu/hw/pass-through.c	Fri Jul 04 11:51:59 2008 +0100
     1.2 +++ b/tools/ioemu/hw/pass-through.c	Fri Jul 04 11:54:21 2008 +0100
     1.3 @@ -46,6 +46,629 @@ struct dpci_infos {
     1.4  
     1.5  } dpci_infos;
     1.6  
     1.7 +/* prototype */
     1.8 +static uint32_t pt_common_reg_init(struct pt_dev *ptdev,
     1.9 +    struct pt_reg_info_tbl *reg, uint32_t real_offset);
    1.10 +static uint32_t pt_ptr_reg_init(struct pt_dev *ptdev,
    1.11 +    struct pt_reg_info_tbl *reg, uint32_t real_offset);
    1.12 +static uint32_t pt_status_reg_init(struct pt_dev *ptdev,
    1.13 +    struct pt_reg_info_tbl *reg, uint32_t real_offset);
    1.14 +static uint32_t pt_irqpin_reg_init(struct pt_dev *ptdev,
    1.15 +    struct pt_reg_info_tbl *reg, uint32_t real_offset);
    1.16 +static uint32_t pt_bar_reg_init(struct pt_dev *ptdev,
    1.17 +    struct pt_reg_info_tbl *reg, uint32_t real_offset);
    1.18 +static uint32_t pt_linkctrl2_reg_init(struct pt_dev *ptdev,
    1.19 +    struct pt_reg_info_tbl *reg, uint32_t real_offset);
    1.20 +static uint32_t pt_msgctrl_reg_init(struct pt_dev *ptdev,
    1.21 +    struct pt_reg_info_tbl *reg, uint32_t real_offset);
    1.22 +static uint32_t pt_msgaddr32_reg_init(struct pt_dev *ptdev,
    1.23 +    struct pt_reg_info_tbl *reg, uint32_t real_offset);
    1.24 +static uint32_t pt_msgaddr64_reg_init(struct pt_dev *ptdev,
    1.25 +    struct pt_reg_info_tbl *reg, uint32_t real_offset);
    1.26 +static uint32_t pt_msgdata_reg_init(struct pt_dev *ptdev,
    1.27 +    struct pt_reg_info_tbl *reg, uint32_t real_offset);
    1.28 +static uint32_t pt_msixctrl_reg_init(struct pt_dev *ptdev,
    1.29 +    struct pt_reg_info_tbl *reg, uint32_t real_offset);
    1.30 +static uint8_t pt_reg_grp_size_init(struct pt_dev *ptdev,
    1.31 +    struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
    1.32 +static uint8_t pt_msi_size_init(struct pt_dev *ptdev,
    1.33 +    struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
    1.34 +static uint8_t pt_msix_size_init(struct pt_dev *ptdev,
    1.35 +    struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
    1.36 +static uint8_t pt_vendor_size_init(struct pt_dev *ptdev,
    1.37 +    struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
    1.38 +static int pt_byte_reg_read(struct pt_dev *ptdev,
    1.39 +    struct pt_reg_tbl *cfg_entry,
    1.40 +    uint8_t *valueu, uint8_t valid_mask);
    1.41 +static int pt_word_reg_read(struct pt_dev *ptdev,
    1.42 +    struct pt_reg_tbl *cfg_entry,
    1.43 +    uint16_t *value, uint16_t valid_mask);
    1.44 +static int pt_long_reg_read(struct pt_dev *ptdev,
    1.45 +    struct pt_reg_tbl *cfg_entry,
    1.46 +    uint32_t *value, uint32_t valid_mask);
    1.47 +static int pt_bar_reg_read(struct pt_dev *ptdev,
    1.48 +    struct pt_reg_tbl *cfg_entry,
    1.49 +    uint32_t *value, uint32_t valid_mask);
    1.50 +static int pt_byte_reg_write(struct pt_dev *ptdev, 
    1.51 +    struct pt_reg_tbl *cfg_entry, 
    1.52 +    uint8_t *value, uint8_t dev_value, uint8_t valid_mask);
    1.53 +static int pt_word_reg_write(struct pt_dev *ptdev, 
    1.54 +    struct pt_reg_tbl *cfg_entry, 
    1.55 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
    1.56 +static int pt_long_reg_write(struct pt_dev *ptdev, 
    1.57 +    struct pt_reg_tbl *cfg_entry, 
    1.58 +    uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
    1.59 +static int pt_cmd_reg_write(struct pt_dev *ptdev, 
    1.60 +    struct pt_reg_tbl *cfg_entry, 
    1.61 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
    1.62 +static int pt_bar_reg_write(struct pt_dev *ptdev, 
    1.63 +    struct pt_reg_tbl *cfg_entry, 
    1.64 +    uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
    1.65 +static int pt_exp_rom_bar_reg_write(struct pt_dev *ptdev, 
    1.66 +    struct pt_reg_tbl *cfg_entry, 
    1.67 +    uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
    1.68 +static int pt_pmcsr_reg_write(struct pt_dev *ptdev, 
    1.69 +    struct pt_reg_tbl *cfg_entry, 
    1.70 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
    1.71 +static int pt_devctrl_reg_write(struct pt_dev *ptdev, 
    1.72 +    struct pt_reg_tbl *cfg_entry, 
    1.73 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
    1.74 +static int pt_linkctrl_reg_write(struct pt_dev *ptdev, 
    1.75 +    struct pt_reg_tbl *cfg_entry, 
    1.76 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
    1.77 +static int pt_devctrl2_reg_write(struct pt_dev *ptdev, 
    1.78 +    struct pt_reg_tbl *cfg_entry, 
    1.79 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
    1.80 +static int pt_linkctrl2_reg_write(struct pt_dev *ptdev, 
    1.81 +    struct pt_reg_tbl *cfg_entry, 
    1.82 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
    1.83 +static int pt_msgctrl_reg_write(struct pt_dev *ptdev, 
    1.84 +    struct pt_reg_tbl *cfg_entry, 
    1.85 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
    1.86 +static int pt_msgaddr32_reg_write(struct pt_dev *ptdev, 
    1.87 +    struct pt_reg_tbl *cfg_entry, 
    1.88 +    uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
    1.89 +static int pt_msgaddr64_reg_write(struct pt_dev *ptdev, 
    1.90 +    struct pt_reg_tbl *cfg_entry, 
    1.91 +    uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
    1.92 +static int pt_msgdata_reg_write(struct pt_dev *ptdev, 
    1.93 +    struct pt_reg_tbl *cfg_entry, 
    1.94 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
    1.95 +static int pt_msixctrl_reg_write(struct pt_dev *ptdev, 
    1.96 +    struct pt_reg_tbl *cfg_entry, 
    1.97 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
    1.98 +
    1.99 +/* Header Type0 reg static infomation table */
   1.100 +static struct pt_reg_info_tbl pt_emu_reg_header0_tbl[] = {
   1.101 +    /* Command reg */
   1.102 +    {
   1.103 +        .offset     = PCI_COMMAND,
   1.104 +        .size       = 2,
   1.105 +        .init_val   = 0x0000,
   1.106 +        .ro_mask    = 0xF880,
   1.107 +        .emu_mask   = 0x0340,
   1.108 +        .init       = pt_common_reg_init,
   1.109 +        .u.w.read   = pt_word_reg_read,
   1.110 +        .u.w.write  = pt_cmd_reg_write,
   1.111 +    },
   1.112 +    /* Capabilities Pointer reg */
   1.113 +    {
   1.114 +        .offset     = PCI_CAPABILITY_LIST,
   1.115 +        .size       = 1,
   1.116 +        .init_val   = 0x00,
   1.117 +        .ro_mask    = 0xFF,
   1.118 +        .emu_mask   = 0xFF,
   1.119 +        .init       = pt_ptr_reg_init,
   1.120 +        .u.b.read   = pt_byte_reg_read,
   1.121 +        .u.b.write  = pt_byte_reg_write,
   1.122 +    },
   1.123 +    /* Status reg */
   1.124 +    /* use emulated Cap Ptr value to initialize, 
   1.125 +     * so need to be declared after Cap Ptr reg 
   1.126 +     */
   1.127 +    {
   1.128 +        .offset     = PCI_STATUS,
   1.129 +        .size       = 2,
   1.130 +        .init_val   = 0x0000,
   1.131 +        .ro_mask    = 0x06FF,
   1.132 +        .emu_mask   = 0x0010,
   1.133 +        .init       = pt_status_reg_init,
   1.134 +        .u.w.read   = pt_word_reg_read,
   1.135 +        .u.w.write  = pt_word_reg_write,
   1.136 +    },
   1.137 +    /* Cache Line Size reg */
   1.138 +    {
   1.139 +        .offset     = PCI_CACHE_LINE_SIZE,
   1.140 +        .size       = 1,
   1.141 +        .init_val   = 0x00,
   1.142 +        .ro_mask    = 0x00,
   1.143 +        .emu_mask   = 0xFF,
   1.144 +        .init       = pt_common_reg_init,
   1.145 +        .u.b.read   = pt_byte_reg_read,
   1.146 +        .u.b.write  = pt_byte_reg_write,
   1.147 +    },
   1.148 +    /* Latency Timer reg */
   1.149 +    {
   1.150 +        .offset     = PCI_LATENCY_TIMER,
   1.151 +        .size       = 1,
   1.152 +        .init_val   = 0x00,
   1.153 +        .ro_mask    = 0x00,
   1.154 +        .emu_mask   = 0xFF,
   1.155 +        .init       = pt_common_reg_init,
   1.156 +        .u.b.read   = pt_byte_reg_read,
   1.157 +        .u.b.write  = pt_byte_reg_write,
   1.158 +    },
   1.159 +    /* Header Type reg */
   1.160 +    {
   1.161 +        .offset     = PCI_HEADER_TYPE,
   1.162 +        .size       = 1,
   1.163 +        .init_val   = 0x00,
   1.164 +        .ro_mask    = 0xFF,
   1.165 +        .emu_mask   = 0x80,
   1.166 +        .init       = pt_common_reg_init,
   1.167 +        .u.b.read   = pt_byte_reg_read,
   1.168 +        .u.b.write  = pt_byte_reg_write,
   1.169 +    },
   1.170 +    /* Interrupt Line reg */
   1.171 +    {
   1.172 +        .offset     = PCI_INTERRUPT_LINE,
   1.173 +        .size       = 1,
   1.174 +        .init_val   = 0x00,
   1.175 +        .ro_mask    = 0x00,
   1.176 +        .emu_mask   = 0xFF,
   1.177 +        .init       = pt_common_reg_init,
   1.178 +        .u.b.read   = pt_byte_reg_read,
   1.179 +        .u.b.write  = pt_byte_reg_write,
   1.180 +    },
   1.181 +    /* Interrupt Pin reg */
   1.182 +    {
   1.183 +        .offset     = PCI_INTERRUPT_PIN,
   1.184 +        .size       = 1,
   1.185 +        .init_val   = 0x00,
   1.186 +        .ro_mask    = 0xFF,
   1.187 +        .emu_mask   = 0xFF,
   1.188 +        .init       = pt_irqpin_reg_init,
   1.189 +        .u.b.read   = pt_byte_reg_read,
   1.190 +        .u.b.write  = pt_byte_reg_write,
   1.191 +    },
   1.192 +    /* BAR 0 reg */
   1.193 +    /* mask of BAR need to be decided later, depends on IO/MEM type */
   1.194 +    {
   1.195 +        .offset     = PCI_BASE_ADDRESS_0,
   1.196 +        .size       = 4,
   1.197 +        .init_val   = 0x00000000,
   1.198 +        .init       = pt_bar_reg_init,
   1.199 +        .u.dw.read  = pt_bar_reg_read,
   1.200 +        .u.dw.write = pt_bar_reg_write,
   1.201 +    },
   1.202 +    /* BAR 1 reg */
   1.203 +    {
   1.204 +        .offset     = PCI_BASE_ADDRESS_1,
   1.205 +        .size       = 4,
   1.206 +        .init_val   = 0x00000000,
   1.207 +        .init       = pt_bar_reg_init,
   1.208 +        .u.dw.read  = pt_bar_reg_read,
   1.209 +        .u.dw.write = pt_bar_reg_write,
   1.210 +    },
   1.211 +    /* BAR 2 reg */
   1.212 +    {
   1.213 +        .offset     = PCI_BASE_ADDRESS_2,
   1.214 +        .size       = 4,
   1.215 +        .init_val   = 0x00000000,
   1.216 +        .init       = pt_bar_reg_init,
   1.217 +        .u.dw.read  = pt_bar_reg_read,
   1.218 +        .u.dw.write = pt_bar_reg_write,
   1.219 +    },
   1.220 +    /* BAR 3 reg */
   1.221 +    {
   1.222 +        .offset     = PCI_BASE_ADDRESS_3,
   1.223 +        .size       = 4,
   1.224 +        .init_val   = 0x00000000,
   1.225 +        .init       = pt_bar_reg_init,
   1.226 +        .u.dw.read  = pt_bar_reg_read,
   1.227 +        .u.dw.write = pt_bar_reg_write,
   1.228 +    },
   1.229 +    /* BAR 4 reg */
   1.230 +    {
   1.231 +        .offset     = PCI_BASE_ADDRESS_4,
   1.232 +        .size       = 4,
   1.233 +        .init_val   = 0x00000000,
   1.234 +        .init       = pt_bar_reg_init,
   1.235 +        .u.dw.read  = pt_bar_reg_read,
   1.236 +        .u.dw.write = pt_bar_reg_write,
   1.237 +    },
   1.238 +    /* BAR 5 reg */
   1.239 +    {
   1.240 +        .offset     = PCI_BASE_ADDRESS_5,
   1.241 +        .size       = 4,
   1.242 +        .init_val   = 0x00000000,
   1.243 +        .init       = pt_bar_reg_init,
   1.244 +        .u.dw.read  = pt_bar_reg_read,
   1.245 +        .u.dw.write = pt_bar_reg_write,
   1.246 +    },
   1.247 +    /* Expansion ROM BAR reg */
   1.248 +    {
   1.249 +        .offset     = PCI_ROM_ADDRESS,
   1.250 +        .size       = 4,
   1.251 +        .init_val   = 0x00000000,
   1.252 +        .ro_mask    = 0x000007FE,
   1.253 +        .emu_mask   = 0xFFFFF800,
   1.254 +        .init       = pt_bar_reg_init,
   1.255 +        .u.dw.read  = pt_long_reg_read,
   1.256 +        .u.dw.write = pt_exp_rom_bar_reg_write,
   1.257 +    },
   1.258 +    {
   1.259 +        .size = 0,
   1.260 +    }, 
   1.261 +};
   1.262 +
   1.263 +/* Power Management Capability reg static infomation table */
   1.264 +static struct pt_reg_info_tbl pt_emu_reg_pm_tbl[] = {
   1.265 +    /* Next Pointer reg */
   1.266 +    {
   1.267 +        .offset     = PCI_CAP_LIST_NEXT,
   1.268 +        .size       = 1,
   1.269 +        .init_val   = 0x00,
   1.270 +        .ro_mask    = 0xFF,
   1.271 +        .emu_mask   = 0xFF,
   1.272 +        .init       = pt_ptr_reg_init,
   1.273 +        .u.b.read   = pt_byte_reg_read,
   1.274 +        .u.b.write  = pt_byte_reg_write,
   1.275 +    },
   1.276 +    /* Power Management Capabilities reg */
   1.277 +    {
   1.278 +        .offset     = PCI_CAP_FLAGS,
   1.279 +        .size       = 2,
   1.280 +        .init_val   = 0x0000,
   1.281 +        .ro_mask    = 0xFFFF,
   1.282 +        .emu_mask   = 0xFFE8,
   1.283 +        .init       = pt_common_reg_init,
   1.284 +        .u.w.read   = pt_word_reg_read,
   1.285 +        .u.w.write  = pt_word_reg_write,
   1.286 +    },
   1.287 +    /* PCI Power Management Control/Status reg */
   1.288 +    {
   1.289 +        .offset     = PCI_PM_CTRL,
   1.290 +        .size       = 2,
   1.291 +        .init_val   = 0x0008,
   1.292 +        .ro_mask    = 0x60FC,
   1.293 +        .emu_mask   = 0xFF0B,
   1.294 +        .init       = pt_common_reg_init,
   1.295 +        .u.w.read   = pt_word_reg_read,
   1.296 +        .u.w.write  = pt_pmcsr_reg_write,
   1.297 +    },
   1.298 +    /* Data reg */
   1.299 +    {
   1.300 +        .offset     = PCI_PM_DATA_REGISTER,
   1.301 +        .size       = 1,
   1.302 +        .init_val   = 0x00,
   1.303 +        .ro_mask    = 0xFF,
   1.304 +        .emu_mask   = 0xFF,
   1.305 +        .init       = pt_common_reg_init,
   1.306 +        .u.b.read   = pt_byte_reg_read,
   1.307 +        .u.b.write  = pt_byte_reg_write,
   1.308 +    },
   1.309 +    {
   1.310 +        .size = 0,
   1.311 +    }, 
   1.312 +};
   1.313 +
   1.314 +/* Vital Product Data Capability Structure reg static infomation table */
   1.315 +static struct pt_reg_info_tbl pt_emu_reg_vpd_tbl[] = {
   1.316 +    /* Next Pointer reg */
   1.317 +    {
   1.318 +        .offset     = PCI_CAP_LIST_NEXT,
   1.319 +        .size       = 1,
   1.320 +        .init_val   = 0x00,
   1.321 +        .ro_mask    = 0xFF,
   1.322 +        .emu_mask   = 0xFF,
   1.323 +        .init       = pt_ptr_reg_init,
   1.324 +        .u.b.read   = pt_byte_reg_read,
   1.325 +        .u.b.write  = pt_byte_reg_write,
   1.326 +    },
   1.327 +    {
   1.328 +        .size = 0,
   1.329 +    }, 
   1.330 +};
   1.331 +
   1.332 +/* Vendor Specific Capability Structure reg static infomation table */
   1.333 +static struct pt_reg_info_tbl pt_emu_reg_vendor_tbl[] = {
   1.334 +    /* Next Pointer reg */
   1.335 +    {
   1.336 +        .offset     = PCI_CAP_LIST_NEXT,
   1.337 +        .size       = 1,
   1.338 +        .init_val   = 0x00,
   1.339 +        .ro_mask    = 0xFF,
   1.340 +        .emu_mask   = 0xFF,
   1.341 +        .init       = pt_ptr_reg_init,
   1.342 +        .u.b.read   = pt_byte_reg_read,
   1.343 +        .u.b.write  = pt_byte_reg_write,
   1.344 +    },
   1.345 +    {
   1.346 +        .size = 0,
   1.347 +    }, 
   1.348 +};
   1.349 +
   1.350 +/* PCI Express Capability Structure reg static infomation table */
   1.351 +static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = {
   1.352 +    /* Next Pointer reg */
   1.353 +    {
   1.354 +        .offset     = PCI_CAP_LIST_NEXT,
   1.355 +        .size       = 1,
   1.356 +        .init_val   = 0x00,
   1.357 +        .ro_mask    = 0xFF,
   1.358 +        .emu_mask   = 0xFF,
   1.359 +        .init       = pt_ptr_reg_init,
   1.360 +        .u.b.read   = pt_byte_reg_read,
   1.361 +        .u.b.write  = pt_byte_reg_write,
   1.362 +    },
   1.363 +    /* Device Capabilities reg */
   1.364 +    {
   1.365 +        .offset     = PCI_EXP_DEVCAP,
   1.366 +        .size       = 4,
   1.367 +        .init_val   = 0x00000000,
   1.368 +        .ro_mask    = 0x1FFCFFFF,
   1.369 +        .emu_mask   = 0x10000000,
   1.370 +        .init       = pt_common_reg_init,
   1.371 +        .u.dw.read  = pt_long_reg_read,
   1.372 +        .u.dw.write = pt_long_reg_write,
   1.373 +    },
   1.374 +    /* Device Control reg */
   1.375 +    {
   1.376 +        .offset     = PCI_EXP_DEVCTL,
   1.377 +        .size       = 2,
   1.378 +        .init_val   = 0x2810,
   1.379 +        .ro_mask    = 0x0000,
   1.380 +        .emu_mask   = 0xFFFF,
   1.381 +        .init       = pt_common_reg_init,
   1.382 +        .u.w.read   = pt_word_reg_read,
   1.383 +        .u.w.write  = pt_devctrl_reg_write,
   1.384 +    },
   1.385 +    /* Link Control reg */
   1.386 +    {
   1.387 +        .offset     = PCI_EXP_LNKCTL,
   1.388 +        .size       = 2,
   1.389 +        .init_val   = 0x0000,
   1.390 +        .ro_mask    = 0x0000,
   1.391 +        .emu_mask   = 0xFFFF,
   1.392 +        .init       = pt_common_reg_init,
   1.393 +        .u.w.read   = pt_word_reg_read,
   1.394 +        .u.w.write  = pt_linkctrl_reg_write,
   1.395 +    },
   1.396 +    /* Device Control 2 reg */
   1.397 +    {
   1.398 +        .offset     = 0x28,
   1.399 +        .size       = 2,
   1.400 +        .init_val   = 0x0000,
   1.401 +        .ro_mask    = 0x0000,
   1.402 +        .emu_mask   = 0xFFFF,
   1.403 +        .init       = pt_common_reg_init,
   1.404 +        .u.w.read   = pt_word_reg_read,
   1.405 +        .u.w.write  = pt_devctrl2_reg_write,
   1.406 +    },
   1.407 +    /* Link Control 2 reg */
   1.408 +    {
   1.409 +        .offset     = 0x30,
   1.410 +        .size       = 2,
   1.411 +        .init_val   = 0x0000,
   1.412 +        .ro_mask    = 0x0000,
   1.413 +        .emu_mask   = 0xFFFF,
   1.414 +        .init       = pt_linkctrl2_reg_init,
   1.415 +        .u.w.read   = pt_word_reg_read,
   1.416 +        .u.w.write  = pt_linkctrl2_reg_write,
   1.417 +    },
   1.418 +    {
   1.419 +        .size = 0,
   1.420 +    }, 
   1.421 +};
   1.422 +
   1.423 +/* MSI Capability Structure reg static infomation table */
   1.424 +static struct pt_reg_info_tbl pt_emu_reg_msi_tbl[] = {
   1.425 +    /* Next Pointer reg */
   1.426 +    {
   1.427 +        .offset     = PCI_CAP_LIST_NEXT,
   1.428 +        .size       = 1,
   1.429 +        .init_val   = 0x00,
   1.430 +        .ro_mask    = 0xFF,
   1.431 +        .emu_mask   = 0xFF,
   1.432 +        .init       = pt_ptr_reg_init,
   1.433 +        .u.b.read   = pt_byte_reg_read,
   1.434 +        .u.b.write  = pt_byte_reg_write,
   1.435 +    },
   1.436 +    /* Message Control reg */
   1.437 +    {
   1.438 +        .offset     = PCI_MSI_FLAGS, // 2
   1.439 +        .size       = 2,
   1.440 +        .init_val   = 0x0000,
   1.441 +        .ro_mask    = 0x018E,
   1.442 +        .emu_mask   = 0xFFFE,
   1.443 +        .init       = pt_msgctrl_reg_init,
   1.444 +        .u.w.read   = pt_word_reg_read,
   1.445 +        .u.w.write  = pt_msgctrl_reg_write,
   1.446 +    },
   1.447 +    /* Message Address reg */
   1.448 +    {
   1.449 +        .offset     = PCI_MSI_ADDRESS_LO, // 4
   1.450 +        .size       = 4,
   1.451 +        .init_val   = 0x00000000,
   1.452 +        .ro_mask    = 0x00000FF0,    /* bit 4~11 is reserved for MSI in x86 */
   1.453 +        .emu_mask   = 0xFFFFFFFF,
   1.454 +        .init       = pt_msgaddr32_reg_init,
   1.455 +        .u.dw.read  = pt_long_reg_read,
   1.456 +        .u.dw.write = pt_msgaddr32_reg_write,
   1.457 +    },
   1.458 +    /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
   1.459 +    {
   1.460 +        .offset     = PCI_MSI_ADDRESS_HI, // 8
   1.461 +        .size       = 4,
   1.462 +        .init_val   = 0x00000000,
   1.463 +        .ro_mask    = 0x00000000,
   1.464 +        .emu_mask   = 0xFFFFFFFF,
   1.465 +        .init       = pt_msgaddr64_reg_init,
   1.466 +        .u.dw.read  = pt_long_reg_read,
   1.467 +        .u.dw.write = pt_msgaddr64_reg_write,
   1.468 +    },
   1.469 +    /* Message Data reg (16 bits of data for 32-bit devices) */
   1.470 +    {
   1.471 +        .offset     = PCI_MSI_DATA_32, // 8
   1.472 +        .size       = 2,
   1.473 +        .init_val   = 0x0000,
   1.474 +        .ro_mask    = 0x3800,
   1.475 +        .emu_mask   = 0xFFFF,
   1.476 +        .init       = pt_msgdata_reg_init,
   1.477 +        .u.w.read   = pt_word_reg_read,
   1.478 +        .u.w.write  = pt_msgdata_reg_write,
   1.479 +    },
   1.480 +    /* Message Data reg (16 bits of data for 64-bit devices) */
   1.481 +    {
   1.482 +        .offset     = PCI_MSI_DATA_64, // 12
   1.483 +        .size       = 2,
   1.484 +        .init_val   = 0x0000,
   1.485 +        .ro_mask    = 0x3800,
   1.486 +        .emu_mask   = 0xFFFF,
   1.487 +        .init       = pt_msgdata_reg_init,
   1.488 +        .u.w.read   = pt_word_reg_read,
   1.489 +        .u.w.write  = pt_msgdata_reg_write,
   1.490 +    },
   1.491 +    {
   1.492 +        .size = 0,
   1.493 +    }, 
   1.494 +};
   1.495 +
   1.496 +/* MSI-X Capability Structure reg static infomation table */
   1.497 +static struct pt_reg_info_tbl pt_emu_reg_msix_tbl[] = {
   1.498 +    /* Next Pointer reg */
   1.499 +    {
   1.500 +        .offset     = PCI_CAP_LIST_NEXT,
   1.501 +        .size       = 1,
   1.502 +        .init_val   = 0x00,
   1.503 +        .ro_mask    = 0xFF,
   1.504 +        .emu_mask   = 0xFF,
   1.505 +        .init       = pt_ptr_reg_init,
   1.506 +        .u.b.read   = pt_byte_reg_read,
   1.507 +        .u.b.write  = pt_byte_reg_write,
   1.508 +    },
   1.509 +    /* Message Control reg */
   1.510 +    {
   1.511 +        .offset     = PCI_MSI_FLAGS, // 2
   1.512 +        .size       = 2,
   1.513 +        .init_val   = 0x0000,
   1.514 +        .ro_mask    = 0x3FFF,
   1.515 +        .emu_mask   = 0x0000,
   1.516 +        .init       = pt_msixctrl_reg_init,
   1.517 +        .u.w.read   = pt_word_reg_read,
   1.518 +        .u.w.write  = pt_msixctrl_reg_write,
   1.519 +    },
   1.520 +    {
   1.521 +        .size = 0,
   1.522 +    }, 
   1.523 +};
   1.524 +
   1.525 +/* emul reg group static infomation table */
   1.526 +static const struct pt_reg_grp_info_tbl pt_emu_reg_grp_tbl[] = {
   1.527 +    /* Header Type0 reg group */
   1.528 +    {
   1.529 +        .grp_id     = 0xFF,
   1.530 +        .grp_type   = GRP_TYPE_EMU,
   1.531 +        .grp_size   = 0x40,
   1.532 +        .size_init  = pt_reg_grp_size_init,
   1.533 +        .emu_reg_tbl= pt_emu_reg_header0_tbl,
   1.534 +    },
   1.535 +    /* PCI PowerManagement Capability reg group */
   1.536 +    {
   1.537 +        .grp_id     = PCI_CAP_ID_PM,
   1.538 +        .grp_type   = GRP_TYPE_EMU,
   1.539 +        .grp_size   = PCI_PM_SIZEOF,
   1.540 +        .size_init  = pt_reg_grp_size_init,
   1.541 +        .emu_reg_tbl= pt_emu_reg_pm_tbl,
   1.542 +    },
   1.543 +    /* AGP Capability Structure reg group */
   1.544 +    {
   1.545 +        .grp_id     = PCI_CAP_ID_AGP,
   1.546 +        .grp_type   = GRP_TYPE_HARDWIRED,
   1.547 +        .grp_size   = 0x30,
   1.548 +        .size_init  = pt_reg_grp_size_init,
   1.549 +    },
   1.550 +    /* Vital Product Data Capability Structure reg group */
   1.551 +    {
   1.552 +        .grp_id     = PCI_CAP_ID_VPD,
   1.553 +        .grp_type   = GRP_TYPE_EMU,
   1.554 +        .grp_size   = 0x08,
   1.555 +        .size_init  = pt_reg_grp_size_init,
   1.556 +        .emu_reg_tbl= pt_emu_reg_vpd_tbl,
   1.557 +    },
   1.558 +    /* Slot Identification reg group */
   1.559 +    {
   1.560 +        .grp_id     = PCI_CAP_ID_SLOTID,
   1.561 +        .grp_type   = GRP_TYPE_HARDWIRED,
   1.562 +        .grp_size   = 0x04,
   1.563 +        .size_init  = pt_reg_grp_size_init,
   1.564 +    },
   1.565 +    /* MSI Capability Structure reg group */
   1.566 +    {
   1.567 +        .grp_id     = PCI_CAP_ID_MSI,
   1.568 +        .grp_type   = GRP_TYPE_EMU,
   1.569 +        .grp_size   = 0xFF,
   1.570 +        .size_init  = pt_msi_size_init,
   1.571 +        .emu_reg_tbl= pt_emu_reg_msi_tbl,
   1.572 +    },
   1.573 +    /* PCI-X Capabilities List Item reg group */
   1.574 +    {
   1.575 +        .grp_id     = PCI_CAP_ID_PCIX,
   1.576 +        .grp_type   = GRP_TYPE_HARDWIRED,
   1.577 +        .grp_size   = 0x18,
   1.578 +        .size_init  = pt_reg_grp_size_init,
   1.579 +    },
   1.580 +    /* Vendor Specific Capability Structure reg group */
   1.581 +    {
   1.582 +        .grp_id     = PCI_CAP_ID_VNDR,
   1.583 +        .grp_type   = GRP_TYPE_EMU,
   1.584 +        .grp_size   = 0xFF,
   1.585 +        .size_init  = pt_vendor_size_init,
   1.586 +        .emu_reg_tbl= pt_emu_reg_vendor_tbl,
   1.587 +    },
   1.588 +    /* SHPC Capability List Item reg group */
   1.589 +    {
   1.590 +        .grp_id     = PCI_CAP_ID_HOTPLUG,
   1.591 +        .grp_type   = GRP_TYPE_HARDWIRED,
   1.592 +        .grp_size   = 0x08,
   1.593 +        .size_init  = pt_reg_grp_size_init,
   1.594 +    },
   1.595 +    /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
   1.596 +    {
   1.597 +        .grp_id     = PCI_CAP_ID_SSVID,
   1.598 +        .grp_type   = GRP_TYPE_HARDWIRED,
   1.599 +        .grp_size   = 0x08,
   1.600 +        .size_init  = pt_reg_grp_size_init,
   1.601 +    },
   1.602 +    /* AGP 8x Capability Structure reg group */
   1.603 +    {
   1.604 +        .grp_id     = PCI_CAP_ID_AGP3,
   1.605 +        .grp_type   = GRP_TYPE_HARDWIRED,
   1.606 +        .grp_size   = 0x30,
   1.607 +        .size_init  = pt_reg_grp_size_init,
   1.608 +    },
   1.609 +    /* PCI Express Capability Structure reg group */
   1.610 +    {
   1.611 +        .grp_id     = PCI_CAP_ID_EXP,
   1.612 +        .grp_type   = GRP_TYPE_EMU,
   1.613 +        .grp_size   = 0x3C,
   1.614 +        .size_init  = pt_reg_grp_size_init,
   1.615 +        .emu_reg_tbl= pt_emu_reg_pcie_tbl,
   1.616 +    },
   1.617 +    /* MSI-X Capability Structure reg group */
   1.618 +    {
   1.619 +        .grp_id     = PCI_CAP_ID_MSIX,
   1.620 +        .grp_type   = GRP_TYPE_EMU,
   1.621 +        .grp_size   = 0x0C,
   1.622 +        .size_init  = pt_msix_size_init,
   1.623 +        .emu_reg_tbl= pt_emu_reg_msix_tbl,
   1.624 +    },
   1.625 +    {
   1.626 +        .grp_size = 0,
   1.627 +    }, 
   1.628 +};
   1.629 +
   1.630  static int token_value(char *token)
   1.631  {
   1.632      return strtol(token, NULL, 16);
   1.633 @@ -197,8 +820,9 @@ void pt_iomem_map(PCIDevice *d, int i, u
   1.634      assigned_device->bases[i].e_physbase = e_phys;
   1.635      assigned_device->bases[i].e_size= e_size;
   1.636  
   1.637 -    PT_LOG("e_phys=%08x maddr=%08x type=%d len=%08x index=%d\n",
   1.638 -        e_phys, assigned_device->bases[i].access.maddr, type, e_size, i);
   1.639 +    PT_LOG("e_phys=%08x maddr=%lx type=%d len=%d index=%d first_map=%d\n",
   1.640 +        e_phys, assigned_device->bases[i].access.maddr, 
   1.641 +        type, e_size, i, first_map);
   1.642  
   1.643      if ( e_size == 0 )
   1.644          return;
   1.645 @@ -219,18 +843,25 @@ void pt_iomem_map(PCIDevice *d, int i, u
   1.646          }
   1.647      }
   1.648  
   1.649 -    /* Create new mapping */
   1.650 -    ret = xc_domain_memory_mapping(xc_handle, domid,
   1.651 -            assigned_device->bases[i].e_physbase >> XC_PAGE_SHIFT,
   1.652 -            assigned_device->bases[i].access.maddr >> XC_PAGE_SHIFT,
   1.653 -            (e_size+XC_PAGE_SIZE-1) >> XC_PAGE_SHIFT,
   1.654 -            DPCI_ADD_MAPPING);
   1.655 -    if ( ret != 0 )
   1.656 -        PT_LOG("Error: create new mapping failed!\n");
   1.657 +    /* map only valid guest address (include 0) */
   1.658 +    if (e_phys != -1)
   1.659 +    {
   1.660 +        /* Create new mapping */
   1.661 +        ret = xc_domain_memory_mapping(xc_handle, domid,
   1.662 +                assigned_device->bases[i].e_physbase >> XC_PAGE_SHIFT,
   1.663 +                assigned_device->bases[i].access.maddr >> XC_PAGE_SHIFT,
   1.664 +                (e_size+XC_PAGE_SIZE-1) >> XC_PAGE_SHIFT,
   1.665 +                DPCI_ADD_MAPPING);
   1.666  
   1.667 -    ret = remove_msix_mapping(assigned_device, i);
   1.668 -    if ( ret != 0 )
   1.669 -        PT_LOG("Error: remove MSX-X mmio mapping failed!\n");
   1.670 +        if ( ret != 0 )
   1.671 +        {
   1.672 +            PT_LOG("Error: create new mapping failed!\n");
   1.673 +        }
   1.674 +        
   1.675 +        ret = remove_msix_mapping(assigned_device, i);
   1.676 +        if ( ret != 0 )
   1.677 +            PT_LOG("Error: remove MSX-X mmio mapping failed!\n");
   1.678 +    }
   1.679  }
   1.680  
   1.681  /* Being called each time a pio region has been updated */
   1.682 @@ -245,9 +876,9 @@ void pt_ioport_map(PCIDevice *d, int i,
   1.683      assigned_device->bases[i].e_physbase = e_phys;
   1.684      assigned_device->bases[i].e_size= e_size;
   1.685  
   1.686 -    PT_LOG("e_phys=%04x pio_base=%04x len=%04x index=%d\n",
   1.687 +    PT_LOG("e_phys=%04x pio_base=%04x len=%d index=%d first_map=%d\n",
   1.688          (uint16_t)e_phys, (uint16_t)assigned_device->bases[i].access.pio_base,
   1.689 -        (uint16_t)e_size, i);
   1.690 +        (uint16_t)e_size, i, first_map);
   1.691  
   1.692      if ( e_size == 0 )
   1.693          return;
   1.694 @@ -265,13 +896,86 @@ void pt_ioport_map(PCIDevice *d, int i,
   1.695          }
   1.696      }
   1.697  
   1.698 -    /* Create new mapping */
   1.699 -    ret = xc_domain_ioport_mapping(xc_handle, domid, e_phys,
   1.700 -                assigned_device->bases[i].access.pio_base, e_size,
   1.701 -                DPCI_ADD_MAPPING);
   1.702 -    if ( ret != 0 )
   1.703 -        PT_LOG("Error: create new mapping failed!\n");
   1.704 +    /* map only valid guest address (include 0) */
   1.705 +    if (e_phys != -1)
   1.706 +    {
   1.707 +        /* Create new mapping */
   1.708 +        ret = xc_domain_ioport_mapping(xc_handle, domid, e_phys,
   1.709 +                    assigned_device->bases[i].access.pio_base, e_size,
   1.710 +                    DPCI_ADD_MAPPING);
   1.711 +        if ( ret != 0 )
   1.712 +        {
   1.713 +            PT_LOG("Error: create new mapping failed!\n");
   1.714 +        }
   1.715 +    }
   1.716 +}
   1.717 +
   1.718 +/* find emulate register group entry */
   1.719 +struct pt_reg_grp_tbl* pt_find_reg_grp(
   1.720 +        struct pt_dev *ptdev, uint32_t address)
   1.721 +{
   1.722 +    struct pt_reg_grp_tbl* reg_grp_entry = NULL;
   1.723 +
   1.724 +    /* find register group entry */
   1.725 +    for (reg_grp_entry = ptdev->reg_grp_tbl_head.lh_first; reg_grp_entry;
   1.726 +        reg_grp_entry = reg_grp_entry->entries.le_next)
   1.727 +    {
   1.728 +        /* check address */
   1.729 +        if ((reg_grp_entry->base_offset <= address) &&
   1.730 +            ((reg_grp_entry->base_offset + reg_grp_entry->size) > address))
   1.731 +            goto out;
   1.732 +    }
   1.733 +    /* group entry not found */
   1.734 +    reg_grp_entry = NULL;
   1.735 +
   1.736 +out:
   1.737 +    return reg_grp_entry;
   1.738 +}
   1.739  
   1.740 +/* find emulate register entry */
   1.741 +struct pt_reg_tbl* pt_find_reg(
   1.742 +        struct pt_reg_grp_tbl* reg_grp, uint32_t address)
   1.743 +{
   1.744 +    struct pt_reg_tbl* reg_entry = NULL;
   1.745 +    struct pt_reg_info_tbl* reg = NULL;
   1.746 +    uint32_t real_offset = 0;
   1.747 +
   1.748 +    /* find register entry */
   1.749 +    for (reg_entry = reg_grp->reg_tbl_head.lh_first; reg_entry;
   1.750 +        reg_entry = reg_entry->entries.le_next)
   1.751 +    {
   1.752 +        reg = reg_entry->reg;
   1.753 +        real_offset = (reg_grp->base_offset + reg->offset);
   1.754 +        /* check address */
   1.755 +        if ((real_offset <= address) && ((real_offset + reg->size) > address))
   1.756 +            goto out;
   1.757 +    }
   1.758 +    /* register entry not found */
   1.759 +    reg_entry = NULL;
   1.760 +
   1.761 +out:
   1.762 +    return reg_entry;
   1.763 +}
   1.764 +
   1.765 +/* get BAR index */
   1.766 +static int pt_bar_offset_to_index(uint32_t offset)
   1.767 +{
   1.768 +    int index = 0;
   1.769 +
   1.770 +    /* check Exp ROM BAR */
   1.771 +    if (offset == PCI_ROM_ADDRESS)
   1.772 +    {
   1.773 +        index = PCI_ROM_SLOT;
   1.774 +        goto out;
   1.775 +    }
   1.776 +
   1.777 +    /* calculate BAR index */
   1.778 +    index = ((offset - PCI_BASE_ADDRESS_0) >> 2);
   1.779 +    if (index >= PCI_NUM_REGIONS)
   1.780 +        index = -1;
   1.781 +
   1.782 +out:
   1.783 +    return index;
   1.784  }
   1.785  
   1.786  static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val,
   1.787 @@ -279,60 +983,258 @@ static void pt_pci_write_config(PCIDevic
   1.788  {
   1.789      struct pt_dev *assigned_device = (struct pt_dev *)d;
   1.790      struct pci_dev *pci_dev = assigned_device->pci_dev;
   1.791 -
   1.792 -#ifdef PT_DEBUG_PCI_CONFIG_ACCESS
   1.793 -    PT_LOG("(%x.%x): address=%04x val=0x%08x len=%d\n",
   1.794 -       (d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val, len);
   1.795 -#endif
   1.796 +    struct pt_reg_grp_tbl *reg_grp_entry = NULL;
   1.797 +    struct pt_reg_grp_info_tbl *reg_grp = NULL;
   1.798 +    struct pt_reg_tbl *reg_entry = NULL;
   1.799 +    struct pt_reg_info_tbl *reg = NULL;
   1.800 +    uint32_t find_addr = address;
   1.801 +    uint32_t real_offset = 0;
   1.802 +    uint32_t valid_mask = 0xFFFFFFFF;
   1.803 +    uint32_t read_val = 0;
   1.804 +    uint8_t *ptr_val = NULL;
   1.805 +    int emul_len = 0;
   1.806 +    int index = 0;
   1.807 +    int ret = 0;
   1.808  
   1.809 -    /* Pre-write hooking */
   1.810 -    switch ( address ) {
   1.811 -    case 0x0C ... 0x3F:
   1.812 -        pci_default_write_config(d, address, val, len);
   1.813 -        return;
   1.814 +    PT_LOG("write(%x.%x): address=%04x val=0x%08x len=%d\n",
   1.815 +        (d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val, len);
   1.816 +
   1.817 +    /* check offset range */
   1.818 +    if (address >= 0xFF)
   1.819 +    {
   1.820 +        PT_LOG("Failed to write register with offset exceeding FFh. "
   1.821 +            "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
   1.822 +            pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
   1.823 +            address, len);
   1.824 +        goto exit;
   1.825      }
   1.826  
   1.827 -    if ( pt_msi_write(assigned_device, address, val, len) )
   1.828 -        return;
   1.829 +    /* check write size */
   1.830 +    if ((len != 1) && (len != 2) && (len != 4))
   1.831 +    {
   1.832 +        PT_LOG("Failed to write register with invalid access length. "
   1.833 +            "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
   1.834 +            pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
   1.835 +            address, len);
   1.836 +        goto exit;
   1.837 +    }
   1.838  
   1.839 -    if ( pt_msix_write(assigned_device, address, val, len) )
   1.840 -        return;
   1.841 +    /* check offset alignment */
   1.842 +    if (address & (len-1))
   1.843 +    {
   1.844 +        PT_LOG("Failed to write register with invalid access size alignment. "
   1.845 +            "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
   1.846 +            pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
   1.847 +            address, len);
   1.848 +        goto exit;
   1.849 +    }
   1.850  
   1.851 -    /* PCI config pass-through */
   1.852 -    if (address == 0x4) {
   1.853 -        switch (len){
   1.854 -        case 1:
   1.855 -            pci_write_byte(pci_dev, address, val);
   1.856 -            break;
   1.857 -        case 2:
   1.858 -            pci_write_word(pci_dev, address, val);
   1.859 -            break;
   1.860 -        case 4:
   1.861 -            pci_write_long(pci_dev, address, val);
   1.862 -            break;
   1.863 +    /* check unused BAR register */
   1.864 +    index = pt_bar_offset_to_index(address);
   1.865 +    if ((index >= 0) && (val > 0 && val < PT_BAR_ALLF) &&
   1.866 +        (assigned_device->bases[index].bar_flag == PT_BAR_FLAG_UNUSED))
   1.867 +    {
   1.868 +        PT_LOG("Guest attempt to set address to unused Base Address Register. "
   1.869 +            "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
   1.870 +            pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), 
   1.871 +            (d->devfn & 0x7), address, len);
   1.872 +    }
   1.873 +
   1.874 +    /* find register group entry */
   1.875 +    reg_grp_entry = pt_find_reg_grp(assigned_device, address);
   1.876 +    if (reg_grp_entry)
   1.877 +    {
   1.878 +        reg_grp = reg_grp_entry->reg_grp;
   1.879 +        /* check 0 Hardwired register group */
   1.880 +        if (reg_grp->grp_type == GRP_TYPE_HARDWIRED)
   1.881 +        {
   1.882 +            /* ignore silently */
   1.883 +            PT_LOG("Access to 0 Hardwired register.\n");
   1.884 +            goto exit;
   1.885          }
   1.886      }
   1.887  
   1.888 -    if (address == 0x4) {
   1.889 -        /* Post-write hooking */
   1.890 -        pci_default_write_config(d, address, val, len);
   1.891 +    /* read I/O device register value */
   1.892 +    switch (len) {
   1.893 +    case 1:
   1.894 +        read_val = pci_read_byte(pci_dev, address);
   1.895 +        break;
   1.896 +    case 2:
   1.897 +        read_val = pci_read_word(pci_dev, address);
   1.898 +        break;
   1.899 +    case 4:
   1.900 +        read_val = pci_read_long(pci_dev, address);
   1.901 +        break;
   1.902 +    }
   1.903 +
   1.904 +    /* check libpci error */
   1.905 +    valid_mask = (0xFFFFFFFF >> ((4 - len) << 3));
   1.906 +    if ((read_val & valid_mask) == valid_mask)
   1.907 +    {
   1.908 +        PT_LOG("libpci read error. No emulation. "
   1.909 +            "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
   1.910 +            pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
   1.911 +            address, len);
   1.912 +        goto exit;
   1.913      }
   1.914 +    
   1.915 +    /* pass directly to libpci for passthrough type register group */
   1.916 +    if (reg_grp_entry == NULL)
   1.917 +        goto out;
   1.918 +
   1.919 +    /* adjust the write value to appropriate CFC-CFF window */
   1.920 +    val <<= ((address & 3) << 3);
   1.921 +    emul_len = len;
   1.922 +
   1.923 +    /* loop Guest request size */
   1.924 +    while (0 < emul_len)
   1.925 +    {
   1.926 +        /* find register entry to be emulated */
   1.927 +        reg_entry = pt_find_reg(reg_grp_entry, find_addr);
   1.928 +        if (reg_entry)
   1.929 +        {
   1.930 +            reg = reg_entry->reg;
   1.931 +            real_offset = (reg_grp_entry->base_offset + reg->offset);
   1.932 +            valid_mask = (0xFFFFFFFF >> ((4 - emul_len) << 3));
   1.933 +            valid_mask <<= ((find_addr - real_offset) << 3);
   1.934 +            ptr_val = ((uint8_t *)&val + (real_offset & 3));
   1.935 +
   1.936 +            /* do emulation depend on register size */
   1.937 +            switch (reg->size) {
   1.938 +            case 1:
   1.939 +                /* emulate write to byte register */
   1.940 +                if (reg->u.b.write)
   1.941 +                    ret = reg->u.b.write(assigned_device, reg_entry,
   1.942 +                               (uint8_t *)ptr_val, 
   1.943 +                               (uint8_t)(read_val >> ((real_offset & 3) << 3)),
   1.944 +                               (uint8_t)valid_mask);
   1.945 +                break;
   1.946 +            case 2:
   1.947 +                /* emulate write to word register */
   1.948 +                if (reg->u.w.write)
   1.949 +                    ret = reg->u.w.write(assigned_device, reg_entry,
   1.950 +                               (uint16_t *)ptr_val, 
   1.951 +                               (uint16_t)(read_val >> ((real_offset & 3) << 3)),
   1.952 +                               (uint16_t)valid_mask);
   1.953 +                break;
   1.954 +            case 4:
   1.955 +                /* emulate write to double word register */
   1.956 +                if (reg->u.dw.write)
   1.957 +                    ret = reg->u.dw.write(assigned_device, reg_entry,
   1.958 +                               (uint32_t *)ptr_val, 
   1.959 +                               (uint32_t)(read_val >> ((real_offset & 3) << 3)),
   1.960 +                               (uint32_t)valid_mask);
   1.961 +                break;
   1.962 +            }
   1.963 +
   1.964 +            /* write emulation error */
   1.965 +            if (ret < 0)
   1.966 +            {
   1.967 +                /* exit I/O emulator */
   1.968 +                PT_LOG("I/O emulator exit()\n");
   1.969 +                exit(1);
   1.970 +            }
   1.971 +
   1.972 +            /* calculate next address to find */
   1.973 +            emul_len -= reg->size;
   1.974 +            if (emul_len > 0)
   1.975 +                find_addr = real_offset + reg->size;
   1.976 +        }
   1.977 +        else
   1.978 +        {
   1.979 +            /* nothing to do with passthrough type register, 
   1.980 +             * continue to find next byte 
   1.981 +             */
   1.982 +            emul_len--;
   1.983 +            find_addr++;
   1.984 +        }
   1.985 +    }
   1.986 +    
   1.987 +    /* need to shift back before passing them to libpci */
   1.988 +    val >>= ((address & 3) << 3);
   1.989 +
   1.990 +out:
   1.991 +    switch (len){
   1.992 +    case 1:
   1.993 +        pci_write_byte(pci_dev, address, val);
   1.994 +        break;
   1.995 +    case 2:
   1.996 +        pci_write_word(pci_dev, address, val);
   1.997 +        break;
   1.998 +    case 4:
   1.999 +        pci_write_long(pci_dev, address, val);
  1.1000 +        break;
  1.1001 +    }
  1.1002 +
  1.1003 +exit:
  1.1004 +    return;
  1.1005  }
  1.1006  
  1.1007  static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len)
  1.1008  {
  1.1009      struct pt_dev *assigned_device = (struct pt_dev *)d;
  1.1010      struct pci_dev *pci_dev = assigned_device->pci_dev;
  1.1011 -    uint32_t val = 0xFF;
  1.1012 +    uint32_t val = 0xFFFFFFFF;
  1.1013 +    struct pt_reg_grp_tbl *reg_grp_entry = NULL;
  1.1014 +    struct pt_reg_grp_info_tbl *reg_grp = NULL;
  1.1015 +    struct pt_reg_tbl *reg_entry = NULL;
  1.1016 +    struct pt_reg_info_tbl *reg = NULL;
  1.1017 +    uint32_t find_addr = address;
  1.1018 +    uint32_t real_offset = 0;
  1.1019 +    uint32_t valid_mask = 0xFFFFFFFF;
  1.1020 +    uint8_t *ptr_val = NULL;
  1.1021 +    int emul_len = 0;
  1.1022 +    int ret = 0;
  1.1023  
  1.1024 -    /* Pre-hooking */
  1.1025 -    switch ( address ) {
  1.1026 -    case 0x0C ... 0x3F:
  1.1027 -        val = pci_default_read_config(d, address, len);
  1.1028 +    PT_LOG("read(%x.%x): address=%04x len=%d\n",
  1.1029 +        (d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, len);
  1.1030 +
  1.1031 +    /* check offset range */
  1.1032 +    if (address >= 0xFF)
  1.1033 +    {
  1.1034 +        PT_LOG("Failed to read register with offset exceeding FFh. "
  1.1035 +            "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
  1.1036 +            pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
  1.1037 +            address, len);
  1.1038          goto exit;
  1.1039      }
  1.1040  
  1.1041 -    switch ( len ) {
  1.1042 +    /* check read size */
  1.1043 +    if ((len != 1) && (len != 2) && (len != 4))
  1.1044 +    {
  1.1045 +        PT_LOG("Failed to read register with invalid access length. "
  1.1046 +            "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
  1.1047 +            pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
  1.1048 +            address, len);
  1.1049 +        goto exit;
  1.1050 +    }
  1.1051 +
  1.1052 +    /* check offset alignment */
  1.1053 +    if (address & (len-1))
  1.1054 +    {
  1.1055 +        PT_LOG("Failed to read register with invalid access size alignment. "
  1.1056 +            "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
  1.1057 +            pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
  1.1058 +            address, len);
  1.1059 +        goto exit;
  1.1060 +    }
  1.1061 +
  1.1062 +    /* find register group entry */
  1.1063 +    reg_grp_entry = pt_find_reg_grp(assigned_device, address);
  1.1064 +    if (reg_grp_entry)
  1.1065 +    {
  1.1066 +        reg_grp = reg_grp_entry->reg_grp;
  1.1067 +        /* check 0 Hardwired register group */
  1.1068 +        if (reg_grp->grp_type == GRP_TYPE_HARDWIRED)
  1.1069 +        {
  1.1070 +            /* no need to emulate, just return 0 */
  1.1071 +            val = 0;
  1.1072 +            goto exit;
  1.1073 +        }
  1.1074 +    }
  1.1075 +
  1.1076 +    /* read I/O device register value */
  1.1077 +    switch (len) {
  1.1078      case 1:
  1.1079          val = pci_read_byte(pci_dev, address);
  1.1080          break;
  1.1081 @@ -344,15 +1246,92 @@ static uint32_t pt_pci_read_config(PCIDe
  1.1082          break;
  1.1083      }
  1.1084  
  1.1085 -    pt_msi_read(assigned_device, address, len, &val);
  1.1086 -    pt_msix_read(assigned_device, address, len, &val);
  1.1087 -exit:
  1.1088 +    /* check libpci error */
  1.1089 +    valid_mask = (0xFFFFFFFF >> ((4 - len) << 3));
  1.1090 +    if ((val & valid_mask) == valid_mask)
  1.1091 +    {
  1.1092 +        PT_LOG("libpci read error. No emulation. "
  1.1093 +            "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
  1.1094 +            pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
  1.1095 +            address, len);
  1.1096 +        goto exit;
  1.1097 +    }
  1.1098 +
  1.1099 +    /* just return the I/O device register value for 
  1.1100 +     * passthrough type register group 
  1.1101 +     */
  1.1102 +    if (reg_grp_entry == NULL)
  1.1103 +        goto exit;
  1.1104 +
  1.1105 +    /* adjust the read value to appropriate CFC-CFF window */
  1.1106 +    val <<= ((address & 3) << 3);
  1.1107 +    emul_len = len;
  1.1108 +
  1.1109 +    /* loop Guest request size */
  1.1110 +    while (0 < emul_len)
  1.1111 +    {
  1.1112 +        /* find register entry to be emulated */
  1.1113 +        reg_entry = pt_find_reg(reg_grp_entry, find_addr);
  1.1114 +        if (reg_entry)
  1.1115 +        {
  1.1116 +            reg = reg_entry->reg;
  1.1117 +            real_offset = (reg_grp_entry->base_offset + reg->offset);
  1.1118 +            valid_mask = (0xFFFFFFFF >> ((4 - emul_len) << 3));
  1.1119 +            valid_mask <<= ((find_addr - real_offset) << 3);
  1.1120 +            ptr_val = ((uint8_t *)&val + (real_offset & 3));
  1.1121  
  1.1122 -#ifdef PT_DEBUG_PCI_CONFIG_ACCESS
  1.1123 -    PT_LOG("(%x.%x): address=%04x val=0x%08x len=%d\n",
  1.1124 -       (d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val, len);
  1.1125 -#endif
  1.1126 +            /* do emulation depend on register size */
  1.1127 +            switch (reg->size) {
  1.1128 +            case 1:
  1.1129 +                /* emulate read to byte register */
  1.1130 +                if (reg->u.b.read)
  1.1131 +                    ret = reg->u.b.read(assigned_device, reg_entry,
  1.1132 +                                        (uint8_t *)ptr_val, 
  1.1133 +                                        (uint8_t)valid_mask);
  1.1134 +                break;
  1.1135 +            case 2:
  1.1136 +                /* emulate read to word register */
  1.1137 +                if (reg->u.w.read)
  1.1138 +                    ret = reg->u.w.read(assigned_device, reg_entry,
  1.1139 +                                        (uint16_t *)ptr_val, 
  1.1140 +                                        (uint16_t)valid_mask);
  1.1141 +                break;
  1.1142 +            case 4:
  1.1143 +                /* emulate read to double word register */
  1.1144 +                if (reg->u.dw.read)
  1.1145 +                    ret = reg->u.dw.read(assigned_device, reg_entry,
  1.1146 +                                        (uint32_t *)ptr_val, 
  1.1147 +                                        (uint32_t)valid_mask);
  1.1148 +                break;
  1.1149 +            }
  1.1150  
  1.1151 +            /* read emulation error */
  1.1152 +            if (ret < 0)
  1.1153 +            {
  1.1154 +                /* exit I/O emulator */
  1.1155 +                PT_LOG("I/O emulator exit()\n");
  1.1156 +                exit(1);
  1.1157 +            }
  1.1158 +
  1.1159 +            /* calculate next address to find */
  1.1160 +            emul_len -= reg->size;
  1.1161 +            if (emul_len > 0)
  1.1162 +                find_addr = real_offset + reg->size;
  1.1163 +        }
  1.1164 +        else
  1.1165 +        {
  1.1166 +            /* nothing to do with passthrough type register, 
  1.1167 +             * continue to find next byte 
  1.1168 +             */
  1.1169 +            emul_len--;
  1.1170 +            find_addr++;
  1.1171 +        }
  1.1172 +    }
  1.1173 +    
  1.1174 +    /* need to shift back before returning them to pci bus emulator */
  1.1175 +    val >>= ((address & 3) << 3);
  1.1176 +
  1.1177 +exit:
  1.1178      return val;
  1.1179  }
  1.1180  
  1.1181 @@ -488,11 +1467,1211 @@ uint8_t find_cap_offset(struct pci_dev *
  1.1182      return 0;
  1.1183  }
  1.1184  
  1.1185 +/* parse BAR */
  1.1186 +static int pt_bar_reg_parse(
  1.1187 +        struct pt_dev *ptdev, struct pt_reg_info_tbl *reg)
  1.1188 +{
  1.1189 +    PCIDevice *d = &ptdev->dev;
  1.1190 +    struct pt_region *region = NULL;
  1.1191 +    PCIIORegion *r;
  1.1192 +    uint32_t bar_64 = (reg->offset - 4);
  1.1193 +    int bar_flag = PT_BAR_FLAG_UNUSED;
  1.1194 +    int index = 0;
  1.1195 +    int i;
  1.1196 +
  1.1197 +    /* set again the BAR config because it has been overwritten
  1.1198 +     * by pci_register_io_region()
  1.1199 +     */
  1.1200 +    for (i=reg->offset; i<(reg->offset + 4); i++)
  1.1201 +        d->config[i] = pci_read_byte(ptdev->pci_dev, i);
  1.1202 +
  1.1203 +    /* check 64bit BAR */
  1.1204 +    index = pt_bar_offset_to_index(reg->offset);
  1.1205 +    if ((index > 0) && (index < PCI_ROM_SLOT) &&
  1.1206 +        (d->config[bar_64] & PCI_BASE_ADDRESS_MEM_TYPE_64))
  1.1207 +    {
  1.1208 +        region = &ptdev->bases[index-1];
  1.1209 +        if (region->bar_flag != PT_BAR_FLAG_UPPER)
  1.1210 +        {
  1.1211 +            bar_flag = PT_BAR_FLAG_UPPER;
  1.1212 +            goto out;
  1.1213 +        }
  1.1214 +    }
  1.1215 +
  1.1216 +    /* check unused BAR */
  1.1217 +    r = &d->io_regions[index];
  1.1218 +    if (!r->size)
  1.1219 +        goto out;
  1.1220 +
  1.1221 +    /* check BAR I/O indicator */
  1.1222 +    if (d->config[reg->offset] & PCI_BASE_ADDRESS_SPACE_IO)
  1.1223 +        bar_flag = PT_BAR_FLAG_IO;
  1.1224 +    else
  1.1225 +        bar_flag = PT_BAR_FLAG_MEM;
  1.1226 +
  1.1227 +out:
  1.1228 +    return bar_flag;
  1.1229 +}
  1.1230 +
  1.1231 +/* mapping BAR */
  1.1232 +static void pt_bar_mapping(struct pt_dev *ptdev, int io_enable, int mem_enable)
  1.1233 +{
  1.1234 +    PCIDevice *dev = (PCIDevice *)&ptdev->dev;
  1.1235 +    PCIIORegion *r;
  1.1236 +    struct pt_region *base = NULL;
  1.1237 +    uint32_t r_size = 0;
  1.1238 +    int ret = 0;
  1.1239 +    int i;
  1.1240 +
  1.1241 +    for (i=0; i<PCI_NUM_REGIONS; i++)
  1.1242 +    {
  1.1243 +        r = &dev->io_regions[i];
  1.1244 +
  1.1245 +        /* check valid region */
  1.1246 +        if (!r->size)
  1.1247 +            continue;
  1.1248 +
  1.1249 +        base = &ptdev->bases[i];
  1.1250 +        /* skip unused BAR or upper 64bit BAR */
  1.1251 +        if ((base->bar_flag == PT_BAR_FLAG_UNUSED) || 
  1.1252 +           (base->bar_flag == PT_BAR_FLAG_UPPER))
  1.1253 +               continue;
  1.1254 +
  1.1255 +        /* clear region address in case I/O Space or Memory Space disable */
  1.1256 +        if (((base->bar_flag == PT_BAR_FLAG_IO) && !io_enable ) ||
  1.1257 +            ((base->bar_flag == PT_BAR_FLAG_MEM) && !mem_enable ))
  1.1258 +            r->addr = -1;
  1.1259 +
  1.1260 +        /* prevent guest software mapping memory resource to 00000000h */
  1.1261 +        if ((base->bar_flag == PT_BAR_FLAG_MEM) && (r->addr == 0))
  1.1262 +            r->addr = -1;
  1.1263 +
  1.1264 +        /* align resource size (memory type only) */
  1.1265 +        r_size = r->size;
  1.1266 +        PT_GET_EMUL_SIZE(base->bar_flag, r_size);
  1.1267 +
  1.1268 +        /* check overlapped address */
  1.1269 +        ret = pt_chk_bar_overlap(dev->bus, dev->devfn, r->addr, r_size);
  1.1270 +        if (ret > 0)
  1.1271 +            PT_LOG("Base Address[%d] is overlapped. "
  1.1272 +                "[Address:%08xh][Size:%04xh]\n", i, r->addr, r_size);
  1.1273 +
  1.1274 +        /* check whether we need to update the mapping or not */
  1.1275 +        if (r->addr != ptdev->bases[i].e_physbase)
  1.1276 +        {
  1.1277 +            /* mapping BAR */
  1.1278 +            r->map_func((PCIDevice *)ptdev, i, r->addr, 
  1.1279 +                         r_size, r->type);
  1.1280 +        }
  1.1281 +    }
  1.1282 +
  1.1283 +    return;
  1.1284 +}
  1.1285 +
  1.1286 +/* initialize emulate register */
  1.1287 +static int pt_config_reg_init(struct pt_dev *ptdev,
  1.1288 +        struct pt_reg_grp_tbl *reg_grp,
  1.1289 +        struct pt_reg_info_tbl *reg)
  1.1290 +{
  1.1291 +    struct pt_reg_tbl *reg_entry;
  1.1292 +    uint32_t data = 0;
  1.1293 +    int err = 0;
  1.1294 +
  1.1295 +    /* allocate register entry */
  1.1296 +    reg_entry = qemu_mallocz(sizeof(struct pt_reg_tbl));
  1.1297 +    if (reg_entry == NULL)
  1.1298 +    {
  1.1299 +        PT_LOG("Failed to allocate memory.\n");
  1.1300 +        err = -1;
  1.1301 +        goto out;
  1.1302 +    }
  1.1303 +
  1.1304 +    /* initialize register entry */
  1.1305 +    reg_entry->reg = reg;
  1.1306 +    reg_entry->data = 0;
  1.1307 +
  1.1308 +    if (reg->init)
  1.1309 +    {
  1.1310 +        /* initialize emulate register */
  1.1311 +        data = reg->init(ptdev, reg_entry->reg,
  1.1312 +                        (reg_grp->base_offset + reg->offset));
  1.1313 +        if (data == PT_INVALID_REG)
  1.1314 +        {
  1.1315 +            /* free unused BAR register entry */
  1.1316 +            free(reg_entry);
  1.1317 +            goto out;
  1.1318 +        }
  1.1319 +        /* set register value */
  1.1320 +        reg_entry->data = data;
  1.1321 +    }
  1.1322 +    /* list add register entry */
  1.1323 +    QEMU_LIST_INSERT_HEAD(&reg_grp->reg_tbl_head, reg_entry, entries);
  1.1324 +
  1.1325 +out:
  1.1326 +    return err;
  1.1327 +}
  1.1328 +
  1.1329 +/* initialize emulate register group */
  1.1330 +static int pt_config_init(struct pt_dev *ptdev)
  1.1331 +{
  1.1332 +    struct pt_reg_grp_tbl *reg_grp_entry = NULL;
  1.1333 +    struct pt_reg_info_tbl *reg_tbl = NULL;
  1.1334 +    uint32_t reg_grp_offset = 0;
  1.1335 +    int i, j, err = 0;
  1.1336 +
  1.1337 +    /* initialize register group list */
  1.1338 +    QEMU_LIST_INIT(&ptdev->reg_grp_tbl_head);
  1.1339 +
  1.1340 +    /* initialize register group */
  1.1341 +    for (i=0; pt_emu_reg_grp_tbl[i].grp_size != 0; i++)
  1.1342 +    {
  1.1343 +        if (pt_emu_reg_grp_tbl[i].grp_id != 0xFF)
  1.1344 +        {
  1.1345 +            reg_grp_offset = (uint32_t)find_cap_offset(ptdev->pci_dev, 
  1.1346 +                                 pt_emu_reg_grp_tbl[i].grp_id);
  1.1347 +            if (!reg_grp_offset) 
  1.1348 +                continue;
  1.1349 +        }
  1.1350 +
  1.1351 +        /* allocate register group table */
  1.1352 +        reg_grp_entry = qemu_mallocz(sizeof(struct pt_reg_grp_tbl));
  1.1353 +        if (reg_grp_entry == NULL)
  1.1354 +        {
  1.1355 +            PT_LOG("Failed to allocate memory.\n");
  1.1356 +            err = -1;
  1.1357 +            goto out;
  1.1358 +        }
  1.1359 +
  1.1360 +        /* initialize register group entry */
  1.1361 +        QEMU_LIST_INIT(&reg_grp_entry->reg_tbl_head);
  1.1362 +
  1.1363 +        /* need to declare here, to enable searching Cap Ptr reg 
  1.1364 +         * (which is in the same reg group) when initializing Status reg 
  1.1365 +         */
  1.1366 +        QEMU_LIST_INSERT_HEAD(&ptdev->reg_grp_tbl_head, reg_grp_entry, entries);
  1.1367 +
  1.1368 +        reg_grp_entry->base_offset = reg_grp_offset;
  1.1369 +        reg_grp_entry->reg_grp = 
  1.1370 +                (struct pt_reg_grp_info_tbl*)&pt_emu_reg_grp_tbl[i];
  1.1371 +        if (pt_emu_reg_grp_tbl[i].size_init)
  1.1372 +        {
  1.1373 +            /* get register group size */
  1.1374 +            reg_grp_entry->size = pt_emu_reg_grp_tbl[i].size_init(ptdev,
  1.1375 +                                      reg_grp_entry->reg_grp, 
  1.1376 +                                      reg_grp_offset);
  1.1377 +        }
  1.1378 +
  1.1379 +        if (pt_emu_reg_grp_tbl[i].grp_type == GRP_TYPE_EMU)
  1.1380 +        {
  1.1381 +            if (pt_emu_reg_grp_tbl[i].emu_reg_tbl)
  1.1382 +            {
  1.1383 +                reg_tbl = pt_emu_reg_grp_tbl[i].emu_reg_tbl;
  1.1384 +                /* initialize capability register */
  1.1385 +                for (j=0; reg_tbl->size != 0; j++, reg_tbl++)
  1.1386 +                {
  1.1387 +                    /* initialize capability register */
  1.1388 +                    err = pt_config_reg_init(ptdev, reg_grp_entry, reg_tbl);
  1.1389 +                    if (err < 0)
  1.1390 +                        goto out;
  1.1391 +                }
  1.1392 +            }
  1.1393 +        }
  1.1394 +        reg_grp_offset = 0;
  1.1395 +    }
  1.1396 +
  1.1397 +out:
  1.1398 +    return err;
  1.1399 +}
  1.1400 +
  1.1401 +/* initialize common register value */
  1.1402 +static uint32_t pt_common_reg_init(struct pt_dev *ptdev,
  1.1403 +        struct pt_reg_info_tbl *reg, uint32_t real_offset)
  1.1404 +{
  1.1405 +    return reg->init_val;
  1.1406 +}
  1.1407 +
  1.1408 +/* initialize Capabilities Pointer or Next Pointer register */
  1.1409 +static uint32_t pt_ptr_reg_init(struct pt_dev *ptdev,
  1.1410 +        struct pt_reg_info_tbl *reg, uint32_t real_offset)
  1.1411 +{
  1.1412 +    uint32_t reg_field = (uint32_t)ptdev->dev.config[real_offset];
  1.1413 +    int i;
  1.1414 +
  1.1415 +    /* find capability offset */
  1.1416 +    while (reg_field)
  1.1417 +    {
  1.1418 +        for (i=0; pt_emu_reg_grp_tbl[i].grp_size != 0; i++)
  1.1419 +        {
  1.1420 +            /* check whether the next capability 
  1.1421 +             * should be exported to guest or not 
  1.1422 +             */
  1.1423 +            if (pt_emu_reg_grp_tbl[i].grp_id == ptdev->dev.config[reg_field])
  1.1424 +            {
  1.1425 +                if (pt_emu_reg_grp_tbl[i].grp_type == GRP_TYPE_EMU)
  1.1426 +                    goto out;
  1.1427 +                /* ignore the 0 hardwired capability, find next one */
  1.1428 +                break;
  1.1429 +            }
  1.1430 +        }
  1.1431 +        /* next capability */
  1.1432 +        reg_field = (uint32_t)ptdev->dev.config[reg_field + 1];
  1.1433 +    }
  1.1434 +
  1.1435 +out:
  1.1436 +    return reg_field;
  1.1437 +}
  1.1438 +
  1.1439 +/* initialize Status register */
  1.1440 +static uint32_t pt_status_reg_init(struct pt_dev *ptdev,
  1.1441 +        struct pt_reg_info_tbl *reg, uint32_t real_offset)
  1.1442 +{
  1.1443 +    struct pt_reg_grp_tbl *reg_grp_entry = NULL;
  1.1444 +    struct pt_reg_tbl *reg_entry = NULL;
  1.1445 +    int reg_field = 0;
  1.1446 +
  1.1447 +    /* find Header register group */
  1.1448 +    reg_grp_entry = pt_find_reg_grp(ptdev, PCI_CAPABILITY_LIST);
  1.1449 +    if (reg_grp_entry)
  1.1450 +    {
  1.1451 +        /* find Capabilities Pointer register */
  1.1452 +        reg_entry = pt_find_reg(reg_grp_entry, PCI_CAPABILITY_LIST);
  1.1453 +        if (reg_entry)
  1.1454 +        {
  1.1455 +            /* check Capabilities Pointer register */
  1.1456 +            if (reg_entry->data)
  1.1457 +                reg_field |= PCI_STATUS_CAP_LIST;
  1.1458 +            else
  1.1459 +                reg_field &= ~PCI_STATUS_CAP_LIST;
  1.1460 +        }
  1.1461 +        else
  1.1462 +        {
  1.1463 +            /* exit I/O emulator */
  1.1464 +            PT_LOG("I/O emulator exit()\n");
  1.1465 +            exit(1);
  1.1466 +        }
  1.1467 +    }
  1.1468 +    else
  1.1469 +    {
  1.1470 +        /* exit I/O emulator */
  1.1471 +        PT_LOG("I/O emulator exit()\n");
  1.1472 +        exit(1);
  1.1473 +    }
  1.1474 +
  1.1475 +    return reg_field;
  1.1476 +}
  1.1477 +
  1.1478 +/* initialize Interrupt Pin register */
  1.1479 +static uint32_t pt_irqpin_reg_init(struct pt_dev *ptdev,
  1.1480 +        struct pt_reg_info_tbl *reg, uint32_t real_offset)
  1.1481 +{
  1.1482 +    int reg_field = 0;
  1.1483 +
  1.1484 +    /* set Interrupt Pin register to use INTA# if it has */
  1.1485 +    if (ptdev->dev.config[real_offset])
  1.1486 +        reg_field = 0x01;
  1.1487 +
  1.1488 +    return reg_field;
  1.1489 +}
  1.1490 +
  1.1491 +/* initialize BAR */
  1.1492 +static uint32_t pt_bar_reg_init(struct pt_dev *ptdev,
  1.1493 +        struct pt_reg_info_tbl *reg, uint32_t real_offset)
  1.1494 +{
  1.1495 +    int reg_field = 0;
  1.1496 +    int index;
  1.1497 +
  1.1498 +    /* get BAR index */
  1.1499 +    index = pt_bar_offset_to_index(reg->offset);
  1.1500 +    if (index < 0)
  1.1501 +    {
  1.1502 +        /* exit I/O emulator */
  1.1503 +        PT_LOG("I/O emulator exit()\n");
  1.1504 +        exit(1);
  1.1505 +    }
  1.1506 +
  1.1507 +    /* set initial guest physical base address to -1 */
  1.1508 +    ptdev->bases[index].e_physbase = -1;
  1.1509 +
  1.1510 +    /* set BAR flag */
  1.1511 +    ptdev->bases[index].bar_flag = pt_bar_reg_parse(ptdev, reg);
  1.1512 +    if (ptdev->bases[index].bar_flag == PT_BAR_FLAG_UNUSED)
  1.1513 +        reg_field = PT_INVALID_REG;
  1.1514 +
  1.1515 +    return reg_field;
  1.1516 +}
  1.1517 +
  1.1518 +/* initialize Link Control 2 register */
  1.1519 +static uint32_t pt_linkctrl2_reg_init(struct pt_dev *ptdev,
  1.1520 +        struct pt_reg_info_tbl *reg, uint32_t real_offset)
  1.1521 +{
  1.1522 +    int reg_field = 0;
  1.1523 +
  1.1524 +    /* set Supported Link Speed */
  1.1525 +    reg_field |= 
  1.1526 +        (0x0F & 
  1.1527 +         ptdev->dev.config[(real_offset - reg->offset) + PCI_EXP_LNKCAP]);
  1.1528 +
  1.1529 +    return reg_field;
  1.1530 +}
  1.1531 +
  1.1532 +/* initialize Message Control register */
  1.1533 +static uint32_t pt_msgctrl_reg_init(struct pt_dev *ptdev,
  1.1534 +        struct pt_reg_info_tbl *reg, uint32_t real_offset)
  1.1535 +{
  1.1536 +    PCIDevice *d = (struct PCIDevice *)ptdev;
  1.1537 +    struct pci_dev *pdev = ptdev->pci_dev;
  1.1538 +    uint32_t reg_field = 0;
  1.1539 +    
  1.1540 +    /* use I/O device register's value as initial value */
  1.1541 +    reg_field |= *((uint16_t*)(d->config + real_offset));
  1.1542 +    
  1.1543 +    if (reg_field & PCI_MSI_FLAGS_ENABLE)
  1.1544 +    {
  1.1545 +        PT_LOG("MSI enabled already, disable first\n");
  1.1546 +        pci_write_word(pdev, real_offset, reg_field & ~PCI_MSI_FLAGS_ENABLE);
  1.1547 +    }
  1.1548 +    ptdev->msi->flags |= (reg_field | MSI_FLAG_UNINIT);
  1.1549 +    
  1.1550 +    /* All register is 0 after reset, except first 4 byte */
  1.1551 +    reg_field &= reg->ro_mask;
  1.1552 +    
  1.1553 +    return reg_field;
  1.1554 +}
  1.1555 +
  1.1556 +/* initialize Message Address register */
  1.1557 +static uint32_t pt_msgaddr32_reg_init(struct pt_dev *ptdev,
  1.1558 +        struct pt_reg_info_tbl *reg, uint32_t real_offset)
  1.1559 +{
  1.1560 +    PCIDevice *d = (struct PCIDevice *)ptdev;
  1.1561 +    uint32_t reg_field = 0;
  1.1562 +    
  1.1563 +    /* use I/O device register's value as initial value */
  1.1564 +    reg_field |= *((uint32_t*)(d->config + real_offset));
  1.1565 +    
  1.1566 +    return reg_field;
  1.1567 +}
  1.1568 +
  1.1569 +/* initialize Message Upper Address register */
  1.1570 +static uint32_t pt_msgaddr64_reg_init(struct pt_dev *ptdev,
  1.1571 +        struct pt_reg_info_tbl *reg, uint32_t real_offset)
  1.1572 +{
  1.1573 +    PCIDevice *d = (struct PCIDevice *)ptdev;
  1.1574 +    uint32_t reg_field = 0;
  1.1575 +    
  1.1576 +    /* no need to initialize in case of 32 bit type */
  1.1577 +    if (!(ptdev->msi->flags & PCI_MSI_FLAGS_64BIT))
  1.1578 +        return PT_INVALID_REG;
  1.1579 +    
  1.1580 +    /* use I/O device register's value as initial value */
  1.1581 +    reg_field |= *((uint32_t*)(d->config + real_offset));
  1.1582 +    
  1.1583 +    return reg_field;
  1.1584 +}
  1.1585 +
  1.1586 +/* this function will be called twice (for 32 bit and 64 bit type) */
  1.1587 +/* initialize Message Data register */
  1.1588 +static uint32_t pt_msgdata_reg_init(struct pt_dev *ptdev,
  1.1589 +        struct pt_reg_info_tbl *reg, uint32_t real_offset)
  1.1590 +{
  1.1591 +    PCIDevice *d = (struct PCIDevice *)ptdev;
  1.1592 +    uint32_t flags = ptdev->msi->flags;
  1.1593 +    uint32_t offset = reg->offset;
  1.1594 +    
  1.1595 +    /* check the offset whether matches the type or not */
  1.1596 +    if (((offset == PCI_MSI_DATA_64) &&  (flags & PCI_MSI_FLAGS_64BIT)) ||
  1.1597 +        ((offset == PCI_MSI_DATA_32) && !(flags & PCI_MSI_FLAGS_64BIT)))
  1.1598 +        return *((uint16_t*)(d->config + real_offset));
  1.1599 +    else
  1.1600 +        return PT_INVALID_REG;
  1.1601 +}
  1.1602 +
  1.1603 +/* initialize Message Control register for MSI-X */
  1.1604 +static uint32_t pt_msixctrl_reg_init(struct pt_dev *ptdev,
  1.1605 +        struct pt_reg_info_tbl *reg, uint32_t real_offset)
  1.1606 +{
  1.1607 +    PCIDevice *d = (struct PCIDevice *)ptdev;
  1.1608 +    struct pci_dev *pdev = ptdev->pci_dev;
  1.1609 +    uint16_t reg_field = 0;
  1.1610 +    
  1.1611 +    /* use I/O device register's value as initial value */
  1.1612 +    reg_field |= *((uint16_t*)(d->config + real_offset));
  1.1613 +    
  1.1614 +    if (reg_field & PCI_MSIX_ENABLE)
  1.1615 +    {
  1.1616 +        PT_LOG("MSIX enabled already, disable first\n");
  1.1617 +        pci_write_word(pdev, real_offset, reg_field & ~PCI_MSIX_ENABLE);
  1.1618 +        reg_field &= ~(PCI_MSIX_ENABLE | PCI_MSIX_MASK);
  1.1619 +    }
  1.1620 +    
  1.1621 +    return reg_field;
  1.1622 +}
  1.1623 +
  1.1624 +/* get register group size */
  1.1625 +static uint8_t pt_reg_grp_size_init(struct pt_dev *ptdev,
  1.1626 +        struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
  1.1627 +{
  1.1628 +    return grp_reg->grp_size;
  1.1629 +}
  1.1630 +
  1.1631 +/* get MSI Capability Structure register group size */
  1.1632 +static uint8_t pt_msi_size_init(struct pt_dev *ptdev,
  1.1633 +        struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
  1.1634 +{
  1.1635 +    PCIDevice *d = &ptdev->dev;
  1.1636 +    uint16_t msg_ctrl = 0;
  1.1637 +    uint8_t msi_size = 0xa;
  1.1638 +
  1.1639 +    msg_ctrl = *((uint16_t*)(d->config + (base_offset + PCI_MSI_FLAGS)));
  1.1640 +
  1.1641 +    /* check 64 bit address capable & Per-vector masking capable */
  1.1642 +    if (msg_ctrl & PCI_MSI_FLAGS_64BIT)
  1.1643 +        msi_size += 4;
  1.1644 +    if (msg_ctrl & PCI_MSI_FLAGS_MASK_BIT)
  1.1645 +        msi_size += 10;
  1.1646 +
  1.1647 +    ptdev->msi = malloc(sizeof(struct pt_msi_info));
  1.1648 +    if ( !ptdev->msi )
  1.1649 +    {
  1.1650 +        PT_LOG("error allocation pt_msi_info\n");
  1.1651 +        /* exit I/O emulator */
  1.1652 +        PT_LOG("I/O emulator exit()\n");
  1.1653 +        exit(1);
  1.1654 +    }
  1.1655 +    memset(ptdev->msi, 0, sizeof(struct pt_msi_info));
  1.1656 +    
  1.1657 +    return msi_size;
  1.1658 +}
  1.1659 +
  1.1660 +/* get MSI-X Capability Structure register group size */
  1.1661 +static uint8_t pt_msix_size_init(struct pt_dev *ptdev,
  1.1662 +        struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
  1.1663 +{
  1.1664 +    int ret = 0;
  1.1665 +
  1.1666 +    ret = pt_msix_init(ptdev, base_offset);
  1.1667 +
  1.1668 +    if (ret == -1)
  1.1669 +    {
  1.1670 +        /* exit I/O emulator */
  1.1671 +        PT_LOG("I/O emulator exit()\n");
  1.1672 +        exit(1);
  1.1673 +    }
  1.1674 +
  1.1675 +    return grp_reg->grp_size;
  1.1676 +}
  1.1677 +
  1.1678 +/* get Vendor Specific Capability Structure register group size */
  1.1679 +static uint8_t pt_vendor_size_init(struct pt_dev *ptdev,
  1.1680 +        struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
  1.1681 +{
  1.1682 +    return ptdev->dev.config[base_offset + 0x02];
  1.1683 +}
  1.1684 +
  1.1685 +/* read byte size emulate register */
  1.1686 +static int pt_byte_reg_read(struct pt_dev *ptdev,
  1.1687 +        struct pt_reg_tbl *cfg_entry,
  1.1688 +        uint8_t *value, uint8_t valid_mask)
  1.1689 +{
  1.1690 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.1691 +    uint8_t valid_emu_mask = 0;
  1.1692 +
  1.1693 +    /* emulate byte register */
  1.1694 +    valid_emu_mask = reg->emu_mask & valid_mask;
  1.1695 +    *value = ((*value & ~valid_emu_mask) | 
  1.1696 +              (cfg_entry->data & valid_emu_mask));
  1.1697 +
  1.1698 +    return 0;
  1.1699 +}
  1.1700 +
  1.1701 +/* read word size emulate register */
  1.1702 +static int pt_word_reg_read(struct pt_dev *ptdev,
  1.1703 +        struct pt_reg_tbl *cfg_entry,
  1.1704 +        uint16_t *value, uint16_t valid_mask)
  1.1705 +{
  1.1706 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.1707 +    uint16_t valid_emu_mask = 0;
  1.1708 +
  1.1709 +    /* emulate word register */
  1.1710 +    valid_emu_mask = reg->emu_mask & valid_mask;
  1.1711 +    *value = ((*value & ~valid_emu_mask) | 
  1.1712 +              (cfg_entry->data & valid_emu_mask));
  1.1713 +
  1.1714 +    return 0;
  1.1715 +}
  1.1716 +
  1.1717 +/* read long size emulate register */
  1.1718 +static int pt_long_reg_read(struct pt_dev *ptdev,
  1.1719 +        struct pt_reg_tbl *cfg_entry,
  1.1720 +        uint32_t *value, uint32_t valid_mask)
  1.1721 +{
  1.1722 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.1723 +    uint32_t valid_emu_mask = 0;
  1.1724 +
  1.1725 +    /* emulate long register */
  1.1726 +    valid_emu_mask = reg->emu_mask & valid_mask;
  1.1727 +    *value = ((*value & ~valid_emu_mask) | 
  1.1728 +              (cfg_entry->data & valid_emu_mask));
  1.1729 +
  1.1730 +   return 0;
  1.1731 +}
  1.1732 +
  1.1733 +/* read BAR */
  1.1734 +static int pt_bar_reg_read(struct pt_dev *ptdev,
  1.1735 +        struct pt_reg_tbl *cfg_entry,
  1.1736 +        uint32_t *value, uint32_t valid_mask)
  1.1737 +{
  1.1738 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.1739 +    uint32_t valid_emu_mask = 0;
  1.1740 +    uint32_t bar_emu_mask = 0;
  1.1741 +    int index;
  1.1742 +
  1.1743 +    /* get BAR index */
  1.1744 +    index = pt_bar_offset_to_index(reg->offset);
  1.1745 +    if (index < 0)
  1.1746 +    {
  1.1747 +        /* exit I/O emulator */
  1.1748 +        PT_LOG("I/O emulator exit()\n");
  1.1749 +        exit(1);
  1.1750 +    }
  1.1751 +
  1.1752 +    /* set emulate mask depend on BAR flag */
  1.1753 +    switch (ptdev->bases[index].bar_flag)
  1.1754 +    {
  1.1755 +    case PT_BAR_FLAG_MEM:
  1.1756 +        bar_emu_mask = PT_BAR_MEM_EMU_MASK;
  1.1757 +        break;
  1.1758 +    case PT_BAR_FLAG_IO:
  1.1759 +        bar_emu_mask = PT_BAR_IO_EMU_MASK;
  1.1760 +        break;
  1.1761 +    case PT_BAR_FLAG_UPPER:
  1.1762 +        *value = 0;
  1.1763 +        goto out;
  1.1764 +    default:
  1.1765 +        break;
  1.1766 +    }
  1.1767 +
  1.1768 +    /* emulate BAR */
  1.1769 +    valid_emu_mask = bar_emu_mask & valid_mask;
  1.1770 +    *value = ((*value & ~valid_emu_mask) | 
  1.1771 +              (cfg_entry->data & valid_emu_mask));
  1.1772 +
  1.1773 +out:
  1.1774 +   return 0;
  1.1775 +}
  1.1776 +
  1.1777 +/* write byte size emulate register */
  1.1778 +static int pt_byte_reg_write(struct pt_dev *ptdev, 
  1.1779 +        struct pt_reg_tbl *cfg_entry, 
  1.1780 +        uint8_t *value, uint8_t dev_value, uint8_t valid_mask)
  1.1781 +{
  1.1782 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.1783 +    uint8_t writable_mask = 0;
  1.1784 +    uint8_t throughable_mask = 0;
  1.1785 +
  1.1786 +    /* modify emulate register */
  1.1787 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
  1.1788 +    cfg_entry->data = ((*value & writable_mask) |
  1.1789 +                       (cfg_entry->data & ~writable_mask));
  1.1790 +
  1.1791 +    /* create value for writing to I/O device register */
  1.1792 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.1793 +    *value = ((*value & throughable_mask) |
  1.1794 +              (dev_value & ~throughable_mask));
  1.1795 +
  1.1796 +    return 0;
  1.1797 +}
  1.1798 +
  1.1799 +/* write word size emulate register */
  1.1800 +static int pt_word_reg_write(struct pt_dev *ptdev, 
  1.1801 +        struct pt_reg_tbl *cfg_entry, 
  1.1802 +        uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
  1.1803 +{
  1.1804 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.1805 +    uint16_t writable_mask = 0;
  1.1806 +    uint16_t throughable_mask = 0;
  1.1807 +
  1.1808 +    /* modify emulate register */
  1.1809 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
  1.1810 +    cfg_entry->data = ((*value & writable_mask) |
  1.1811 +                       (cfg_entry->data & ~writable_mask));
  1.1812 +
  1.1813 +    /* create value for writing to I/O device register */
  1.1814 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.1815 +    *value = ((*value & throughable_mask) |
  1.1816 +              (dev_value & ~throughable_mask));
  1.1817 +
  1.1818 +    return 0;
  1.1819 +}
  1.1820 +
  1.1821 +/* write long size emulate register */
  1.1822 +static int pt_long_reg_write(struct pt_dev *ptdev, 
  1.1823 +        struct pt_reg_tbl *cfg_entry, 
  1.1824 +        uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
  1.1825 +{
  1.1826 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.1827 +    uint32_t writable_mask = 0;
  1.1828 +    uint32_t throughable_mask = 0;
  1.1829 +
  1.1830 +    /* modify emulate register */
  1.1831 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
  1.1832 +    cfg_entry->data = ((*value & writable_mask) |
  1.1833 +                       (cfg_entry->data & ~writable_mask));
  1.1834 +
  1.1835 +    /* create value for writing to I/O device register */
  1.1836 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.1837 +    *value = ((*value & throughable_mask) |
  1.1838 +              (dev_value & ~throughable_mask));
  1.1839 +
  1.1840 +    return 0;
  1.1841 +}
  1.1842 +
  1.1843 +/* write Command register */
  1.1844 +static int pt_cmd_reg_write(struct pt_dev *ptdev, 
  1.1845 +        struct pt_reg_tbl *cfg_entry, 
  1.1846 +        uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
  1.1847 +{
  1.1848 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.1849 +    uint16_t writable_mask = 0;
  1.1850 +    uint16_t throughable_mask = 0;
  1.1851 +    uint16_t wr_value = *value;
  1.1852 +
  1.1853 +    /* modify emulate register */
  1.1854 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
  1.1855 +    cfg_entry->data = ((*value & writable_mask) |
  1.1856 +                       (cfg_entry->data & ~writable_mask));
  1.1857 +
  1.1858 +    /* create value for writing to I/O device register */
  1.1859 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.1860 +    *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
  1.1861 +
  1.1862 +    /* mapping BAR */
  1.1863 +    pt_bar_mapping(ptdev, wr_value & PCI_COMMAND_IO, 
  1.1864 +                          wr_value & PCI_COMMAND_MEMORY);
  1.1865 +
  1.1866 +    return 0;
  1.1867 +}
  1.1868 +
  1.1869 +/* write BAR */
  1.1870 +static int pt_bar_reg_write(struct pt_dev *ptdev, 
  1.1871 +        struct pt_reg_tbl *cfg_entry, 
  1.1872 +        uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
  1.1873 +{
  1.1874 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.1875 +    struct pt_reg_grp_tbl *reg_grp_entry = NULL;
  1.1876 +    struct pt_reg_tbl *reg_entry = NULL;
  1.1877 +    struct pt_region *base = NULL;
  1.1878 +    PCIDevice *d = (PCIDevice *)&ptdev->dev;
  1.1879 +    PCIIORegion *r;
  1.1880 +    uint32_t writable_mask = 0;
  1.1881 +    uint32_t throughable_mask = 0;
  1.1882 +    uint32_t bar_emu_mask = 0;
  1.1883 +    uint32_t bar_ro_mask = 0;
  1.1884 +    uint32_t new_addr, last_addr;
  1.1885 +    uint32_t prev_offset;
  1.1886 +    uint32_t r_size = 0;
  1.1887 +    int index = 0;
  1.1888 +
  1.1889 +   /* get BAR index */
  1.1890 +    index = pt_bar_offset_to_index(reg->offset);
  1.1891 +    if (index < 0)
  1.1892 +    {
  1.1893 +        /* exit I/O emulator */
  1.1894 +        PT_LOG("I/O emulator exit()\n");
  1.1895 +        exit(1);
  1.1896 +    }
  1.1897 +
  1.1898 +    r = &d->io_regions[index];
  1.1899 +    r_size = r->size;
  1.1900 +    base = &ptdev->bases[index];
  1.1901 +    /* align resource size (memory type only) */
  1.1902 +    PT_GET_EMUL_SIZE(base->bar_flag, r_size);
  1.1903 +
  1.1904 +    /* check guest write value */
  1.1905 +    if (*value == PT_BAR_ALLF)
  1.1906 +    {
  1.1907 +        /* set register with resource size alligned to page size */
  1.1908 +        cfg_entry->data = ~(r_size - 1);
  1.1909 +        /* avoid writing ALL F to I/O device register */
  1.1910 +        *value = dev_value;
  1.1911 +    }
  1.1912 +    else
  1.1913 +    {
  1.1914 +        /* set emulate mask and read-only mask depend on BAR flag */
  1.1915 +        switch (ptdev->bases[index].bar_flag)
  1.1916 +        {
  1.1917 +        case PT_BAR_FLAG_MEM:
  1.1918 +            bar_emu_mask = PT_BAR_MEM_EMU_MASK;
  1.1919 +            bar_ro_mask = PT_BAR_MEM_RO_MASK;
  1.1920 +            break;
  1.1921 +        case PT_BAR_FLAG_IO:
  1.1922 +            new_addr = *value;
  1.1923 +            last_addr = new_addr + r_size - 1;
  1.1924 +            /* check 64K range */
  1.1925 +            if (last_addr <= new_addr || !new_addr || last_addr >= 0x10000)
  1.1926 +            {
  1.1927 +                PT_LOG("Guest attempt to set Base Address over the 64KB. "
  1.1928 +                    "[%02x:%02x.%x][Offset:%02xh][Range:%08xh-%08xh]\n",
  1.1929 +                    pci_bus_num(d->bus), 
  1.1930 +                    ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
  1.1931 +                    reg->offset, new_addr, last_addr);
  1.1932 +                /* just remove mapping */
  1.1933 +                r->addr = -1;
  1.1934 +                goto exit;
  1.1935 +            }
  1.1936 +            bar_emu_mask = PT_BAR_IO_EMU_MASK;
  1.1937 +            bar_ro_mask = PT_BAR_IO_RO_MASK;
  1.1938 +            break;
  1.1939 +        case PT_BAR_FLAG_UPPER:
  1.1940 +            if (*value)
  1.1941 +            {
  1.1942 +                PT_LOG("Guest attempt to set high MMIO Base Address. "
  1.1943 +                   "Ignore mapping. "
  1.1944 +                   "[%02x:%02x.%x][Offset:%02xh][High Address:%08xh]\n",
  1.1945 +                    pci_bus_num(d->bus), 
  1.1946 +                    ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
  1.1947 +                    reg->offset, *value);
  1.1948 +                /* clear lower address */
  1.1949 +                d->io_regions[index-1].addr = -1;
  1.1950 +            }
  1.1951 +            else
  1.1952 +            {
  1.1953 +                /* find lower 32bit BAR */
  1.1954 +                prev_offset = (reg->offset - 4);
  1.1955 +                reg_grp_entry = pt_find_reg_grp(ptdev, prev_offset);
  1.1956 +                if (reg_grp_entry)
  1.1957 +                {
  1.1958 +                    reg_entry = pt_find_reg(reg_grp_entry, prev_offset);
  1.1959 +                    if (reg_entry)
  1.1960 +                        /* restore lower address */
  1.1961 +                        d->io_regions[index-1].addr = reg_entry->data;
  1.1962 +                    else
  1.1963 +                        return -1;
  1.1964 +                }
  1.1965 +                else
  1.1966 +                    return -1;
  1.1967 +            }
  1.1968 +            cfg_entry->data = 0;
  1.1969 +            r->addr = -1;
  1.1970 +            goto exit;
  1.1971 +        }
  1.1972 +
  1.1973 +        /* modify emulate register */
  1.1974 +        writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
  1.1975 +        cfg_entry->data = ((*value & writable_mask) |
  1.1976 +                           (cfg_entry->data & ~writable_mask));
  1.1977 +        /* update the corresponding virtual region address */
  1.1978 +        r->addr = cfg_entry->data;
  1.1979 +
  1.1980 +        /* create value for writing to I/O device register */
  1.1981 +        throughable_mask = ~bar_emu_mask & valid_mask;
  1.1982 +        *value = ((*value & throughable_mask) |
  1.1983 +                  (dev_value & ~throughable_mask));
  1.1984 +    }
  1.1985 +
  1.1986 +exit:
  1.1987 +    return 0;
  1.1988 +}
  1.1989 +
  1.1990 +/* write Exp ROM BAR */
  1.1991 +static int pt_exp_rom_bar_reg_write(struct pt_dev *ptdev, 
  1.1992 +        struct pt_reg_tbl *cfg_entry, 
  1.1993 +        uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
  1.1994 +{
  1.1995 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.1996 +    struct pt_region *base = NULL;
  1.1997 +    PCIDevice *d = (PCIDevice *)&ptdev->dev;
  1.1998 +    PCIIORegion *r;
  1.1999 +    uint32_t writable_mask = 0;
  1.2000 +    uint32_t throughable_mask = 0;
  1.2001 +    uint32_t r_size = 0;
  1.2002 +
  1.2003 +    r = &d->io_regions[PCI_ROM_SLOT];
  1.2004 +    r_size = r->size;
  1.2005 +    base = &ptdev->bases[PCI_ROM_SLOT];
  1.2006 +    /* align memory type resource size */
  1.2007 +    PT_GET_EMUL_SIZE(base->bar_flag, r_size);
  1.2008 +
  1.2009 +    /* check guest write value */
  1.2010 +    if (*value == PT_BAR_ALLF)
  1.2011 +    {
  1.2012 +        /* set register with resource size alligned to page size */
  1.2013 +        cfg_entry->data = ~(r_size - 1);
  1.2014 +        /* avoid writing ALL F to I/O device register */
  1.2015 +        *value = dev_value;
  1.2016 +    }
  1.2017 +    else
  1.2018 +    {
  1.2019 +        /* modify emulate register */
  1.2020 +        writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
  1.2021 +        cfg_entry->data = ((*value & writable_mask) |
  1.2022 +                           (cfg_entry->data & ~writable_mask));
  1.2023 +        /* update the corresponding virtual region address */
  1.2024 +        r->addr = cfg_entry->data;
  1.2025 +
  1.2026 +        /* create value for writing to I/O device register */
  1.2027 +        throughable_mask = ~reg->emu_mask & valid_mask;
  1.2028 +        *value = ((*value & throughable_mask) |
  1.2029 +                  (dev_value & ~throughable_mask));
  1.2030 +    }
  1.2031 +
  1.2032 +    return 0;
  1.2033 +}
  1.2034 +
  1.2035 +/* write Power Management Control/Status register */
  1.2036 +static int pt_pmcsr_reg_write(struct pt_dev *ptdev, 
  1.2037 +        struct pt_reg_tbl *cfg_entry, 
  1.2038 +        uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
  1.2039 +{
  1.2040 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.2041 +    uint16_t writable_mask = 0;
  1.2042 +    uint16_t throughable_mask = 0;
  1.2043 +    uint16_t pmcsr_mask = (PCI_PM_CTRL_PME_ENABLE | 
  1.2044 +                           PCI_PM_CTRL_DATA_SEL_MASK |
  1.2045 +                           PCI_PM_CTRL_PME_STATUS);
  1.2046 +
  1.2047 +    /* modify emulate register */
  1.2048 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~pmcsr_mask;
  1.2049 +    /* ignore it when the requested state neither D3 nor D0 */
  1.2050 +    if (((*value & PCI_PM_CTRL_STATE_MASK) != PCI_PM_CTRL_STATE_MASK) &&
  1.2051 +        ((*value & PCI_PM_CTRL_STATE_MASK) != 0))
  1.2052 +        writable_mask &= ~PCI_PM_CTRL_STATE_MASK;
  1.2053 +
  1.2054 +    cfg_entry->data = ((*value & writable_mask) |
  1.2055 +                       (cfg_entry->data & ~writable_mask));
  1.2056 +
  1.2057 +    /* create value for writing to I/O device register */
  1.2058 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.2059 +    *value = ((*value & throughable_mask) |
  1.2060 +              (dev_value & ~throughable_mask));
  1.2061 +
  1.2062 +    return 0;
  1.2063 +}
  1.2064 +
  1.2065 +/* write Device Control register */
  1.2066 +static int pt_devctrl_reg_write(struct pt_dev *ptdev, 
  1.2067 +        struct pt_reg_tbl *cfg_entry, 
  1.2068 +        uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
  1.2069 +{
  1.2070 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.2071 +    uint16_t writable_mask = 0;
  1.2072 +    uint16_t throughable_mask = 0;
  1.2073 +    uint16_t devctrl_mask = (PCI_EXP_DEVCTL_AUX_PME | 0x8000);
  1.2074 +
  1.2075 +    /* modify emulate register */
  1.2076 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~devctrl_mask;
  1.2077 +    cfg_entry->data = ((*value & writable_mask) |
  1.2078 +                       (cfg_entry->data & ~writable_mask));
  1.2079 +
  1.2080 +    /* create value for writing to I/O device register */
  1.2081 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.2082 +    *value = ((*value & throughable_mask) |
  1.2083 +              (dev_value & ~throughable_mask));
  1.2084 +
  1.2085 +    return 0;
  1.2086 +}
  1.2087 +
  1.2088 +/* write Link Control register */
  1.2089 +static int pt_linkctrl_reg_write(struct pt_dev *ptdev, 
  1.2090 +        struct pt_reg_tbl *cfg_entry, 
  1.2091 +        uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
  1.2092 +{
  1.2093 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.2094 +    uint16_t writable_mask = 0;
  1.2095 +    uint16_t throughable_mask = 0;
  1.2096 +    uint16_t linkctrl_mask = (PCI_EXP_LNKCTL_ASPM | 0x04 |
  1.2097 +                              PCI_EXP_LNKCTL_DISABLE |
  1.2098 +                              PCI_EXP_LNKCTL_RETRAIN | 
  1.2099 +                              0x0400 | 0x0800 | 0xF000);
  1.2100 +
  1.2101 +    /* modify emulate register */
  1.2102 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~linkctrl_mask;
  1.2103 +    cfg_entry->data = ((*value & writable_mask) |
  1.2104 +                       (cfg_entry->data & ~writable_mask));
  1.2105 +
  1.2106 +    /* create value for writing to I/O device register */
  1.2107 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.2108 +    *value = ((*value & throughable_mask) |
  1.2109 +              (dev_value & ~throughable_mask));
  1.2110 +
  1.2111 +    return 0;
  1.2112 +}
  1.2113 +
  1.2114 +/* write Device Control2 register */
  1.2115 +static int pt_devctrl2_reg_write(struct pt_dev *ptdev, 
  1.2116 +        struct pt_reg_tbl *cfg_entry, 
  1.2117 +        uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
  1.2118 +{
  1.2119 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.2120 +    uint16_t writable_mask = 0;
  1.2121 +    uint16_t throughable_mask = 0;
  1.2122 +    uint16_t devctrl2_mask = 0xFFE0;
  1.2123 +
  1.2124 +    /* modify emulate register */
  1.2125 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~devctrl2_mask;
  1.2126 +    cfg_entry->data = ((*value & writable_mask) |
  1.2127 +                       (cfg_entry->data & ~writable_mask));
  1.2128 +
  1.2129 +    /* create value for writing to I/O device register */
  1.2130 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.2131 +    *value = ((*value & throughable_mask) |
  1.2132 +              (dev_value & ~throughable_mask));
  1.2133 +
  1.2134 +    return 0;
  1.2135 +}
  1.2136 +
  1.2137 +/* write Link Control2 register */
  1.2138 +static int pt_linkctrl2_reg_write(struct pt_dev *ptdev, 
  1.2139 +        struct pt_reg_tbl *cfg_entry, 
  1.2140 +        uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
  1.2141 +{
  1.2142 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.2143 +    uint16_t writable_mask = 0;
  1.2144 +    uint16_t throughable_mask = 0;
  1.2145 +    uint16_t linkctrl2_mask = (0x0040 | 0xE000);
  1.2146 +
  1.2147 +    /* modify emulate register */
  1.2148 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & 
  1.2149 +                    ~linkctrl2_mask;
  1.2150 +    cfg_entry->data = ((*value & writable_mask) |
  1.2151 +                       (cfg_entry->data & ~writable_mask));
  1.2152 +
  1.2153 +    /* create value for writing to I/O device register */
  1.2154 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.2155 +    *value = ((*value & throughable_mask) |
  1.2156 +              (dev_value & ~throughable_mask));
  1.2157 +
  1.2158 +    return 0;
  1.2159 +}
  1.2160 +
  1.2161 +/* write Message Control register */
  1.2162 +static int pt_msgctrl_reg_write(struct pt_dev *ptdev, 
  1.2163 +    struct pt_reg_tbl *cfg_entry, 
  1.2164 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
  1.2165 +{
  1.2166 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.2167 +    uint16_t writable_mask = 0;
  1.2168 +    uint16_t throughable_mask = 0;
  1.2169 +    uint16_t old_ctrl = cfg_entry->data;
  1.2170 +    PCIDevice *pd = (PCIDevice *)ptdev;
  1.2171 +
  1.2172 +    PT_LOG("[before] dev_val:%xh wr_val:%xh\n", dev_value, *value);
  1.2173 +
  1.2174 +    /* Currently no support for multi-vector */
  1.2175 +    if ((*value & PCI_MSI_FLAGS_QSIZE) != 0x0)
  1.2176 +        PT_LOG("try to set more than 1 vector ctrl %x\n", *value);
  1.2177 +
  1.2178 +    /* modify emulate register */
  1.2179 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
  1.2180 +    cfg_entry->data = ((*value & writable_mask) |
  1.2181 +                       (cfg_entry->data & ~writable_mask));
  1.2182 +    /* update the msi_info too */
  1.2183 +    ptdev->msi->flags |= cfg_entry->data & 
  1.2184 +        ~(MSI_FLAG_UNINIT | PT_MSI_MAPPED | PCI_MSI_FLAGS_ENABLE);
  1.2185 +
  1.2186 +    PT_LOG("old_ctrl:%04xh new_ctrl:%04xh\n", old_ctrl, cfg_entry->data);
  1.2187 +    
  1.2188 +    /* create value for writing to I/O device register */
  1.2189 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.2190 +    *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
  1.2191 +
  1.2192 +    /* update MSI */
  1.2193 +    if (*value & PCI_MSI_FLAGS_ENABLE)
  1.2194 +    {
  1.2195 +        /* setup MSI pirq for the first time */
  1.2196 +        if (ptdev->msi->flags & MSI_FLAG_UNINIT)
  1.2197 +        {
  1.2198 +            /* Init physical one */
  1.2199 +            PT_LOG("setup msi for dev %x\n", pd->devfn);
  1.2200 +            if (pt_msi_setup(ptdev))
  1.2201 +            {
  1.2202 +                PT_LOG("pt_msi_setup error!!!\n");
  1.2203 +                return -1;
  1.2204 +            }
  1.2205 +            pt_msi_update(ptdev);
  1.2206 +
  1.2207 +            ptdev->msi->flags &= ~MSI_FLAG_UNINIT;
  1.2208 +            ptdev->msi->flags |= PT_MSI_MAPPED;
  1.2209 +        }
  1.2210 +        ptdev->msi->flags |= PCI_MSI_FLAGS_ENABLE;
  1.2211 +    }
  1.2212 +    else
  1.2213 +        ptdev->msi->flags &= ~PCI_MSI_FLAGS_ENABLE;
  1.2214 +
  1.2215 +    PT_LOG("[after] wr_val:%xh\n", *value);
  1.2216 +
  1.2217 +    return 0;
  1.2218 +}
  1.2219 +
  1.2220 +/* write Message Address register */
  1.2221 +static int pt_msgaddr32_reg_write(struct pt_dev *ptdev, 
  1.2222 +        struct pt_reg_tbl *cfg_entry, 
  1.2223 +        uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
  1.2224 +{
  1.2225 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.2226 +    uint32_t writable_mask = 0;
  1.2227 +    uint32_t throughable_mask = 0;
  1.2228 +    uint32_t old_addr = cfg_entry->data;
  1.2229 +
  1.2230 +    PT_LOG("[before] dev_val:%xh wr_val:%xh\n", dev_value, *value);
  1.2231 +
  1.2232 +    /* modify emulate register */
  1.2233 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
  1.2234 +    cfg_entry->data = ((*value & writable_mask) |
  1.2235 +                       (cfg_entry->data & ~writable_mask));
  1.2236 +    /* update the msi_info too */
  1.2237 +    ptdev->msi->addr_lo = cfg_entry->data;
  1.2238 +    
  1.2239 +    PT_LOG("old_addr_lo:%08xh new_addr_lo:%08xh\n", old_addr, cfg_entry->data);
  1.2240 +    
  1.2241 +    /* create value for writing to I/O device register */
  1.2242 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.2243 +    *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
  1.2244 +
  1.2245 +    /* update MSI */
  1.2246 +    if (cfg_entry->data != old_addr)
  1.2247 +    {
  1.2248 +        if (ptdev->msi->flags & PCI_MSI_FLAGS_ENABLE)
  1.2249 +            pt_msi_update(ptdev);
  1.2250 +    }
  1.2251 +
  1.2252 +    PT_LOG("[after] wr_val:%xh\n", *value);
  1.2253 +
  1.2254 +    return 0;
  1.2255 +}
  1.2256 +
  1.2257 +/* write Message Upper Address register */
  1.2258 +static int pt_msgaddr64_reg_write(struct pt_dev *ptdev, 
  1.2259 +        struct pt_reg_tbl *cfg_entry, 
  1.2260 +        uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
  1.2261 +{
  1.2262 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.2263 +    uint32_t writable_mask = 0;
  1.2264 +    uint32_t throughable_mask = 0;
  1.2265 +    uint32_t old_addr = cfg_entry->data;
  1.2266 +
  1.2267 +    PT_LOG("[before] dev_val:%xh wr_val:%xh\n", dev_value, *value);
  1.2268 +
  1.2269 +    /* check whether the type is 64 bit or not */
  1.2270 +    if (!(ptdev->msi->flags & PCI_MSI_FLAGS_64BIT))
  1.2271 +    {
  1.2272 +        /* exit I/O emulator */
  1.2273 +        PT_LOG("why comes to Upper Address without 64 bit support??\n");
  1.2274 +        return -1;
  1.2275 +    }
  1.2276 +
  1.2277 +    /* modify emulate register */
  1.2278 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
  1.2279 +    cfg_entry->data = ((*value & writable_mask) |
  1.2280 +                       (cfg_entry->data & ~writable_mask));
  1.2281 +    /* update the msi_info too */
  1.2282 +    ptdev->msi->addr_hi = cfg_entry->data;
  1.2283 +    
  1.2284 +    PT_LOG("old_addr_hi:%08xh new_addr_hi:%08xh\n", old_addr, cfg_entry->data);
  1.2285 +    
  1.2286 +    /* create value for writing to I/O device register */
  1.2287 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.2288 +    *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
  1.2289 +
  1.2290 +    /* update MSI */
  1.2291 +    if (cfg_entry->data != old_addr)
  1.2292 +    {
  1.2293 +        if (ptdev->msi->flags & PCI_MSI_FLAGS_ENABLE)
  1.2294 +            pt_msi_update(ptdev);
  1.2295 +    }
  1.2296 +
  1.2297 +    PT_LOG("[after] wr_val:%xh\n", *value);
  1.2298 +
  1.2299 +    return 0;
  1.2300 +}
  1.2301 +
  1.2302 +/* this function will be called twice (for 32 bit and 64 bit type) */
  1.2303 +/* write Message Data register */
  1.2304 +static int pt_msgdata_reg_write(struct pt_dev *ptdev, 
  1.2305 +    struct pt_reg_tbl *cfg_entry, 
  1.2306 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
  1.2307 +{
  1.2308 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.2309 +    uint16_t writable_mask = 0;
  1.2310 +    uint16_t throughable_mask = 0;
  1.2311 +    uint16_t old_data = cfg_entry->data;
  1.2312 +    uint32_t flags = ptdev->msi->flags;
  1.2313 +    uint32_t offset = reg->offset;
  1.2314 +
  1.2315 +    PT_LOG("[before] dev_val:%xh wr_val:%xh\n", dev_value, *value);
  1.2316 +
  1.2317 +    /* check the offset whether matches the type or not */
  1.2318 +    if (!((offset == PCI_MSI_DATA_64) &&  (flags & PCI_MSI_FLAGS_64BIT)) &&
  1.2319 +        !((offset == PCI_MSI_DATA_32) && !(flags & PCI_MSI_FLAGS_64BIT)))
  1.2320 +    {
  1.2321 +        /* exit I/O emulator */
  1.2322 +        PT_LOG("Error: the offset is not match with the 32/64 bit type!!\n");
  1.2323 +        return -1;
  1.2324 +    }
  1.2325 +
  1.2326 +    /* modify emulate register */
  1.2327 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
  1.2328 +    cfg_entry->data = ((*value & writable_mask) |
  1.2329 +                       (cfg_entry->data & ~writable_mask));
  1.2330 +    /* update the msi_info too */
  1.2331 +    ptdev->msi->data = cfg_entry->data;
  1.2332 +
  1.2333 +    PT_LOG("old_data:%04xh new_data:%04xh\n", old_data, cfg_entry->data);
  1.2334 +
  1.2335 +    /* create value for writing to I/O device register */
  1.2336 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.2337 +    *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
  1.2338 +
  1.2339 +    /* update MSI */
  1.2340 +    if (cfg_entry->data != old_data)
  1.2341 +    {
  1.2342 +        if (flags & PCI_MSI_FLAGS_ENABLE)
  1.2343 +            pt_msi_update(ptdev);
  1.2344 +    }
  1.2345 +
  1.2346 +    PT_LOG("[after] wr_val:%xh\n", *value);
  1.2347 +
  1.2348 +    return 0;
  1.2349 +}
  1.2350 +
  1.2351 +/* write Message Control register for MSI-X */
  1.2352 +static int pt_msixctrl_reg_write(struct pt_dev *ptdev, 
  1.2353 +    struct pt_reg_tbl *cfg_entry, 
  1.2354 +    uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
  1.2355 +{
  1.2356 +    struct pt_reg_info_tbl *reg = cfg_entry->reg;
  1.2357 +    uint16_t writable_mask = 0;
  1.2358 +    uint16_t throughable_mask = 0;
  1.2359 +    uint16_t old_ctrl = cfg_entry->data;
  1.2360 +
  1.2361 +    PT_LOG("[before] dev_val:%xh wr_val:%xh\n", dev_value, *value);
  1.2362 +
  1.2363 +    /* modify emulate register */
  1.2364 +    writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
  1.2365 +    cfg_entry->data = ((*value & writable_mask) |
  1.2366 +                       (cfg_entry->data & ~writable_mask));
  1.2367 +
  1.2368 +    PT_LOG("old_ctrl:%04xh new_ctrl:%04xh\n", old_ctrl, cfg_entry->data);
  1.2369 +    
  1.2370 +    /* create value for writing to I/O device register */
  1.2371 +    throughable_mask = ~reg->emu_mask & valid_mask;
  1.2372 +    *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
  1.2373 +
  1.2374 +    /* update MSI-X */
  1.2375 +    if ((*value & PCI_MSIX_ENABLE) && !(*value & PCI_MSIX_MASK))
  1.2376 +        pt_msix_update(ptdev);
  1.2377 +
  1.2378 +    ptdev->msix->enabled = !!(*value & PCI_MSIX_ENABLE);
  1.2379 +
  1.2380 +    PT_LOG("[after] wr_val:%xh\n", *value);
  1.2381 +
  1.2382 +    return 0;
  1.2383 +}
  1.2384 +
  1.2385  struct pt_dev * register_real_device(PCIBus *e_bus,
  1.2386          const char *e_dev_name, int e_devfn, uint8_t r_bus, uint8_t r_dev,
  1.2387          uint8_t r_func, uint32_t machine_irq, struct pci_access *pci_access)
  1.2388  {
  1.2389 -    int rc = -1, i, pos;
  1.2390 +    int rc = -1, i;
  1.2391      struct pt_dev *assigned_device = NULL;
  1.2392      struct pci_dev *pci_dev;
  1.2393      uint8_t e_device, e_intx;
  1.2394 @@ -541,7 +2720,6 @@ struct pt_dev * register_real_device(PCI
  1.2395  
  1.2396      assigned_device->pci_dev = pci_dev;
  1.2397  
  1.2398 -
  1.2399      /* Assign device */
  1.2400      machine_bdf.reg = 0;
  1.2401      machine_bdf.bus = r_bus;
  1.2402 @@ -555,18 +2733,22 @@ struct pt_dev * register_real_device(PCI
  1.2403      for ( i = 0; i < PCI_CONFIG_SIZE; i++ )
  1.2404          assigned_device->dev.config[i] = pci_read_byte(pci_dev, i);
  1.2405  
  1.2406 -    if ( (pos = find_cap_offset(pci_dev, PCI_CAP_ID_MSI)) )
  1.2407 -        pt_msi_init(assigned_device, pos);
  1.2408 -
  1.2409 -    if ( (pos = find_cap_offset(pci_dev, PCI_CAP_ID_MSIX)) )
  1.2410 -        pt_msix_init(assigned_device, pos);
  1.2411 -
  1.2412      /* Handle real device's MMIO/PIO BARs */
  1.2413      pt_register_regions(assigned_device);
  1.2414  
  1.2415 +    /* reinitialize each config register to be emulated */
  1.2416 +    rc = pt_config_init(assigned_device);
  1.2417 +    if ( rc < 0 ) {
  1.2418 +        return NULL;
  1.2419 +    }
  1.2420 +
  1.2421      /* Bind interrupt */
  1.2422 +    if (!assigned_device->dev.config[0x3d])
  1.2423 +        goto out;
  1.2424 +
  1.2425      e_device = (assigned_device->dev.devfn >> 3) & 0x1f;
  1.2426 -    e_intx = assigned_device->dev.config[0x3d]-1;
  1.2427 +    /* fix virtual interrupt pin to INTA# */
  1.2428 +    e_intx = 0;
  1.2429  
  1.2430      if ( PT_MACHINE_IRQ_AUTO == machine_irq )
  1.2431      {
  1.2432 @@ -603,6 +2785,7 @@ struct pt_dev * register_real_device(PCI
  1.2433              *(uint16_t *)(&assigned_device->dev.config[0x04]));
  1.2434      }
  1.2435  
  1.2436 +out:
  1.2437      PT_LOG("Real physical device %02x:%02x.%x registered successfuly!\n", 
  1.2438          r_bus, r_dev, r_func);
  1.2439  
  1.2440 @@ -756,3 +2939,4 @@ int pt_init(PCIBus *e_bus, char *direct_
  1.2441      /* Success */
  1.2442      return 0;
  1.2443  }
  1.2444 +
     2.1 --- a/tools/ioemu/hw/pass-through.h	Fri Jul 04 11:51:59 2008 +0100
     2.2 +++ b/tools/ioemu/hw/pass-through.h	Fri Jul 04 11:54:21 2008 +0100
     2.3 @@ -21,6 +21,7 @@
     2.4  #include "vl.h"
     2.5  #include "pci/header.h"
     2.6  #include "pci/pci.h"
     2.7 +#include "audio/sys-queue.h"
     2.8  
     2.9  /* Log acesss */
    2.10  #define PT_LOGGING_ENABLED
    2.11 @@ -43,36 +44,72 @@
    2.12  #define PCI_EXP_DEVCTL_FLR      (1 << 15)
    2.13  #define PCI_BAR_ENTRIES         (6)
    2.14  
    2.15 +/* because the current version of libpci (2.2.0) doesn't define these ID,
    2.16 + * so we define Capability ID here.
    2.17 + */
    2.18 +/* SHPC Capability List Item reg group */
    2.19 +#define PCI_CAP_ID_HOTPLUG      0x0C
    2.20 +/* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
    2.21 +#define PCI_CAP_ID_SSVID        0x0D
    2.22 +/* interrupt masking & reporting supported */
    2.23 +#define PCI_MSI_FLAGS_MASK_BIT  0x0100
    2.24 +
    2.25 +#define PT_INVALID_REG          0xFFFFFFFF      /* invalid register value */
    2.26 +#define PT_BAR_ALLF             0xFFFFFFFF      /* BAR ALLF value */
    2.27 +#define PT_BAR_MEM_RO_MASK      0x0000000F      /* BAR ReadOnly mask(Memory) */
    2.28 +#define PT_BAR_MEM_EMU_MASK     0xFFFFFFF0      /* BAR emul mask(Memory) */
    2.29 +#define PT_BAR_IO_RO_MASK       0x00000003      /* BAR ReadOnly mask(I/O) */
    2.30 +#define PT_BAR_IO_EMU_MASK      0xFFFFFFFC      /* BAR emul mask(I/O) */
    2.31 +enum {
    2.32 +    PT_BAR_FLAG_MEM = 0,                        /* Memory type BAR */
    2.33 +    PT_BAR_FLAG_IO,                             /* I/O type BAR */
    2.34 +    PT_BAR_FLAG_UPPER,                          /* upper 64bit BAR */
    2.35 +    PT_BAR_FLAG_UNUSED,                         /* unused BAR */
    2.36 +};
    2.37 +enum {
    2.38 +    GRP_TYPE_HARDWIRED = 0,                     /* 0 Hardwired reg group */
    2.39 +    GRP_TYPE_EMU,                               /* emul reg group */
    2.40 +};
    2.41 +
    2.42 +#define PT_GET_EMUL_SIZE(flag, r_size) do { \
    2.43 +    if (flag == PT_BAR_FLAG_MEM) {\
    2.44 +        r_size = (((r_size) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1)); \
    2.45 +    }\
    2.46 +} while(0)
    2.47 +
    2.48 +
    2.49  struct pt_region {
    2.50      /* Virtual phys base & size */
    2.51      uint32_t e_physbase;
    2.52      uint32_t e_size;
    2.53      /* Index of region in qemu */
    2.54      uint32_t memory_index;
    2.55 +    /* BAR flag */
    2.56 +    uint32_t bar_flag;
    2.57      /* Translation of the emulated address */
    2.58      union {
    2.59 -        uint32_t maddr;
    2.60 -        uint32_t pio_base;
    2.61 -        uint32_t u;
    2.62 +        uint64_t maddr;
    2.63 +        uint64_t pio_base;
    2.64 +        uint64_t u;
    2.65      } access;
    2.66  };
    2.67  
    2.68  struct pt_msi_info {
    2.69      uint32_t flags;
    2.70 -    int offset;
    2.71 -    int size;
    2.72 -    int pirq;  /* guest pirq corresponding */
    2.73 +    int pirq;          /* guest pirq corresponding */
    2.74 +    uint32_t addr_lo;  /* guest message address */
    2.75 +    uint32_t addr_hi;  /* guest message upper address */
    2.76 +    uint16_t data;     /* guest message data */
    2.77  };
    2.78  
    2.79  struct msix_entry_info {
    2.80 -    int pirq;   /* -1 means unmapped */
    2.81 -    int flags;  /* flags indicting whether MSI ADDR or DATA is updated */
    2.82 +    int pirq;          /* -1 means unmapped */
    2.83 +    int flags;         /* flags indicting whether MSI ADDR or DATA is updated */
    2.84      uint32_t io_mem[4];
    2.85  };
    2.86  
    2.87  struct pt_msix_info {
    2.88      int enabled;
    2.89 -    int offset;
    2.90      int total_entries;
    2.91      int bar_index;
    2.92      uint32_t table_off;
    2.93 @@ -89,8 +126,10 @@ struct pt_msix_info {
    2.94  */
    2.95  struct pt_dev {
    2.96      PCIDevice dev;
    2.97 -    struct pci_dev *pci_dev;                     /* libpci struct */
    2.98 +    struct pci_dev *pci_dev;                    /* libpci struct */
    2.99      struct pt_region bases[PCI_NUM_REGIONS];    /* Access regions */
   2.100 +    QEMU_LIST_HEAD (reg_grp_tbl_listhead, pt_reg_grp_tbl) reg_grp_tbl_head;
   2.101 +                                                /* emul reg group list */
   2.102      struct pt_msi_info *msi;                    /* MSI virtualization */
   2.103      struct pt_msix_info *msix;                  /* MSI-X virtualization */
   2.104  };
   2.105 @@ -113,5 +152,121 @@ struct pci_config_cf8 {
   2.106  
   2.107  int pt_init(PCIBus * e_bus, char * direct_pci);
   2.108  
   2.109 +/* emul reg group management table */
   2.110 +struct pt_reg_grp_tbl {
   2.111 +    /* emul reg group list */
   2.112 +    QEMU_LIST_ENTRY (pt_reg_grp_tbl) entries;
   2.113 +    /* emul reg group info table */
   2.114 +    struct pt_reg_grp_info_tbl *reg_grp;
   2.115 +    /* emul reg group base offset */
   2.116 +    uint32_t base_offset;
   2.117 +    /* emul reg group size */
   2.118 +    uint8_t size;
   2.119 +    /* emul reg management table list */
   2.120 +    QEMU_LIST_HEAD (reg_tbl_listhead, pt_reg_tbl) reg_tbl_head;
   2.121 +};
   2.122 +
   2.123 +/* emul reg group size initialize method */
   2.124 +typedef uint8_t (*pt_reg_size_init) (struct pt_dev *ptdev, 
   2.125 +                                     struct pt_reg_grp_info_tbl *grp_reg, 
   2.126 +                                     uint32_t base_offset);
   2.127 +/* emul reg group infomation table */
   2.128 +struct pt_reg_grp_info_tbl {
   2.129 +    /* emul reg group ID */
   2.130 +    uint8_t grp_id;
   2.131 +    /* emul reg group type */
   2.132 +    uint8_t grp_type;
   2.133 +    /* emul reg group size */
   2.134 +    uint8_t grp_size;
   2.135 +    /* emul reg get size method */
   2.136 +    pt_reg_size_init size_init;
   2.137 +    /* emul reg info table */
   2.138 +    struct pt_reg_info_tbl *emu_reg_tbl;
   2.139 +};
   2.140 +
   2.141 +/* emul reg management table */
   2.142 +struct pt_reg_tbl {
   2.143 +    /* emul reg table list */
   2.144 +    QEMU_LIST_ENTRY (pt_reg_tbl) entries;
   2.145 +    /* emul reg info table */
   2.146 +    struct pt_reg_info_tbl *reg;
   2.147 +    /* emul reg value */
   2.148 +    uint32_t data;
   2.149 +};
   2.150 +
   2.151 +/* emul reg initialize method */
   2.152 +typedef uint32_t (*conf_reg_init) (struct pt_dev *ptdev, 
   2.153 +                                   struct pt_reg_info_tbl *reg, 
   2.154 +                                   uint32_t real_offset);
   2.155 +/* emul reg long write method */
   2.156 +typedef int (*conf_dword_write) (struct pt_dev *ptdev,
   2.157 +                                 struct pt_reg_tbl *cfg_entry, 
   2.158 +                                 uint32_t *value, 
   2.159 +                                 uint32_t dev_value,
   2.160 +                                 uint32_t valid_mask);
   2.161 +/* emul reg word write method */
   2.162 +typedef int (*conf_word_write) (struct pt_dev *ptdev,
   2.163 +                                struct pt_reg_tbl *cfg_entry, 
   2.164 +                                uint16_t *value, 
   2.165 +                                uint16_t dev_value,
   2.166 +                                uint16_t valid_mask);
   2.167 +/* emul reg byte write method */
   2.168 +typedef int (*conf_byte_write) (struct pt_dev *ptdev,
   2.169 +                                struct pt_reg_tbl *cfg_entry, 
   2.170 +                                uint8_t *value, 
   2.171 +                                uint8_t dev_value,
   2.172 +                                uint8_t valid_mask);
   2.173 +/* emul reg long read methods */
   2.174 +typedef int (*conf_dword_read) (struct pt_dev *ptdev,
   2.175 +                                struct pt_reg_tbl *cfg_entry, 
   2.176 +                                uint32_t *value,
   2.177 +                                uint32_t valid_mask);
   2.178 +/* emul reg word read method */
   2.179 +typedef int (*conf_word_read) (struct pt_dev *ptdev,
   2.180 +                               struct pt_reg_tbl *cfg_entry, 
   2.181 +                               uint16_t *value,
   2.182 +                               uint16_t valid_mask);
   2.183 +/* emul reg byte read method */
   2.184 +typedef int (*conf_byte_read) (struct pt_dev *ptdev,
   2.185 +                               struct pt_reg_tbl *cfg_entry, 
   2.186 +                               uint8_t *value,
   2.187 +                               uint8_t valid_mask);
   2.188 +
   2.189 +/* emul reg infomation table */
   2.190 +struct pt_reg_info_tbl {
   2.191 +    /* reg relative offset */
   2.192 +    uint32_t offset;
   2.193 +    /* reg size */
   2.194 +    uint32_t size;
   2.195 +    /* reg initial value */
   2.196 +    uint32_t init_val;
   2.197 +    /* reg read only field mask (ON:RO/ROS, OFF:other) */
   2.198 +    uint32_t ro_mask;
   2.199 +    /* reg emulate field mask (ON:emu, OFF:passthrough) */
   2.200 +    uint32_t emu_mask;
   2.201 +    /* emul reg initialize method */
   2.202 +    conf_reg_init init;
   2.203 +    union {
   2.204 +        struct {
   2.205 +            /* emul reg long write method */
   2.206 +            conf_dword_write write;
   2.207 +            /* emul reg long read method */
   2.208 +            conf_dword_read read;
   2.209 +        } dw;
   2.210 +        struct {
   2.211 +            /* emul reg word write method */
   2.212 +            conf_word_write write;
   2.213 +            /* emul reg word read method */
   2.214 +            conf_word_read read;
   2.215 +        } w;
   2.216 +        struct {
   2.217 +            /* emul reg byte write method */
   2.218 +            conf_byte_write write;
   2.219 +            /* emul reg byte read method */
   2.220 +            conf_byte_read read;
   2.221 +        } b;
   2.222 +    } u;
   2.223 +};
   2.224 +
   2.225  #endif /* __PASSTHROUGH_H__ */
   2.226  
     3.1 --- a/tools/ioemu/hw/pci.c	Fri Jul 04 11:51:59 2008 +0100
     3.2 +++ b/tools/ioemu/hw/pci.c	Fri Jul 04 11:54:21 2008 +0100
     3.3 @@ -641,3 +641,34 @@ PCIBus *pci_bridge_init(PCIBus *bus, int
     3.4      s->bus = pci_register_secondary_bus(&s->dev, map_irq);
     3.5      return s->bus;
     3.6  }
     3.7 +
     3.8 +int pt_chk_bar_overlap(PCIBus *bus, int devfn, uint32_t addr, uint32_t size)
     3.9 +{
    3.10 +    PCIDevice *devices = (PCIDevice *)bus->devices;
    3.11 +    PCIIORegion *r;
    3.12 +    int ret = 0;
    3.13 +    int i, j;
    3.14 +
    3.15 +    /* check Overlapped to Base Address */
    3.16 +    for (i=0; i<256; i++, devices++)
    3.17 +    {
    3.18 +        if ((devices == NULL) || (devices->devfn == devfn))
    3.19 +            continue;
    3.20 +
    3.21 +        for (j=0; j<PCI_NUM_REGIONS; j++)
    3.22 +        {
    3.23 +            r = &devices->io_regions[j];
    3.24 +            if ((addr < (r->addr + r->size)) && ((addr + size) > r->addr))
    3.25 +            {
    3.26 +                printf("Overlapped to device[%02x:%02x.%x] region:%d addr:%08x"
    3.27 +                    " size:%08x\n", bus->bus_num, (devices->devfn >> 3) & 0x1F,
    3.28 +                    (devices->devfn & 0x7), j, r->addr, r->size);
    3.29 +                ret = 1;
    3.30 +                goto out;
    3.31 +            }
    3.32 +        }
    3.33 +    }
    3.34 +
    3.35 +out:
    3.36 +    return ret;
    3.37 +}
     4.1 --- a/tools/ioemu/hw/pt-msi.c	Fri Jul 04 11:51:59 2008 +0100
     4.2 +++ b/tools/ioemu/hw/pt-msi.c	Fri Jul 04 11:54:21 2008 +0100
     4.3 @@ -23,60 +23,11 @@
     4.4  #include <sys/mman.h>
     4.5  
     4.6  /* MSI virtuailization functions */
     4.7 -#define PT_MSI_CTRL_WR_MASK_HI      (0x1)
     4.8 -#define PT_MSI_CTRL_WR_MASK_LO      (0x8E)
     4.9 -#define PT_MSI_DATA_WR_MASK         (0x38)
    4.10 -int pt_msi_init(struct pt_dev *dev, int pos)
    4.11 -{
    4.12 -    uint8_t id;
    4.13 -    uint16_t flags;
    4.14 -    struct pci_dev *pd = dev->pci_dev;
    4.15 -    PCIDevice *d = (struct PCIDevice *)dev;
    4.16 -
    4.17 -    id = pci_read_byte(pd, pos + PCI_CAP_LIST_ID);
    4.18 -
    4.19 -    if ( id != PCI_CAP_ID_MSI )
    4.20 -    {
    4.21 -        PT_LOG("pt_msi_init: error id %x pos %x\n", id, pos);
    4.22 -        return -1;
    4.23 -    }
    4.24 -
    4.25 -    dev->msi = malloc(sizeof(struct pt_msi_info));
    4.26 -    if ( !dev->msi )
    4.27 -    {
    4.28 -        PT_LOG("pt_msi_init: error allocation pt_msi_info\n");
    4.29 -        return -1;
    4.30 -    }
    4.31 -    memset(dev->msi, 0, sizeof(struct pt_msi_info));
    4.32 -
    4.33 -    dev->msi->offset = pos;
    4.34 -    dev->msi->size = 0xa;
    4.35 -
    4.36 -    flags = pci_read_byte(pd, pos + PCI_MSI_FLAGS);
    4.37 -    if ( flags & PCI_MSI_FLAGS_ENABLE )
    4.38 -    {
    4.39 -        PT_LOG("pt_msi_init: MSI enabled already, disable first\n");
    4.40 -        pci_write_byte(pd, pos + PCI_MSI_FLAGS, flags & ~PCI_MSI_FLAGS_ENABLE);
    4.41 -    }
    4.42 -    dev->msi->flags |= (flags | MSI_FLAG_UNINIT);
    4.43 -
    4.44 -    if ( flags & PCI_MSI_FLAGS_64BIT )
    4.45 -        dev->msi->size += 4;
    4.46 -    if ( flags & PCI_MSI_FLAGS_PVMASK )
    4.47 -        dev->msi->size += 10;
    4.48 -
    4.49 -    /* All register is 0 after reset, except first 4 byte */
    4.50 -    *(uint32_t *)(&d->config[pos]) = pci_read_long(pd, pos);
    4.51 -    d->config[pos + 2] &=  PT_MSI_CTRL_WR_MASK_LO;
    4.52 -    d->config[pos + 3] &=  PT_MSI_CTRL_WR_MASK_HI;
    4.53 -
    4.54 -    return 0;
    4.55 -}
    4.56  
    4.57  /*
    4.58   * setup physical msi, but didn't enable it
    4.59   */
    4.60 -static int pt_msi_setup(struct pt_dev *dev)
    4.61 +int pt_msi_setup(struct pt_dev *dev)
    4.62  {
    4.63      int pirq = -1;
    4.64  
    4.65 @@ -107,56 +58,7 @@ static int pt_msi_setup(struct pt_dev *d
    4.66      return 0;
    4.67  }
    4.68  
    4.69 -/*
    4.70 - * caller should make sure mask is supported
    4.71 - */
    4.72 -static uint32_t get_msi_gmask(struct pt_dev *d)
    4.73 -{
    4.74 -    struct PCIDevice *pd = (struct PCIDevice *)d;
    4.75 -
    4.76 -    if ( d->msi->flags & PCI_MSI_FLAGS_64BIT )
    4.77 -        return *(uint32_t *)(pd->config + d->msi->offset + 0xc);
    4.78 -    else
    4.79 -        return *(uint32_t *)(pd->config + d->msi->offset + 0x10);
    4.80 -
    4.81 -}
    4.82 -
    4.83 -static uint16_t get_msi_gdata(struct pt_dev *d)
    4.84 -{
    4.85 -    struct PCIDevice *pd = (struct PCIDevice *)d;
    4.86 -
    4.87 -    if ( d->msi->flags & PCI_MSI_FLAGS_64BIT )
    4.88 -        return *(uint16_t *)(pd->config + d->msi->offset + PCI_MSI_DATA_64);
    4.89 -    else
    4.90 -        return *(uint16_t *)(pd->config + d->msi->offset + PCI_MSI_DATA_32);
    4.91 -}
    4.92 -
    4.93 -static uint64_t get_msi_gaddr(struct pt_dev *d)
    4.94 -{
    4.95 -    struct PCIDevice *pd = (struct PCIDevice *)d;
    4.96 -    uint32_t addr_hi;
    4.97 -    uint64_t addr = 0;
    4.98 -
    4.99 -    addr =(uint64_t)(*(uint32_t *)(pd->config +
   4.100 -                     d->msi->offset + PCI_MSI_ADDRESS_LO));
   4.101 -
   4.102 -    if ( d->msi->flags & PCI_MSI_FLAGS_64BIT )
   4.103 -    {
   4.104 -        addr_hi = *(uint32_t *)(pd->config + d->msi->offset
   4.105 -                                + PCI_MSI_ADDRESS_HI);
   4.106 -        addr |= (uint64_t)addr_hi << 32;
   4.107 -    }
   4.108 -    return addr;
   4.109 -}
   4.110 -
   4.111 -static uint8_t get_msi_gctrl(struct pt_dev *d)
   4.112 -{
   4.113 -    struct PCIDevice *pd = (struct PCIDevice *)d;
   4.114 -
   4.115 -    return  *(uint8_t *)(pd->config + d->msi->offset + PCI_MSI_FLAGS);
   4.116 -}
   4.117 -
   4.118 -static uint32_t __get_msi_gflags(uint32_t data, uint64_t addr)
   4.119 +uint32_t __get_msi_gflags(uint32_t data, uint64_t addr)
   4.120  {
   4.121      uint32_t result = 0;
   4.122      int rh, dm, dest_id, deliv_mode, trig_mode;
   4.123 @@ -174,320 +76,27 @@ static uint32_t __get_msi_gflags(uint32_
   4.124      return result;
   4.125  }
   4.126  
   4.127 -static uint32_t get_msi_gflags(struct pt_dev *d)
   4.128 -{
   4.129 -    uint16_t data = get_msi_gdata(d);
   4.130 -    uint64_t addr = get_msi_gaddr(d);
   4.131 -
   4.132 -    return __get_msi_gflags(data, addr);
   4.133 -}
   4.134 -
   4.135 -/*
   4.136 - * This may be arch different
   4.137 - */
   4.138 -static inline uint8_t get_msi_gvec(struct pt_dev *d)
   4.139 -{
   4.140 -    return get_msi_gdata(d) & 0xff;
   4.141 -}
   4.142 -
   4.143  /*
   4.144   * Update msi mapping, usually called when MSI enabled,
   4.145   * except the first time
   4.146   */
   4.147 -static int pt_msi_update(struct pt_dev *d)
   4.148 -{
   4.149 -    PT_LOG("now update msi with pirq %x gvec %x\n",
   4.150 -            d->msi->pirq, get_msi_gvec(d));
   4.151 -    return xc_domain_update_msi_irq(xc_handle, domid, get_msi_gvec(d),
   4.152 -                                     d->msi->pirq, get_msi_gflags(d));
   4.153 -}
   4.154 -
   4.155 -static int pt_msi_enable(struct pt_dev *d, int enable)
   4.156 -{
   4.157 -    uint16_t ctrl;
   4.158 -    struct pci_dev *pd = d->pci_dev;
   4.159 -
   4.160 -    if ( !pd )
   4.161 -        return -1;
   4.162 -
   4.163 -    ctrl = pci_read_word(pd, d->msi->offset + PCI_MSI_FLAGS);
   4.164 -
   4.165 -    if ( enable )
   4.166 -        ctrl |= PCI_MSI_FLAGS_ENABLE;
   4.167 -    else
   4.168 -        ctrl &= ~PCI_MSI_FLAGS_ENABLE;
   4.169 -
   4.170 -    pci_write_word(pd, d->msi->offset + PCI_MSI_FLAGS, ctrl);
   4.171 -    return 0;
   4.172 -}
   4.173 -
   4.174 -static int pt_msi_control_update(struct pt_dev *d, uint16_t old_ctrl)
   4.175 -{
   4.176 -    uint16_t new_ctrl;
   4.177 -    PCIDevice *pd = (PCIDevice *)d;
   4.178 -
   4.179 -    new_ctrl = get_msi_gctrl(d);
   4.180 -
   4.181 -    PT_LOG("old_ctrl %x new_Ctrl %x\n", old_ctrl, new_ctrl);
   4.182 -
   4.183 -    if ( new_ctrl & PCI_MSI_FLAGS_ENABLE )
   4.184 -    {
   4.185 -        if ( d->msi->flags & MSI_FLAG_UNINIT )
   4.186 -        {
   4.187 -            /* Init physical one */
   4.188 -            PT_LOG("setup msi for dev %x\n", pd->devfn);
   4.189 -            if ( pt_msi_setup(d) )
   4.190 -            {
   4.191 -                PT_LOG("pt_msi_setup error!!!\n");
   4.192 -                return -1;
   4.193 -            }
   4.194 -            pt_msi_update(d);
   4.195 -
   4.196 -            d->msi->flags &= ~MSI_FLAG_UNINIT;
   4.197 -            d->msi->flags |= PT_MSI_MAPPED;
   4.198 -
   4.199 -            /* Enable physical MSI only after bind */
   4.200 -            pt_msi_enable(d, 1);
   4.201 -        }
   4.202 -        else if ( !(old_ctrl & PCI_MSI_FLAGS_ENABLE) )
   4.203 -            pt_msi_enable(d, 1);
   4.204 -    }
   4.205 -    else if ( old_ctrl & PCI_MSI_FLAGS_ENABLE )
   4.206 -        pt_msi_enable(d, 0);
   4.207 -
   4.208 -    /* Currently no support for multi-vector */
   4.209 -    if ( (new_ctrl & PCI_MSI_FLAGS_QSIZE) != 0x0 )
   4.210 -        PT_LOG("try to set more than 1 vector ctrl %x\n", new_ctrl);
   4.211 -
   4.212 -    return 0;
   4.213 -}
   4.214 -
   4.215 -static int
   4.216 -pt_msi_map_update(struct pt_dev *d, uint32_t old_data, uint64_t old_addr)
   4.217 -{
   4.218 -    uint32_t data;
   4.219 -    uint64_t addr;
   4.220 -
   4.221 -    data = get_msi_gdata(d);
   4.222 -    addr = get_msi_gaddr(d);
   4.223 -
   4.224 -    PT_LOG("old_data %x old_addr %lx data %x addr %lx\n",
   4.225 -            old_data, old_addr, data, addr);
   4.226 -
   4.227 -    if ( data != old_data || addr != old_addr )
   4.228 -        if ( get_msi_gctrl(d) & PCI_MSI_FLAGS_ENABLE )
   4.229 -            pt_msi_update(d);
   4.230 -
   4.231 -    return 0;
   4.232 -}
   4.233 -
   4.234 -static int pt_msi_mask_update(struct pt_dev *d, uint32_t old_mask)
   4.235 -{
   4.236 -    struct pci_dev *pd = d->pci_dev;
   4.237 -    uint32_t mask;
   4.238 -    int offset;
   4.239 -
   4.240 -    if ( !(d->msi->flags & PCI_MSI_FLAGS_PVMASK) )
   4.241 -        return -1;
   4.242 -
   4.243 -    mask = get_msi_gmask(d);
   4.244 -
   4.245 -    if ( d->msi->flags & PCI_MSI_FLAGS_64BIT )
   4.246 -        offset = d->msi->offset + 0xc;
   4.247 -    else
   4.248 -        offset = d->msi->offset + 0x10;
   4.249 -
   4.250 -    if ( old_mask != mask )
   4.251 -        pci_write_long(pd, offset, mask);
   4.252 -
   4.253 -    return 0;
   4.254 -}
   4.255 -
   4.256 -#define ACCESSED_DATA 0x2
   4.257 -#define ACCESSED_MASK 0x4
   4.258 -#define ACCESSED_ADDR 0x8
   4.259 -#define ACCESSED_CTRL 0x10
   4.260 -
   4.261 -int pt_msi_write(struct pt_dev *d, uint32_t addr, uint32_t val, uint32_t len)
   4.262 +int pt_msi_update(struct pt_dev *d)
   4.263  {
   4.264 -    struct pci_dev *pd;
   4.265 -    int i, cur = addr;
   4.266 -    uint8_t value, flags = 0;
   4.267 -    uint16_t old_ctrl = 0, old_data = 0;
   4.268 -    uint32_t old_mask = 0;
   4.269 -    uint64_t old_addr = 0;
   4.270 -    PCIDevice *dev = (PCIDevice *)d;
   4.271 -    int can_write = 1;
   4.272 -
   4.273 -    if ( !d || !d->msi )
   4.274 -        return 0;
   4.275 -
   4.276 -    if ( (addr >= (d->msi->offset + d->msi->size) ) ||
   4.277 -         (addr + len) < d->msi->offset)
   4.278 -        return 0;
   4.279 -
   4.280 -    PT_LOG("addr %x val %x len %x offset %x size %x\n",
   4.281 -            addr, val, len, d->msi->offset, d->msi->size);
   4.282 -
   4.283 -    pd = d->pci_dev;
   4.284 -    old_ctrl = get_msi_gctrl(d);
   4.285 -    old_addr = get_msi_gaddr(d);
   4.286 -    old_data = get_msi_gdata(d);
   4.287 -
   4.288 -    if ( d->msi->flags & PCI_MSI_FLAGS_PVMASK )
   4.289 -        old_mask = get_msi_gmask(d);
   4.290 -
   4.291 -    for ( i = 0; i < len; i++, cur++ )
   4.292 -    {
   4.293 -        int off;
   4.294 -        uint8_t orig_value;
   4.295 -
   4.296 -        if ( cur < d->msi->offset )
   4.297 -            continue;
   4.298 -        else if ( cur >= (d->msi->offset + d->msi->size) )
   4.299 -            break;
   4.300 -
   4.301 -        off = cur - d->msi->offset;
   4.302 -        value = (val >> (i * 8)) & 0xff;
   4.303 -
   4.304 -        switch ( off )
   4.305 -        {
   4.306 -            case 0x0 ... 0x1:
   4.307 -                can_write = 0;
   4.308 -                break;
   4.309 -            case 0x2:
   4.310 -            case 0x3:
   4.311 -                flags |= ACCESSED_CTRL;
   4.312 -
   4.313 -                orig_value = pci_read_byte(pd, d->msi->offset + off);
   4.314 -
   4.315 -                orig_value &= (off == 2) ? PT_MSI_CTRL_WR_MASK_LO:
   4.316 -                                      PT_MSI_CTRL_WR_MASK_HI;
   4.317 -
   4.318 -                orig_value |= value & ( (off == 2) ? ~PT_MSI_CTRL_WR_MASK_LO:
   4.319 -                                              ~PT_MSI_CTRL_WR_MASK_HI);
   4.320 -                value = orig_value;
   4.321 -                break;
   4.322 -            case 0x4 ... 0x7:
   4.323 -                flags |= ACCESSED_ADDR;
   4.324 -                /* bit 4 ~ 11 is reserved for MSI in x86 */
   4.325 -                if ( off == 0x4 )
   4.326 -                    value &= 0x0f;
   4.327 -                if ( off == 0x5 )
   4.328 -                    value &= 0xf0;
   4.329 -                break;
   4.330 -            case 0x8 ... 0xb:
   4.331 -                if ( d->msi->flags & PCI_MSI_FLAGS_64BIT )
   4.332 -                {
   4.333 -                    /* Up 32bit is reserved in x86 */
   4.334 -                    flags |= ACCESSED_ADDR;
   4.335 -                    if ( value )
   4.336 -                        PT_LOG("Write up32 addr with %x \n", value);
   4.337 -                }
   4.338 -                else
   4.339 -                {
   4.340 -                    if ( off == 0xa || off == 0xb )
   4.341 -                        can_write = 0;
   4.342 -                    else
   4.343 -                        flags |= ACCESSED_DATA;
   4.344 -                    if ( off == 0x9 )
   4.345 -                        value &= ~PT_MSI_DATA_WR_MASK;
   4.346 -                }
   4.347 -                break;
   4.348 -            case 0xc ... 0xf:
   4.349 -                if ( d->msi->flags & PCI_MSI_FLAGS_64BIT )
   4.350 -                {
   4.351 -                    if ( off == 0xe || off == 0xf )
   4.352 -                        can_write = 0;
   4.353 -                    else
   4.354 -                    {
   4.355 -                        flags |= ACCESSED_DATA;
   4.356 -                        if (off == 0xd)
   4.357 -                            value &= ~PT_MSI_DATA_WR_MASK;
   4.358 -                    }
   4.359 -                }
   4.360 -                else
   4.361 -                {
   4.362 -                    if ( d->msi->flags & PCI_MSI_FLAGS_PVMASK )
   4.363 -                        flags |= ACCESSED_MASK;
   4.364 -                    else
   4.365 -                        PT_LOG("why comes to MASK without mask support??\n");
   4.366 -                }
   4.367 -                break;
   4.368 -            case 0x10 ... 0x13:
   4.369 -                if ( d->msi->flags & PCI_MSI_FLAGS_64BIT )
   4.370 -                {
   4.371 -                    if ( d->msi->flags & PCI_MSI_FLAGS_PVMASK )
   4.372 -                        flags |= ACCESSED_MASK;
   4.373 -                    else
   4.374 -                        PT_LOG("why comes to MASK without mask support??\n");
   4.375 -                }
   4.376 -                else
   4.377 -                    can_write = 0;
   4.378 -                break;
   4.379 -            case 0x14 ... 0x18:
   4.380 -                can_write = 0;
   4.381 -                break;
   4.382 -            default:
   4.383 -                PT_LOG("Non MSI register!!!\n");
   4.384 -                break;
   4.385 -        }
   4.386 -
   4.387 -        if ( can_write )
   4.388 -            dev->config[cur] = value;
   4.389 -    }
   4.390 -
   4.391 -    if ( flags & ACCESSED_DATA || flags & ACCESSED_ADDR )
   4.392 -        pt_msi_map_update(d, old_data, old_addr);
   4.393 -
   4.394 -    if ( flags & ACCESSED_MASK )
   4.395 -        pt_msi_mask_update(d, old_mask);
   4.396 -
   4.397 -    /* This will enable physical one, do it in last step */
   4.398 -    if ( flags & ACCESSED_CTRL )
   4.399 -        pt_msi_control_update(d, old_ctrl);
   4.400 -
   4.401 -    return 1;
   4.402 -}
   4.403 -
   4.404 -int pt_msi_read(struct pt_dev *d, int addr, int len, uint32_t *val)
   4.405 -{
   4.406 -    int e_addr = addr, e_len = len, offset = 0, i;
   4.407 -    uint8_t e_val = 0;
   4.408 -    PCIDevice *pd = (PCIDevice *)d;
   4.409 -
   4.410 -    if ( !d || !d->msi )
   4.411 -        return 0;
   4.412 -
   4.413 -    if ( (addr > (d->msi->offset + d->msi->size) ) ||
   4.414 -         (addr + len) <= d->msi->offset )
   4.415 -        return 0;
   4.416 -
   4.417 -    PT_LOG("pt_msi_read addr %x len %x val %x offset %x size %x\n",
   4.418 -            addr, len, *val, d->msi->offset, d->msi->size);
   4.419 -
   4.420 -    if ( (addr + len ) > (d->msi->offset + d->msi->size) )
   4.421 -        e_len -= addr + len - d->msi->offset - d->msi->size;
   4.422 -
   4.423 -    if ( addr < d->msi->offset )
   4.424 -    {
   4.425 -        e_addr = d->msi->offset;
   4.426 -        offset = d->msi->offset - addr;
   4.427 -        e_len -= offset;
   4.428 -    }
   4.429 -
   4.430 -    for ( i = 0; i < e_len; i++ )
   4.431 -    {
   4.432 -        e_val = *(uint8_t *)(&pd->config[e_addr] + i);
   4.433 -        *val &= ~(0xff << ( (offset + i) * 8));
   4.434 -        *val |= (e_val << ( (offset + i) * 8));
   4.435 -    }
   4.436 -
   4.437 -    return e_len;
   4.438 +    uint8_t gvec = 0;
   4.439 +    uint32_t gflags = 0;
   4.440 +    uint64_t addr = 0;
   4.441 +    
   4.442 +    /* get vector, address, flags info, etc. */
   4.443 +    gvec = d->msi->data & 0xFF;
   4.444 +    addr = (uint64_t)d->msi->addr_hi << 32 | d->msi->addr_lo;
   4.445 +    gflags = __get_msi_gflags(d->msi->data, addr);
   4.446 +    
   4.447 +    PT_LOG("now update msi with pirq %x gvec %x\n", d->msi->pirq, gvec);
   4.448 +    return xc_domain_update_msi_irq(xc_handle, domid, gvec,
   4.449 +                                     d->msi->pirq, gflags);
   4.450  }
   4.451  
   4.452  /* MSI-X virtulization functions */
   4.453 -#define PT_MSIX_CTRL_WR_MASK_HI      (0xC0)
   4.454  static void mask_physical_msix_entry(struct pt_dev *dev, int entry_nr, int mask)
   4.455  {
   4.456      void *phys_off;
   4.457 @@ -538,7 +147,7 @@ static int pt_msix_update_one(struct pt_
   4.458      return 0;
   4.459  }
   4.460  
   4.461 -static int pt_msix_update(struct pt_dev *dev)
   4.462 +int pt_msix_update(struct pt_dev *dev)
   4.463  {
   4.464      struct pt_msix_info *msix = dev->msix;
   4.465      int i;
   4.466 @@ -671,7 +280,7 @@ int remove_msix_mapping(struct pt_dev *d
   4.467  int pt_msix_init(struct pt_dev *dev, int pos)
   4.468  {
   4.469      uint8_t id;
   4.470 -    uint16_t flags, control;
   4.471 +    uint16_t control;
   4.472      int i, total_entries, table_off, bar_index;
   4.473      uint64_t bar_base;
   4.474      struct pci_dev *pd = dev->pci_dev;
   4.475 @@ -698,22 +307,12 @@ int pt_msix_init(struct pt_dev *dev, int
   4.476      memset(dev->msix, 0, sizeof(struct pt_msix_info)
   4.477                           + total_entries*sizeof(struct msix_entry_info));
   4.478      dev->msix->total_entries = total_entries;
   4.479 -    dev->msix->offset = pos;
   4.480      for ( i = 0; i < total_entries; i++ )
   4.481          dev->msix->msix_entry[i].pirq = -1;
   4.482  
   4.483      dev->msix->mmio_index =
   4.484          cpu_register_io_memory(0, pci_msix_read, pci_msix_write, dev);
   4.485  
   4.486 -    flags = pci_read_word(pd, pos + PCI_MSI_FLAGS);
   4.487 -    if ( flags & PCI_MSIX_ENABLE )
   4.488 -    {
   4.489 -        PT_LOG("MSIX enabled already, disable first\n");
   4.490 -        pci_write_word(pd, pos + PCI_MSI_FLAGS, flags & ~PCI_MSIX_ENABLE);
   4.491 -        *(uint16_t *)&dev->dev.config[pos + PCI_MSI_FLAGS]
   4.492 -            = flags & ~(PCI_MSIX_ENABLE | PCI_MSIX_MASK);
   4.493 -    }
   4.494 -
   4.495      table_off = pci_read_long(pd, pos + PCI_MSIX_TABLE);
   4.496      bar_index = dev->msix->bar_index = table_off & PCI_MSIX_BIR;
   4.497      table_off &= table_off & ~PCI_MSIX_BIR;
   4.498 @@ -733,131 +332,3 @@ int pt_msix_init(struct pt_dev *dev, int
   4.499             (unsigned long)dev->msix->phys_iomem_base);
   4.500      return 0;
   4.501  }
   4.502 -
   4.503 -static int pt_msix_enable(struct pt_dev *d, int enable)
   4.504 -{
   4.505 -    uint16_t ctrl;
   4.506 -    struct pci_dev *pd = d->pci_dev;
   4.507 -
   4.508 -    if ( !pd )
   4.509 -        return -1;
   4.510 -
   4.511 -    ctrl = pci_read_word(pd, d->msix->offset + PCI_MSI_FLAGS);
   4.512 -    if ( enable )
   4.513 -        ctrl |= PCI_MSIX_ENABLE;
   4.514 -    else
   4.515 -        ctrl &= ~PCI_MSIX_ENABLE;
   4.516 -    pci_write_word(pd, d->msix->offset + PCI_MSI_FLAGS, ctrl);
   4.517 -    d->msix->enabled = !!enable;
   4.518 -
   4.519 -    return 0;
   4.520 -}
   4.521 -
   4.522 -static int pt_msix_func_mask(struct pt_dev *d, int mask)
   4.523 -{
   4.524 -    uint16_t ctrl;
   4.525 -    struct pci_dev *pd = d->pci_dev;
   4.526 -
   4.527 -    if ( !pd )
   4.528 -        return -1;
   4.529 -
   4.530 -    ctrl = pci_read_word(pd, d->msix->offset + PCI_MSI_FLAGS);
   4.531 -
   4.532 -    if ( mask )
   4.533 -        ctrl |= PCI_MSIX_MASK;
   4.534 -    else
   4.535 -        ctrl &= ~PCI_MSIX_MASK;
   4.536 -
   4.537 -    pci_write_word(pd, d->msix->offset + PCI_MSI_FLAGS, ctrl);
   4.538 -    return 0;
   4.539 -}
   4.540 -
   4.541 -static int pt_msix_control_update(struct pt_dev *d)
   4.542 -{
   4.543 -    PCIDevice *pd = (PCIDevice *)d;
   4.544 -    uint16_t ctrl = *(uint16_t *)(&pd->config[d->msix->offset + 2]);
   4.545 -
   4.546 -    if ( ctrl & PCI_MSIX_ENABLE && !(ctrl & PCI_MSIX_MASK ) )
   4.547 -        pt_msix_update(d);
   4.548 -
   4.549 -    pt_msix_func_mask(d, ctrl & PCI_MSIX_MASK);
   4.550 -    pt_msix_enable(d, ctrl & PCI_MSIX_ENABLE);
   4.551 -
   4.552 -    return 0;
   4.553 -}
   4.554 -
   4.555 -int pt_msix_write(struct pt_dev *d, uint32_t addr, uint32_t val, uint32_t len)
   4.556 -{
   4.557 -    struct pci_dev *pd;
   4.558 -    int i, cur = addr;
   4.559 -    uint8_t value;
   4.560 -    PCIDevice *dev = (PCIDevice *)d;
   4.561 -
   4.562 -    if ( !d || !d->msix )
   4.563 -        return 0;
   4.564 -
   4.565 -    if ( (addr >= (d->msix->offset + 4) ) ||
   4.566 -         (addr + len) < d->msix->offset)
   4.567 -        return 0;
   4.568 -
   4.569 -    PT_LOG("addr %x val %x len %x offset %x\n",
   4.570 -            addr, val, len, d->msix->offset);
   4.571 -
   4.572 -    pd = d->pci_dev;
   4.573 -
   4.574 -    for ( i = 0; i < len; i++, cur++ )
   4.575 -    {
   4.576 -        uint8_t orig_value;
   4.577 -
   4.578 -        if ( cur != d->msix->offset + 3 )
   4.579 -            continue;
   4.580 -
   4.581 -        value = (val >> (i * 8)) & 0xff;
   4.582 -
   4.583 -        orig_value = pci_read_byte(pd, cur);
   4.584 -        value = (orig_value & ~PT_MSIX_CTRL_WR_MASK_HI) |
   4.585 -                (value & PT_MSIX_CTRL_WR_MASK_HI);
   4.586 -        dev->config[cur] = value;
   4.587 -        pt_msix_control_update(d);
   4.588 -        return 1;
   4.589 -    }
   4.590 -
   4.591 -    return 0;
   4.592 -}
   4.593 -
   4.594 -int pt_msix_read(struct pt_dev *d, int addr, int len, uint32_t *val)
   4.595 -{
   4.596 -    int e_addr = addr, e_len = len, offset = 0, i;
   4.597 -    uint8_t e_val = 0;
   4.598 -    PCIDevice *pd = (PCIDevice *)d;
   4.599 -
   4.600 -    if ( !d || !d->msix )
   4.601 -        return 0;
   4.602 -
   4.603 -    if ( (addr > (d->msix->offset + 3) ) ||
   4.604 -         (addr + len) <= d->msix->offset )
   4.605 -        return 0;
   4.606 -
   4.607 -    if ( (addr + len ) > (d->msix->offset + 3) )
   4.608 -        e_len -= addr + len - d->msix->offset - 3;
   4.609 -
   4.610 -    if ( addr < d->msix->offset )
   4.611 -    {
   4.612 -        e_addr = d->msix->offset;
   4.613 -        offset = d->msix->offset - addr;
   4.614 -        e_len -= offset;
   4.615 -    }
   4.616 -
   4.617 -    for ( i = 0; i < e_len; i++ )
   4.618 -    {
   4.619 -        e_val = *(uint8_t *)(&pd->config[e_addr] + i);
   4.620 -        *val &= ~(0xff << ( (offset + i) * 8));
   4.621 -        *val |= (e_val << ( (offset + i) * 8));
   4.622 -    }
   4.623 -
   4.624 -    PT_LOG("addr %x len %x val %x offset %x\n",
   4.625 -            addr, len, *val, d->msix->offset);
   4.626 -
   4.627 -    return e_len;
   4.628 -}
   4.629 -
     5.1 --- a/tools/ioemu/hw/pt-msi.h	Fri Jul 04 11:51:59 2008 +0100
     5.2 +++ b/tools/ioemu/hw/pt-msi.h	Fri Jul 04 11:54:21 2008 +0100
     5.3 @@ -64,8 +64,6 @@
     5.4  #define     MSI_ADDR_REDIRECTION_CPU   (0 << MSI_ADDR_REDIRECTION_SHIFT)
     5.5  #define     MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
     5.6  
     5.7 -#define PCI_MSI_FLAGS_PVMASK           0x100
     5.8 -
     5.9  #define AUTO_ASSIGN -1
    5.10  
    5.11  /* shift count for gflags */
    5.12 @@ -76,13 +74,16 @@
    5.13  #define GLFAGS_SHIFT_TRG_MODE       15
    5.14  
    5.15  int
    5.16 -pt_msi_init(struct pt_dev *dev, int pos);
    5.17 +pt_msi_setup(struct pt_dev *dev);
    5.18 +
    5.19 +uint32_t
    5.20 +__get_msi_gflags(uint32_t data, uint64_t addr);
    5.21  
    5.22  int
    5.23 -pt_msi_write(struct pt_dev *d, uint32_t addr, uint32_t val, uint32_t len);
    5.24 +pt_msi_update(struct pt_dev *d);
    5.25  
    5.26  int
    5.27 -pt_msi_read(struct pt_dev *d, int addr, int len, uint32_t *val);
    5.28 +pt_msix_update(struct pt_dev *dev);
    5.29  
    5.30  int
    5.31  remove_msix_mapping(struct pt_dev *dev, int bar_index);
    5.32 @@ -93,10 +94,4 @@ add_msix_mapping(struct pt_dev *dev, int
    5.33  int
    5.34  pt_msix_init(struct pt_dev *dev, int pos);
    5.35  
    5.36 -int
    5.37 -pt_msix_write(struct pt_dev *d, uint32_t addr, uint32_t val, uint32_t len);
    5.38 -
    5.39 -int
    5.40 -pt_msix_read(struct pt_dev *d, int addr, int len, uint32_t *val);
    5.41 -
    5.42  #endif
     6.1 --- a/tools/ioemu/vl.h	Fri Jul 04 11:51:59 2008 +0100
     6.2 +++ b/tools/ioemu/vl.h	Fri Jul 04 11:54:21 2008 +0100
     6.3 @@ -832,6 +832,8 @@ void pci_register_io_region(PCIDevice *p
     6.4                              uint32_t size, int type, 
     6.5                              PCIMapIORegionFunc *map_func);
     6.6  
     6.7 +int pt_chk_bar_overlap(PCIBus *bus, int devfn, uint32_t addr, uint32_t size);
     6.8 +
     6.9  void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level);
    6.10  
    6.11  uint32_t pci_default_read_config(PCIDevice *d,