ia64/xen-unstable

changeset 16216:9adec82f7bfe

[IA64] Simplify emulate_io_inst

Simplify emulate_io_inst: no more per insn memory access.
So a breakpoint/debug event can be put at a single place.

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author Alex Williamson <alex.williamson@hp.com>
date Tue Oct 30 11:21:23 2007 -0600 (2007-10-30)
parents 9e0fe6aaac49
children c17bfb091790
files xen/arch/ia64/vmx/mmio.c
line diff
     1.1 --- a/xen/arch/ia64/vmx/mmio.c	Tue Oct 30 11:17:28 2007 -0600
     1.2 +++ b/xen/arch/ia64/vmx/mmio.c	Tue Oct 30 11:21:23 2007 -0600
     1.3 @@ -309,18 +309,15 @@ static void mmio_access(VCPU *vcpu, u64 
     1.4  
     1.5  /*
     1.6     dir 1: read 0:write
     1.7 -    inst_type 0:integer 1:floating point
     1.8   */
     1.9 -#define SL_INTEGER  0        // store/load interger
    1.10 -#define SL_FLOATING    1       // store/load floating
    1.11 -
    1.12  void emulate_io_inst(VCPU *vcpu, u64 padr, u64 ma)
    1.13  {
    1.14      REGS *regs;
    1.15      IA64_BUNDLE bundle;
    1.16 -    int slot, dir=0, inst_type;
    1.17 +    int slot, dir=0;
    1.18 +    enum { SL_INTEGER, SL_FLOATING, SL_FLOATING_FP8 } inst_type;
    1.19      size_t size;
    1.20 -    u64 data, slot1a, slot1b, temp, update_reg;
    1.21 +    u64 data, data1, temp, update_reg;
    1.22      s32 imm;
    1.23      INST64 inst;
    1.24  
    1.25 @@ -332,10 +329,9 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
    1.26      slot = ((struct ia64_psr *)&(regs->cr_ipsr))->ri;
    1.27      if (!slot)
    1.28          inst.inst = bundle.slot0;
    1.29 -    else if (slot == 1){
    1.30 -        slot1a = bundle.slot1a;
    1.31 -        slot1b = bundle.slot1b;
    1.32 -        inst.inst = slot1a + (slot1b << 18);
    1.33 +    else if (slot == 1) {
    1.34 +        u64 slot1b = bundle.slot1b;
    1.35 +        inst.inst = bundle.slot1a + (slot1b << 18);
    1.36      }
    1.37      else if (slot == 2)
    1.38          inst.inst = bundle.slot2;
    1.39 @@ -343,19 +339,19 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
    1.40  
    1.41      // Integer Load/Store
    1.42      if (inst.M1.major == 4 && inst.M1.m == 0 && inst.M1.x == 0) {
    1.43 -        inst_type = SL_INTEGER;  //
    1.44 +        inst_type = SL_INTEGER;
    1.45          size = (inst.M1.x6 & 0x3);
    1.46          if ((inst.M1.x6 >> 2) > 0xb) {
    1.47 -            dir = IOREQ_WRITE;     // write
    1.48 +            dir = IOREQ_WRITE;
    1.49              vcpu_get_gr_nat(vcpu, inst.M4.r2, &data);
    1.50 -        } else if ((inst.M1.x6 >> 2) < 0xb) {   // read
    1.51 +        } else if ((inst.M1.x6 >> 2) < 0xb) {
    1.52              dir = IOREQ_READ;
    1.53          }
    1.54      }
    1.55      // Integer Load + Reg update
    1.56      else if (inst.M2.major == 4 && inst.M2.m == 1 && inst.M2.x == 0) {
    1.57          inst_type = SL_INTEGER;
    1.58 -        dir = IOREQ_READ;     //write
    1.59 +        dir = IOREQ_READ;
    1.60          size = (inst.M2.x6 & 0x3);
    1.61          vcpu_get_gr_nat(vcpu, inst.M2.r3, &temp);
    1.62          vcpu_get_gr_nat(vcpu, inst.M2.r2, &update_reg);
    1.63 @@ -364,21 +360,19 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
    1.64      }
    1.65      // Integer Load/Store + Imm update
    1.66      else if (inst.M3.major == 5) {
    1.67 -        inst_type = SL_INTEGER;  //
    1.68 +        inst_type = SL_INTEGER;
    1.69          size = (inst.M3.x6 & 0x3);
    1.70 -        if ((inst.M5.x6 >> 2) > 0xb) {      // write
    1.71 -            dir = IOREQ_WRITE;     // write
    1.72 +        if ((inst.M5.x6 >> 2) > 0xb) {
    1.73 +            dir = IOREQ_WRITE;
    1.74              vcpu_get_gr_nat(vcpu, inst.M5.r2, &data);
    1.75              vcpu_get_gr_nat(vcpu, inst.M5.r3, &temp);
    1.76 -            imm =
    1.77 -                (inst.M5.s << 31) | (inst.M5.i << 30) | (inst.M5.imm7 << 23);
    1.78 +            imm = (inst.M5.s << 31) | (inst.M5.i << 30) | (inst.M5.imm7 << 23);
    1.79              temp += imm >> 23;
    1.80              vcpu_set_gr(vcpu, inst.M5.r3, temp, 0);
    1.81 -        } else if ((inst.M3.x6 >> 2) < 0xb) {   // read
    1.82 +        } else if ((inst.M3.x6 >> 2) < 0xb) {
    1.83              dir = IOREQ_READ;
    1.84              vcpu_get_gr_nat(vcpu, inst.M3.r3, &temp);
    1.85 -            imm =
    1.86 -                (inst.M3.s << 31) | (inst.M3.i << 30) | (inst.M3.imm7 << 23);
    1.87 +            imm = (inst.M3.s << 31) | (inst.M3.i << 30) | (inst.M3.imm7 << 23);
    1.88              temp += imm >> 23;
    1.89              vcpu_set_gr(vcpu, inst.M3.r3, temp, 0);
    1.90          }
    1.91 @@ -391,12 +385,9 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
    1.92          inst_type = SL_FLOATING;
    1.93          dir = IOREQ_WRITE;
    1.94          vcpu_get_fpreg(vcpu, inst.M9.f2, &v);
    1.95 -        /* Write high word.
    1.96 -           FIXME: this is a kludge!  */
    1.97 -        v.u.bits[1] &= 0x3ffff;
    1.98 -        mmio_access(vcpu, padr + 8, &v.u.bits[1], 8, ma, IOREQ_WRITE);
    1.99 +        data1 = v.u.bits[1] & 0x3ffff;
   1.100          data = v.u.bits[0];
   1.101 -        size = 3;
   1.102 +        size = 4;
   1.103      }
   1.104      // Floating-point spill + Imm update
   1.105      else if (inst.M10.major == 7 && inst.M10.x6 == 0x3B) {
   1.106 @@ -406,17 +397,12 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
   1.107          dir = IOREQ_WRITE;
   1.108          vcpu_get_fpreg(vcpu, inst.M10.f2, &v);
   1.109          vcpu_get_gr_nat(vcpu, inst.M10.r3, &temp);
   1.110 -        imm =
   1.111 -            (inst.M10.s << 31) | (inst.M10.i << 30) | (inst.M10.imm7 << 23);
   1.112 +        imm = (inst.M10.s << 31) | (inst.M10.i << 30) | (inst.M10.imm7 << 23);
   1.113          temp += imm >> 23;
   1.114          vcpu_set_gr(vcpu, inst.M10.r3, temp, 0);
   1.115 -
   1.116 -        /* Write high word.
   1.117 -           FIXME: this is a kludge!  */
   1.118 -        v.u.bits[1] &= 0x3ffff;
   1.119 -        mmio_access(vcpu, padr + 8, &v.u.bits[1], 8, ma, IOREQ_WRITE);
   1.120 +        data1 = v.u.bits[1] & 0x3ffff;
   1.121          data = v.u.bits[0];
   1.122 -        size = 3;
   1.123 +        size = 4;
   1.124      }
   1.125      // Floating-point stf8 + Imm update
   1.126      else if (inst.M10.major == 7 && inst.M10.x6 == 0x31) {
   1.127 @@ -428,21 +414,14 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
   1.128          vcpu_get_fpreg(vcpu, inst.M10.f2, &v);
   1.129          data = v.u.bits[0]; /* Significand.  */
   1.130          vcpu_get_gr_nat(vcpu, inst.M10.r3, &temp);
   1.131 -        imm =
   1.132 -            (inst.M10.s << 31) | (inst.M10.i << 30) | (inst.M10.imm7 << 23);
   1.133 +        imm = (inst.M10.s << 31) | (inst.M10.i << 30) | (inst.M10.imm7 << 23);
   1.134          temp += imm >> 23;
   1.135          vcpu_set_gr(vcpu, inst.M10.r3, temp, 0);
   1.136      }
   1.137 -//    else if(inst.M6.major==6&&inst.M6.m==0&&inst.M6.x==0&&inst.M6.x6==3){
   1.138 -//        inst_type=SL_FLOATING;  //fp
   1.139 -//        dir=IOREQ_READ;
   1.140 -//        size=3;     //ldfd
   1.141 -//    }
   1.142      //  lfetch - do not perform accesses.
   1.143      else if (inst.M15.major== 7 && inst.M15.x6 >=0x2c && inst.M15.x6 <= 0x2f) {
   1.144          vcpu_get_gr_nat(vcpu, inst.M15.r3, &temp);
   1.145 -        imm =
   1.146 -            (inst.M15.s << 31) | (inst.M15.i << 30) | (inst.M15.imm7 << 23);
   1.147 +        imm = (inst.M15.s << 31) | (inst.M15.i << 30) | (inst.M15.imm7 << 23);
   1.148          temp += imm >> 23;
   1.149          vcpu_set_gr(vcpu, inst.M15.r3, temp, 0);
   1.150  
   1.151 @@ -452,24 +431,10 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
   1.152      // Floating-point Load Pair + Imm ldfp8 M12
   1.153      else if (inst.M12.major == 6 && inst.M12.m == 1
   1.154               && inst.M12.x == 1 && inst.M12.x6 == 1) {
   1.155 -        struct ia64_fpreg v;
   1.156 -
   1.157 -        inst_type = SL_FLOATING;
   1.158 +        inst_type = SL_FLOATING_FP8;
   1.159          dir = IOREQ_READ;
   1.160 -        size = 8;     //ldfd
   1.161 -        mmio_access(vcpu, padr, &data, size, ma, dir);
   1.162 -        v.u.bits[0] = data;
   1.163 -        v.u.bits[1] = 0x1003E;
   1.164 -        vcpu_set_fpreg(vcpu, inst.M12.f1, &v);
   1.165 -        padr += 8;
   1.166 -        mmio_access(vcpu, padr, &data, size, ma, dir);
   1.167 -        v.u.bits[0] = data;
   1.168 -        v.u.bits[1] = 0x1003E;
   1.169 -        vcpu_set_fpreg(vcpu, inst.M12.f2, &v);
   1.170 -        padr += 8;
   1.171 -        vcpu_set_gr(vcpu,inst.M12.r3,padr, 0);
   1.172 -        vcpu_increment_iip(vcpu);
   1.173 -        return;
   1.174 +        size = 4;     //ldfd
   1.175 +        vcpu_set_gr(vcpu,inst.M12.r3,padr + 16, 0);
   1.176      }
   1.177      else {
   1.178          panic_domain
   1.179 @@ -477,11 +442,24 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
   1.180               inst.inst, regs->cr_iip);
   1.181      }
   1.182  
   1.183 -    size = 1 << size;
   1.184 -    mmio_access(vcpu, padr, &data, size, ma, dir);
   1.185 +    if (size == 4) {
   1.186 +        mmio_access(vcpu, padr + 8, &data1, 1 << 3, ma, dir);
   1.187 +        size = 3;
   1.188 +    }
   1.189 +    mmio_access(vcpu, padr, &data, 1 << size, ma, dir);
   1.190 +
   1.191      if (dir == IOREQ_READ) {
   1.192          if (inst_type == SL_INTEGER) {
   1.193              vcpu_set_gr(vcpu, inst.M1.r1, data, 0);
   1.194 +        } else if (inst_type == SL_FLOATING_FP8) {
   1.195 +            struct ia64_fpreg v;
   1.196 +
   1.197 +            v.u.bits[0] = data;
   1.198 +            v.u.bits[1] = 0x1003E;
   1.199 +            vcpu_set_fpreg(vcpu, inst.M12.f1, &v);
   1.200 +            v.u.bits[0] = data1;
   1.201 +            v.u.bits[1] = 0x1003E;
   1.202 +            vcpu_set_fpreg(vcpu, inst.M12.f2, &v);
   1.203          } else {
   1.204              panic_domain(NULL, "Don't support ldfd now !");
   1.205          }