1.1 --- a/tools/ioemu/hw/piix4acpi.c	Mon Nov 13 14:20:26 2006 +0000
     1.2 +++ b/tools/ioemu/hw/piix4acpi.c	Mon Nov 13 14:25:48 2006 +0000
     1.3 @@ -406,7 +406,7 @@ void pci_piix4_acpi_init(PCIBus *bus, in
     1.4       * TODO:  if Guest Firmware or Guest OS will change this PMBA,
     1.5       * More logic will be added.
     1.6       */
     1.7 -    pci_conf[0x40] = 0x41;
     1.8 +    pci_conf[0x40] = 0x41; /* Special device-specific BAR at 0x40 */
     1.9      pci_conf[0x41] = 0x1f;
    1.10      acpi_map(d, 0, 0x1f40, 0x10, PCI_ADDRESS_SPACE_IO);
    1.11      acpi_reset(d);

     2.1 --- a/tools/ioemu/hw/piix_pci.c	Mon Nov 13 14:20:26 2006 +0000
     2.2 +++ b/tools/ioemu/hw/piix_pci.c	Mon Nov 13 14:25:48 2006 +0000
     2.3 @@ -338,10 +338,14 @@ static void pci_bios_init_device(PCIDevi
     2.4          break;
     2.5      case 0x0680:
     2.6          if (vendor_id == 0x8086 && device_id == 0x7113) {
     2.7 -            /* PIIX4 ACPI PM */
     2.8 -            pci_config_writew(d, 0x20, 0x0000); /* NO smb bus IO enable in PIIX4 */
     2.9 +            /*
    2.10 +             * PIIX4 ACPI PM.
    2.11 +             * Special device with special PCI config space. No ordinary BARs.
    2.12 +             */
    2.13 +            pci_config_writew(d, 0x20, 0x0000); // No smb bus IO enable
    2.14              pci_config_writew(d, 0x22, 0x0000);
    2.15 -            goto default_map;
    2.16 +            pci_config_writew(d, 0x3c, 0x0009); // Hardcoded IRQ9
    2.17 +            pci_config_writew(d, 0x3d, 0x0001);
    2.18          }
    2.19          break;
    2.20      case 0x0300:
    2.21 @@ -394,14 +398,6 @@ static void pci_bios_init_device(PCIDevi
    2.22          pic_irq = pci_irqs[pin];
    2.23          pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
    2.24      }
    2.25 -
    2.26 -    if (class== 0x0680&& vendor_id == 0x8086 && device_id == 0x7113) {
    2.27 -         // PIIX4 ACPI PM
    2.28 -       pci_config_writew(d, 0x20, 0x0000); // NO smb bus IO enable in PIIX4
    2.29 -       pci_config_writew(d, 0x22, 0x0000);
    2.30 -       pci_config_writew(d, 0x3c, 0x0009); // Hardcodeed IRQ9
    2.31 -       pci_config_writew(d, 0x3d, 0x0001);
    2.32 -    }
    2.33  }
    2.34  
    2.35  /*