ia64/xen-unstable

changeset 18618:98d5370fec1a

xend: fixup the Secondary Bus Reset.

Use the read-modify-write operation.
Change the wrong 'I' to a correct 'H'.

Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Oct 13 10:08:36 2008 +0100 (2008-10-13)
parents 0d1875d2e5f2
children e4bddd01cb3e
files tools/python/xen/util/pci.py
line diff
     1.1 --- a/tools/python/xen/util/pci.py	Mon Oct 13 10:08:16 2008 +0100
     1.2 +++ b/tools/python/xen/util/pci.py	Mon Oct 13 10:08:36 2008 +0100
     1.3 @@ -476,15 +476,16 @@ class PciDevice:
     1.4          parent_path = sysfs_mnt + SYSFS_PCI_DEVS_PATH + '/' + \
     1.5              target_bus + SYSFS_PCI_DEV_CONFIG_PATH
     1.6          fd = os.open(parent_path, os.O_RDWR)
     1.7 -        # Save state of bridge control register - restore after reset
     1.8          os.lseek(fd, PCI_CB_BRIDGE_CONTROL, 0)
     1.9          br_cntl = (struct.unpack('H', os.read(fd, 2)))[0]
    1.10          # Assert Secondary Bus Reset
    1.11          os.lseek(fd, PCI_CB_BRIDGE_CONTROL, 0)
    1.12 -        os.write(fd, struct.pack('I', PCI_BRIDGE_CTL_BUS_RESET))
    1.13 +        br_cntl |= PCI_BRIDGE_CTL_BUS_RESET
    1.14 +        os.write(fd, struct.pack('H', br_cntl))
    1.15          time.sleep(0.200)
    1.16          # De-assert Secondary Bus Reset
    1.17          os.lseek(fd, PCI_CB_BRIDGE_CONTROL, 0)
    1.18 +        br_cntl &= ~PCI_BRIDGE_CTL_BUS_RESET
    1.19          os.write(fd, struct.pack('H', br_cntl))
    1.20          time.sleep(0.200)
    1.21          os.close(fd)