ia64/xen-unstable
changeset 9081:983311b895be
[IA64] VTI: Use 16K page size to emulate guest physical mode
Previously VMM use 4k to emulate guest physical mode on VTI-domain to
satisfy the requirement of speculation attribute in physical mode, please
refer to 4.4.6 Speculation Attributes of Itanium SDM 2
Seems like guest doesn't need to conform to this
Signed-off-by: Anthony Xu <anthony.xu@intel.com>
Previously VMM use 4k to emulate guest physical mode on VTI-domain to
satisfy the requirement of speculation attribute in physical mode, please
refer to 4.4.6 Speculation Attributes of Itanium SDM 2
Seems like guest doesn't need to conform to this
Signed-off-by: Anthony Xu <anthony.xu@intel.com>
| author | awilliam@xenbuild.aw |
|---|---|
| date | Fri Mar 03 13:03:39 2006 -0700 (2006-03-03) |
| parents | 333db05b8bbb |
| children | c870c7f66abc |
| files | xen/arch/ia64/vmx/vmx_phy_mode.c xen/arch/ia64/vmx/vmx_process.c xen/include/asm-ia64/vmx_phy_mode.h |
line diff
1.1 --- a/xen/arch/ia64/vmx/vmx_phy_mode.c Fri Mar 03 10:11:33 2006 -0700 1.2 +++ b/xen/arch/ia64/vmx/vmx_phy_mode.c Fri Mar 03 13:03:39 2006 -0700 1.3 @@ -104,57 +104,51 @@ physical_mode_init(VCPU *vcpu) 1.4 vcpu->arch.mode_flags = GUEST_IN_PHY; 1.5 } 1.6 1.7 -extern u64 get_mfn(struct domain *d, u64 gpfn); 1.8 extern void vmx_switch_rr7(unsigned long ,shared_info_t*,void *,void *,void *); 1.9 -void 1.10 -physical_itlb_miss_dom0(VCPU *vcpu, u64 vadr) 1.11 +/*void 1.12 +physical_itlb_miss(VCPU *vcpu, u64 vadr) 1.13 { 1.14 u64 psr; 1.15 IA64_PSR vpsr; 1.16 - u64 mppn,gppn; 1.17 + u64 xen_mppn,xen_gppn; 1.18 vpsr.val=vmx_vcpu_get_psr(vcpu); 1.19 - gppn=(vadr<<1)>>13; 1.20 - mppn = get_mfn(vcpu->domain,gppn); 1.21 - mppn=(mppn<<12)|(vpsr.cpl<<7); 1.22 -// if(vadr>>63) 1.23 -// mppn |= PHY_PAGE_UC; 1.24 -// else 1.25 - mppn |= PHY_PAGE_WB; 1.26 + xen_gppn=(vadr<<1)>>(PAGE_SHIFT+1); 1.27 + xen_mppn = gmfn_to_mfn(vcpu->domain, xen_gppn); 1.28 + xen_mppn=(xen_mppn<<PAGE_SHIFT)|(vpsr.cpl<<7); 1.29 + if(vadr>>63) 1.30 + xen_mppn |= PHY_PAGE_UC; 1.31 + else 1.32 + xen_mppn |= PHY_PAGE_WB; 1.33 1.34 psr=ia64_clear_ic(); 1.35 - ia64_itc(1,vadr&(~0xfff),mppn,EMUL_PHY_PAGE_SHIFT); 1.36 + ia64_itc(1,vadr&PAGE_MASK,xen_mppn,PAGE_SHIFT); 1.37 ia64_set_psr(psr); 1.38 ia64_srlz_i(); 1.39 return; 1.40 } 1.41 1.42 - 1.43 +*/ 1.44 +/* 1.45 + * vec=1, itlb miss 1.46 + * vec=2, dtlb miss 1.47 + */ 1.48 void 1.49 -physical_itlb_miss(VCPU *vcpu, u64 vadr) 1.50 -{ 1.51 - physical_itlb_miss_dom0(vcpu, vadr); 1.52 -} 1.53 - 1.54 - 1.55 -void 1.56 -physical_dtlb_miss(VCPU *vcpu, u64 vadr) 1.57 +physical_tlb_miss(VCPU *vcpu, u64 vadr, u64 vec) 1.58 { 1.59 u64 psr; 1.60 IA64_PSR vpsr; 1.61 - u64 mppn,gppn; 1.62 -// if(vcpu->domain!=dom0) 1.63 -// panic("dom n physical dtlb miss happen\n"); 1.64 + u64 xen_mppn,xen_gppn; 1.65 vpsr.val=vmx_vcpu_get_psr(vcpu); 1.66 - gppn=(vadr<<1)>>13; 1.67 - mppn = get_mfn(vcpu->domain, gppn); 1.68 - mppn=(mppn<<12)|(vpsr.cpl<<7); 1.69 + xen_gppn=(vadr<<1)>>(PAGE_SHIFT+1); 1.70 + xen_mppn = gmfn_to_mfn(vcpu->domain, xen_gppn); 1.71 + xen_mppn=(xen_mppn<<PAGE_SHIFT)|(vpsr.cpl<<7); 1.72 if(vadr>>63) 1.73 - mppn |= PHY_PAGE_UC; 1.74 + xen_mppn |= PHY_PAGE_UC; 1.75 else 1.76 - mppn |= PHY_PAGE_WB; 1.77 + xen_mppn |= PHY_PAGE_WB; 1.78 1.79 psr=ia64_clear_ic(); 1.80 - ia64_itc(2,vadr&(~0xfff),mppn,EMUL_PHY_PAGE_SHIFT); 1.81 + ia64_itc(vec,vadr&PAGE_MASK,xen_mppn,PAGE_SHIFT); 1.82 ia64_set_psr(psr); 1.83 ia64_srlz_i(); 1.84 return; 1.85 @@ -193,13 +187,13 @@ vmx_load_all_rr(VCPU *vcpu) 1.86 if (is_physical_mode(vcpu)) { 1.87 if (vcpu->arch.mode_flags & GUEST_PHY_EMUL) 1.88 panic("Unexpected domain switch in phy emul\n"); 1.89 - phy_rr.rrval = vcpu->domain->arch.metaphysical_rr0; 1.90 - phy_rr.ps = EMUL_PHY_PAGE_SHIFT; 1.91 + phy_rr.rrval = vcpu->arch.metaphysical_rr0; 1.92 + // phy_rr.ps = PAGE_SHIFT; 1.93 phy_rr.ve = 1; 1.94 1.95 ia64_set_rr((VRN0 << VRN_SHIFT), phy_rr.rrval); 1.96 - phy_rr.rrval = vcpu->domain->arch.metaphysical_rr4; 1.97 - phy_rr.ps = EMUL_PHY_PAGE_SHIFT; 1.98 + phy_rr.rrval = vcpu->arch.metaphysical_rr4; 1.99 +// phy_rr.ps = PAGE_SHIFT; 1.100 phy_rr.ve = 1; 1.101 1.102 ia64_set_rr((VRN4 << VRN_SHIFT), phy_rr.rrval); 1.103 @@ -242,12 +236,12 @@ switch_to_physical_rid(VCPU *vcpu) 1.104 /* Save original virtual mode rr[0] and rr[4] */ 1.105 psr=ia64_clear_ic(); 1.106 phy_rr.rrval = vcpu->domain->arch.metaphysical_rr0; 1.107 - phy_rr.ps = EMUL_PHY_PAGE_SHIFT; 1.108 +// phy_rr.ps = EMUL_PHY_PAGE_SHIFT; 1.109 phy_rr.ve = 1; 1.110 ia64_set_rr(VRN0<<VRN_SHIFT, phy_rr.rrval); 1.111 ia64_srlz_d(); 1.112 phy_rr.rrval = vcpu->domain->arch.metaphysical_rr4; 1.113 - phy_rr.ps = EMUL_PHY_PAGE_SHIFT; 1.114 +// phy_rr.ps = EMUL_PHY_PAGE_SHIFT; 1.115 phy_rr.ve = 1; 1.116 ia64_set_rr(VRN4<<VRN_SHIFT, phy_rr.rrval); 1.117 ia64_srlz_d();
2.1 --- a/xen/arch/ia64/vmx/vmx_process.c Fri Mar 03 10:11:33 2006 -0700 2.2 +++ b/xen/arch/ia64/vmx/vmx_process.c Fri Mar 03 13:03:39 2006 -0700 2.3 @@ -315,23 +315,20 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r 2.4 return; 2.5 } 2.6 */ 2.7 - if(vadr == 0x1ea18c00 ){ 2.8 +/* if(vadr == 0x1ea18c00 ){ 2.9 ia64_clear_ic(); 2.10 while(1); 2.11 } 2.12 + */ 2.13 if(is_physical_mode(v)&&(!(vadr<<1>>62))){ 2.14 - if(vec==1){ 2.15 - physical_itlb_miss(v, vadr); 2.16 - return IA64_FAULT; 2.17 - } 2.18 if(vec==2){ 2.19 if(v->domain!=dom0&&__gpfn_is_io(v->domain,(vadr<<1)>>(PAGE_SHIFT+1))){ 2.20 emulate_io_inst(v,((vadr<<1)>>1),4); // UC 2.21 - }else{ 2.22 - physical_dtlb_miss(v, vadr); 2.23 + return IA64_FAULT; 2.24 } 2.25 - return IA64_FAULT; 2.26 } 2.27 + physical_tlb_miss(v, vadr, vec); 2.28 + return IA64_FAULT; 2.29 } 2.30 vrr = vmx_vcpu_rr(v, vadr); 2.31 if(vec == 1) type = ISIDE_TLB;
3.1 --- a/xen/include/asm-ia64/vmx_phy_mode.h Fri Mar 03 10:11:33 2006 -0700 3.2 +++ b/xen/include/asm-ia64/vmx_phy_mode.h Fri Mar 03 13:03:39 2006 -0700 3.3 @@ -75,11 +75,11 @@ 3.4 #define PHY_PAGE_UC (_PAGE_A|_PAGE_D|_PAGE_P|_PAGE_MA_UC|_PAGE_AR_RWX) 3.5 #define PHY_PAGE_WB (_PAGE_A|_PAGE_D|_PAGE_P|_PAGE_MA_WB|_PAGE_AR_RWX) 3.6 3.7 -#ifdef PHY_16M /* 16M: large granule for test*/ 3.8 -#define EMUL_PHY_PAGE_SHIFT 24 3.9 -#else /* 4K: emulated physical page granule */ 3.10 -#define EMUL_PHY_PAGE_SHIFT 12 3.11 -#endif 3.12 +//#ifdef PHY_16M /* 16M: large granule for test*/ 3.13 +//#define EMUL_PHY_PAGE_SHIFT 24 3.14 +//#else /* 4K: emulated physical page granule */ 3.15 +//#define EMUL_PHY_PAGE_SHIFT 12 3.16 +//#endif 3.17 #define IA64_RSC_MODE 0x0000000000000003 3.18 #define XEN_RR7_RID (0xf00010) 3.19 #define GUEST_IN_PHY 0x1 3.20 @@ -96,8 +96,7 @@ extern void prepare_if_physical_mode(VCP 3.21 extern void recover_if_physical_mode(VCPU *vcpu); 3.22 extern void vmx_init_all_rr(VCPU *vcpu); 3.23 extern void vmx_load_all_rr(VCPU *vcpu); 3.24 -extern void physical_itlb_miss(VCPU *vcpu, u64 vadr); 3.25 -extern void physical_dtlb_miss(VCPU *vcpu, u64 vadr); 3.26 +extern void physical_tlb_miss(VCPU *vcpu, u64 vadr, u64 vec); 3.27 /* 3.28 * No sanity check here, since all psr changes have been 3.29 * checked in switch_mm_mode().