ia64/xen-unstable

changeset 11698:96a6649fa691

[HVM] Add RDMSR/WRMSR instruction emulation to VMXAssist decoder
AP of PAE SMP windows will use it to set NX bit in EFER.

Signed-off-by: Xin Li <xin.b.li@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Sat Sep 30 11:11:54 2006 +0100 (2006-09-30)
parents 2d155d41fe46
children 82983c636549
files tools/firmware/vmxassist/vm86.c
line diff
     1.1 --- a/tools/firmware/vmxassist/vm86.c	Sat Sep 30 11:08:41 2006 +0100
     1.2 +++ b/tools/firmware/vmxassist/vm86.c	Sat Sep 30 11:11:54 2006 +0100
     1.3 @@ -1230,6 +1230,18 @@ pushrm(struct regs *regs, int prefix, un
     1.4  
     1.5  enum { OPC_INVALID, OPC_EMULATED };
     1.6  
     1.7 +#define rdmsr(msr,val1,val2)				\
     1.8 +	__asm__ __volatile__(				\
     1.9 +		"rdmsr"					\
    1.10 +		: "=a" (val1), "=d" (val2)		\
    1.11 +		: "c" (msr))
    1.12 +
    1.13 +#define wrmsr(msr,val1,val2)				\
    1.14 +	__asm__ __volatile__(				\
    1.15 +		"wrmsr"					\
    1.16 +		: /* no outputs */			\
    1.17 +		: "c" (msr), "a" (val1), "d" (val2))
    1.18 +
    1.19  /*
    1.20   * Emulate a single instruction, including all its prefixes. We only implement
    1.21   * a small subset of the opcodes, and not all opcodes are implemented for each
    1.22 @@ -1288,6 +1300,12 @@ opcode(struct regs *regs)
    1.23  				if (!movcr(regs, prefix, opc))
    1.24  					goto invalid;
    1.25  				return OPC_EMULATED;
    1.26 +			case 0x30: /* WRMSR */
    1.27 +				wrmsr(regs->ecx, regs->eax, regs->edx);
    1.28 +				return OPC_EMULATED;
    1.29 +			case 0x32: /* RDMSR */
    1.30 +				rdmsr(regs->ecx, regs->eax, regs->edx);
    1.31 +				return OPC_EMULATED;
    1.32  			default:
    1.33  				goto invalid;
    1.34  			}