ia64/xen-unstable

changeset 15419:962f22223817

[IA64] Domain debugger for VTi: virtualize ibr and dbr.

Misc cleanup.

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author Alex Williamson <alex.williamson@hp.com>
date Mon Jul 02 10:10:32 2007 -0600 (2007-07-02)
parents c7e16caf4e63
children 9b9815e29638
files xen/arch/ia64/vmx/vmmu.c xen/arch/ia64/vmx/vmx_ivt.S xen/arch/ia64/vmx/vmx_process.c xen/arch/ia64/vmx/vmx_utility.c xen/arch/ia64/vmx/vmx_vcpu.c xen/arch/ia64/vmx/vmx_virt.c xen/arch/ia64/xen/vcpu.c xen/include/asm-ia64/linux-xen/asm/ptrace.h xen/include/asm-ia64/vmx.h xen/include/asm-ia64/vmx_vcpu.h
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmmu.c	Mon Jul 02 09:54:53 2007 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmmu.c	Mon Jul 02 10:10:32 2007 -0600
     1.3 @@ -540,8 +540,7 @@ IA64FAULT vmx_vcpu_ptc_e(VCPU *vcpu, u64
     1.4  
     1.5  IA64FAULT vmx_vcpu_ptc_g(VCPU *vcpu, u64 va, u64 ps)
     1.6  {
     1.7 -    vmx_vcpu_ptc_ga(vcpu, va, ps);
     1.8 -    return IA64_ILLOP_FAULT;
     1.9 +    return vmx_vcpu_ptc_ga(vcpu, va, ps);
    1.10  }
    1.11  /*
    1.12  IA64FAULT vmx_vcpu_ptc_ga(VCPU *vcpu, u64 va, u64 ps)
     2.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Mon Jul 02 09:54:53 2007 -0600
     2.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Mon Jul 02 10:10:32 2007 -0600
     2.3 @@ -1001,7 +1001,7 @@ END(vmx_speculation_vector)
     2.4  // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
     2.5  ENTRY(vmx_debug_vector)
     2.6      VMX_DBG_FAULT(29)
     2.7 -    VMX_FAULT(29)
     2.8 +    VMX_REFLECT(29)
     2.9  END(vmx_debug_vector)
    2.10  
    2.11      .org vmx_ia64_ivt+0x5a00
     3.1 --- a/xen/arch/ia64/vmx/vmx_process.c	Mon Jul 02 09:54:53 2007 -0600
     3.2 +++ b/xen/arch/ia64/vmx/vmx_process.c	Mon Jul 02 10:10:32 2007 -0600
     3.3 @@ -86,19 +86,20 @@ void vmx_reflect_interruption(u64 ifa, u
     3.4      u64 vpsr = VCPU(vcpu, vpsr);
     3.5      
     3.6      vector = vec2off[vec];
     3.7 -    if(!(vpsr&IA64_PSR_IC)&&(vector!=IA64_DATA_NESTED_TLB_VECTOR)){
     3.8 -        panic_domain(regs, "Guest nested fault vector=%lx!\n", vector);
     3.9 -    }
    3.10  
    3.11      switch (vec) {
    3.12 -
    3.13 +    case 5:  // IA64_DATA_NESTED_TLB_VECTOR
    3.14 +        break;
    3.15      case 22:	// IA64_INST_ACCESS_RIGHTS_VECTOR
    3.16 +        if (!(vpsr & IA64_PSR_IC))
    3.17 +            goto nested_fault;
    3.18          if (vhpt_access_rights_fixup(vcpu, ifa, 0))
    3.19              return;
    3.20          break;
    3.21  
    3.22      case 25:	// IA64_DISABLED_FPREG_VECTOR
    3.23 -
    3.24 +        if (!(vpsr & IA64_PSR_IC))
    3.25 +            goto nested_fault;
    3.26          if (FP_PSR(vcpu) & IA64_PSR_DFH) {
    3.27              FP_PSR(vcpu) = IA64_PSR_MFH;
    3.28              if (__ia64_per_cpu_var(fp_owner) != vcpu)
    3.29 @@ -110,8 +111,10 @@ void vmx_reflect_interruption(u64 ifa, u
    3.30          }
    3.31  
    3.32          break;       
    3.33 -        
    3.34 +
    3.35      case 32:	// IA64_FP_FAULT_VECTOR
    3.36 +        if (!(vpsr & IA64_PSR_IC))
    3.37 +            goto nested_fault;
    3.38          // handle fpswa emulation
    3.39          // fp fault
    3.40          status = handle_fpu_swa(1, regs, isr);
    3.41 @@ -123,6 +126,8 @@ void vmx_reflect_interruption(u64 ifa, u
    3.42          break;
    3.43  
    3.44      case 33:	// IA64_FP_TRAP_VECTOR
    3.45 +        if (!(vpsr & IA64_PSR_IC))
    3.46 +            goto nested_fault;
    3.47          //fp trap
    3.48          status = handle_fpu_swa(0, regs, isr);
    3.49          if (!status)
    3.50 @@ -132,7 +137,23 @@ void vmx_reflect_interruption(u64 ifa, u
    3.51              return;
    3.52          }
    3.53          break;
    3.54 -    
    3.55 +
    3.56 +    case 29: // IA64_DEBUG_VECTOR
    3.57 +    case 35: // IA64_TAKEN_BRANCH_TRAP_VECTOR
    3.58 +    case 36: // IA64_SINGLE_STEP_TRAP_VECTOR
    3.59 +        if (vmx_guest_kernel_mode(regs)
    3.60 +            && current->domain->debugger_attached) {
    3.61 +            domain_pause_for_debugger();
    3.62 +            return;
    3.63 +        }
    3.64 +        if (!(vpsr & IA64_PSR_IC))
    3.65 +            goto nested_fault;
    3.66 +        break;
    3.67 +
    3.68 +    default:
    3.69 +        if (!(vpsr & IA64_PSR_IC))
    3.70 +            goto nested_fault;
    3.71 +        break;
    3.72      } 
    3.73      VCPU(vcpu,isr)=isr;
    3.74      VCPU(vcpu,iipa) = regs->cr_iip;
    3.75 @@ -142,6 +163,10 @@ void vmx_reflect_interruption(u64 ifa, u
    3.76          set_ifa_itir_iha(vcpu,ifa,1,1,1);
    3.77      }
    3.78      inject_guest_interruption(vcpu, vector);
    3.79 +    return;
    3.80 +
    3.81 + nested_fault:
    3.82 +    panic_domain(regs, "Guest nested fault vector=%lx!\n", vector);
    3.83  }
    3.84  
    3.85  
     4.1 --- a/xen/arch/ia64/vmx/vmx_utility.c	Mon Jul 02 09:54:53 2007 -0600
     4.2 +++ b/xen/arch/ia64/vmx/vmx_utility.c	Mon Jul 02 10:10:32 2007 -0600
     4.3 @@ -26,7 +26,7 @@
     4.4  #include <asm/processor.h>
     4.5  #include <asm/vmx_mm_def.h>
     4.6  
     4.7 -
     4.8 +#ifdef CHECK_FAULT
     4.9  /*
    4.10   * Return:
    4.11   *  0:  Not reserved indirect registers
    4.12 @@ -71,6 +71,7 @@ is_reserved_indirect_register (
    4.13      return 0;
    4.14  
    4.15  }
    4.16 +#endif
    4.17  
    4.18  /*
    4.19   * Return:
    4.20 @@ -207,7 +208,7 @@ check_psr_rsv_fields (u64 value)
    4.21  }
    4.22  
    4.23  
    4.24 -
    4.25 +#ifdef CHECK_FAULT
    4.26  /*
    4.27   * Return:
    4.28   *  1: CR reserved fields are not zero
    4.29 @@ -310,9 +311,9 @@ check_cr_rsv_fields (int index, u64 valu
    4.30      panic ("Unsupported CR");
    4.31      return 0;
    4.32  }
    4.33 +#endif
    4.34  
    4.35 -
    4.36 -
    4.37 +#if 0
    4.38  /*
    4.39   * Return:
    4.40   *  0:  Indirect Reg reserved fields are not zero
    4.41 @@ -361,7 +362,7 @@ check_indirect_reg_rsv_fields ( int type
    4.42  
    4.43      return 1;
    4.44  }
    4.45 -
    4.46 +#endif
    4.47  
    4.48  
    4.49  
     5.1 --- a/xen/arch/ia64/vmx/vmx_vcpu.c	Mon Jul 02 09:54:53 2007 -0600
     5.2 +++ b/xen/arch/ia64/vmx/vmx_vcpu.c	Mon Jul 02 10:10:32 2007 -0600
     5.3 @@ -96,8 +96,7 @@ vmx_vcpu_set_psr(VCPU *vcpu, unsigned lo
     5.4       */
     5.5      VCPU(vcpu,vpsr) = value &
     5.6              (~ (IA64_PSR_ID |IA64_PSR_DA | IA64_PSR_DD |
     5.7 -                IA64_PSR_SS | IA64_PSR_ED | IA64_PSR_IA
     5.8 -            ));
     5.9 +                IA64_PSR_ED | IA64_PSR_IA));
    5.10  
    5.11      if ( !old_psr.i && (value & IA64_PSR_I) ) {
    5.12          // vpsr.i 0->1
     6.1 --- a/xen/arch/ia64/vmx/vmx_virt.c	Mon Jul 02 09:54:53 2007 -0600
     6.2 +++ b/xen/arch/ia64/vmx/vmx_virt.c	Mon Jul 02 10:10:32 2007 -0600
     6.3 @@ -178,8 +178,8 @@ static IA64FAULT vmx_emul_mov_to_psr(VCP
     6.4  {
     6.5      u64 val;
     6.6  
     6.7 -    if(vcpu_get_gr_nat(vcpu, inst.M35.r2, &val) != IA64_NO_FAULT)
     6.8 -	panic_domain(vcpu_regs(vcpu),"get_psr nat bit fault\n");
     6.9 +    if (vcpu_get_gr_nat(vcpu, inst.M35.r2, &val) != IA64_NO_FAULT)
    6.10 +        panic_domain(vcpu_regs(vcpu),"get_psr nat bit fault\n");
    6.11  
    6.12      return vmx_vcpu_set_psr_l(vcpu, val);
    6.13  }
    6.14 @@ -914,7 +914,6 @@ static IA64FAULT vmx_emul_mov_to_dbr(VCP
    6.15  static IA64FAULT vmx_emul_mov_to_ibr(VCPU *vcpu, INST64 inst)
    6.16  {
    6.17      u64 r3,r2;
    6.18 -    return IA64_NO_FAULT;
    6.19  #ifdef  CHECK_FAULT
    6.20      IA64_PSR vpsr;
    6.21      vpsr.val=vmx_vcpu_get_psr(vcpu);
    6.22 @@ -932,7 +931,7 @@ static IA64FAULT vmx_emul_mov_to_ibr(VCP
    6.23          return IA64_FAULT;
    6.24  #endif  //CHECK_FAULT
    6.25      }
    6.26 -    return (vmx_vcpu_set_ibr(vcpu,r3,r2));
    6.27 +    return vmx_vcpu_set_ibr(vcpu,r3,r2);
    6.28  }
    6.29  
    6.30  static IA64FAULT vmx_emul_mov_to_pmc(VCPU *vcpu, INST64 inst)
    6.31 @@ -1062,6 +1061,7 @@ static IA64FAULT vmx_emul_mov_from_pkr(V
    6.32  static IA64FAULT vmx_emul_mov_from_dbr(VCPU *vcpu, INST64 inst)
    6.33  {
    6.34      u64 r3,r1;
    6.35 +    IA64FAULT res;
    6.36  #ifdef  CHECK_FAULT
    6.37      if(check_target_register(vcpu, inst.M43.r1)){
    6.38          set_illegal_op_isr(vcpu);
    6.39 @@ -1092,13 +1092,16 @@ static IA64FAULT vmx_emul_mov_from_dbr(V
    6.40          return IA64_FAULT;
    6.41      }
    6.42  #endif  //CHECK_FAULT
    6.43 -    r1 = vmx_vcpu_get_dbr(vcpu, r3);
    6.44 +    res = vmx_vcpu_get_ibr(vcpu, r3, &r1);
    6.45 +    if (res != IA64_NO_FAULT)
    6.46 +        return res;
    6.47      return vcpu_set_gr(vcpu, inst.M43.r1, r1,0);
    6.48  }
    6.49  
    6.50  static IA64FAULT vmx_emul_mov_from_ibr(VCPU *vcpu, INST64 inst)
    6.51  {
    6.52      u64 r3,r1;
    6.53 +    IA64FAULT res;
    6.54  #ifdef  CHECK_FAULT
    6.55      if(check_target_register(vcpu, inst.M43.r1)){
    6.56          set_illegal_op_isr(vcpu);
    6.57 @@ -1129,7 +1132,9 @@ static IA64FAULT vmx_emul_mov_from_ibr(V
    6.58          return IA64_FAULT;
    6.59      }
    6.60  #endif  //CHECK_FAULT
    6.61 -    r1 = vmx_vcpu_get_ibr(vcpu, r3);
    6.62 +    res = vmx_vcpu_get_dbr(vcpu, r3, &r1);
    6.63 +    if (res != IA64_NO_FAULT)
    6.64 +        return res;
    6.65      return vcpu_set_gr(vcpu, inst.M43.r1, r1,0);
    6.66  }
    6.67  
    6.68 @@ -1562,22 +1567,38 @@ if ( (cause == 0xff && opcode == 0x1e000
    6.69          break;
    6.70      case EVENT_VMSW:
    6.71          printk ("Unimplemented instruction %ld\n", cause);
    6.72 -	status=IA64_FAULT;
    6.73 +        status=IA64_FAULT;
    6.74          break;
    6.75      default:
    6.76 -        panic_domain(regs,"unknown cause %ld, iip: %lx, ipsr: %lx\n", cause,regs->cr_iip,regs->cr_ipsr);
    6.77 +        panic_domain(regs,"unknown cause %ld, iip: %lx, ipsr: %lx\n",
    6.78 +                     cause,regs->cr_iip,regs->cr_ipsr);
    6.79          break;
    6.80      };
    6.81  
    6.82  #if 0
    6.83 -    if (status == IA64_FAULT)
    6.84 +    if (status != IA64_NO_FAULT)
    6.85  	panic("Emulation failed with cause %d:\n", cause);
    6.86  #endif
    6.87  
    6.88 -    if ( status == IA64_NO_FAULT && cause !=EVENT_RFI ) {
    6.89 -        vcpu_increment_iip(vcpu);
    6.90 +    switch (status) {
    6.91 +    case IA64_RSVDREG_FAULT:
    6.92 +        set_rsv_reg_field_isr(vcpu);
    6.93 +        rsv_reg_field(vcpu);
    6.94 +        break;
    6.95 +    case IA64_ILLOP_FAULT:
    6.96 +        set_illegal_op_isr(vcpu);
    6.97 +        illegal_op(vcpu);
    6.98 +        break;
    6.99 +    case IA64_FAULT:
   6.100 +        /* Registers aleady set.  */
   6.101 +        break;
   6.102 +    case IA64_NO_FAULT:
   6.103 +        if ( cause != EVENT_RFI )
   6.104 +            vcpu_increment_iip(vcpu);
   6.105 +        break;
   6.106      }
   6.107  
   6.108 +
   6.109      recover_if_physical_mode(vcpu);
   6.110      return;
   6.111  
     7.1 --- a/xen/arch/ia64/xen/vcpu.c	Mon Jul 02 09:54:53 2007 -0600
     7.2 +++ b/xen/arch/ia64/xen/vcpu.c	Mon Jul 02 10:10:32 2007 -0600
     7.3 @@ -1780,8 +1780,10 @@ IA64FAULT vcpu_set_dbr(VCPU * vcpu, u64 
     7.4  		if (val >= HYPERVISOR_VIRT_START && val <= HYPERVISOR_VIRT_END)
     7.5  			return IA64_ILLOP_FAULT;
     7.6  	} else {
     7.7 -		/* Mask PL0.  */
     7.8 -		val &= ~(1UL << 56);
     7.9 +		if (!VMX_DOMAIN(vcpu)) {
    7.10 +			/* Mask PL0. */
    7.11 +			val &= ~(1UL << 56);
    7.12 +		}
    7.13  	}
    7.14  	if (val != 0)
    7.15  		vcpu->arch.dbg_used |= (1 << reg);
    7.16 @@ -1802,8 +1804,10 @@ IA64FAULT vcpu_set_ibr(VCPU * vcpu, u64 
    7.17  		if (val >= HYPERVISOR_VIRT_START && val <= HYPERVISOR_VIRT_END)
    7.18  			return IA64_ILLOP_FAULT;
    7.19  	} else {
    7.20 -		/* Mask PL0.  */
    7.21 -		val &= ~(1UL << 56);
    7.22 +		if (!VMX_DOMAIN(vcpu)) {
    7.23 +			/* Mask PL0. */
    7.24 +			val &= ~(1UL << 56);
    7.25 +		}
    7.26  	}
    7.27  	if (val != 0)
    7.28  		vcpu->arch.dbg_used |= (1 << (reg + IA64_NUM_DBG_REGS));
     8.1 --- a/xen/include/asm-ia64/linux-xen/asm/ptrace.h	Mon Jul 02 09:54:53 2007 -0600
     8.2 +++ b/xen/include/asm-ia64/linux-xen/asm/ptrace.h	Mon Jul 02 10:10:32 2007 -0600
     8.3 @@ -278,6 +278,7 @@ struct switch_stack {
     8.4  #ifdef XEN
     8.5  # define guest_mode(regs)		(ia64_psr(regs)->cpl != 0)
     8.6  # define guest_kernel_mode(regs)	(ia64_psr(regs)->cpl == CONFIG_CPL0_EMUL)
     8.7 +# define vmx_guest_kernel_mode(regs)	(ia64_psr(regs)->cpl == 0)
     8.8  #else
     8.9  # define user_mode(regs)		(((struct ia64_psr *) &(regs)->cr_ipsr)->cpl != 0)
    8.10  #endif
     9.1 --- a/xen/include/asm-ia64/vmx.h	Mon Jul 02 09:54:53 2007 -0600
     9.2 +++ b/xen/include/asm-ia64/vmx.h	Mon Jul 02 10:10:32 2007 -0600
     9.3 @@ -50,6 +50,8 @@ extern void set_ifa_itir_iha (struct vcp
     9.4  extern void inject_guest_interruption(struct vcpu *vcpu, u64 vec);
     9.5  extern void set_illegal_op_isr (struct vcpu *vcpu);
     9.6  extern void illegal_op (struct vcpu *vcpu);
     9.7 +extern void set_rsv_reg_field_isr (struct vcpu *vcpu);
     9.8 +extern void rsv_reg_field (struct vcpu *vcpu);
     9.9  extern void vmx_relinquish_guest_resources(struct domain *d);
    9.10  extern void vmx_relinquish_vcpu_resources(struct vcpu *v);
    9.11  extern void vmx_die_if_kernel(char *str, struct pt_regs *regs, long err);
    10.1 --- a/xen/include/asm-ia64/vmx_vcpu.h	Mon Jul 02 09:54:53 2007 -0600
    10.2 +++ b/xen/include/asm-ia64/vmx_vcpu.h	Mon Jul 02 10:10:32 2007 -0600
    10.3 @@ -313,30 +313,22 @@ static inline u64 vmx_vcpu_get_cpuid(VCP
    10.4  
    10.5  static inline IA64FAULT vmx_vcpu_set_dbr(VCPU * vcpu, u64 reg, u64 val)
    10.6  {
    10.7 -	// TODO: unimplemented DBRs return a reserved register fault
    10.8 -	// TODO: Should set Logical CPU state, not just physical
    10.9 -	ia64_set_dbr(reg, val);
   10.10 -	return IA64_NO_FAULT;
   10.11 +        return vcpu_set_dbr(vcpu, reg, val);
   10.12  }
   10.13  
   10.14  static inline IA64FAULT vmx_vcpu_set_ibr(VCPU * vcpu, u64 reg, u64 val)
   10.15  {
   10.16 -	// TODO: unimplemented IBRs return a reserved register fault
   10.17 -	// TODO: Should set Logical CPU state, not just physical
   10.18 -	ia64_set_ibr(reg, val);
   10.19 -	return IA64_NO_FAULT;
   10.20 +        return vcpu_set_ibr(vcpu, reg, val);
   10.21  }
   10.22  
   10.23 -static inline u64 vmx_vcpu_get_dbr(VCPU * vcpu, u64 reg)
   10.24 +static inline IA64FAULT vmx_vcpu_get_dbr(VCPU * vcpu, u64 reg, u64 *pval)
   10.25  {
   10.26 -	// TODO: unimplemented DBRs return a reserved register fault
   10.27 -	return ((u64)ia64_get_dbr(reg));
   10.28 +        return vcpu_get_dbr(vcpu, reg, pval);
   10.29  }
   10.30  
   10.31 -static inline u64 vmx_vcpu_get_ibr(VCPU * vcpu, u64 reg)
   10.32 +static inline IA64FAULT vmx_vcpu_get_ibr(VCPU * vcpu, u64 reg, u64 *pval)
   10.33  {
   10.34 -	// TODO: unimplemented IBRs return a reserved register fault
   10.35 -	return ((u64)ia64_get_ibr(reg));
   10.36 +        return vcpu_get_ibr(vcpu, reg, pval);
   10.37  }
   10.38  
   10.39  /**************************************************************************