ia64/xen-unstable

changeset 15810:9554ec3e27cd

Support extensions to Intel architecture for TXT/SMX.
Signed-off-by: Joseph Cihula <joseph.cihula@intel.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Thu Aug 30 18:53:54 2007 +0100 (2007-08-30)
parents d032a17aced2
children 9fd5becfba6b
files xen/arch/x86/domain_build.c xen/arch/x86/hvm/vmx/vmcs.c xen/include/asm-x86/cpufeature.h xen/include/asm-x86/msr.h xen/include/asm-x86/processor.h
line diff
     1.1 --- a/xen/arch/x86/domain_build.c	Thu Aug 30 16:41:57 2007 +0100
     1.2 +++ b/xen/arch/x86/domain_build.c	Thu Aug 30 18:53:54 2007 +0100
     1.3 @@ -26,6 +26,7 @@
     1.4  #include <asm/desc.h>
     1.5  #include <asm/i387.h>
     1.6  #include <asm/paging.h>
     1.7 +#include <asm/e820.h>
     1.8  
     1.9  #include <public/version.h>
    1.10  #include <public/libelf.h>
     2.1 --- a/xen/arch/x86/hvm/vmx/vmcs.c	Thu Aug 30 16:41:57 2007 +0100
     2.2 +++ b/xen/arch/x86/hvm/vmx/vmcs.c	Thu Aug 30 18:53:54 2007 +0100
     2.3 @@ -262,17 +262,19 @@ int vmx_cpu_up(void)
     2.4  
     2.5      if ( eax & IA32_FEATURE_CONTROL_MSR_LOCK )
     2.6      {
     2.7 -        if ( !(eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON) )
     2.8 +        if ( !(eax & (IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX |
     2.9 +                      IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX)) )
    2.10          {
    2.11 -            printk("CPU%d: VMX disabled\n", cpu);
    2.12 +            printk("CPU%d: VMX disabled by BIOS.\n", cpu);
    2.13              return 0;
    2.14          }
    2.15      }
    2.16      else
    2.17      {
    2.18 -        wrmsr(IA32_FEATURE_CONTROL_MSR,
    2.19 -              IA32_FEATURE_CONTROL_MSR_LOCK |
    2.20 -              IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON, 0);
    2.21 +        eax = (IA32_FEATURE_CONTROL_MSR_LOCK |
    2.22 +               IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX |
    2.23 +               IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX);
    2.24 +        wrmsr(IA32_FEATURE_CONTROL_MSR, eax, 0);
    2.25      }
    2.26  
    2.27      vmx_init_vmcs_config();
     3.1 --- a/xen/include/asm-x86/cpufeature.h	Thu Aug 30 16:41:57 2007 +0100
     3.2 +++ b/xen/include/asm-x86/cpufeature.h	Thu Aug 30 18:53:54 2007 +0100
     3.3 @@ -77,6 +77,7 @@
     3.4  #define X86_FEATURE_MWAIT	(4*32+ 3) /* Monitor/Mwait support */
     3.5  #define X86_FEATURE_DSCPL	(4*32+ 4) /* CPL Qualified Debug Store */
     3.6  #define X86_FEATURE_VMXE	(4*32+ 5) /* Virtual Machine Extensions */
     3.7 +#define X86_FEATURE_SMXE	(4*32+ 6) /* Safer Mode Extensions */
     3.8  #define X86_FEATURE_EST		(4*32+ 7) /* Enhanced SpeedStep */
     3.9  #define X86_FEATURE_TM2		(4*32+ 8) /* Thermal Monitor 2 */
    3.10  #define X86_FEATURE_CID		(4*32+10) /* Context ID */
     4.1 --- a/xen/include/asm-x86/msr.h	Thu Aug 30 16:41:57 2007 +0100
     4.2 +++ b/xen/include/asm-x86/msr.h	Thu Aug 30 18:53:54 2007 +0100
     4.3 @@ -122,8 +122,11 @@ static inline void wrmsrl(unsigned int m
     4.4  #define MSR_IA32_VMX_CR4_FIXED1                 0x489
     4.5  #define MSR_IA32_VMX_PROCBASED_CTLS2            0x48b
     4.6  #define IA32_FEATURE_CONTROL_MSR                0x3a
     4.7 -#define IA32_FEATURE_CONTROL_MSR_LOCK           0x1
     4.8 -#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON   0x4
     4.9 +#define IA32_FEATURE_CONTROL_MSR_LOCK                     0x0001
    4.10 +#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX  0x0002
    4.11 +#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX 0x0004
    4.12 +#define IA32_FEATURE_CONTROL_MSR_SENTER_PARAM_CTL         0x7f00
    4.13 +#define IA32_FEATURE_CONTROL_MSR_ENABLE_SENTER            0x8000
    4.14  
    4.15  /* AMD/K8 specific MSRs */ 
    4.16  #define MSR_EFER 0xc0000080		/* extended feature register */
     5.1 --- a/xen/include/asm-x86/processor.h	Thu Aug 30 16:41:57 2007 +0100
     5.2 +++ b/xen/include/asm-x86/processor.h	Thu Aug 30 18:53:54 2007 +0100
     5.3 @@ -80,6 +80,7 @@
     5.4  #define X86_CR4_OSFXSR		0x0200	/* enable fast FPU save and restore */
     5.5  #define X86_CR4_OSXMMEXCPT	0x0400	/* enable unmasked SSE exceptions */
     5.6  #define X86_CR4_VMXE		0x2000  /* enable VMX */
     5.7 +#define X86_CR4_SMXE		0x4000  /* enable SMX */
     5.8  
     5.9  /*
    5.10   * Trap/fault mnemonics.