ia64/xen-unstable

changeset 5389:949970efef98

bitkeeper revision 1.1694 (42a809c2ifgYRhvnYmx3rxzVbUxHaQ)

Merge arcadians.cl.cam.ac.uk:/auto/groups/xeno-xenod/BK/xeno.bk
into arcadians.cl.cam.ac.uk:/auto/anfs/nos1/akw27/xeno-clone/xeno.bk
author akw27@arcadians.cl.cam.ac.uk
date Thu Jun 09 09:20:02 2005 +0000 (2005-06-09)
parents 5cc07785693b 017d8690d834
children 1c2fe32ca700
files docs/src/user.tex linux-2.6.11-xen-sparse/drivers/xen/blkfront/vbd.c tools/firmware/Makefile xen/arch/ia64/irq.c xen/arch/ia64/xensetup.c xen/arch/x86/acpi/boot.c xen/arch/x86/domain_build.c xen/arch/x86/i8259.c xen/arch/x86/io_apic.c xen/arch/x86/irq.c xen/arch/x86/mm.c xen/arch/x86/physdev.c xen/arch/x86/setup.c xen/arch/x86/smpboot.c xen/arch/x86/vmx.c xen/arch/x86/vmx_vmcs.c xen/include/asm-ia64/config.h xen/include/asm-x86/hardirq.h xen/include/asm-x86/io_apic.h xen/include/asm-x86/irq.h xen/include/asm-x86/page.h xen/include/xen/irq.h xen/include/xen/smp.h
line diff
     1.1 --- a/docs/src/user.tex	Wed Jun 08 12:48:07 2005 +0000
     1.2 +++ b/docs/src/user.tex	Thu Jun 09 09:20:02 2005 +0000
     1.3 @@ -1692,9 +1692,6 @@ editing \path{grub.conf}.
     1.4  \item [watchdog ] 
     1.5   Enable NMI watchdog which can report certain failures. 
     1.6  
     1.7 -\item [noht ] 
     1.8 - Disable Hyperthreading. 
     1.9 -
    1.10  \item [badpage=$<$page number$>$,$<$page number$>$, \ldots ] 
    1.11   Specify a list of pages not to be allocated for use 
    1.12   because they contain bad bytes. For example, if your
     3.1 --- a/tools/firmware/Makefile	Wed Jun 08 12:48:07 2005 +0000
     3.2 +++ b/tools/firmware/Makefile	Thu Jun 09 09:20:02 2005 +0000
     3.3 @@ -2,7 +2,7 @@ XEN_ROOT = ../..
     3.4  include $(XEN_ROOT)/tools/Rules.mk
     3.5  
     3.6  TARGET      := vmxassist/vmxloader
     3.7 -INSTALL_DIR := $(DESTDIR)/usr/share/xen
     3.8 +INSTALL_DIR := $(DESTDIR)/usr/lib/xen/boot
     3.9  
    3.10  SUBDIRS :=
    3.11  SUBDIRS += rombios
     4.1 --- a/xen/arch/ia64/irq.c	Wed Jun 08 12:48:07 2005 +0000
     4.2 +++ b/xen/arch/ia64/irq.c	Thu Jun 09 09:20:02 2005 +0000
     4.3 @@ -1471,28 +1471,6 @@ int pirq_guest_unbind(struct domain *d, 
     4.4      return 0;
     4.5  }
     4.6  
     4.7 -int pirq_guest_bindable(int irq, int will_share)
     4.8 -{
     4.9 -    irq_desc_t         *desc = &irq_desc[irq];
    4.10 -    irq_guest_action_t *action;
    4.11 -    unsigned long       flags;
    4.12 -    int                 okay;
    4.13 -
    4.14 -    spin_lock_irqsave(&desc->lock, flags);
    4.15 -
    4.16 -    action = (irq_guest_action_t *)desc->action;
    4.17 -
    4.18 -    /*
    4.19 -     * To be bindable the IRQ must either be not currently bound (1), or
    4.20 -     * it must be shareable (2) and not at its share limit (3).
    4.21 -     */
    4.22 -    okay = ((!(desc->status & IRQ_GUEST) && (action == NULL)) || /* 1 */
    4.23 -            (action->shareable && will_share &&                  /* 2 */
    4.24 -             (action->nr_guests != IRQ_MAX_GUESTS)));            /* 3 */
    4.25 -
    4.26 -    spin_unlock_irqrestore(&desc->lock, flags);
    4.27 -    return okay;
    4.28 -}
    4.29  #endif
    4.30  
    4.31  #ifdef XEN
     5.1 --- a/xen/arch/ia64/xensetup.c	Wed Jun 08 12:48:07 2005 +0000
     5.2 +++ b/xen/arch/ia64/xensetup.c	Thu Jun 09 09:20:02 2005 +0000
     5.3 @@ -36,10 +36,6 @@ extern unsigned long domain0_ready;
     5.4  int find_max_pfn (unsigned long, unsigned long, void *);
     5.5  void start_of_day(void);
     5.6  
     5.7 -/* opt_noht: If true, Hyperthreading is ignored. */
     5.8 -int opt_noht = 0;
     5.9 -boolean_param("noht", opt_noht);
    5.10 -
    5.11  /* opt_nosmp: If true, secondary processors are ignored. */
    5.12  static int opt_nosmp = 0;
    5.13  boolean_param("nosmp", opt_nosmp);
     6.1 --- a/xen/arch/x86/acpi/boot.c	Wed Jun 08 12:48:07 2005 +0000
     6.2 +++ b/xen/arch/x86/acpi/boot.c	Thu Jun 09 09:20:02 2005 +0000
     6.3 @@ -88,22 +88,6 @@ EXPORT_SYMBOL(x86_acpiid_to_apicid);
     6.4   */
     6.5  enum acpi_irq_model_id		acpi_irq_model = ACPI_IRQ_MODEL_PIC;
     6.6  
     6.7 -#if 0/*def	CONFIG_X86_64*/
     6.8 -
     6.9 -/* rely on all ACPI tables being in the direct mapping */
    6.10 -char *__acpi_map_table(unsigned long phys_addr, unsigned long size)
    6.11 -{
    6.12 -	if (!phys_addr || !size)
    6.13 -	return NULL;
    6.14 -
    6.15 -	if (phys_addr < (end_pfn_map << PAGE_SHIFT))
    6.16 -		return __va(phys_addr);
    6.17 -
    6.18 -	return NULL;
    6.19 -}
    6.20 -
    6.21 -#else
    6.22 -
    6.23  /*
    6.24   * Temporarily use the virtual area starting from FIX_IO_APIC_BASE_END,
    6.25   * to map the target physical address. The problem is that set_fixmap()
    6.26 @@ -143,7 +127,6 @@ char *__acpi_map_table(unsigned long phy
    6.27  
    6.28  	return ((char *) base + offset);
    6.29  }
    6.30 -#endif
    6.31  
    6.32  #ifdef CONFIG_PCI_MMCONFIG
    6.33  static int __init acpi_parse_mcfg(unsigned long phys_addr, unsigned long size)
    6.34 @@ -289,42 +272,6 @@ acpi_parse_ioapic (
    6.35  	return 0;
    6.36  }
    6.37  
    6.38 -#ifdef CONFIG_ACPI_INTERPRETER
    6.39 -/*
    6.40 - * Parse Interrupt Source Override for the ACPI SCI
    6.41 - */
    6.42 -static void
    6.43 -acpi_sci_ioapic_setup(u32 gsi, u16 polarity, u16 trigger)
    6.44 -{
    6.45 -	if (trigger == 0)	/* compatible SCI trigger is level */
    6.46 -		trigger = 3;
    6.47 -
    6.48 -	if (polarity == 0)	/* compatible SCI polarity is low */
    6.49 -		polarity = 3;
    6.50 -
    6.51 -	/* Command-line over-ride via acpi_sci= */
    6.52 -	if (acpi_sci_flags.trigger)
    6.53 -		trigger = acpi_sci_flags.trigger;
    6.54 -
    6.55 -	if (acpi_sci_flags.polarity)
    6.56 -		polarity = acpi_sci_flags.polarity;
    6.57 -
    6.58 -	/*
    6.59 - 	 * mp_config_acpi_legacy_irqs() already setup IRQs < 16
    6.60 -	 * If GSI is < 16, this will update its flags,
    6.61 -	 * else it will create a new mp_irqs[] entry.
    6.62 -	 */
    6.63 -	mp_override_legacy_irq(gsi, polarity, trigger, gsi);
    6.64 -
    6.65 -	/*
    6.66 -	 * stash over-ride to indicate we've been here
    6.67 -	 * and for later update of acpi_fadt
    6.68 -	 */
    6.69 -	acpi_sci_override_gsi = gsi;
    6.70 -	return;
    6.71 -}
    6.72 -#endif
    6.73 -
    6.74  static int __init
    6.75  acpi_parse_int_src_ovr (
    6.76  	acpi_table_entry_header *header, const unsigned long end)
    6.77 @@ -338,14 +285,6 @@ acpi_parse_int_src_ovr (
    6.78  
    6.79  	acpi_table_print_madt_entry(header);
    6.80  
    6.81 -#ifdef CONFIG_ACPI_INTERPRETER
    6.82 -	if (intsrc->bus_irq == acpi_fadt.sci_int) {
    6.83 -		acpi_sci_ioapic_setup(intsrc->global_irq,
    6.84 -			intsrc->flags.polarity, intsrc->flags.trigger);
    6.85 -		return 0;
    6.86 -	}
    6.87 -#endif
    6.88 -
    6.89  	if (acpi_skip_timer_override &&
    6.90  		intsrc->bus_irq == 0 && intsrc->global_irq == 2) {
    6.91  			printk(PREFIX "BIOS IRQ0 pin2 override ignored.\n");
    6.92 @@ -382,122 +321,6 @@ acpi_parse_nmi_src (
    6.93  
    6.94  #endif /* CONFIG_X86_IO_APIC */
    6.95  
    6.96 -#ifdef	CONFIG_ACPI_BUS
    6.97 -
    6.98 -/*
    6.99 - * acpi_pic_sci_set_trigger()
   6.100 - * 
   6.101 - * use ELCR to set PIC-mode trigger type for SCI
   6.102 - *
   6.103 - * If a PIC-mode SCI is not recognized or gives spurious IRQ7's
   6.104 - * it may require Edge Trigger -- use "acpi_sci=edge"
   6.105 - *
   6.106 - * Port 0x4d0-4d1 are ECLR1 and ECLR2, the Edge/Level Control Registers
   6.107 - * for the 8259 PIC.  bit[n] = 1 means irq[n] is Level, otherwise Edge.
   6.108 - * ECLR1 is IRQ's 0-7 (IRQ 0, 1, 2 must be 0)
   6.109 - * ECLR2 is IRQ's 8-15 (IRQ 8, 13 must be 0)
   6.110 - */
   6.111 -
   6.112 -void __init
   6.113 -acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
   6.114 -{
   6.115 -	unsigned int mask = 1 << irq;
   6.116 -	unsigned int old, new;
   6.117 -
   6.118 -	/* Real old ELCR mask */
   6.119 -	old = inb(0x4d0) | (inb(0x4d1) << 8);
   6.120 -
   6.121 -	/*
   6.122 -	 * If we use ACPI to set PCI irq's, then we should clear ELCR
   6.123 -	 * since we will set it correctly as we enable the PCI irq
   6.124 -	 * routing.
   6.125 -	 */
   6.126 -	new = acpi_noirq ? old : 0;
   6.127 -
   6.128 -	/*
   6.129 -	 * Update SCI information in the ELCR, it isn't in the PCI
   6.130 -	 * routing tables..
   6.131 -	 */
   6.132 -	switch (trigger) {
   6.133 -	case 1:	/* Edge - clear */
   6.134 -		new &= ~mask;
   6.135 -		break;
   6.136 -	case 3: /* Level - set */
   6.137 -		new |= mask;
   6.138 -		break;
   6.139 -	}
   6.140 -
   6.141 -	if (old == new)
   6.142 -		return;
   6.143 -
   6.144 -	printk(PREFIX "setting ELCR to %04x (from %04x)\n", new, old);
   6.145 -	outb(new, 0x4d0);
   6.146 -	outb(new >> 8, 0x4d1);
   6.147 -}
   6.148 -
   6.149 -
   6.150 -#endif /* CONFIG_ACPI_BUS */
   6.151 -
   6.152 -int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
   6.153 -{
   6.154 -#ifdef CONFIG_X86_IO_APIC
   6.155 -	if (use_pci_vector() && !platform_legacy_irq(gsi))
   6.156 - 		*irq = IO_APIC_VECTOR(gsi);
   6.157 -	else
   6.158 -#endif
   6.159 -		*irq = gsi;
   6.160 -	return 0;
   6.161 -}
   6.162 -
   6.163 -unsigned int acpi_register_gsi(u32 gsi, int edge_level, int active_high_low)
   6.164 -{
   6.165 -	unsigned int irq;
   6.166 -	unsigned int plat_gsi = gsi;
   6.167 -
   6.168 -#ifdef CONFIG_PCI
   6.169 -	/*
   6.170 -	 * Make sure all (legacy) PCI IRQs are set as level-triggered.
   6.171 -	 */
   6.172 -	if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
   6.173 -		extern void eisa_set_level_irq(unsigned int irq);
   6.174 -
   6.175 -		if (edge_level == ACPI_LEVEL_SENSITIVE)
   6.176 -				eisa_set_level_irq(gsi);
   6.177 -	}
   6.178 -#endif
   6.179 -
   6.180 -#ifdef CONFIG_X86_IO_APIC
   6.181 -	if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) {
   6.182 -		plat_gsi = mp_register_gsi(gsi, edge_level, active_high_low);
   6.183 -	}
   6.184 -#endif
   6.185 -	acpi_gsi_to_irq(plat_gsi, &irq);
   6.186 -	return irq;
   6.187 -}
   6.188 -EXPORT_SYMBOL(acpi_register_gsi);
   6.189 -
   6.190 -/*
   6.191 - *  ACPI based hotplug support for CPU
   6.192 - */
   6.193 -#ifdef CONFIG_ACPI_HOTPLUG_CPU
   6.194 -int
   6.195 -acpi_map_lsapic(acpi_handle handle, int *pcpu)
   6.196 -{
   6.197 -	/* TBD */
   6.198 -	return -EINVAL;
   6.199 -}
   6.200 -EXPORT_SYMBOL(acpi_map_lsapic);
   6.201 -
   6.202 -
   6.203 -int
   6.204 -acpi_unmap_lsapic(int cpu)
   6.205 -{
   6.206 -	/* TBD */
   6.207 -	return -EINVAL;
   6.208 -}
   6.209 -EXPORT_SYMBOL(acpi_unmap_lsapic);
   6.210 -#endif /* CONFIG_ACPI_HOTPLUG_CPU */
   6.211 -
   6.212  static unsigned long __init
   6.213  acpi_scan_rsdp (
   6.214  	unsigned long		start,
     7.1 --- a/xen/arch/x86/domain_build.c	Wed Jun 08 12:48:07 2005 +0000
     7.2 +++ b/xen/arch/x86/domain_build.c	Thu Jun 09 09:20:02 2005 +0000
     7.3 @@ -597,7 +597,7 @@ int construct_dom0(struct domain *d,
     7.4  
     7.5      memset(si->cmd_line, 0, sizeof(si->cmd_line));
     7.6      if ( cmdline != NULL )
     7.7 -        strncpy(si->cmd_line, cmdline, sizeof(si->cmd_line)-1);
     7.8 +        strncpy((char *)si->cmd_line, cmdline, sizeof(si->cmd_line)-1);
     7.9  
    7.10      /* Reinstate the caller's page tables. */
    7.11      write_ptbase(current);
     8.1 --- a/xen/arch/x86/i8259.c	Wed Jun 08 12:48:07 2005 +0000
     8.2 +++ b/xen/arch/x86/i8259.c	Thu Jun 09 09:20:02 2005 +0000
     8.3 @@ -35,36 +35,18 @@
     8.4  BUILD_COMMON_IRQ()
     8.5  
     8.6  #define BI(x,y) \
     8.7 -	BUILD_IRQ(x##y)
     8.8 +    BUILD_IRQ(x##y)
     8.9  
    8.10  #define BUILD_16_IRQS(x) \
    8.11 -	BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
    8.12 -	BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
    8.13 -	BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
    8.14 -	BI(x,c) BI(x,d) BI(x,e) BI(x,f)
    8.15 -
    8.16 -/*
    8.17 - * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
    8.18 - * (these are usually mapped to vectors 0x20-0x2f)
    8.19 - */
    8.20 -BUILD_16_IRQS(0x0)
    8.21 +    BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
    8.22 +    BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
    8.23 +    BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
    8.24 +    BI(x,c) BI(x,d) BI(x,e) BI(x,f)
    8.25  
    8.26 -#ifdef CONFIG_X86_IO_APIC
    8.27 -/*
    8.28 - * The IO-APIC gives us many more interrupt sources. Most of these 
    8.29 - * are unused but an SMP system is supposed to have enough memory ...
    8.30 - * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
    8.31 - * across the spectrum, so we really want to be prepared to get all
    8.32 - * of these. Plus, more powerful systems might have more than 64
    8.33 - * IO-APIC registers.
    8.34 - *
    8.35 - * (these are usually mapped into the 0x20-0xff vector range)
    8.36 - */
    8.37 -BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
    8.38 +BUILD_16_IRQS(0x0) BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
    8.39  BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
    8.40  BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
    8.41 -BUILD_16_IRQS(0xc)
    8.42 -#endif
    8.43 +BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
    8.44  
    8.45  #undef BUILD_16_IRQS
    8.46  #undef BI
    8.47 @@ -75,11 +57,9 @@ BUILD_16_IRQS(0xc)
    8.48   * is no hardware IRQ pin equivalent for them, they are triggered
    8.49   * through the ICC by us (IPIs)
    8.50   */
    8.51 -#ifdef CONFIG_SMP
    8.52  BUILD_SMP_INTERRUPT(event_check_interrupt,EVENT_CHECK_VECTOR)
    8.53  BUILD_SMP_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
    8.54  BUILD_SMP_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
    8.55 -#endif
    8.56  
    8.57  /*
    8.58   * Every pentium local APIC has two 'local interrupts', with a
    8.59 @@ -93,23 +73,19 @@ BUILD_SMP_INTERRUPT(error_interrupt,ERRO
    8.60  BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
    8.61  
    8.62  #define IRQ(x,y) \
    8.63 -	IRQ##x##y##_interrupt
    8.64 +    IRQ##x##y##_interrupt
    8.65  
    8.66  #define IRQLIST_16(x) \
    8.67 -	IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
    8.68 -	IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
    8.69 -	IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
    8.70 -	IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
    8.71 +    IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
    8.72 +    IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
    8.73 +    IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
    8.74 +    IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
    8.75  
    8.76 -    void (*interrupt[NR_IRQS])(void) = {
    8.77 -	IRQLIST_16(0x0),
    8.78 -
    8.79 -#ifdef CONFIG_X86_IO_APIC
    8.80 -        IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
    8.81 -	IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
    8.82 -	IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
    8.83 -	IRQLIST_16(0xc)
    8.84 -#endif
    8.85 +    static void (*interrupt[])(void) = {
    8.86 +        IRQLIST_16(0x0), IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
    8.87 +        IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
    8.88 +        IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
    8.89 +        IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
    8.90      };
    8.91  
    8.92  #undef IRQ
    8.93 @@ -126,31 +102,38 @@ BUILD_SMP_INTERRUPT(spurious_interrupt,S
    8.94  
    8.95  spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
    8.96  
    8.97 -static void end_8259A_irq (unsigned int irq)
    8.98 +static void disable_8259A_vector(unsigned int vector)
    8.99  {
   8.100 -    if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
   8.101 -        enable_8259A_irq(irq);
   8.102 +    disable_8259A_irq(LEGACY_IRQ_FROM_VECTOR(vector));
   8.103 +}
   8.104 +
   8.105 +static void enable_8259A_vector(unsigned int vector)
   8.106 +{
   8.107 +    enable_8259A_irq(LEGACY_IRQ_FROM_VECTOR(vector));
   8.108  }
   8.109  
   8.110 -#define shutdown_8259A_irq	disable_8259A_irq
   8.111 -
   8.112 -void mask_and_ack_8259A(unsigned int);
   8.113 +static void mask_and_ack_8259A_vector(unsigned int);
   8.114  
   8.115 -static unsigned int startup_8259A_irq(unsigned int irq)
   8.116 +static void end_8259A_vector(unsigned int vector)
   8.117 +{
   8.118 +    if (!(irq_desc[vector].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
   8.119 +        enable_8259A_vector(vector);
   8.120 +}
   8.121 +
   8.122 +static unsigned int startup_8259A_vector(unsigned int vector)
   8.123  { 
   8.124 -    enable_8259A_irq(irq);
   8.125 +    enable_8259A_vector(vector);
   8.126      return 0; /* never anything pending */
   8.127  }
   8.128  
   8.129  static struct hw_interrupt_type i8259A_irq_type = {
   8.130 -    "XT-PIC",
   8.131 -    startup_8259A_irq,
   8.132 -    shutdown_8259A_irq,
   8.133 -    enable_8259A_irq,
   8.134 -    disable_8259A_irq,
   8.135 -    mask_and_ack_8259A,
   8.136 -    end_8259A_irq,
   8.137 -    NULL
   8.138 +    .typename = "XT-PIC",
   8.139 +    .startup  = startup_8259A_vector,
   8.140 +    .shutdown = disable_8259A_vector,
   8.141 +    .enable   = enable_8259A_vector,
   8.142 +    .disable  = disable_8259A_vector,
   8.143 +    .ack      = mask_and_ack_8259A_vector,
   8.144 +    .end      = end_8259A_vector
   8.145  };
   8.146  
   8.147  /*
   8.148 @@ -162,9 +145,9 @@ static struct hw_interrupt_type i8259A_i
   8.149   */
   8.150  static unsigned int cached_irq_mask = 0xffff;
   8.151  
   8.152 -#define __byte(x,y) 	(((unsigned char *)&(y))[x])
   8.153 -#define cached_21	(__byte(0,cached_irq_mask))
   8.154 -#define cached_A1	(__byte(1,cached_irq_mask))
   8.155 +#define __byte(x,y) (((unsigned char *)&(y))[x])
   8.156 +#define cached_21   (__byte(0,cached_irq_mask))
   8.157 +#define cached_A1   (__byte(1,cached_irq_mask))
   8.158  
   8.159  /*
   8.160   * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
   8.161 @@ -225,7 +208,6 @@ void make_8259A_irq(unsigned int irq)
   8.162  {
   8.163      disable_irq_nosync(irq);
   8.164      io_apic_irqs &= ~(1<<irq);
   8.165 -    irq_desc[irq].handler = &i8259A_irq_type;
   8.166      enable_irq(irq);
   8.167  }
   8.168  
   8.169 @@ -241,14 +223,14 @@ static inline int i8259A_irq_real(unsign
   8.170      int irqmask = 1<<irq;
   8.171  
   8.172      if (irq < 8) {
   8.173 -        outb(0x0B,0x20);		/* ISR register */
   8.174 +        outb(0x0B,0x20);                /* ISR register */
   8.175          value = inb(0x20) & irqmask;
   8.176 -        outb(0x0A,0x20);		/* back to the IRR register */
   8.177 +        outb(0x0A,0x20);                /* back to the IRR register */
   8.178          return value;
   8.179      }
   8.180 -    outb(0x0B,0xA0);		/* ISR register */
   8.181 +    outb(0x0B,0xA0);                    /* ISR register */
   8.182      value = inb(0xA0) & (irqmask >> 8);
   8.183 -    outb(0x0A,0xA0);		/* back to the IRR register */
   8.184 +    outb(0x0A,0xA0);                    /* back to the IRR register */
   8.185      return value;
   8.186  }
   8.187  
   8.188 @@ -258,8 +240,9 @@ static inline int i8259A_irq_real(unsign
   8.189   * first, _then_ send the EOI, and the order of EOI
   8.190   * to the two 8259s is important!
   8.191   */
   8.192 -void mask_and_ack_8259A(unsigned int irq)
   8.193 +static void mask_and_ack_8259A_vector(unsigned int vector)
   8.194  {
   8.195 +    unsigned int irq = LEGACY_IRQ_FROM_VECTOR(vector);
   8.196      unsigned int irqmask = 1 << irq;
   8.197      unsigned long flags;
   8.198  
   8.199 @@ -285,14 +268,14 @@ void mask_and_ack_8259A(unsigned int irq
   8.200  
   8.201   handle_real_irq:
   8.202      if (irq & 8) {
   8.203 -        inb(0xA1);		/* DUMMY - (do we need this?) */
   8.204 +        inb(0xA1);              /* DUMMY - (do we need this?) */
   8.205          outb(cached_A1,0xA1);
   8.206          outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
   8.207 -        outb(0x62,0x20);	/* 'Specific EOI' to master-IRQ2 */
   8.208 +        outb(0x62,0x20);        /* 'Specific EOI' to master-IRQ2 */
   8.209      } else {
   8.210 -        inb(0x21);		/* DUMMY - (do we need this?) */
   8.211 +        inb(0x21);              /* DUMMY - (do we need this?) */
   8.212          outb(cached_21,0x21);
   8.213 -        outb(0x60+irq,0x20);	/* 'Specific EOI' to master */
   8.214 +        outb(0x60+irq,0x20);    /* 'Specific EOI' to master */
   8.215      }
   8.216      spin_unlock_irqrestore(&i8259A_lock, flags);
   8.217      return;
   8.218 @@ -334,39 +317,39 @@ void __init init_8259A(int auto_eoi)
   8.219  
   8.220      spin_lock_irqsave(&i8259A_lock, flags);
   8.221  
   8.222 -    outb(0xff, 0x21);	/* mask all of 8259A-1 */
   8.223 -    outb(0xff, 0xA1);	/* mask all of 8259A-2 */
   8.224 +    outb(0xff, 0x21);   /* mask all of 8259A-1 */
   8.225 +    outb(0xff, 0xA1);   /* mask all of 8259A-2 */
   8.226  
   8.227      /*
   8.228       * outb_p - this has to work on a wide range of PC hardware.
   8.229       */
   8.230 -    outb_p(0x11, 0x20);	/* ICW1: select 8259A-1 init */
   8.231 -    outb_p(0x20 + 0, 0x21);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
   8.232 -    outb_p(0x04, 0x21);	/* 8259A-1 (the master) has a slave on IR2 */
   8.233 +    outb_p(0x11, 0x20);     /* ICW1: select 8259A-1 init */
   8.234 +    outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
   8.235 +    outb_p(0x04, 0x21);     /* 8259A-1 (the master) has a slave on IR2 */
   8.236      if (auto_eoi)
   8.237 -        outb_p(0x03, 0x21);	/* master does Auto EOI */
   8.238 +        outb_p(0x03, 0x21); /* master does Auto EOI */
   8.239      else
   8.240 -        outb_p(0x01, 0x21);	/* master expects normal EOI */
   8.241 +        outb_p(0x01, 0x21); /* master expects normal EOI */
   8.242  
   8.243 -    outb_p(0x11, 0xA0);	/* ICW1: select 8259A-2 init */
   8.244 -    outb_p(0x20 + 8, 0xA1);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
   8.245 -    outb_p(0x02, 0xA1);	/* 8259A-2 is a slave on master's IR2 */
   8.246 -    outb_p(0x01, 0xA1);	/* (slave's support for AEOI in flat mode
   8.247 -                           is to be investigated) */
   8.248 +    outb_p(0x11, 0xA0);     /* ICW1: select 8259A-2 init */
   8.249 +    outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
   8.250 +    outb_p(0x02, 0xA1);     /* 8259A-2 is a slave on master's IR2 */
   8.251 +    outb_p(0x01, 0xA1);     /* (slave's support for AEOI in flat mode
   8.252 +                               is to be investigated) */
   8.253  
   8.254      if (auto_eoi)
   8.255          /*
   8.256           * in AEOI mode we just have to mask the interrupt
   8.257           * when acking.
   8.258           */
   8.259 -        i8259A_irq_type.ack = disable_8259A_irq;
   8.260 +        i8259A_irq_type.ack = disable_8259A_vector;
   8.261      else
   8.262 -        i8259A_irq_type.ack = mask_and_ack_8259A;
   8.263 +        i8259A_irq_type.ack = mask_and_ack_8259A_vector;
   8.264  
   8.265 -    udelay(100);		/* wait for 8259A to initialize */
   8.266 +    udelay(100);            /* wait for 8259A to initialize */
   8.267  
   8.268 -    outb(cached_21, 0x21);	/* restore master IRQ mask */
   8.269 -    outb(cached_A1, 0xA1);	/* restore slave IRQ mask */
   8.270 +    outb(cached_21, 0x21);  /* restore master IRQ mask */
   8.271 +    outb(cached_A1, 0xA1);  /* restore slave IRQ mask */
   8.272  
   8.273      spin_unlock_irqrestore(&i8259A_lock, flags);
   8.274  }
   8.275 @@ -384,11 +367,17 @@ void __init init_IRQ(void)
   8.276      for ( i = 0; i < NR_IRQS; i++ )
   8.277      {
   8.278          irq_desc[i].status  = IRQ_DISABLED;
   8.279 -        irq_desc[i].handler = (i<16) ? &i8259A_irq_type : &no_irq_type;
   8.280 +        irq_desc[i].handler = &no_irq_type;
   8.281          irq_desc[i].action  = NULL;
   8.282          irq_desc[i].depth   = 1;
   8.283          spin_lock_init(&irq_desc[i].lock);
   8.284 -        set_intr_gate(FIRST_EXTERNAL_VECTOR+i, interrupt[i]);
   8.285 +        set_intr_gate(i, interrupt[i]);
   8.286 +    }
   8.287 +
   8.288 +    for ( i = 0; i < 16; i++ )
   8.289 +    {
   8.290 +        vector_irq[LEGACY_VECTOR(i)] = i;
   8.291 +        irq_desc[LEGACY_VECTOR(i)].handler = &i8259A_irq_type;
   8.292      }
   8.293  
   8.294      /*
   8.295 @@ -397,7 +386,6 @@ void __init init_IRQ(void)
   8.296       */
   8.297      irq_vector[0] = FIRST_DEVICE_VECTOR;
   8.298      vector_irq[FIRST_DEVICE_VECTOR] = 0;
   8.299 -    set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
   8.300  
   8.301      /* Various IPI functions. */
   8.302      set_intr_gate(EVENT_CHECK_VECTOR, event_check_interrupt);
   8.303 @@ -414,9 +402,9 @@ void __init init_IRQ(void)
   8.304      /* Set the clock to HZ Hz */
   8.305  #define CLOCK_TICK_RATE 1193180 /* crystal freq (Hz) */
   8.306  #define LATCH (((CLOCK_TICK_RATE)+(HZ/2))/HZ)
   8.307 -    outb_p(0x34,0x43);		/* binary, mode 2, LSB/MSB, ch 0 */
   8.308 -    outb_p(LATCH & 0xff , 0x40);	/* LSB */
   8.309 -    outb(LATCH >> 8 , 0x40);	/* MSB */
   8.310 +    outb_p(0x34,0x43);           /* binary, mode 2, LSB/MSB, ch 0 */
   8.311 +    outb_p(LATCH & 0xff , 0x40); /* LSB */
   8.312 +    outb(LATCH >> 8 , 0x40);     /* MSB */
   8.313  
   8.314      setup_irq(2, &cascade);
   8.315  }
     9.1 --- a/xen/arch/x86/io_apic.c	Wed Jun 08 12:48:07 2005 +0000
     9.2 +++ b/xen/arch/x86/io_apic.c	Thu Jun 09 09:20:02 2005 +0000
     9.3 @@ -61,16 +61,10 @@ int nr_ioapic_registers[MAX_IO_APICS];
     9.4   */
     9.5  
     9.6  static struct irq_pin_list {
     9.7 -	int apic, pin, next;
     9.8 +    int apic, pin, next;
     9.9  } irq_2_pin[PIN_MAP_SIZE];
    9.10  
    9.11  int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
    9.12 -#ifdef CONFIG_PCI_MSI
    9.13 -#define vector_to_irq(vector) 	\
    9.14 -	(platform_legacy_irq(vector) ? vector : vector_irq[vector])
    9.15 -#else
    9.16 -#define vector_to_irq(vector)	(vector)
    9.17 -#endif
    9.18  
    9.19  /*
    9.20   * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
    9.21 @@ -79,20 +73,20 @@ int vector_irq[NR_VECTORS] = { [0 ... NR
    9.22   */
    9.23  static void add_pin_to_irq(unsigned int irq, int apic, int pin)
    9.24  {
    9.25 -	static int first_free_entry = NR_IRQS;
    9.26 -	struct irq_pin_list *entry = irq_2_pin + irq;
    9.27 +    static int first_free_entry = NR_IRQS;
    9.28 +    struct irq_pin_list *entry = irq_2_pin + irq;
    9.29  
    9.30 -	while (entry->next)
    9.31 -		entry = irq_2_pin + entry->next;
    9.32 +    while (entry->next)
    9.33 +        entry = irq_2_pin + entry->next;
    9.34  
    9.35 -	if (entry->pin != -1) {
    9.36 -		entry->next = first_free_entry;
    9.37 -		entry = irq_2_pin + entry->next;
    9.38 -		if (++first_free_entry >= PIN_MAP_SIZE)
    9.39 -			panic("io_apic.c: whoops");
    9.40 -	}
    9.41 -	entry->apic = apic;
    9.42 -	entry->pin = pin;
    9.43 +    if (entry->pin != -1) {
    9.44 +        entry->next = first_free_entry;
    9.45 +        entry = irq_2_pin + entry->next;
    9.46 +        if (++first_free_entry >= PIN_MAP_SIZE)
    9.47 +            panic("io_apic.c: whoops");
    9.48 +    }
    9.49 +    entry->apic = apic;
    9.50 +    entry->pin = pin;
    9.51  }
    9.52  
    9.53  /*
    9.54 @@ -102,134 +96,134 @@ static void __init replace_pin_at_irq(un
    9.55  				      int oldapic, int oldpin,
    9.56  				      int newapic, int newpin)
    9.57  {
    9.58 -	struct irq_pin_list *entry = irq_2_pin + irq;
    9.59 +    struct irq_pin_list *entry = irq_2_pin + irq;
    9.60  
    9.61 -	while (1) {
    9.62 -		if (entry->apic == oldapic && entry->pin == oldpin) {
    9.63 -			entry->apic = newapic;
    9.64 -			entry->pin = newpin;
    9.65 -		}
    9.66 -		if (!entry->next)
    9.67 -			break;
    9.68 -		entry = irq_2_pin + entry->next;
    9.69 -	}
    9.70 +    while (1) {
    9.71 +        if (entry->apic == oldapic && entry->pin == oldpin) {
    9.72 +            entry->apic = newapic;
    9.73 +            entry->pin = newpin;
    9.74 +        }
    9.75 +        if (!entry->next)
    9.76 +            break;
    9.77 +        entry = irq_2_pin + entry->next;
    9.78 +    }
    9.79  }
    9.80  
    9.81  static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
    9.82  {
    9.83 -	struct irq_pin_list *entry = irq_2_pin + irq;
    9.84 -	unsigned int pin, reg;
    9.85 +    struct irq_pin_list *entry = irq_2_pin + irq;
    9.86 +    unsigned int pin, reg;
    9.87  
    9.88 -	for (;;) {
    9.89 -		pin = entry->pin;
    9.90 -		if (pin == -1)
    9.91 -			break;
    9.92 -		reg = io_apic_read(entry->apic, 0x10 + pin*2);
    9.93 -		reg &= ~disable;
    9.94 -		reg |= enable;
    9.95 -		io_apic_modify(entry->apic, 0x10 + pin*2, reg);
    9.96 -		if (!entry->next)
    9.97 -			break;
    9.98 -		entry = irq_2_pin + entry->next;
    9.99 -	}
   9.100 +    for (;;) {
   9.101 +        pin = entry->pin;
   9.102 +        if (pin == -1)
   9.103 +            break;
   9.104 +        reg = io_apic_read(entry->apic, 0x10 + pin*2);
   9.105 +        reg &= ~disable;
   9.106 +        reg |= enable;
   9.107 +        io_apic_modify(entry->apic, 0x10 + pin*2, reg);
   9.108 +        if (!entry->next)
   9.109 +            break;
   9.110 +        entry = irq_2_pin + entry->next;
   9.111 +    }
   9.112  }
   9.113  
   9.114  /* mask = 1 */
   9.115  static void __mask_IO_APIC_irq (unsigned int irq)
   9.116  {
   9.117 -	__modify_IO_APIC_irq(irq, 0x00010000, 0);
   9.118 +    __modify_IO_APIC_irq(irq, 0x00010000, 0);
   9.119  }
   9.120  
   9.121  /* mask = 0 */
   9.122  static void __unmask_IO_APIC_irq (unsigned int irq)
   9.123  {
   9.124 -	__modify_IO_APIC_irq(irq, 0, 0x00010000);
   9.125 +    __modify_IO_APIC_irq(irq, 0, 0x00010000);
   9.126  }
   9.127  
   9.128  /* trigger = 0 */
   9.129  static void __edge_IO_APIC_irq (unsigned int irq)
   9.130  {
   9.131 -	__modify_IO_APIC_irq(irq, 0, 0x00008000);
   9.132 +    __modify_IO_APIC_irq(irq, 0, 0x00008000);
   9.133  }
   9.134  
   9.135  /* trigger = 1 */
   9.136  static void __level_IO_APIC_irq (unsigned int irq)
   9.137  {
   9.138 -	__modify_IO_APIC_irq(irq, 0x00008000, 0);
   9.139 +    __modify_IO_APIC_irq(irq, 0x00008000, 0);
   9.140  }
   9.141  
   9.142  static void mask_IO_APIC_irq (unsigned int irq)
   9.143  {
   9.144 -	unsigned long flags;
   9.145 +    unsigned long flags;
   9.146  
   9.147 -	spin_lock_irqsave(&ioapic_lock, flags);
   9.148 -	__mask_IO_APIC_irq(irq);
   9.149 -	spin_unlock_irqrestore(&ioapic_lock, flags);
   9.150 +    spin_lock_irqsave(&ioapic_lock, flags);
   9.151 +    __mask_IO_APIC_irq(irq);
   9.152 +    spin_unlock_irqrestore(&ioapic_lock, flags);
   9.153  }
   9.154  
   9.155  static void unmask_IO_APIC_irq (unsigned int irq)
   9.156  {
   9.157 -	unsigned long flags;
   9.158 +    unsigned long flags;
   9.159  
   9.160 -	spin_lock_irqsave(&ioapic_lock, flags);
   9.161 -	__unmask_IO_APIC_irq(irq);
   9.162 -	spin_unlock_irqrestore(&ioapic_lock, flags);
   9.163 +    spin_lock_irqsave(&ioapic_lock, flags);
   9.164 +    __unmask_IO_APIC_irq(irq);
   9.165 +    spin_unlock_irqrestore(&ioapic_lock, flags);
   9.166  }
   9.167  
   9.168  void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
   9.169  {
   9.170 -	struct IO_APIC_route_entry entry;
   9.171 -	unsigned long flags;
   9.172 +    struct IO_APIC_route_entry entry;
   9.173 +    unsigned long flags;
   9.174  	
   9.175 -	/* Check delivery_mode to be sure we're not clearing an SMI pin */
   9.176 -	spin_lock_irqsave(&ioapic_lock, flags);
   9.177 -	*(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
   9.178 -	*(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
   9.179 -	spin_unlock_irqrestore(&ioapic_lock, flags);
   9.180 -	if (entry.delivery_mode == dest_SMI)
   9.181 -		return;
   9.182 +    /* Check delivery_mode to be sure we're not clearing an SMI pin */
   9.183 +    spin_lock_irqsave(&ioapic_lock, flags);
   9.184 +    *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
   9.185 +    *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
   9.186 +    spin_unlock_irqrestore(&ioapic_lock, flags);
   9.187 +    if (entry.delivery_mode == dest_SMI)
   9.188 +        return;
   9.189  
   9.190 -	/*
   9.191 -	 * Disable it in the IO-APIC irq-routing table:
   9.192 -	 */
   9.193 -	memset(&entry, 0, sizeof(entry));
   9.194 -	entry.mask = 1;
   9.195 -	spin_lock_irqsave(&ioapic_lock, flags);
   9.196 -	io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
   9.197 -	io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
   9.198 -	spin_unlock_irqrestore(&ioapic_lock, flags);
   9.199 +    /*
   9.200 +     * Disable it in the IO-APIC irq-routing table:
   9.201 +     */
   9.202 +    memset(&entry, 0, sizeof(entry));
   9.203 +    entry.mask = 1;
   9.204 +    spin_lock_irqsave(&ioapic_lock, flags);
   9.205 +    io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
   9.206 +    io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
   9.207 +    spin_unlock_irqrestore(&ioapic_lock, flags);
   9.208  }
   9.209  
   9.210  static void clear_IO_APIC (void)
   9.211  {
   9.212 -	int apic, pin;
   9.213 +    int apic, pin;
   9.214  
   9.215 -	for (apic = 0; apic < nr_ioapics; apic++)
   9.216 -		for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
   9.217 -			clear_IO_APIC_pin(apic, pin);
   9.218 +    for (apic = 0; apic < nr_ioapics; apic++)
   9.219 +        for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
   9.220 +            clear_IO_APIC_pin(apic, pin);
   9.221  }
   9.222  
   9.223  static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
   9.224  {
   9.225 -	unsigned long flags;
   9.226 -	int pin;
   9.227 -	struct irq_pin_list *entry = irq_2_pin + irq;
   9.228 -	unsigned int apicid_value;
   9.229 +    unsigned long flags;
   9.230 +    int pin;
   9.231 +    struct irq_pin_list *entry = irq_2_pin + irq;
   9.232 +    unsigned int apicid_value;
   9.233  	
   9.234 -	apicid_value = cpu_mask_to_apicid(cpumask);
   9.235 -	/* Prepare to do the io_apic_write */
   9.236 -	apicid_value = apicid_value << 24;
   9.237 -	spin_lock_irqsave(&ioapic_lock, flags);
   9.238 -	for (;;) {
   9.239 -		pin = entry->pin;
   9.240 -		if (pin == -1)
   9.241 -			break;
   9.242 -		io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
   9.243 -		if (!entry->next)
   9.244 -			break;
   9.245 -		entry = irq_2_pin + entry->next;
   9.246 -	}
   9.247 -	spin_unlock_irqrestore(&ioapic_lock, flags);
   9.248 +    apicid_value = cpu_mask_to_apicid(cpumask);
   9.249 +    /* Prepare to do the io_apic_write */
   9.250 +    apicid_value = apicid_value << 24;
   9.251 +    spin_lock_irqsave(&ioapic_lock, flags);
   9.252 +    for (;;) {
   9.253 +        pin = entry->pin;
   9.254 +        if (pin == -1)
   9.255 +            break;
   9.256 +        io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
   9.257 +        if (!entry->next)
   9.258 +            break;
   9.259 +        entry = irq_2_pin + entry->next;
   9.260 +    }
   9.261 +    spin_unlock_irqrestore(&ioapic_lock, flags);
   9.262  }
   9.263  
   9.264  /*
   9.265 @@ -237,16 +231,16 @@ static void set_ioapic_affinity_irq(unsi
   9.266   */
   9.267  static int find_irq_entry(int apic, int pin, int type)
   9.268  {
   9.269 -	int i;
   9.270 +    int i;
   9.271  
   9.272 -	for (i = 0; i < mp_irq_entries; i++)
   9.273 -		if (mp_irqs[i].mpc_irqtype == type &&
   9.274 -		    (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
   9.275 -		     mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
   9.276 -		    mp_irqs[i].mpc_dstirq == pin)
   9.277 -			return i;
   9.278 +    for (i = 0; i < mp_irq_entries; i++)
   9.279 +        if (mp_irqs[i].mpc_irqtype == type &&
   9.280 +            (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
   9.281 +             mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
   9.282 +            mp_irqs[i].mpc_dstirq == pin)
   9.283 +            return i;
   9.284  
   9.285 -	return -1;
   9.286 +    return -1;
   9.287  }
   9.288  
   9.289  /*
   9.290 @@ -254,22 +248,22 @@ static int find_irq_entry(int apic, int 
   9.291   */
   9.292  static int find_isa_irq_pin(int irq, int type)
   9.293  {
   9.294 -	int i;
   9.295 +    int i;
   9.296  
   9.297 -	for (i = 0; i < mp_irq_entries; i++) {
   9.298 -		int lbus = mp_irqs[i].mpc_srcbus;
   9.299 +    for (i = 0; i < mp_irq_entries; i++) {
   9.300 +        int lbus = mp_irqs[i].mpc_srcbus;
   9.301  
   9.302 -		if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
   9.303 -		     mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
   9.304 -		     mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
   9.305 -		     mp_bus_id_to_type[lbus] == MP_BUS_NEC98
   9.306 -		    ) &&
   9.307 -		    (mp_irqs[i].mpc_irqtype == type) &&
   9.308 -		    (mp_irqs[i].mpc_srcbusirq == irq))
   9.309 +        if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
   9.310 +             mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
   9.311 +             mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
   9.312 +             mp_bus_id_to_type[lbus] == MP_BUS_NEC98
   9.313 +            ) &&
   9.314 +            (mp_irqs[i].mpc_irqtype == type) &&
   9.315 +            (mp_irqs[i].mpc_srcbusirq == irq))
   9.316  
   9.317 -			return mp_irqs[i].mpc_dstirq;
   9.318 -	}
   9.319 -	return -1;
   9.320 +            return mp_irqs[i].mpc_dstirq;
   9.321 +    }
   9.322 +    return -1;
   9.323  }
   9.324  
   9.325  /*
   9.326 @@ -278,68 +272,28 @@ static int find_isa_irq_pin(int irq, int
   9.327   */
   9.328  static int pin_2_irq(int idx, int apic, int pin);
   9.329  
   9.330 -int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
   9.331 -{
   9.332 -	int apic, i, best_guess = -1;
   9.333 -
   9.334 -	apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
   9.335 -		"slot:%d, pin:%d.\n", bus, slot, pin);
   9.336 -	if (mp_bus_id_to_pci_bus[bus] == -1) {
   9.337 -		printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
   9.338 -		return -1;
   9.339 -	}
   9.340 -	for (i = 0; i < mp_irq_entries; i++) {
   9.341 -		int lbus = mp_irqs[i].mpc_srcbus;
   9.342 -
   9.343 -		for (apic = 0; apic < nr_ioapics; apic++)
   9.344 -			if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
   9.345 -			    mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
   9.346 -				break;
   9.347 -
   9.348 -		if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
   9.349 -		    !mp_irqs[i].mpc_irqtype &&
   9.350 -		    (bus == lbus) &&
   9.351 -		    (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
   9.352 -			int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
   9.353 -
   9.354 -			if (!(apic || IO_APIC_IRQ(irq)))
   9.355 -				continue;
   9.356 -
   9.357 -			if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
   9.358 -				return irq;
   9.359 -			/*
   9.360 -			 * Use the first all-but-pin matching entry as a
   9.361 -			 * best-guess fuzzy result for broken mptables.
   9.362 -			 */
   9.363 -			if (best_guess < 0)
   9.364 -				best_guess = irq;
   9.365 -		}
   9.366 -	}
   9.367 -	return best_guess;
   9.368 -}
   9.369 -
   9.370  /*
   9.371 - * This function currently is only a helper for the i386 smp boot process where 
   9.372 - * we need to reprogram the ioredtbls to cater for the cpus which have come online
   9.373 - * so mask in all cases should simply be TARGET_CPUS
   9.374 + * This function currently is only a helper for the i386 smp boot process where
   9.375 + * we need to reprogram the ioredtbls to cater for the cpus which have come
   9.376 + * online so mask in all cases should simply be TARGET_CPUS
   9.377   */
   9.378  void __init setup_ioapic_dest(void)
   9.379  {
   9.380 -	int pin, ioapic, irq, irq_entry;
   9.381 +    int pin, ioapic, irq, irq_entry;
   9.382  
   9.383 -	if (skip_ioapic_setup == 1)
   9.384 -		return;
   9.385 +    if (skip_ioapic_setup == 1)
   9.386 +        return;
   9.387  
   9.388 -	for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
   9.389 -		for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
   9.390 -			irq_entry = find_irq_entry(ioapic, pin, mp_INT);
   9.391 -			if (irq_entry == -1)
   9.392 -				continue;
   9.393 -			irq = pin_2_irq(irq_entry, ioapic, pin);
   9.394 -			set_ioapic_affinity_irq(irq, TARGET_CPUS);
   9.395 -		}
   9.396 +    for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
   9.397 +        for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
   9.398 +            irq_entry = find_irq_entry(ioapic, pin, mp_INT);
   9.399 +            if (irq_entry == -1)
   9.400 +                continue;
   9.401 +            irq = pin_2_irq(irq_entry, ioapic, pin);
   9.402 +            set_ioapic_affinity_irq(irq, TARGET_CPUS);
   9.403 +        }
   9.404  
   9.405 -	}
   9.406 +    }
   9.407  }
   9.408  
   9.409  /*
   9.410 @@ -347,13 +301,13 @@ void __init setup_ioapic_dest(void)
   9.411   */
   9.412  static int EISA_ELCR(unsigned int irq)
   9.413  {
   9.414 -	if (irq < 16) {
   9.415 -		unsigned int port = 0x4d0 + (irq >> 3);
   9.416 -		return (inb(port) >> (irq & 7)) & 1;
   9.417 -	}
   9.418 -	apic_printk(APIC_VERBOSE, KERN_INFO
   9.419 -			"Broken MPtable reports ISA irq %d\n", irq);
   9.420 -	return 0;
   9.421 +    if (irq < 16) {
   9.422 +        unsigned int port = 0x4d0 + (irq >> 3);
   9.423 +        return (inb(port) >> (irq & 7)) & 1;
   9.424 +    }
   9.425 +    apic_printk(APIC_VERBOSE, KERN_INFO
   9.426 +                "Broken MPtable reports ISA irq %d\n", irq);
   9.427 +    return 0;
   9.428  }
   9.429  
   9.430  /* EISA interrupts are always polarity zero and can be edge or level
   9.431 @@ -390,227 +344,227 @@ static int EISA_ELCR(unsigned int irq)
   9.432  
   9.433  static int __init MPBIOS_polarity(int idx)
   9.434  {
   9.435 -	int bus = mp_irqs[idx].mpc_srcbus;
   9.436 -	int polarity;
   9.437 +    int bus = mp_irqs[idx].mpc_srcbus;
   9.438 +    int polarity;
   9.439  
   9.440 -	/*
   9.441 -	 * Determine IRQ line polarity (high active or low active):
   9.442 -	 */
   9.443 -	switch (mp_irqs[idx].mpc_irqflag & 3)
   9.444 -	{
   9.445 -		case 0: /* conforms, ie. bus-type dependent polarity */
   9.446 -		{
   9.447 -			switch (mp_bus_id_to_type[bus])
   9.448 -			{
   9.449 -				case MP_BUS_ISA: /* ISA pin */
   9.450 -				{
   9.451 -					polarity = default_ISA_polarity(idx);
   9.452 -					break;
   9.453 -				}
   9.454 -				case MP_BUS_EISA: /* EISA pin */
   9.455 -				{
   9.456 -					polarity = default_EISA_polarity(idx);
   9.457 -					break;
   9.458 -				}
   9.459 -				case MP_BUS_PCI: /* PCI pin */
   9.460 -				{
   9.461 -					polarity = default_PCI_polarity(idx);
   9.462 -					break;
   9.463 -				}
   9.464 -				case MP_BUS_MCA: /* MCA pin */
   9.465 -				{
   9.466 -					polarity = default_MCA_polarity(idx);
   9.467 -					break;
   9.468 -				}
   9.469 -				case MP_BUS_NEC98: /* NEC 98 pin */
   9.470 -				{
   9.471 -					polarity = default_NEC98_polarity(idx);
   9.472 -					break;
   9.473 -				}
   9.474 -				default:
   9.475 -				{
   9.476 -					printk(KERN_WARNING "broken BIOS!!\n");
   9.477 -					polarity = 1;
   9.478 -					break;
   9.479 -				}
   9.480 -			}
   9.481 -			break;
   9.482 -		}
   9.483 -		case 1: /* high active */
   9.484 -		{
   9.485 -			polarity = 0;
   9.486 -			break;
   9.487 -		}
   9.488 -		case 2: /* reserved */
   9.489 -		{
   9.490 -			printk(KERN_WARNING "broken BIOS!!\n");
   9.491 -			polarity = 1;
   9.492 -			break;
   9.493 -		}
   9.494 -		case 3: /* low active */
   9.495 -		{
   9.496 -			polarity = 1;
   9.497 -			break;
   9.498 -		}
   9.499 -		default: /* invalid */
   9.500 -		{
   9.501 -			printk(KERN_WARNING "broken BIOS!!\n");
   9.502 -			polarity = 1;
   9.503 -			break;
   9.504 -		}
   9.505 -	}
   9.506 -	return polarity;
   9.507 +    /*
   9.508 +     * Determine IRQ line polarity (high active or low active):
   9.509 +     */
   9.510 +    switch (mp_irqs[idx].mpc_irqflag & 3)
   9.511 +    {
   9.512 +    case 0: /* conforms, ie. bus-type dependent polarity */
   9.513 +    {
   9.514 +        switch (mp_bus_id_to_type[bus])
   9.515 +        {
   9.516 +        case MP_BUS_ISA: /* ISA pin */
   9.517 +        {
   9.518 +            polarity = default_ISA_polarity(idx);
   9.519 +            break;
   9.520 +        }
   9.521 +        case MP_BUS_EISA: /* EISA pin */
   9.522 +        {
   9.523 +            polarity = default_EISA_polarity(idx);
   9.524 +            break;
   9.525 +        }
   9.526 +        case MP_BUS_PCI: /* PCI pin */
   9.527 +        {
   9.528 +            polarity = default_PCI_polarity(idx);
   9.529 +            break;
   9.530 +        }
   9.531 +        case MP_BUS_MCA: /* MCA pin */
   9.532 +        {
   9.533 +            polarity = default_MCA_polarity(idx);
   9.534 +            break;
   9.535 +        }
   9.536 +        case MP_BUS_NEC98: /* NEC 98 pin */
   9.537 +        {
   9.538 +            polarity = default_NEC98_polarity(idx);
   9.539 +            break;
   9.540 +        }
   9.541 +        default:
   9.542 +        {
   9.543 +            printk(KERN_WARNING "broken BIOS!!\n");
   9.544 +            polarity = 1;
   9.545 +            break;
   9.546 +        }
   9.547 +        }
   9.548 +        break;
   9.549 +    }
   9.550 +    case 1: /* high active */
   9.551 +    {
   9.552 +        polarity = 0;
   9.553 +        break;
   9.554 +    }
   9.555 +    case 2: /* reserved */
   9.556 +    {
   9.557 +        printk(KERN_WARNING "broken BIOS!!\n");
   9.558 +        polarity = 1;
   9.559 +        break;
   9.560 +    }
   9.561 +    case 3: /* low active */
   9.562 +    {
   9.563 +        polarity = 1;
   9.564 +        break;
   9.565 +    }
   9.566 +    default: /* invalid */
   9.567 +    {
   9.568 +        printk(KERN_WARNING "broken BIOS!!\n");
   9.569 +        polarity = 1;
   9.570 +        break;
   9.571 +    }
   9.572 +    }
   9.573 +    return polarity;
   9.574  }
   9.575  
   9.576  static int MPBIOS_trigger(int idx)
   9.577  {
   9.578 -	int bus = mp_irqs[idx].mpc_srcbus;
   9.579 -	int trigger;
   9.580 +    int bus = mp_irqs[idx].mpc_srcbus;
   9.581 +    int trigger;
   9.582  
   9.583 -	/*
   9.584 -	 * Determine IRQ trigger mode (edge or level sensitive):
   9.585 -	 */
   9.586 -	switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
   9.587 -	{
   9.588 -		case 0: /* conforms, ie. bus-type dependent */
   9.589 -		{
   9.590 -			switch (mp_bus_id_to_type[bus])
   9.591 -			{
   9.592 -				case MP_BUS_ISA: /* ISA pin */
   9.593 -				{
   9.594 -					trigger = default_ISA_trigger(idx);
   9.595 -					break;
   9.596 -				}
   9.597 -				case MP_BUS_EISA: /* EISA pin */
   9.598 -				{
   9.599 -					trigger = default_EISA_trigger(idx);
   9.600 -					break;
   9.601 -				}
   9.602 -				case MP_BUS_PCI: /* PCI pin */
   9.603 -				{
   9.604 -					trigger = default_PCI_trigger(idx);
   9.605 -					break;
   9.606 -				}
   9.607 -				case MP_BUS_MCA: /* MCA pin */
   9.608 -				{
   9.609 -					trigger = default_MCA_trigger(idx);
   9.610 -					break;
   9.611 -				}
   9.612 -				case MP_BUS_NEC98: /* NEC 98 pin */
   9.613 -				{
   9.614 -					trigger = default_NEC98_trigger(idx);
   9.615 -					break;
   9.616 -				}
   9.617 -				default:
   9.618 -				{
   9.619 -					printk(KERN_WARNING "broken BIOS!!\n");
   9.620 -					trigger = 1;
   9.621 -					break;
   9.622 -				}
   9.623 -			}
   9.624 -			break;
   9.625 -		}
   9.626 -		case 1: /* edge */
   9.627 -		{
   9.628 -			trigger = 0;
   9.629 -			break;
   9.630 -		}
   9.631 -		case 2: /* reserved */
   9.632 -		{
   9.633 -			printk(KERN_WARNING "broken BIOS!!\n");
   9.634 -			trigger = 1;
   9.635 -			break;
   9.636 -		}
   9.637 -		case 3: /* level */
   9.638 -		{
   9.639 -			trigger = 1;
   9.640 -			break;
   9.641 -		}
   9.642 -		default: /* invalid */
   9.643 -		{
   9.644 -			printk(KERN_WARNING "broken BIOS!!\n");
   9.645 -			trigger = 0;
   9.646 -			break;
   9.647 -		}
   9.648 -	}
   9.649 -	return trigger;
   9.650 +    /*
   9.651 +     * Determine IRQ trigger mode (edge or level sensitive):
   9.652 +     */
   9.653 +    switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
   9.654 +    {
   9.655 +    case 0: /* conforms, ie. bus-type dependent */
   9.656 +    {
   9.657 +        switch (mp_bus_id_to_type[bus])
   9.658 +        {
   9.659 +        case MP_BUS_ISA: /* ISA pin */
   9.660 +        {
   9.661 +            trigger = default_ISA_trigger(idx);
   9.662 +            break;
   9.663 +        }
   9.664 +        case MP_BUS_EISA: /* EISA pin */
   9.665 +        {
   9.666 +            trigger = default_EISA_trigger(idx);
   9.667 +            break;
   9.668 +        }
   9.669 +        case MP_BUS_PCI: /* PCI pin */
   9.670 +        {
   9.671 +            trigger = default_PCI_trigger(idx);
   9.672 +            break;
   9.673 +        }
   9.674 +        case MP_BUS_MCA: /* MCA pin */
   9.675 +        {
   9.676 +            trigger = default_MCA_trigger(idx);
   9.677 +            break;
   9.678 +        }
   9.679 +        case MP_BUS_NEC98: /* NEC 98 pin */
   9.680 +        {
   9.681 +            trigger = default_NEC98_trigger(idx);
   9.682 +            break;
   9.683 +        }
   9.684 +        default:
   9.685 +        {
   9.686 +            printk(KERN_WARNING "broken BIOS!!\n");
   9.687 +            trigger = 1;
   9.688 +            break;
   9.689 +        }
   9.690 +        }
   9.691 +        break;
   9.692 +    }
   9.693 +    case 1: /* edge */
   9.694 +    {
   9.695 +        trigger = 0;
   9.696 +        break;
   9.697 +    }
   9.698 +    case 2: /* reserved */
   9.699 +    {
   9.700 +        printk(KERN_WARNING "broken BIOS!!\n");
   9.701 +        trigger = 1;
   9.702 +        break;
   9.703 +    }
   9.704 +    case 3: /* level */
   9.705 +    {
   9.706 +        trigger = 1;
   9.707 +        break;
   9.708 +    }
   9.709 +    default: /* invalid */
   9.710 +    {
   9.711 +        printk(KERN_WARNING "broken BIOS!!\n");
   9.712 +        trigger = 0;
   9.713 +        break;
   9.714 +    }
   9.715 +    }
   9.716 +    return trigger;
   9.717  }
   9.718  
   9.719  static inline int irq_polarity(int idx)
   9.720  {
   9.721 -	return MPBIOS_polarity(idx);
   9.722 +    return MPBIOS_polarity(idx);
   9.723  }
   9.724  
   9.725  static inline int irq_trigger(int idx)
   9.726  {
   9.727 -	return MPBIOS_trigger(idx);
   9.728 +    return MPBIOS_trigger(idx);
   9.729  }
   9.730  
   9.731  static int pin_2_irq(int idx, int apic, int pin)
   9.732  {
   9.733 -	int irq, i;
   9.734 -	int bus = mp_irqs[idx].mpc_srcbus;
   9.735 +    int irq, i;
   9.736 +    int bus = mp_irqs[idx].mpc_srcbus;
   9.737  
   9.738 -	/*
   9.739 -	 * Debugging check, we are in big trouble if this message pops up!
   9.740 -	 */
   9.741 -	if (mp_irqs[idx].mpc_dstirq != pin)
   9.742 -		printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
   9.743 +    /*
   9.744 +     * Debugging check, we are in big trouble if this message pops up!
   9.745 +     */
   9.746 +    if (mp_irqs[idx].mpc_dstirq != pin)
   9.747 +        printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
   9.748  
   9.749 -	switch (mp_bus_id_to_type[bus])
   9.750 -	{
   9.751 -		case MP_BUS_ISA: /* ISA pin */
   9.752 -		case MP_BUS_EISA:
   9.753 -		case MP_BUS_MCA:
   9.754 -		case MP_BUS_NEC98:
   9.755 -		{
   9.756 -			irq = mp_irqs[idx].mpc_srcbusirq;
   9.757 -			break;
   9.758 -		}
   9.759 -		case MP_BUS_PCI: /* PCI pin */
   9.760 -		{
   9.761 -			/*
   9.762 -			 * PCI IRQs are mapped in order
   9.763 -			 */
   9.764 -			i = irq = 0;
   9.765 -			while (i < apic)
   9.766 -				irq += nr_ioapic_registers[i++];
   9.767 -			irq += pin;
   9.768 +    switch (mp_bus_id_to_type[bus])
   9.769 +    {
   9.770 +    case MP_BUS_ISA: /* ISA pin */
   9.771 +    case MP_BUS_EISA:
   9.772 +    case MP_BUS_MCA:
   9.773 +    case MP_BUS_NEC98:
   9.774 +    {
   9.775 +        irq = mp_irqs[idx].mpc_srcbusirq;
   9.776 +        break;
   9.777 +    }
   9.778 +    case MP_BUS_PCI: /* PCI pin */
   9.779 +    {
   9.780 +        /*
   9.781 +         * PCI IRQs are mapped in order
   9.782 +         */
   9.783 +        i = irq = 0;
   9.784 +        while (i < apic)
   9.785 +            irq += nr_ioapic_registers[i++];
   9.786 +        irq += pin;
   9.787  
   9.788 -			/*
   9.789 -			 * For MPS mode, so far only needed by ES7000 platform
   9.790 -			 */
   9.791 -			if (ioapic_renumber_irq)
   9.792 -				irq = ioapic_renumber_irq(apic, irq);
   9.793 +        /*
   9.794 +         * For MPS mode, so far only needed by ES7000 platform
   9.795 +         */
   9.796 +        if (ioapic_renumber_irq)
   9.797 +            irq = ioapic_renumber_irq(apic, irq);
   9.798  
   9.799 -			break;
   9.800 -		}
   9.801 -		default:
   9.802 -		{
   9.803 -			printk(KERN_ERR "unknown bus type %d.\n",bus); 
   9.804 -			irq = 0;
   9.805 -			break;
   9.806 -		}
   9.807 -	}
   9.808 +        break;
   9.809 +    }
   9.810 +    default:
   9.811 +    {
   9.812 +        printk(KERN_ERR "unknown bus type %d.\n",bus); 
   9.813 +        irq = 0;
   9.814 +        break;
   9.815 +    }
   9.816 +    }
   9.817  
   9.818 -	return irq;
   9.819 +    return irq;
   9.820  }
   9.821  
   9.822  static inline int IO_APIC_irq_trigger(int irq)
   9.823  {
   9.824 -	int apic, idx, pin;
   9.825 +    int apic, idx, pin;
   9.826  
   9.827 -	for (apic = 0; apic < nr_ioapics; apic++) {
   9.828 -		for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
   9.829 -			idx = find_irq_entry(apic,pin,mp_INT);
   9.830 -			if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
   9.831 -				return irq_trigger(idx);
   9.832 -		}
   9.833 -	}
   9.834 -	/*
   9.835 -	 * nonexistent IRQs are edge default
   9.836 -	 */
   9.837 -	return 0;
   9.838 +    for (apic = 0; apic < nr_ioapics; apic++) {
   9.839 +        for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
   9.840 +            idx = find_irq_entry(apic,pin,mp_INT);
   9.841 +            if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
   9.842 +                return irq_trigger(idx);
   9.843 +        }
   9.844 +    }
   9.845 +    /*
   9.846 +     * nonexistent IRQs are edge default
   9.847 +     */
   9.848 +    return 0;
   9.849  }
   9.850  
   9.851  /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
   9.852 @@ -618,34 +572,34 @@ u8 irq_vector[NR_IRQ_VECTORS];
   9.853  
   9.854  int assign_irq_vector(int irq)
   9.855  {
   9.856 -	static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
   9.857 +    static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
   9.858  
   9.859 -	BUG_ON(irq >= NR_IRQ_VECTORS);
   9.860 -	if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
   9.861 -		return IO_APIC_VECTOR(irq);
   9.862 -next:
   9.863 -	current_vector += 8;
   9.864 +    BUG_ON(irq >= NR_IRQ_VECTORS);
   9.865 +    if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
   9.866 +        return IO_APIC_VECTOR(irq);
   9.867 + next:
   9.868 +    current_vector += 8;
   9.869  
   9.870 -	/* Skip the hypercall vector. */
   9.871 -	if (current_vector == HYPERCALL_VECTOR)
   9.872 -		goto next;
   9.873 +    /* Skip the hypercall vector. */
   9.874 +    if (current_vector == HYPERCALL_VECTOR)
   9.875 +        goto next;
   9.876  
   9.877 -	/* Skip the Linux/BSD fast-trap vector. */
   9.878 -	if (current_vector == 0x80)
   9.879 -		goto next;
   9.880 +    /* Skip the Linux/BSD fast-trap vector. */
   9.881 +    if (current_vector == 0x80)
   9.882 +        goto next;
   9.883  
   9.884 -	if (current_vector >= FIRST_SYSTEM_VECTOR) {
   9.885 -		offset++;
   9.886 -		if (!(offset%8))
   9.887 -			return -ENOSPC;
   9.888 -		current_vector = FIRST_DEVICE_VECTOR + offset;
   9.889 -	}
   9.890 +    if (current_vector >= FIRST_SYSTEM_VECTOR) {
   9.891 +        offset++;
   9.892 +        if (!(offset%8))
   9.893 +            return -ENOSPC;
   9.894 +        current_vector = FIRST_DEVICE_VECTOR + offset;
   9.895 +    }
   9.896  
   9.897 -	vector_irq[current_vector] = irq;
   9.898 -	if (irq != AUTO_ASSIGN)
   9.899 -		IO_APIC_VECTOR(irq) = current_vector;
   9.900 +    vector_irq[current_vector] = irq;
   9.901 +    if (irq != AUTO_ASSIGN)
   9.902 +        IO_APIC_VECTOR(irq) = current_vector;
   9.903  
   9.904 -	return current_vector;
   9.905 +    return current_vector;
   9.906  }
   9.907  
   9.908  static struct hw_interrupt_type ioapic_level_type;
   9.909 @@ -657,97 +611,87 @@ static struct hw_interrupt_type ioapic_e
   9.910  
   9.911  static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
   9.912  {
   9.913 -	if (use_pci_vector() && !platform_legacy_irq(irq)) {
   9.914 -		if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
   9.915 -				trigger == IOAPIC_LEVEL)
   9.916 -			irq_desc[vector].handler = &ioapic_level_type;
   9.917 -		else
   9.918 -			irq_desc[vector].handler = &ioapic_edge_type;
   9.919 -		set_intr_gate(vector, interrupt[vector]);
   9.920 -	} else	{
   9.921 -		if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
   9.922 -				trigger == IOAPIC_LEVEL)
   9.923 -			irq_desc[irq].handler = &ioapic_level_type;
   9.924 -		else
   9.925 -			irq_desc[irq].handler = &ioapic_edge_type;
   9.926 -		set_intr_gate(vector, interrupt[irq]);
   9.927 -	}
   9.928 +    if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
   9.929 +        trigger == IOAPIC_LEVEL)
   9.930 +        irq_desc[vector].handler = &ioapic_level_type;
   9.931 +    else
   9.932 +        irq_desc[vector].handler = &ioapic_edge_type;
   9.933  }
   9.934  
   9.935  void __init setup_IO_APIC_irqs(void)
   9.936  {
   9.937 -	struct IO_APIC_route_entry entry;
   9.938 -	int apic, pin, idx, irq, first_notcon = 1, vector;
   9.939 -	unsigned long flags;
   9.940 +    struct IO_APIC_route_entry entry;
   9.941 +    int apic, pin, idx, irq, first_notcon = 1, vector;
   9.942 +    unsigned long flags;
   9.943  
   9.944 -	apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
   9.945 +    apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
   9.946  
   9.947 -	for (apic = 0; apic < nr_ioapics; apic++) {
   9.948 +    for (apic = 0; apic < nr_ioapics; apic++) {
   9.949  	for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
   9.950  
   9.951 -		/*
   9.952 -		 * add it to the IO-APIC irq-routing table:
   9.953 -		 */
   9.954 -		memset(&entry,0,sizeof(entry));
   9.955 +            /*
   9.956 +             * add it to the IO-APIC irq-routing table:
   9.957 +             */
   9.958 +            memset(&entry,0,sizeof(entry));
   9.959  
   9.960 -		entry.delivery_mode = INT_DELIVERY_MODE;
   9.961 -		entry.dest_mode = INT_DEST_MODE;
   9.962 -		entry.mask = 0;				/* enable IRQ */
   9.963 -		entry.dest.logical.logical_dest = 
   9.964 -					cpu_mask_to_apicid(TARGET_CPUS);
   9.965 +            entry.delivery_mode = INT_DELIVERY_MODE;
   9.966 +            entry.dest_mode = INT_DEST_MODE;
   9.967 +            entry.mask = 0;				/* enable IRQ */
   9.968 +            entry.dest.logical.logical_dest = 
   9.969 +                cpu_mask_to_apicid(TARGET_CPUS);
   9.970  
   9.971 -		idx = find_irq_entry(apic,pin,mp_INT);
   9.972 -		if (idx == -1) {
   9.973 -			if (first_notcon) {
   9.974 -				apic_printk(APIC_VERBOSE, KERN_DEBUG
   9.975 -						" IO-APIC (apicid-pin) %d-%d",
   9.976 -						mp_ioapics[apic].mpc_apicid,
   9.977 -						pin);
   9.978 -				first_notcon = 0;
   9.979 -			} else
   9.980 -				apic_printk(APIC_VERBOSE, ", %d-%d",
   9.981 -					mp_ioapics[apic].mpc_apicid, pin);
   9.982 -			continue;
   9.983 -		}
   9.984 +            idx = find_irq_entry(apic,pin,mp_INT);
   9.985 +            if (idx == -1) {
   9.986 +                if (first_notcon) {
   9.987 +                    apic_printk(APIC_VERBOSE, KERN_DEBUG
   9.988 +                                " IO-APIC (apicid-pin) %d-%d",
   9.989 +                                mp_ioapics[apic].mpc_apicid,
   9.990 +                                pin);
   9.991 +                    first_notcon = 0;
   9.992 +                } else
   9.993 +                    apic_printk(APIC_VERBOSE, ", %d-%d",
   9.994 +                                mp_ioapics[apic].mpc_apicid, pin);
   9.995 +                continue;
   9.996 +            }
   9.997  
   9.998 -		entry.trigger = irq_trigger(idx);
   9.999 -		entry.polarity = irq_polarity(idx);
  9.1000 +            entry.trigger = irq_trigger(idx);
  9.1001 +            entry.polarity = irq_polarity(idx);
  9.1002  
  9.1003 -		if (irq_trigger(idx)) {
  9.1004 -			entry.trigger = 1;
  9.1005 -			entry.mask = 1;
  9.1006 -		}
  9.1007 +            if (irq_trigger(idx)) {
  9.1008 +                entry.trigger = 1;
  9.1009 +                entry.mask = 1;
  9.1010 +            }
  9.1011  
  9.1012 -		irq = pin_2_irq(idx, apic, pin);
  9.1013 -		/*
  9.1014 -		 * skip adding the timer int on secondary nodes, which causes
  9.1015 -		 * a small but painful rift in the time-space continuum
  9.1016 -		 */
  9.1017 -		if (multi_timer_check(apic, irq))
  9.1018 -			continue;
  9.1019 -		else
  9.1020 -			add_pin_to_irq(irq, apic, pin);
  9.1021 +            irq = pin_2_irq(idx, apic, pin);
  9.1022 +            /*
  9.1023 +             * skip adding the timer int on secondary nodes, which causes
  9.1024 +             * a small but painful rift in the time-space continuum
  9.1025 +             */
  9.1026 +            if (multi_timer_check(apic, irq))
  9.1027 +                continue;
  9.1028 +            else
  9.1029 +                add_pin_to_irq(irq, apic, pin);
  9.1030  
  9.1031 -		if (!apic && !IO_APIC_IRQ(irq))
  9.1032 -			continue;
  9.1033 +            if (!apic && !IO_APIC_IRQ(irq))
  9.1034 +                continue;
  9.1035  
  9.1036 -		if (IO_APIC_IRQ(irq)) {
  9.1037 -			vector = assign_irq_vector(irq);
  9.1038 -			entry.vector = vector;
  9.1039 -			ioapic_register_intr(irq, vector, IOAPIC_AUTO);
  9.1040 +            if (IO_APIC_IRQ(irq)) {
  9.1041 +                vector = assign_irq_vector(irq);
  9.1042 +                entry.vector = vector;
  9.1043 +                ioapic_register_intr(irq, vector, IOAPIC_AUTO);
  9.1044  		
  9.1045 -			if (!apic && (irq < 16))
  9.1046 -				disable_8259A_irq(irq);
  9.1047 -		}
  9.1048 -		spin_lock_irqsave(&ioapic_lock, flags);
  9.1049 -		io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
  9.1050 -		io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
  9.1051 -		spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1052 +                if (!apic && (irq < 16))
  9.1053 +                    disable_8259A_irq(irq);
  9.1054 +            }
  9.1055 +            spin_lock_irqsave(&ioapic_lock, flags);
  9.1056 +            io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
  9.1057 +            io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
  9.1058 +            spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1059  	}
  9.1060 -	}
  9.1061 +    }
  9.1062  
  9.1063 -	if (!first_notcon)
  9.1064 -		apic_printk(APIC_VERBOSE, " not connected.\n");
  9.1065 +    if (!first_notcon)
  9.1066 +        apic_printk(APIC_VERBOSE, " not connected.\n");
  9.1067  }
  9.1068  
  9.1069  /*
  9.1070 @@ -755,43 +699,43 @@ void __init setup_IO_APIC_irqs(void)
  9.1071   */
  9.1072  void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
  9.1073  {
  9.1074 -	struct IO_APIC_route_entry entry;
  9.1075 -	unsigned long flags;
  9.1076 +    struct IO_APIC_route_entry entry;
  9.1077 +    unsigned long flags;
  9.1078  
  9.1079 -	memset(&entry,0,sizeof(entry));
  9.1080 +    memset(&entry,0,sizeof(entry));
  9.1081  
  9.1082 -	disable_8259A_irq(0);
  9.1083 +    disable_8259A_irq(0);
  9.1084  
  9.1085 -	/* mask LVT0 */
  9.1086 -	apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
  9.1087 +    /* mask LVT0 */
  9.1088 +    apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
  9.1089  
  9.1090 -	/*
  9.1091 -	 * We use logical delivery to get the timer IRQ
  9.1092 -	 * to the first CPU.
  9.1093 -	 */
  9.1094 -	entry.dest_mode = INT_DEST_MODE;
  9.1095 -	entry.mask = 0;					/* unmask IRQ now */
  9.1096 -	entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
  9.1097 -	entry.delivery_mode = INT_DELIVERY_MODE;
  9.1098 -	entry.polarity = 0;
  9.1099 -	entry.trigger = 0;
  9.1100 -	entry.vector = vector;
  9.1101 +    /*
  9.1102 +     * We use logical delivery to get the timer IRQ
  9.1103 +     * to the first CPU.
  9.1104 +     */
  9.1105 +    entry.dest_mode = INT_DEST_MODE;
  9.1106 +    entry.mask = 0;					/* unmask IRQ now */
  9.1107 +    entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
  9.1108 +    entry.delivery_mode = INT_DELIVERY_MODE;
  9.1109 +    entry.polarity = 0;
  9.1110 +    entry.trigger = 0;
  9.1111 +    entry.vector = vector;
  9.1112  
  9.1113 -	/*
  9.1114 -	 * The timer IRQ doesn't have to know that behind the
  9.1115 -	 * scene we have a 8259A-master in AEOI mode ...
  9.1116 -	 */
  9.1117 -	irq_desc[0].handler = &ioapic_edge_type;
  9.1118 +    /*
  9.1119 +     * The timer IRQ doesn't have to know that behind the
  9.1120 +     * scene we have a 8259A-master in AEOI mode ...
  9.1121 +     */
  9.1122 +    irq_desc[IO_APIC_VECTOR(0)].handler = &ioapic_edge_type;
  9.1123  
  9.1124 -	/*
  9.1125 -	 * Add it to the IO-APIC irq-routing table:
  9.1126 -	 */
  9.1127 -	spin_lock_irqsave(&ioapic_lock, flags);
  9.1128 -	io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
  9.1129 -	io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
  9.1130 -	spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1131 +    /*
  9.1132 +     * Add it to the IO-APIC irq-routing table:
  9.1133 +     */
  9.1134 +    spin_lock_irqsave(&ioapic_lock, flags);
  9.1135 +    io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
  9.1136 +    io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
  9.1137 +    spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1138  
  9.1139 -	enable_8259A_irq(0);
  9.1140 +    enable_8259A_irq(0);
  9.1141  }
  9.1142  
  9.1143  static inline void UNEXPECTED_IO_APIC(void)
  9.1144 @@ -800,36 +744,36 @@ static inline void UNEXPECTED_IO_APIC(vo
  9.1145  
  9.1146  void __init print_IO_APIC(void)
  9.1147  {
  9.1148 -	int apic, i;
  9.1149 -	union IO_APIC_reg_00 reg_00;
  9.1150 -	union IO_APIC_reg_01 reg_01;
  9.1151 -	union IO_APIC_reg_02 reg_02;
  9.1152 -	union IO_APIC_reg_03 reg_03;
  9.1153 -	unsigned long flags;
  9.1154 +    int apic, i;
  9.1155 +    union IO_APIC_reg_00 reg_00;
  9.1156 +    union IO_APIC_reg_01 reg_01;
  9.1157 +    union IO_APIC_reg_02 reg_02;
  9.1158 +    union IO_APIC_reg_03 reg_03;
  9.1159 +    unsigned long flags;
  9.1160  
  9.1161 -	if (apic_verbosity == APIC_QUIET)
  9.1162 -		return;
  9.1163 +    if (apic_verbosity == APIC_QUIET)
  9.1164 +        return;
  9.1165  
  9.1166 - 	printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
  9.1167 -	for (i = 0; i < nr_ioapics; i++)
  9.1168 -		printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
  9.1169 -		       mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
  9.1170 +    printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
  9.1171 +    for (i = 0; i < nr_ioapics; i++)
  9.1172 +        printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
  9.1173 +               mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
  9.1174  
  9.1175 -	/*
  9.1176 -	 * We are a bit conservative about what we expect.  We have to
  9.1177 -	 * know about every hardware change ASAP.
  9.1178 -	 */
  9.1179 -	printk(KERN_INFO "testing the IO APIC.......................\n");
  9.1180 +    /*
  9.1181 +     * We are a bit conservative about what we expect.  We have to
  9.1182 +     * know about every hardware change ASAP.
  9.1183 +     */
  9.1184 +    printk(KERN_INFO "testing the IO APIC.......................\n");
  9.1185  
  9.1186 -	for (apic = 0; apic < nr_ioapics; apic++) {
  9.1187 +    for (apic = 0; apic < nr_ioapics; apic++) {
  9.1188  
  9.1189  	spin_lock_irqsave(&ioapic_lock, flags);
  9.1190  	reg_00.raw = io_apic_read(apic, 0);
  9.1191  	reg_01.raw = io_apic_read(apic, 1);
  9.1192  	if (reg_01.bits.version >= 0x10)
  9.1193 -		reg_02.raw = io_apic_read(apic, 2);
  9.1194 +            reg_02.raw = io_apic_read(apic, 2);
  9.1195  	if (reg_01.bits.version >= 0x20)
  9.1196 -		reg_03.raw = io_apic_read(apic, 3);
  9.1197 +            reg_03.raw = io_apic_read(apic, 3);
  9.1198  	spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1199  
  9.1200  	printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
  9.1201 @@ -838,9 +782,9 @@ void __init print_IO_APIC(void)
  9.1202  	printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
  9.1203  	printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
  9.1204  	if (reg_00.bits.ID >= get_physical_broadcast())
  9.1205 -		UNEXPECTED_IO_APIC();
  9.1206 +            UNEXPECTED_IO_APIC();
  9.1207  	if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
  9.1208 -		UNEXPECTED_IO_APIC();
  9.1209 +            UNEXPECTED_IO_APIC();
  9.1210  
  9.1211  	printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
  9.1212  	printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
  9.1213 @@ -851,8 +795,8 @@ void __init print_IO_APIC(void)
  9.1214  		(reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
  9.1215  		(reg_01.bits.entries != 0x2E) &&
  9.1216  		(reg_01.bits.entries != 0x3F)
  9.1217 -	)
  9.1218 -		UNEXPECTED_IO_APIC();
  9.1219 +            )
  9.1220 +            UNEXPECTED_IO_APIC();
  9.1221  
  9.1222  	printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
  9.1223  	printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
  9.1224 @@ -861,10 +805,10 @@ void __init print_IO_APIC(void)
  9.1225  		(reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
  9.1226  		(reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
  9.1227  		(reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
  9.1228 -	)
  9.1229 -		UNEXPECTED_IO_APIC();
  9.1230 +            )
  9.1231 +            UNEXPECTED_IO_APIC();
  9.1232  	if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
  9.1233 -		UNEXPECTED_IO_APIC();
  9.1234 +            UNEXPECTED_IO_APIC();
  9.1235  
  9.1236  	/*
  9.1237  	 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
  9.1238 @@ -872,10 +816,10 @@ void __init print_IO_APIC(void)
  9.1239  	 * value, so ignore it if reg_02 == reg_01.
  9.1240  	 */
  9.1241  	if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
  9.1242 -		printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
  9.1243 -		printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
  9.1244 -		if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
  9.1245 -			UNEXPECTED_IO_APIC();
  9.1246 +            printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
  9.1247 +            printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
  9.1248 +            if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
  9.1249 +                UNEXPECTED_IO_APIC();
  9.1250  	}
  9.1251  
  9.1252  	/*
  9.1253 @@ -885,93 +829,89 @@ void __init print_IO_APIC(void)
  9.1254  	 */
  9.1255  	if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
  9.1256  	    reg_03.raw != reg_01.raw) {
  9.1257 -		printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
  9.1258 -		printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
  9.1259 -		if (reg_03.bits.__reserved_1)
  9.1260 -			UNEXPECTED_IO_APIC();
  9.1261 +            printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
  9.1262 +            printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
  9.1263 +            if (reg_03.bits.__reserved_1)
  9.1264 +                UNEXPECTED_IO_APIC();
  9.1265  	}
  9.1266  
  9.1267  	printk(KERN_DEBUG ".... IRQ redirection table:\n");
  9.1268  
  9.1269  	printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
  9.1270 -			  " Stat Dest Deli Vect:   \n");
  9.1271 +               " Stat Dest Deli Vect:   \n");
  9.1272  
  9.1273  	for (i = 0; i <= reg_01.bits.entries; i++) {
  9.1274 -		struct IO_APIC_route_entry entry;
  9.1275 +            struct IO_APIC_route_entry entry;
  9.1276  
  9.1277 -		spin_lock_irqsave(&ioapic_lock, flags);
  9.1278 -		*(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
  9.1279 -		*(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
  9.1280 -		spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1281 +            spin_lock_irqsave(&ioapic_lock, flags);
  9.1282 +            *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
  9.1283 +            *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
  9.1284 +            spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1285  
  9.1286 -		printk(KERN_DEBUG " %02x %03X %02X  ",
  9.1287 -			i,
  9.1288 -			entry.dest.logical.logical_dest,
  9.1289 -			entry.dest.physical.physical_dest
  9.1290 +            printk(KERN_DEBUG " %02x %03X %02X  ",
  9.1291 +                   i,
  9.1292 +                   entry.dest.logical.logical_dest,
  9.1293 +                   entry.dest.physical.physical_dest
  9.1294  		);
  9.1295  
  9.1296 -		printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
  9.1297 -			entry.mask,
  9.1298 -			entry.trigger,
  9.1299 -			entry.irr,
  9.1300 -			entry.polarity,
  9.1301 -			entry.delivery_status,
  9.1302 -			entry.dest_mode,
  9.1303 -			entry.delivery_mode,
  9.1304 -			entry.vector
  9.1305 +            printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
  9.1306 +                   entry.mask,
  9.1307 +                   entry.trigger,
  9.1308 +                   entry.irr,
  9.1309 +                   entry.polarity,
  9.1310 +                   entry.delivery_status,
  9.1311 +                   entry.dest_mode,
  9.1312 +                   entry.delivery_mode,
  9.1313 +                   entry.vector
  9.1314  		);
  9.1315  	}
  9.1316 -	}
  9.1317 -	if (use_pci_vector())
  9.1318 -		printk(KERN_INFO "Using vector-based indexing\n");
  9.1319 -	printk(KERN_DEBUG "IRQ to pin mappings:\n");
  9.1320 -	for (i = 0; i < NR_IRQS; i++) {
  9.1321 -		struct irq_pin_list *entry = irq_2_pin + i;
  9.1322 -		if (entry->pin < 0)
  9.1323 -			continue;
  9.1324 - 		if (use_pci_vector() && !platform_legacy_irq(i))
  9.1325 -			printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
  9.1326 -		else
  9.1327 -			printk(KERN_DEBUG "IRQ%d ", i);
  9.1328 -		for (;;) {
  9.1329 -			printk("-> %d:%d", entry->apic, entry->pin);
  9.1330 -			if (!entry->next)
  9.1331 -				break;
  9.1332 -			entry = irq_2_pin + entry->next;
  9.1333 -		}
  9.1334 -		printk("\n");
  9.1335 -	}
  9.1336 +    }
  9.1337 +    printk(KERN_INFO "Using vector-based indexing\n");
  9.1338 +    printk(KERN_DEBUG "IRQ to pin mappings:\n");
  9.1339 +    for (i = 0; i < NR_IRQS; i++) {
  9.1340 +        struct irq_pin_list *entry = irq_2_pin + i;
  9.1341 +        if (entry->pin < 0)
  9.1342 +            continue;
  9.1343 +        printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
  9.1344 +        for (;;) {
  9.1345 +            printk("-> %d:%d", entry->apic, entry->pin);
  9.1346 +            if (!entry->next)
  9.1347 +                break;
  9.1348 +            entry = irq_2_pin + entry->next;
  9.1349 +        }
  9.1350 +        printk("\n");
  9.1351 +    }
  9.1352  
  9.1353 -	printk(KERN_INFO ".................................... done.\n");
  9.1354 +    printk(KERN_INFO ".................................... done.\n");
  9.1355  
  9.1356 -	return;
  9.1357 +    return;
  9.1358  }
  9.1359  
  9.1360  static void __init enable_IO_APIC(void)
  9.1361  {
  9.1362 -	union IO_APIC_reg_01 reg_01;
  9.1363 -	int i;
  9.1364 -	unsigned long flags;
  9.1365 +    union IO_APIC_reg_01 reg_01;
  9.1366 +    int i;
  9.1367 +    unsigned long flags;
  9.1368  
  9.1369 -	for (i = 0; i < PIN_MAP_SIZE; i++) {
  9.1370 -		irq_2_pin[i].pin = -1;
  9.1371 -		irq_2_pin[i].next = 0;
  9.1372 -	}
  9.1373 +    for (i = 0; i < PIN_MAP_SIZE; i++) {
  9.1374 +        irq_2_pin[i].pin = -1;
  9.1375 +        irq_2_pin[i].next = 0;
  9.1376 +    }
  9.1377  
  9.1378 -	/*
  9.1379 -	 * The number of IO-APIC IRQ registers (== #pins):
  9.1380 -	 */
  9.1381 -	for (i = 0; i < nr_ioapics; i++) {
  9.1382 -		spin_lock_irqsave(&ioapic_lock, flags);
  9.1383 -		reg_01.raw = io_apic_read(i, 1);
  9.1384 -		spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1385 -		nr_ioapic_registers[i] = reg_01.bits.entries+1;
  9.1386 -	}
  9.1387 +    /*
  9.1388 +     * The number of IO-APIC IRQ registers (== #pins):
  9.1389 +     */
  9.1390 +    for (i = 0; i < nr_ioapics; i++) {
  9.1391 +        spin_lock_irqsave(&ioapic_lock, flags);
  9.1392 +        reg_01.raw = io_apic_read(i, 1);
  9.1393 +        spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1394 +        nr_ioapic_registers[i] = reg_01.bits.entries+1;
  9.1395 +    }
  9.1396  
  9.1397 -	/*
  9.1398 -	 * Do not trust the IO-APIC being empty at bootup
  9.1399 -	 */
  9.1400 -	clear_IO_APIC();
  9.1401 +    /*
  9.1402 +     * Do not trust the IO-APIC being empty at bootup
  9.1403 +     */
  9.1404 +    clear_IO_APIC();
  9.1405  }
  9.1406  
  9.1407  /*
  9.1408 @@ -979,12 +919,12 @@ static void __init enable_IO_APIC(void)
  9.1409   */
  9.1410  void disable_IO_APIC(void)
  9.1411  {
  9.1412 -	/*
  9.1413 -	 * Clear the IO-APIC before rebooting:
  9.1414 +    /*
  9.1415 +     * Clear the IO-APIC before rebooting:
  9.1416  	 */
  9.1417 -	clear_IO_APIC();
  9.1418 +    clear_IO_APIC();
  9.1419  
  9.1420 -	disconnect_bsp_APIC();
  9.1421 +    disconnect_bsp_APIC();
  9.1422  }
  9.1423  
  9.1424  /*
  9.1425 @@ -997,105 +937,105 @@ void disable_IO_APIC(void)
  9.1426  #ifndef CONFIG_X86_NUMAQ
  9.1427  static void __init setup_ioapic_ids_from_mpc(void)
  9.1428  {
  9.1429 -	union IO_APIC_reg_00 reg_00;
  9.1430 -	physid_mask_t phys_id_present_map;
  9.1431 -	int apic;
  9.1432 -	int i;
  9.1433 -	unsigned char old_id;
  9.1434 -	unsigned long flags;
  9.1435 +    union IO_APIC_reg_00 reg_00;
  9.1436 +    physid_mask_t phys_id_present_map;
  9.1437 +    int apic;
  9.1438 +    int i;
  9.1439 +    unsigned char old_id;
  9.1440 +    unsigned long flags;
  9.1441  
  9.1442 -	/*
  9.1443 -	 * This is broken; anything with a real cpu count has to
  9.1444 -	 * circumvent this idiocy regardless.
  9.1445 -	 */
  9.1446 -	phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
  9.1447 +    /*
  9.1448 +     * This is broken; anything with a real cpu count has to
  9.1449 +     * circumvent this idiocy regardless.
  9.1450 +     */
  9.1451 +    phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
  9.1452  
  9.1453 -	/*
  9.1454 -	 * Set the IOAPIC ID to the value stored in the MPC table.
  9.1455 -	 */
  9.1456 -	for (apic = 0; apic < nr_ioapics; apic++) {
  9.1457 +    /*
  9.1458 +     * Set the IOAPIC ID to the value stored in the MPC table.
  9.1459 +     */
  9.1460 +    for (apic = 0; apic < nr_ioapics; apic++) {
  9.1461  
  9.1462 -		/* Read the register 0 value */
  9.1463 -		spin_lock_irqsave(&ioapic_lock, flags);
  9.1464 -		reg_00.raw = io_apic_read(apic, 0);
  9.1465 -		spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1466 +        /* Read the register 0 value */
  9.1467 +        spin_lock_irqsave(&ioapic_lock, flags);
  9.1468 +        reg_00.raw = io_apic_read(apic, 0);
  9.1469 +        spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1470  		
  9.1471 -		old_id = mp_ioapics[apic].mpc_apicid;
  9.1472 +        old_id = mp_ioapics[apic].mpc_apicid;
  9.1473  
  9.1474 -		if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
  9.1475 -			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
  9.1476 -				apic, mp_ioapics[apic].mpc_apicid);
  9.1477 -			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
  9.1478 -				reg_00.bits.ID);
  9.1479 -			mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
  9.1480 -		}
  9.1481 +        if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
  9.1482 +            printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
  9.1483 +                   apic, mp_ioapics[apic].mpc_apicid);
  9.1484 +            printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
  9.1485 +                   reg_00.bits.ID);
  9.1486 +            mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
  9.1487 +        }
  9.1488  
  9.1489 -		/* Don't check I/O APIC IDs for some xAPIC systems.  They have
  9.1490 -		 * no meaning without the serial APIC bus. */
  9.1491 -		if (NO_IOAPIC_CHECK)
  9.1492 -			continue;
  9.1493 -		/*
  9.1494 -		 * Sanity check, is the ID really free? Every APIC in a
  9.1495 -		 * system must have a unique ID or we get lots of nice
  9.1496 -		 * 'stuck on smp_invalidate_needed IPI wait' messages.
  9.1497 -		 */
  9.1498 -		if (check_apicid_used(phys_id_present_map,
  9.1499 -					mp_ioapics[apic].mpc_apicid)) {
  9.1500 -			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
  9.1501 -				apic, mp_ioapics[apic].mpc_apicid);
  9.1502 -			for (i = 0; i < get_physical_broadcast(); i++)
  9.1503 -				if (!physid_isset(i, phys_id_present_map))
  9.1504 -					break;
  9.1505 -			if (i >= get_physical_broadcast())
  9.1506 -				panic("Max APIC ID exceeded!\n");
  9.1507 -			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
  9.1508 -				i);
  9.1509 -			physid_set(i, phys_id_present_map);
  9.1510 -			mp_ioapics[apic].mpc_apicid = i;
  9.1511 -		} else {
  9.1512 -			physid_mask_t tmp;
  9.1513 -			tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
  9.1514 -			apic_printk(APIC_VERBOSE, "Setting %d in the "
  9.1515 -					"phys_id_present_map\n",
  9.1516 -					mp_ioapics[apic].mpc_apicid);
  9.1517 -			physids_or(phys_id_present_map, phys_id_present_map, tmp);
  9.1518 -		}
  9.1519 +        /* Don't check I/O APIC IDs for some xAPIC systems.  They have
  9.1520 +         * no meaning without the serial APIC bus. */
  9.1521 +        if (NO_IOAPIC_CHECK)
  9.1522 +            continue;
  9.1523 +        /*
  9.1524 +         * Sanity check, is the ID really free? Every APIC in a
  9.1525 +         * system must have a unique ID or we get lots of nice
  9.1526 +         * 'stuck on smp_invalidate_needed IPI wait' messages.
  9.1527 +         */
  9.1528 +        if (check_apicid_used(phys_id_present_map,
  9.1529 +                              mp_ioapics[apic].mpc_apicid)) {
  9.1530 +            printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
  9.1531 +                   apic, mp_ioapics[apic].mpc_apicid);
  9.1532 +            for (i = 0; i < get_physical_broadcast(); i++)
  9.1533 +                if (!physid_isset(i, phys_id_present_map))
  9.1534 +                    break;
  9.1535 +            if (i >= get_physical_broadcast())
  9.1536 +                panic("Max APIC ID exceeded!\n");
  9.1537 +            printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
  9.1538 +                   i);
  9.1539 +            physid_set(i, phys_id_present_map);
  9.1540 +            mp_ioapics[apic].mpc_apicid = i;
  9.1541 +        } else {
  9.1542 +            physid_mask_t tmp;
  9.1543 +            tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
  9.1544 +            apic_printk(APIC_VERBOSE, "Setting %d in the "
  9.1545 +                        "phys_id_present_map\n",
  9.1546 +                        mp_ioapics[apic].mpc_apicid);
  9.1547 +            physids_or(phys_id_present_map, phys_id_present_map, tmp);
  9.1548 +        }
  9.1549  
  9.1550  
  9.1551 -		/*
  9.1552 -		 * We need to adjust the IRQ routing table
  9.1553 -		 * if the ID changed.
  9.1554 -		 */
  9.1555 -		if (old_id != mp_ioapics[apic].mpc_apicid)
  9.1556 -			for (i = 0; i < mp_irq_entries; i++)
  9.1557 -				if (mp_irqs[i].mpc_dstapic == old_id)
  9.1558 -					mp_irqs[i].mpc_dstapic
  9.1559 -						= mp_ioapics[apic].mpc_apicid;
  9.1560 +        /*
  9.1561 +         * We need to adjust the IRQ routing table
  9.1562 +         * if the ID changed.
  9.1563 +         */
  9.1564 +        if (old_id != mp_ioapics[apic].mpc_apicid)
  9.1565 +            for (i = 0; i < mp_irq_entries; i++)
  9.1566 +                if (mp_irqs[i].mpc_dstapic == old_id)
  9.1567 +                    mp_irqs[i].mpc_dstapic
  9.1568 +                        = mp_ioapics[apic].mpc_apicid;
  9.1569  
  9.1570 -		/*
  9.1571 -		 * Read the right value from the MPC table and
  9.1572 -		 * write it into the ID register.
  9.1573 -	 	 */
  9.1574 -		apic_printk(APIC_VERBOSE, KERN_INFO
  9.1575 -			"...changing IO-APIC physical APIC ID to %d ...",
  9.1576 -			mp_ioapics[apic].mpc_apicid);
  9.1577 +        /*
  9.1578 +         * Read the right value from the MPC table and
  9.1579 +         * write it into the ID register.
  9.1580 +         */
  9.1581 +        apic_printk(APIC_VERBOSE, KERN_INFO
  9.1582 +                    "...changing IO-APIC physical APIC ID to %d ...",
  9.1583 +                    mp_ioapics[apic].mpc_apicid);
  9.1584  
  9.1585 -		reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
  9.1586 -		spin_lock_irqsave(&ioapic_lock, flags);
  9.1587 -		io_apic_write(apic, 0, reg_00.raw);
  9.1588 -		spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1589 +        reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
  9.1590 +        spin_lock_irqsave(&ioapic_lock, flags);
  9.1591 +        io_apic_write(apic, 0, reg_00.raw);
  9.1592 +        spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1593  
  9.1594 -		/*
  9.1595 -		 * Sanity check
  9.1596 -		 */
  9.1597 -		spin_lock_irqsave(&ioapic_lock, flags);
  9.1598 -		reg_00.raw = io_apic_read(apic, 0);
  9.1599 -		spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1600 -		if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
  9.1601 -			printk("could not set ID!\n");
  9.1602 -		else
  9.1603 -			apic_printk(APIC_VERBOSE, " ok.\n");
  9.1604 -	}
  9.1605 +        /*
  9.1606 +         * Sanity check
  9.1607 +         */
  9.1608 +        spin_lock_irqsave(&ioapic_lock, flags);
  9.1609 +        reg_00.raw = io_apic_read(apic, 0);
  9.1610 +        spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1611 +        if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
  9.1612 +            printk("could not set ID!\n");
  9.1613 +        else
  9.1614 +            apic_printk(APIC_VERBOSE, " ok.\n");
  9.1615 +    }
  9.1616  }
  9.1617  #else
  9.1618  static void __init setup_ioapic_ids_from_mpc(void) { }
  9.1619 @@ -1111,23 +1051,23 @@ static void __init setup_ioapic_ids_from
  9.1620   */
  9.1621  static int __init timer_irq_works(void)
  9.1622  {
  9.1623 -	unsigned long t1 = jiffies;
  9.1624 +    unsigned long t1 = jiffies;
  9.1625  
  9.1626 -	local_irq_enable();
  9.1627 -	/* Let ten ticks pass... */
  9.1628 -	mdelay((10 * 1000) / HZ);
  9.1629 +    local_irq_enable();
  9.1630 +    /* Let ten ticks pass... */
  9.1631 +    mdelay((10 * 1000) / HZ);
  9.1632  
  9.1633 -	/*
  9.1634 -	 * Expect a few ticks at least, to be sure some possible
  9.1635 -	 * glue logic does not lock up after one or two first
  9.1636 -	 * ticks in a non-ExtINT mode.  Also the local APIC
  9.1637 -	 * might have cached one ExtINT interrupt.  Finally, at
  9.1638 -	 * least one tick may be lost due to delays.
  9.1639 -	 */
  9.1640 -	if (jiffies - t1 > 4)
  9.1641 -		return 1;
  9.1642 +    /*
  9.1643 +     * Expect a few ticks at least, to be sure some possible
  9.1644 +     * glue logic does not lock up after one or two first
  9.1645 +     * ticks in a non-ExtINT mode.  Also the local APIC
  9.1646 +     * might have cached one ExtINT interrupt.  Finally, at
  9.1647 +     * least one tick may be lost due to delays.
  9.1648 +     */
  9.1649 +    if (jiffies - t1 > 4)
  9.1650 +        return 1;
  9.1651  
  9.1652 -	return 0;
  9.1653 +    return 0;
  9.1654  }
  9.1655  
  9.1656  /*
  9.1657 @@ -1154,19 +1094,19 @@ static int __init timer_irq_works(void)
  9.1658   */
  9.1659  static unsigned int startup_edge_ioapic_irq(unsigned int irq)
  9.1660  {
  9.1661 -	int was_pending = 0;
  9.1662 -	unsigned long flags;
  9.1663 +    int was_pending = 0;
  9.1664 +    unsigned long flags;
  9.1665  
  9.1666 -	spin_lock_irqsave(&ioapic_lock, flags);
  9.1667 -	if (irq < 16) {
  9.1668 -		disable_8259A_irq(irq);
  9.1669 -		if (i8259A_irq_pending(irq))
  9.1670 -			was_pending = 1;
  9.1671 -	}
  9.1672 -	__unmask_IO_APIC_irq(irq);
  9.1673 -	spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1674 +    spin_lock_irqsave(&ioapic_lock, flags);
  9.1675 +    if (irq < 16) {
  9.1676 +        disable_8259A_irq(irq);
  9.1677 +        if (i8259A_irq_pending(irq))
  9.1678 +            was_pending = 1;
  9.1679 +    }
  9.1680 +    __unmask_IO_APIC_irq(irq);
  9.1681 +    spin_unlock_irqrestore(&ioapic_lock, flags);
  9.1682  
  9.1683 -	return was_pending;
  9.1684 +    return was_pending;
  9.1685  }
  9.1686  
  9.1687  /*
  9.1688 @@ -1176,10 +1116,10 @@ static unsigned int startup_edge_ioapic_
  9.1689   */
  9.1690  static void ack_edge_ioapic_irq(unsigned int irq)
  9.1691  {
  9.1692 -	if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
  9.1693 -					== (IRQ_PENDING | IRQ_DISABLED))
  9.1694 -		mask_IO_APIC_irq(irq);
  9.1695 -	ack_APIC_irq();
  9.1696 +    if ((irq_desc[IO_APIC_VECTOR(irq)].status & (IRQ_PENDING | IRQ_DISABLED))
  9.1697 +        == (IRQ_PENDING | IRQ_DISABLED))
  9.1698 +        mask_IO_APIC_irq(irq);
  9.1699 +    ack_APIC_irq();
  9.1700  }
  9.1701  
  9.1702  /*
  9.1703 @@ -1198,17 +1138,17 @@ static void ack_edge_ioapic_irq(unsigned
  9.1704   */
  9.1705  static unsigned int startup_level_ioapic_irq (unsigned int irq)
  9.1706  {
  9.1707 -	unmask_IO_APIC_irq(irq);
  9.1708 +    unmask_IO_APIC_irq(irq);
  9.1709  
  9.1710 -	return 0; /* don't check for pending */
  9.1711 +    return 0; /* don't check for pending */
  9.1712  }
  9.1713  
  9.1714  static void mask_and_ack_level_ioapic_irq (unsigned int irq)
  9.1715  {
  9.1716 -	unsigned long v;
  9.1717 -	int i;
  9.1718 +    unsigned long v;
  9.1719 +    int i;
  9.1720  
  9.1721 -	mask_IO_APIC_irq(irq);
  9.1722 +    mask_IO_APIC_irq(irq);
  9.1723  /*
  9.1724   * It appears there is an erratum which affects at least version 0x11
  9.1725   * of I/O APIC (that's the 82093AA and cores integrated into various
  9.1726 @@ -1228,84 +1168,82 @@ static void mask_and_ack_level_ioapic_ir
  9.1727   * operation to prevent an edge-triggered interrupt escaping meanwhile.
  9.1728   * The idea is from Manfred Spraul.  --macro
  9.1729   */
  9.1730 -	i = IO_APIC_VECTOR(irq);
  9.1731 +    i = IO_APIC_VECTOR(irq);
  9.1732  
  9.1733 -	v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
  9.1734 +    v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
  9.1735  
  9.1736 -	ack_APIC_irq();
  9.1737 +    ack_APIC_irq();
  9.1738  
  9.1739 -	if (!(v & (1 << (i & 0x1f)))) {
  9.1740 -		atomic_inc(&irq_mis_count);
  9.1741 -		spin_lock(&ioapic_lock);
  9.1742 -		__edge_IO_APIC_irq(irq);
  9.1743 -		__level_IO_APIC_irq(irq);
  9.1744 -		spin_unlock(&ioapic_lock);
  9.1745 -	}
  9.1746 +    if (!(v & (1 << (i & 0x1f)))) {
  9.1747 +        atomic_inc(&irq_mis_count);
  9.1748 +        spin_lock(&ioapic_lock);
  9.1749 +        __edge_IO_APIC_irq(irq);
  9.1750 +        __level_IO_APIC_irq(irq);
  9.1751 +        spin_unlock(&ioapic_lock);
  9.1752 +    }
  9.1753  }
  9.1754  
  9.1755  static void end_level_ioapic_irq (unsigned int irq)
  9.1756  {
  9.1757 -	unmask_IO_APIC_irq(irq);
  9.1758 +    unmask_IO_APIC_irq(irq);
  9.1759  }
  9.1760  
  9.1761 -#ifdef CONFIG_PCI_MSI
  9.1762  static unsigned int startup_edge_ioapic_vector(unsigned int vector)
  9.1763  {
  9.1764 -	int irq = vector_to_irq(vector);
  9.1765 -
  9.1766 -	return startup_edge_ioapic_irq(irq);
  9.1767 +    int irq = vector_to_irq(vector);
  9.1768 +    return startup_edge_ioapic_irq(irq);
  9.1769  }
  9.1770  
  9.1771  static void ack_edge_ioapic_vector(unsigned int vector)
  9.1772  {
  9.1773 -	int irq = vector_to_irq(vector);
  9.1774 +    int irq = vector_to_irq(vector);
  9.1775 +    ack_edge_ioapic_irq(irq);
  9.1776 +}
  9.1777  
  9.1778 -	ack_edge_ioapic_irq(irq);
  9.1779 +static unsigned int startup_level_ioapic_vector(unsigned int vector)
  9.1780 +{
  9.1781 +    int irq = vector_to_irq(vector);
  9.1782 +    return startup_level_ioapic_irq (irq);
  9.1783  }
  9.1784  
  9.1785 -static unsigned int startup_level_ioapic_vector (unsigned int vector)
  9.1786 +static void mask_and_ack_level_ioapic_vector(unsigned int vector)
  9.1787  {
  9.1788 -	int irq = vector_to_irq(vector);
  9.1789 -
  9.1790 -	return startup_level_ioapic_irq (irq);
  9.1791 +    int irq = vector_to_irq(vector);
  9.1792 +    mask_and_ack_level_ioapic_irq(irq);
  9.1793  }
  9.1794  
  9.1795 -static void mask_and_ack_level_ioapic_vector (unsigned int vector)
  9.1796 +static void end_level_ioapic_vector(unsigned int vector)
  9.1797  {
  9.1798 -	int irq = vector_to_irq(vector);
  9.1799 -
  9.1800 -	mask_and_ack_level_ioapic_irq(irq);
  9.1801 +    int irq = vector_to_irq(vector);
  9.1802 +    end_level_ioapic_irq(irq);
  9.1803  }
  9.1804  
  9.1805 -static void end_level_ioapic_vector (unsigned int vector)
  9.1806 +static void mask_IO_APIC_vector(unsigned int vector)
  9.1807  {
  9.1808 -	int irq = vector_to_irq(vector);
  9.1809 -
  9.1810 -	end_level_ioapic_irq(irq);
  9.1811 +    int irq = vector_to_irq(vector);
  9.1812 +    mask_IO_APIC_irq(irq);
  9.1813  }
  9.1814  
  9.1815 -static void mask_IO_APIC_vector (unsigned int vector)
  9.1816 +static void unmask_IO_APIC_vector(unsigned int vector)
  9.1817  {
  9.1818 -	int irq = vector_to_irq(vector);
  9.1819 -
  9.1820 -	mask_IO_APIC_irq(irq);
  9.1821 +    int irq = vector_to_irq(vector);
  9.1822 +    unmask_IO_APIC_irq(irq);
  9.1823  }
  9.1824  
  9.1825 -static void unmask_IO_APIC_vector (unsigned int vector)
  9.1826 +static void set_ioapic_affinity_vector(
  9.1827 +    unsigned int vector, cpumask_t cpu_mask)
  9.1828  {
  9.1829 -	int irq = vector_to_irq(vector);
  9.1830 -
  9.1831 -	unmask_IO_APIC_irq(irq);
  9.1832 +    int irq = vector_to_irq(vector);
  9.1833 +    set_ioapic_affinity_irq(irq, cpu_mask);
  9.1834  }
  9.1835  
  9.1836 -static void set_ioapic_affinity_vector (unsigned int vector,
  9.1837 -					cpumask_t cpu_mask)
  9.1838 +static void disable_edge_ioapic_vector(unsigned int vector)
  9.1839  {
  9.1840 -	int irq = vector_to_irq(vector);
  9.1841 +}
  9.1842  
  9.1843 -	set_ioapic_affinity_irq(irq, cpu_mask);
  9.1844 +static void end_edge_ioapic_vector(unsigned int vector)
  9.1845 +{
  9.1846  }
  9.1847 -#endif
  9.1848  
  9.1849  /*
  9.1850   * Level and edge triggered IO-APIC interrupts need different handling,
  9.1851 @@ -1316,95 +1254,66 @@ static void set_ioapic_affinity_vector (
  9.1852   * races.
  9.1853   */
  9.1854  static struct hw_interrupt_type ioapic_edge_type = {
  9.1855 -	.typename 	= "IO-APIC-edge",
  9.1856 -	.startup 	= startup_edge_ioapic,
  9.1857 -	.shutdown 	= shutdown_edge_ioapic,
  9.1858 -	.enable 	= enable_edge_ioapic,
  9.1859 -	.disable 	= disable_edge_ioapic,
  9.1860 -	.ack 		= ack_edge_ioapic,
  9.1861 -	.end 		= end_edge_ioapic,
  9.1862 -	.set_affinity 	= set_ioapic_affinity,
  9.1863 +    .typename 	= "IO-APIC-edge",
  9.1864 +    .startup 	= startup_edge_ioapic_vector,
  9.1865 +    .shutdown 	= disable_edge_ioapic_vector,
  9.1866 +    .enable 	= unmask_IO_APIC_vector,
  9.1867 +    .disable 	= disable_edge_ioapic_vector,
  9.1868 +    .ack 		= ack_edge_ioapic_vector,
  9.1869 +    .end 		= end_edge_ioapic_vector,
  9.1870 +    .set_affinity 	= set_ioapic_affinity_vector,
  9.1871  };
  9.1872  
  9.1873  static struct hw_interrupt_type ioapic_level_type = {
  9.1874 -	.typename 	= "IO-APIC-level",
  9.1875 -	.startup 	= startup_level_ioapic,
  9.1876 -	.shutdown 	= shutdown_level_ioapic,
  9.1877 -	.enable 	= enable_level_ioapic,
  9.1878 -	.disable 	= disable_level_ioapic,
  9.1879 -	.ack 		= mask_and_ack_level_ioapic,
  9.1880 -	.end 		= end_level_ioapic,
  9.1881 -	.set_affinity 	= set_ioapic_affinity,
  9.1882 +    .typename 	= "IO-APIC-level",
  9.1883 +    .startup 	= startup_level_ioapic_vector,
  9.1884 +    .shutdown 	= mask_IO_APIC_vector,
  9.1885 +    .enable 	= unmask_IO_APIC_vector,
  9.1886 +    .disable 	= mask_IO_APIC_vector,
  9.1887 +    .ack 		= mask_and_ack_level_ioapic_vector,
  9.1888 +    .end 		= end_level_ioapic_vector,
  9.1889 +    .set_affinity 	= set_ioapic_affinity_vector,
  9.1890  };
  9.1891  
  9.1892  static inline void init_IO_APIC_traps(void)
  9.1893  {
  9.1894 -	int irq;
  9.1895 +    int irq;
  9.1896 +    for (irq = 0; irq < NR_IRQS ; irq++)
  9.1897 +        if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq) && (irq < 16))
  9.1898 +            make_8259A_irq(irq);
  9.1899 +}
  9.1900  
  9.1901 -	/*
  9.1902 -	 * NOTE! The local APIC isn't very good at handling
  9.1903 -	 * multiple interrupts at the same interrupt level.
  9.1904 -	 * As the interrupt level is determined by taking the
  9.1905 -	 * vector number and shifting that right by 4, we
  9.1906 -	 * want to spread these out a bit so that they don't
  9.1907 -	 * all fall in the same interrupt level.
  9.1908 -	 *
  9.1909 -	 * Also, we've got to be careful not to trash gate
  9.1910 -	 * 0x80, because int 0x80 is hm, kind of importantish. ;)
  9.1911 -	 */
  9.1912 -	for (irq = 0; irq < NR_IRQS ; irq++) {
  9.1913 -		int tmp = irq;
  9.1914 -		if (use_pci_vector()) {
  9.1915 -			if (!platform_legacy_irq(tmp))
  9.1916 -				if ((tmp = vector_to_irq(tmp)) == -1)
  9.1917 -					continue;
  9.1918 -		}
  9.1919 -		if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
  9.1920 -			/*
  9.1921 -			 * Hmm.. We don't have an entry for this,
  9.1922 -			 * so default to an old-fashioned 8259
  9.1923 -			 * interrupt if we can..
  9.1924 -			 */
  9.1925 -			if (irq < 16)
  9.1926 -				make_8259A_irq(irq);
  9.1927 -			else
  9.1928 -				/* Strange. Oh, well.. */
  9.1929 -				irq_desc[irq].handler = &no_irq_type;
  9.1930 -		}
  9.1931 -	}
  9.1932 +static void enable_lapic_vector(unsigned int vector)
  9.1933 +{
  9.1934 +    unsigned long v;
  9.1935 +
  9.1936 +    v = apic_read(APIC_LVT0);
  9.1937 +    apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
  9.1938  }
  9.1939  
  9.1940 -static void enable_lapic_irq (unsigned int irq)
  9.1941 +static void disable_lapic_vector(unsigned int vector)
  9.1942  {
  9.1943 -	unsigned long v;
  9.1944 +    unsigned long v;
  9.1945  
  9.1946 -	v = apic_read(APIC_LVT0);
  9.1947 -	apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
  9.1948 -}
  9.1949 -
  9.1950 -static void disable_lapic_irq (unsigned int irq)
  9.1951 -{
  9.1952 -	unsigned long v;
  9.1953 -
  9.1954 -	v = apic_read(APIC_LVT0);
  9.1955 -	apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
  9.1956 +    v = apic_read(APIC_LVT0);
  9.1957 +    apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
  9.1958  }
  9.1959  
  9.1960 -static void ack_lapic_irq (unsigned int irq)
  9.1961 +static void ack_lapic_vector(unsigned int vector)
  9.1962  {
  9.1963 -	ack_APIC_irq();
  9.1964 +    ack_APIC_irq();
  9.1965  }
  9.1966  
  9.1967 -static void end_lapic_irq (unsigned int i) { /* nothing */ }
  9.1968 +static void end_lapic_vector(unsigned int vector) { /* nothing */ }
  9.1969  
  9.1970  static struct hw_interrupt_type lapic_irq_type = {
  9.1971 -	.typename 	= "local-APIC-edge",
  9.1972 -	.startup 	= NULL, /* startup_irq() not used for IRQ0 */
  9.1973 -	.shutdown 	= NULL, /* shutdown_irq() not used for IRQ0 */
  9.1974 -	.enable 	= enable_lapic_irq,
  9.1975 -	.disable 	= disable_lapic_irq,
  9.1976 -	.ack 		= ack_lapic_irq,
  9.1977 -	.end 		= end_lapic_irq
  9.1978 +    .typename 	= "local-APIC-edge",
  9.1979 +    .startup 	= NULL, /* startup_irq() not used for IRQ0 */
  9.1980 +    .shutdown 	= NULL, /* shutdown_irq() not used for IRQ0 */
  9.1981 +    .enable 	= enable_lapic_vector,
  9.1982 +    .disable 	= disable_lapic_vector,
  9.1983 +    .ack 		= ack_lapic_vector,
  9.1984 +    .end 		= end_lapic_vector
  9.1985  };
  9.1986  
  9.1987  /*
  9.1988 @@ -1416,57 +1325,57 @@ static struct hw_interrupt_type lapic_ir
  9.1989   */
  9.1990  static inline void unlock_ExtINT_logic(void)
  9.1991  {
  9.1992 -	int pin, i;
  9.1993 -	struct IO_APIC_route_entry entry0, entry1;
  9.1994 -	unsigned char save_control, save_freq_select;
  9.1995 -	unsigned long flags;
  9.1996 +    int pin, i;
  9.1997 +    struct IO_APIC_route_entry entry0, entry1;
  9.1998 +    unsigned char save_control, save_freq_select;
  9.1999 +    unsigned long flags;
  9.2000  
  9.2001 -	pin = find_isa_irq_pin(8, mp_INT);
  9.2002 -	if (pin == -1)
  9.2003 -		return;
  9.2004 +    pin = find_isa_irq_pin(8, mp_INT);
  9.2005 +    if (pin == -1)
  9.2006 +        return;
  9.2007  
  9.2008 -	spin_lock_irqsave(&ioapic_lock, flags);
  9.2009 -	*(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
  9.2010 -	*(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
  9.2011 -	spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2012 -	clear_IO_APIC_pin(0, pin);
  9.2013 +    spin_lock_irqsave(&ioapic_lock, flags);
  9.2014 +    *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
  9.2015 +    *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
  9.2016 +    spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2017 +    clear_IO_APIC_pin(0, pin);
  9.2018  
  9.2019 -	memset(&entry1, 0, sizeof(entry1));
  9.2020 +    memset(&entry1, 0, sizeof(entry1));
  9.2021  
  9.2022 -	entry1.dest_mode = 0;			/* physical delivery */
  9.2023 -	entry1.mask = 0;			/* unmask IRQ now */
  9.2024 -	entry1.dest.physical.physical_dest = hard_smp_processor_id();
  9.2025 -	entry1.delivery_mode = dest_ExtINT;
  9.2026 -	entry1.polarity = entry0.polarity;
  9.2027 -	entry1.trigger = 0;
  9.2028 -	entry1.vector = 0;
  9.2029 +    entry1.dest_mode = 0;			/* physical delivery */
  9.2030 +    entry1.mask = 0;			/* unmask IRQ now */
  9.2031 +    entry1.dest.physical.physical_dest = hard_smp_processor_id();
  9.2032 +    entry1.delivery_mode = dest_ExtINT;
  9.2033 +    entry1.polarity = entry0.polarity;
  9.2034 +    entry1.trigger = 0;
  9.2035 +    entry1.vector = 0;
  9.2036  
  9.2037 -	spin_lock_irqsave(&ioapic_lock, flags);
  9.2038 -	io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
  9.2039 -	io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
  9.2040 -	spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2041 +    spin_lock_irqsave(&ioapic_lock, flags);
  9.2042 +    io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
  9.2043 +    io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
  9.2044 +    spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2045  
  9.2046 -	save_control = CMOS_READ(RTC_CONTROL);
  9.2047 -	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
  9.2048 -	CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
  9.2049 -		   RTC_FREQ_SELECT);
  9.2050 -	CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
  9.2051 +    save_control = CMOS_READ(RTC_CONTROL);
  9.2052 +    save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
  9.2053 +    CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
  9.2054 +               RTC_FREQ_SELECT);
  9.2055 +    CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
  9.2056  
  9.2057 -	i = 100;
  9.2058 -	while (i-- > 0) {
  9.2059 -		mdelay(10);
  9.2060 -		if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
  9.2061 -			i -= 10;
  9.2062 -	}
  9.2063 +    i = 100;
  9.2064 +    while (i-- > 0) {
  9.2065 +        mdelay(10);
  9.2066 +        if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
  9.2067 +            i -= 10;
  9.2068 +    }
  9.2069  
  9.2070 -	CMOS_WRITE(save_control, RTC_CONTROL);
  9.2071 -	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
  9.2072 -	clear_IO_APIC_pin(0, pin);
  9.2073 +    CMOS_WRITE(save_control, RTC_CONTROL);
  9.2074 +    CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
  9.2075 +    clear_IO_APIC_pin(0, pin);
  9.2076  
  9.2077 -	spin_lock_irqsave(&ioapic_lock, flags);
  9.2078 -	io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
  9.2079 -	io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
  9.2080 -	spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2081 +    spin_lock_irqsave(&ioapic_lock, flags);
  9.2082 +    io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
  9.2083 +    io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
  9.2084 +    spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2085  }
  9.2086  
  9.2087  /*
  9.2088 @@ -1477,102 +1386,105 @@ static inline void unlock_ExtINT_logic(v
  9.2089   */
  9.2090  static inline void check_timer(void)
  9.2091  {
  9.2092 -	int pin1, pin2;
  9.2093 -	int vector;
  9.2094 +    int pin1, pin2;
  9.2095 +    int vector;
  9.2096  
  9.2097 -	/*
  9.2098 -	 * get/set the timer IRQ vector:
  9.2099 -	 */
  9.2100 -	disable_8259A_irq(0);
  9.2101 -	vector = assign_irq_vector(0);
  9.2102 -	set_intr_gate(vector, interrupt[0]);
  9.2103 +    /*
  9.2104 +     * get/set the timer IRQ vector:
  9.2105 +     */
  9.2106 +    disable_8259A_irq(0);
  9.2107 +    vector = assign_irq_vector(0);
  9.2108 +
  9.2109 +    irq_desc[IO_APIC_VECTOR(0)].action = irq_desc[LEGACY_VECTOR(0)].action;
  9.2110 +    irq_desc[IO_APIC_VECTOR(0)].depth  = 0;
  9.2111 +    irq_desc[IO_APIC_VECTOR(0)].status &= ~IRQ_DISABLED;
  9.2112  
  9.2113 -	/*
  9.2114 -	 * Subtle, code in do_timer_interrupt() expects an AEOI
  9.2115 -	 * mode for the 8259A whenever interrupts are routed
  9.2116 -	 * through I/O APICs.  Also IRQ0 has to be enabled in
  9.2117 -	 * the 8259A which implies the virtual wire has to be
  9.2118 -	 * disabled in the local APIC.
  9.2119 -	 */
  9.2120 -	apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
  9.2121 -	init_8259A(1);
  9.2122 -	timer_ack = 1;
  9.2123 -	enable_8259A_irq(0);
  9.2124 +    /*
  9.2125 +     * Subtle, code in do_timer_interrupt() expects an AEOI
  9.2126 +     * mode for the 8259A whenever interrupts are routed
  9.2127 +     * through I/O APICs.  Also IRQ0 has to be enabled in
  9.2128 +     * the 8259A which implies the virtual wire has to be
  9.2129 +     * disabled in the local APIC.
  9.2130 +     */
  9.2131 +    apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
  9.2132 +    init_8259A(1);
  9.2133 +    timer_ack = 1;
  9.2134 +    enable_8259A_irq(0);
  9.2135  
  9.2136 -	pin1 = find_isa_irq_pin(0, mp_INT);
  9.2137 -	pin2 = find_isa_irq_pin(0, mp_ExtINT);
  9.2138 +    pin1 = find_isa_irq_pin(0, mp_INT);
  9.2139 +    pin2 = find_isa_irq_pin(0, mp_ExtINT);
  9.2140  
  9.2141 -	printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
  9.2142 +    printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
  9.2143  
  9.2144 -	if (pin1 != -1) {
  9.2145 -		/*
  9.2146 -		 * Ok, does IRQ0 through the IOAPIC work?
  9.2147 -		 */
  9.2148 -		unmask_IO_APIC_irq(0);
  9.2149 -		if (timer_irq_works()) {
  9.2150 -			return;
  9.2151 -		}
  9.2152 -		clear_IO_APIC_pin(0, pin1);
  9.2153 -		printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
  9.2154 -	}
  9.2155 +    if (pin1 != -1) {
  9.2156 +        /*
  9.2157 +         * Ok, does IRQ0 through the IOAPIC work?
  9.2158 +         */
  9.2159 +        unmask_IO_APIC_irq(0);
  9.2160 +        if (timer_irq_works()) {
  9.2161 +            return;
  9.2162 +        }
  9.2163 +        clear_IO_APIC_pin(0, pin1);
  9.2164 +        printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
  9.2165 +    }
  9.2166  
  9.2167 -	printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
  9.2168 -	if (pin2 != -1) {
  9.2169 -		printk("\n..... (found pin %d) ...", pin2);
  9.2170 -		/*
  9.2171 -		 * legacy devices should be connected to IO APIC #0
  9.2172 -		 */
  9.2173 -		setup_ExtINT_IRQ0_pin(pin2, vector);
  9.2174 -		if (timer_irq_works()) {
  9.2175 -			printk("works.\n");
  9.2176 -			if (pin1 != -1)
  9.2177 -				replace_pin_at_irq(0, 0, pin1, 0, pin2);
  9.2178 -			else
  9.2179 -				add_pin_to_irq(0, 0, pin2);
  9.2180 -			return;
  9.2181 -		}
  9.2182 -		/*
  9.2183 -		 * Cleanup, just in case ...
  9.2184 -		 */
  9.2185 -		clear_IO_APIC_pin(0, pin2);
  9.2186 -	}
  9.2187 -	printk(" failed.\n");
  9.2188 +    printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
  9.2189 +    if (pin2 != -1) {
  9.2190 +        printk("\n..... (found pin %d) ...", pin2);
  9.2191 +        /*
  9.2192 +         * legacy devices should be connected to IO APIC #0
  9.2193 +         */
  9.2194 +        setup_ExtINT_IRQ0_pin(pin2, vector);
  9.2195 +        if (timer_irq_works()) {
  9.2196 +            printk("works.\n");
  9.2197 +            if (pin1 != -1)
  9.2198 +                replace_pin_at_irq(0, 0, pin1, 0, pin2);
  9.2199 +            else
  9.2200 +                add_pin_to_irq(0, 0, pin2);
  9.2201 +            return;
  9.2202 +        }
  9.2203 +        /*
  9.2204 +         * Cleanup, just in case ...
  9.2205 +         */
  9.2206 +        clear_IO_APIC_pin(0, pin2);
  9.2207 +    }
  9.2208 +    printk(" failed.\n");
  9.2209  
  9.2210 -	if (nmi_watchdog == NMI_IO_APIC) {
  9.2211 -		printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
  9.2212 -		nmi_watchdog = 0;
  9.2213 -	}
  9.2214 +    if (nmi_watchdog == NMI_IO_APIC) {
  9.2215 +        printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
  9.2216 +        nmi_watchdog = 0;
  9.2217 +    }
  9.2218  
  9.2219 -	printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
  9.2220 +    printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
  9.2221  
  9.2222 -	disable_8259A_irq(0);
  9.2223 -	irq_desc[0].handler = &lapic_irq_type;
  9.2224 -	apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);	/* Fixed mode */
  9.2225 -	enable_8259A_irq(0);
  9.2226 +    disable_8259A_irq(0);
  9.2227 +    irq_desc[vector].handler = &lapic_irq_type;
  9.2228 +    apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);	/* Fixed mode */
  9.2229 +    enable_8259A_irq(0);
  9.2230  
  9.2231 -	if (timer_irq_works()) {
  9.2232 -		printk(" works.\n");
  9.2233 -		return;
  9.2234 -	}
  9.2235 -	apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
  9.2236 -	printk(" failed.\n");
  9.2237 +    if (timer_irq_works()) {
  9.2238 +        printk(" works.\n");
  9.2239 +        return;
  9.2240 +    }
  9.2241 +    apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
  9.2242 +    printk(" failed.\n");
  9.2243  
  9.2244 -	printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
  9.2245 +    printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
  9.2246  
  9.2247 -	timer_ack = 0;
  9.2248 -	init_8259A(0);
  9.2249 -	make_8259A_irq(0);
  9.2250 -	apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
  9.2251 +    timer_ack = 0;
  9.2252 +    init_8259A(0);
  9.2253 +    make_8259A_irq(0);
  9.2254 +    apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
  9.2255  
  9.2256 -	unlock_ExtINT_logic();
  9.2257 +    unlock_ExtINT_logic();
  9.2258  
  9.2259 -	if (timer_irq_works()) {
  9.2260 -		printk(" works.\n");
  9.2261 -		return;
  9.2262 -	}
  9.2263 -	printk(" failed :(.\n");
  9.2264 -	panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
  9.2265 -		"report.  Then try booting with the 'noapic' option");
  9.2266 +    if (timer_irq_works()) {
  9.2267 +        printk(" works.\n");
  9.2268 +        return;
  9.2269 +    }
  9.2270 +    printk(" failed :(.\n");
  9.2271 +    panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
  9.2272 +          "report.  Then try booting with the 'noapic' option");
  9.2273  }
  9.2274  
  9.2275  #define NR_IOAPIC_BIOSIDS 256
  9.2276 @@ -1596,27 +1508,27 @@ static void store_ioapic_biosid_mapping(
  9.2277  
  9.2278  void __init setup_IO_APIC(void)
  9.2279  {
  9.2280 -	store_ioapic_biosid_mapping();
  9.2281 +    store_ioapic_biosid_mapping();
  9.2282  
  9.2283 -	enable_IO_APIC();
  9.2284 +    enable_IO_APIC();
  9.2285  
  9.2286 -	if (acpi_ioapic)
  9.2287 -		io_apic_irqs = ~0;	/* all IRQs go through IOAPIC */
  9.2288 -	else
  9.2289 -		io_apic_irqs = ~PIC_IRQS;
  9.2290 +    if (acpi_ioapic)
  9.2291 +        io_apic_irqs = ~0;	/* all IRQs go through IOAPIC */
  9.2292 +    else
  9.2293 +        io_apic_irqs = ~PIC_IRQS;
  9.2294  
  9.2295 -	printk("ENABLING IO-APIC IRQs\n");
  9.2296 +    printk("ENABLING IO-APIC IRQs\n");
  9.2297  
  9.2298 -	/*
  9.2299 -	 * Set up IO-APIC IRQ routing.
  9.2300 -	 */
  9.2301 -	if (!acpi_ioapic)
  9.2302 -		setup_ioapic_ids_from_mpc();
  9.2303 -	sync_Arb_IDs();
  9.2304 -	setup_IO_APIC_irqs();
  9.2305 -	init_IO_APIC_traps();
  9.2306 -	check_timer();
  9.2307 -	print_IO_APIC();
  9.2308 +    /*
  9.2309 +     * Set up IO-APIC IRQ routing.
  9.2310 +     */
  9.2311 +    if (!acpi_ioapic)
  9.2312 +        setup_ioapic_ids_from_mpc();
  9.2313 +    sync_Arb_IDs();
  9.2314 +    setup_IO_APIC_irqs();
  9.2315 +    init_IO_APIC_traps();
  9.2316 +    check_timer();
  9.2317 +    print_IO_APIC();
  9.2318  }
  9.2319  
  9.2320  /* --------------------------------------------------------------------------
  9.2321 @@ -1627,153 +1539,153 @@ void __init setup_IO_APIC(void)
  9.2322  
  9.2323  int __init io_apic_get_unique_id (int ioapic, int apic_id)
  9.2324  {
  9.2325 -	union IO_APIC_reg_00 reg_00;
  9.2326 -	static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
  9.2327 -	physid_mask_t tmp;
  9.2328 -	unsigned long flags;
  9.2329 -	int i = 0;
  9.2330 +    union IO_APIC_reg_00 reg_00;
  9.2331 +    static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
  9.2332 +    physid_mask_t tmp;
  9.2333 +    unsigned long flags;
  9.2334 +    int i = 0;
  9.2335  
  9.2336 -	/*
  9.2337 -	 * The P4 platform supports up to 256 APIC IDs on two separate APIC 
  9.2338 -	 * buses (one for LAPICs, one for IOAPICs), where predecessors only 
  9.2339 -	 * supports up to 16 on one shared APIC bus.
  9.2340 -	 * 
  9.2341 -	 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
  9.2342 -	 *      advantage of new APIC bus architecture.
  9.2343 -	 */
  9.2344 +    /*
  9.2345 +     * The P4 platform supports up to 256 APIC IDs on two separate APIC 
  9.2346 +     * buses (one for LAPICs, one for IOAPICs), where predecessors only 
  9.2347 +     * supports up to 16 on one shared APIC bus.
  9.2348 +     * 
  9.2349 +     * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
  9.2350 +     *      advantage of new APIC bus architecture.
  9.2351 +     */
  9.2352  
  9.2353 -	if (physids_empty(apic_id_map))
  9.2354 -		apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
  9.2355 +    if (physids_empty(apic_id_map))
  9.2356 +        apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
  9.2357  
  9.2358 -	spin_lock_irqsave(&ioapic_lock, flags);
  9.2359 -	reg_00.raw = io_apic_read(ioapic, 0);
  9.2360 -	spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2361 +    spin_lock_irqsave(&ioapic_lock, flags);
  9.2362 +    reg_00.raw = io_apic_read(ioapic, 0);
  9.2363 +    spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2364  
  9.2365 -	if (apic_id >= get_physical_broadcast()) {
  9.2366 -		printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
  9.2367 -			"%d\n", ioapic, apic_id, reg_00.bits.ID);
  9.2368 -		apic_id = reg_00.bits.ID;
  9.2369 -	}
  9.2370 +    if (apic_id >= get_physical_broadcast()) {
  9.2371 +        printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
  9.2372 +               "%d\n", ioapic, apic_id, reg_00.bits.ID);
  9.2373 +        apic_id = reg_00.bits.ID;
  9.2374 +    }
  9.2375  
  9.2376 -	/*
  9.2377 -	 * Every APIC in a system must have a unique ID or we get lots of nice 
  9.2378 -	 * 'stuck on smp_invalidate_needed IPI wait' messages.
  9.2379 -	 */
  9.2380 -	if (check_apicid_used(apic_id_map, apic_id)) {
  9.2381 +    /*
  9.2382 +     * Every APIC in a system must have a unique ID or we get lots of nice 
  9.2383 +     * 'stuck on smp_invalidate_needed IPI wait' messages.
  9.2384 +     */
  9.2385 +    if (check_apicid_used(apic_id_map, apic_id)) {
  9.2386  
  9.2387 -		for (i = 0; i < get_physical_broadcast(); i++) {
  9.2388 -			if (!check_apicid_used(apic_id_map, i))
  9.2389 -				break;
  9.2390 -		}
  9.2391 +        for (i = 0; i < get_physical_broadcast(); i++) {
  9.2392 +            if (!check_apicid_used(apic_id_map, i))
  9.2393 +                break;
  9.2394 +        }
  9.2395  
  9.2396 -		if (i == get_physical_broadcast())
  9.2397 -			panic("Max apic_id exceeded!\n");
  9.2398 +        if (i == get_physical_broadcast())
  9.2399 +            panic("Max apic_id exceeded!\n");
  9.2400  
  9.2401 -		printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
  9.2402 -			"trying %d\n", ioapic, apic_id, i);
  9.2403 +        printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
  9.2404 +               "trying %d\n", ioapic, apic_id, i);
  9.2405  
  9.2406 -		apic_id = i;
  9.2407 -	} 
  9.2408 +        apic_id = i;
  9.2409 +    } 
  9.2410  
  9.2411 -	tmp = apicid_to_cpu_present(apic_id);
  9.2412 -	physids_or(apic_id_map, apic_id_map, tmp);
  9.2413 +    tmp = apicid_to_cpu_present(apic_id);
  9.2414 +    physids_or(apic_id_map, apic_id_map, tmp);
  9.2415  
  9.2416 -	if (reg_00.bits.ID != apic_id) {
  9.2417 -		reg_00.bits.ID = apic_id;
  9.2418 +    if (reg_00.bits.ID != apic_id) {
  9.2419 +        reg_00.bits.ID = apic_id;
  9.2420  
  9.2421 -		spin_lock_irqsave(&ioapic_lock, flags);
  9.2422 -		io_apic_write(ioapic, 0, reg_00.raw);
  9.2423 -		reg_00.raw = io_apic_read(ioapic, 0);
  9.2424 -		spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2425 +        spin_lock_irqsave(&ioapic_lock, flags);
  9.2426 +        io_apic_write(ioapic, 0, reg_00.raw);
  9.2427 +        reg_00.raw = io_apic_read(ioapic, 0);
  9.2428 +        spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2429  
  9.2430 -		/* Sanity check */
  9.2431 -		if (reg_00.bits.ID != apic_id)
  9.2432 -			panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
  9.2433 -	}
  9.2434 +        /* Sanity check */
  9.2435 +        if (reg_00.bits.ID != apic_id)
  9.2436 +            panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
  9.2437 +    }
  9.2438  
  9.2439 -	apic_printk(APIC_VERBOSE, KERN_INFO
  9.2440 -			"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
  9.2441 +    apic_printk(APIC_VERBOSE, KERN_INFO
  9.2442 +                "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
  9.2443  
  9.2444 -	return apic_id;
  9.2445 +    return apic_id;
  9.2446  }
  9.2447  
  9.2448  
  9.2449  int __init io_apic_get_version (int ioapic)
  9.2450  {
  9.2451 -	union IO_APIC_reg_01	reg_01;
  9.2452 -	unsigned long flags;
  9.2453 +    union IO_APIC_reg_01	reg_01;
  9.2454 +    unsigned long flags;
  9.2455  
  9.2456 -	spin_lock_irqsave(&ioapic_lock, flags);
  9.2457 -	reg_01.raw = io_apic_read(ioapic, 1);
  9.2458 -	spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2459 +    spin_lock_irqsave(&ioapic_lock, flags);
  9.2460 +    reg_01.raw = io_apic_read(ioapic, 1);
  9.2461 +    spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2462  
  9.2463 -	return reg_01.bits.version;
  9.2464 +    return reg_01.bits.version;
  9.2465  }
  9.2466  
  9.2467  
  9.2468  int __init io_apic_get_redir_entries (int ioapic)
  9.2469  {
  9.2470 -	union IO_APIC_reg_01	reg_01;
  9.2471 -	unsigned long flags;
  9.2472 +    union IO_APIC_reg_01	reg_01;
  9.2473 +    unsigned long flags;
  9.2474  
  9.2475 -	spin_lock_irqsave(&ioapic_lock, flags);
  9.2476 -	reg_01.raw = io_apic_read(ioapic, 1);
  9.2477 -	spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2478 +    spin_lock_irqsave(&ioapic_lock, flags);
  9.2479 +    reg_01.raw = io_apic_read(ioapic, 1);
  9.2480 +    spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2481  
  9.2482 -	return reg_01.bits.entries;
  9.2483 +    return reg_01.bits.entries;
  9.2484  }
  9.2485  
  9.2486  
  9.2487  int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
  9.2488  {
  9.2489 -	struct IO_APIC_route_entry entry;
  9.2490 -	unsigned long flags;
  9.2491 +    struct IO_APIC_route_entry entry;
  9.2492 +    unsigned long flags;
  9.2493  
  9.2494 -	if (!IO_APIC_IRQ(irq)) {
  9.2495 -		printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
  9.2496 -			ioapic);
  9.2497 -		return -EINVAL;
  9.2498 -	}
  9.2499 +    if (!IO_APIC_IRQ(irq)) {
  9.2500 +        printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
  9.2501 +               ioapic);
  9.2502 +        return -EINVAL;
  9.2503 +    }
  9.2504  
  9.2505 -	/*
  9.2506 -	 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
  9.2507 -	 * Note that we mask (disable) IRQs now -- these get enabled when the
  9.2508 -	 * corresponding device driver registers for this IRQ.
  9.2509 -	 */
  9.2510 +    /*
  9.2511 +     * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
  9.2512 +     * Note that we mask (disable) IRQs now -- these get enabled when the
  9.2513 +     * corresponding device driver registers for this IRQ.
  9.2514 +     */
  9.2515  
  9.2516 -	memset(&entry,0,sizeof(entry));
  9.2517 +    memset(&entry,0,sizeof(entry));
  9.2518  
  9.2519 -	entry.delivery_mode = INT_DELIVERY_MODE;
  9.2520 -	entry.dest_mode = INT_DEST_MODE;
  9.2521 -	entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
  9.2522 -	entry.trigger = edge_level;
  9.2523 -	entry.polarity = active_high_low;
  9.2524 -	entry.mask  = 1;
  9.2525 +    entry.delivery_mode = INT_DELIVERY_MODE;
  9.2526 +    entry.dest_mode = INT_DEST_MODE;
  9.2527 +    entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
  9.2528 +    entry.trigger = edge_level;
  9.2529 +    entry.polarity = active_high_low;
  9.2530 +    entry.mask  = 1;
  9.2531  
  9.2532 -	/*
  9.2533 -	 * IRQs < 16 are already in the irq_2_pin[] map
  9.2534 -	 */
  9.2535 -	if (irq >= 16)
  9.2536 -		add_pin_to_irq(irq, ioapic, pin);
  9.2537 +    /*
  9.2538 +     * IRQs < 16 are already in the irq_2_pin[] map
  9.2539 +     */
  9.2540 +    if (irq >= 16)
  9.2541 +        add_pin_to_irq(irq, ioapic, pin);
  9.2542  
  9.2543 -	entry.vector = assign_irq_vector(irq);
  9.2544 +    entry.vector = assign_irq_vector(irq);
  9.2545  
  9.2546 -	apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
  9.2547 +    apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
  9.2548  		"(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
  9.2549  		mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
  9.2550  		edge_level, active_high_low);
  9.2551  
  9.2552 -	ioapic_register_intr(irq, entry.vector, edge_level);
  9.2553 +    ioapic_register_intr(irq, entry.vector, edge_level);
  9.2554  
  9.2555 -	if (!ioapic && (irq < 16))
  9.2556 -		disable_8259A_irq(irq);
  9.2557 +    if (!ioapic && (irq < 16))
  9.2558 +        disable_8259A_irq(irq);
  9.2559  
  9.2560 -	spin_lock_irqsave(&ioapic_lock, flags);
  9.2561 -	io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
  9.2562 -	io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
  9.2563 -	spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2564 +    spin_lock_irqsave(&ioapic_lock, flags);
  9.2565 +    io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
  9.2566 +    io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
  9.2567 +    spin_unlock_irqrestore(&ioapic_lock, flags);
  9.2568  
  9.2569 -	return 0;
  9.2570 +    return 0;
  9.2571  }
  9.2572  
  9.2573  #endif /*CONFIG_ACPI_BOOT*/
  9.2574 @@ -1788,7 +1700,7 @@ int ioapic_guest_read(int apicid, int ad
  9.2575  
  9.2576      if ( (apicid >= NR_IOAPIC_BIOSIDS) ||
  9.2577           ((apicenum = ioapic_biosid_to_apic_enum[apicid]) >= nr_ioapics) )
  9.2578 -            return -EINVAL;
  9.2579 +        return -EINVAL;
  9.2580  
  9.2581      spin_lock_irqsave(&ioapic_lock, flags);
  9.2582      val = io_apic_read(apicenum, address);
  9.2583 @@ -1815,7 +1727,7 @@ int ioapic_guest_write(int apicid, int a
  9.2584  
  9.2585      if ( (apicid >= NR_IOAPIC_BIOSIDS) ||
  9.2586           ((apicenum = ioapic_biosid_to_apic_enum[apicid]) >= nr_ioapics) )
  9.2587 -            return -EINVAL;
  9.2588 +        return -EINVAL;
  9.2589  
  9.2590      /* Only write to the first half of a route entry. */
  9.2591      if ( (address < 0x10) || (address & 1) )
  9.2592 @@ -1834,7 +1746,7 @@ int ioapic_guest_write(int apicid, int a
  9.2593              return 0;
  9.2594  
  9.2595          /* Set the correct irq-handling type. */
  9.2596 -        irq_desc[irq].handler = rte.trigger ? 
  9.2597 +        irq_desc[IO_APIC_VECTOR(irq)].handler = rte.trigger ? 
  9.2598              &ioapic_level_type: &ioapic_edge_type;
  9.2599  
  9.2600          /* Record the pin<->irq mapping. */
    10.1 --- a/xen/arch/x86/irq.c	Wed Jun 08 12:48:07 2005 +0000
    10.2 +++ b/xen/arch/x86/irq.c	Thu Jun 09 09:20:02 2005 +0000
    10.3 @@ -16,16 +16,16 @@
    10.4  
    10.5  irq_desc_t irq_desc[NR_IRQS];
    10.6  
    10.7 -static void __do_IRQ_guest(int irq);
    10.8 +static void __do_IRQ_guest(int vector);
    10.9  
   10.10  void no_action(int cpl, void *dev_id, struct cpu_user_regs *regs) { }
   10.11  
   10.12 -static void enable_none(unsigned int irq) { }
   10.13 -static unsigned int startup_none(unsigned int irq) { return 0; }
   10.14 -static void disable_none(unsigned int irq) { }
   10.15 -static void ack_none(unsigned int irq)
   10.16 +static void enable_none(unsigned int vector) { }
   10.17 +static unsigned int startup_none(unsigned int vector) { return 0; }
   10.18 +static void disable_none(unsigned int vector) { }
   10.19 +static void ack_none(unsigned int vector)
   10.20  {
   10.21 -    printk("Unexpected IRQ trap at vector %02x.\n", irq);
   10.22 +    printk("Unexpected IRQ trap at vector %02x.\n", vector);
   10.23      ack_APIC_irq();
   10.24  }
   10.25  
   10.26 @@ -46,7 +46,8 @@ atomic_t irq_err_count;
   10.27  
   10.28  inline void disable_irq_nosync(unsigned int irq)
   10.29  {
   10.30 -    irq_desc_t   *desc = &irq_desc[irq];
   10.31 +    unsigned int  vector = irq_to_vector(irq);
   10.32 +    irq_desc_t   *desc = &irq_desc[vector];
   10.33      unsigned long flags;
   10.34  
   10.35      spin_lock_irqsave(&desc->lock, flags);
   10.36 @@ -54,21 +55,16 @@ inline void disable_irq_nosync(unsigned 
   10.37      if ( desc->depth++ == 0 )
   10.38      {
   10.39          desc->status |= IRQ_DISABLED;
   10.40 -        desc->handler->disable(irq);
   10.41 +        desc->handler->disable(vector);
   10.42      }
   10.43  
   10.44      spin_unlock_irqrestore(&desc->lock, flags);
   10.45  }
   10.46  
   10.47 -void disable_irq(unsigned int irq)
   10.48 -{
   10.49 -    disable_irq_nosync(irq);
   10.50 -    do { smp_mb(); } while ( irq_desc[irq].status & IRQ_INPROGRESS );
   10.51 -}
   10.52 -
   10.53  void enable_irq(unsigned int irq)
   10.54  {
   10.55 -    irq_desc_t   *desc = &irq_desc[irq];
   10.56 +    unsigned int  vector = irq_to_vector(irq);
   10.57 +    irq_desc_t   *desc = &irq_desc[vector];
   10.58      unsigned long flags;
   10.59  
   10.60      spin_lock_irqsave(&desc->lock, flags);
   10.61 @@ -77,30 +73,27 @@ void enable_irq(unsigned int irq)
   10.62      {
   10.63          desc->status &= ~IRQ_DISABLED;
   10.64          if ( (desc->status & (IRQ_PENDING | IRQ_REPLAY)) == IRQ_PENDING )
   10.65 -        {
   10.66              desc->status |= IRQ_REPLAY;
   10.67 -            hw_resend_irq(desc->handler,irq);
   10.68 -        }
   10.69 -        desc->handler->enable(irq);
   10.70 +        desc->handler->enable(vector);
   10.71      }
   10.72  
   10.73      spin_unlock_irqrestore(&desc->lock, flags);
   10.74  }
   10.75  
   10.76  asmlinkage void do_IRQ(struct cpu_user_regs *regs)
   10.77 -{       
   10.78 -    unsigned int      irq = regs->entry_vector;
   10.79 -    irq_desc_t       *desc = &irq_desc[irq];
   10.80 +{
   10.81 +    unsigned int      vector = regs->entry_vector;
   10.82 +    irq_desc_t       *desc = &irq_desc[vector];
   10.83      struct irqaction *action;
   10.84  
   10.85      perfc_incrc(irqs);
   10.86  
   10.87      spin_lock(&desc->lock);
   10.88 -    desc->handler->ack(irq);
   10.89 +    desc->handler->ack(vector);
   10.90  
   10.91      if ( likely(desc->status & IRQ_GUEST) )
   10.92      {
   10.93 -        __do_IRQ_guest(irq);
   10.94 +        __do_IRQ_guest(vector);
   10.95          spin_unlock(&desc->lock);
   10.96          return;
   10.97      }
   10.98 @@ -121,23 +114,24 @@ asmlinkage void do_IRQ(struct cpu_user_r
   10.99      while ( desc->status & IRQ_PENDING )
  10.100      {
  10.101          desc->status &= ~IRQ_PENDING;
  10.102 -        irq_enter(smp_processor_id(), irq);
  10.103 +        irq_enter(smp_processor_id());
  10.104          spin_unlock_irq(&desc->lock);
  10.105 -        action->handler(irq, action->dev_id, regs);
  10.106 +        action->handler(vector_to_irq(vector), action->dev_id, regs);
  10.107          spin_lock_irq(&desc->lock);
  10.108 -        irq_exit(smp_processor_id(), irq);
  10.109 +        irq_exit(smp_processor_id());
  10.110      }
  10.111  
  10.112      desc->status &= ~IRQ_INPROGRESS;
  10.113  
  10.114   out:
  10.115 -    desc->handler->end(irq);
  10.116 +    desc->handler->end(vector);
  10.117      spin_unlock(&desc->lock);
  10.118  }
  10.119  
  10.120  void free_irq(unsigned int irq)
  10.121  {
  10.122 -    irq_desc_t   *desc = &irq_desc[irq];
  10.123 +    unsigned int  vector = irq_to_vector(irq);
  10.124 +    irq_desc_t   *desc = &irq_desc[vector];
  10.125      unsigned long flags;
  10.126  
  10.127      spin_lock_irqsave(&desc->lock,flags);
  10.128 @@ -148,12 +142,13 @@ void free_irq(unsigned int irq)
  10.129      spin_unlock_irqrestore(&desc->lock,flags);
  10.130  
  10.131      /* Wait to make sure it's not being used on another CPU */
  10.132 -    do { smp_mb(); } while ( irq_desc[irq].status & IRQ_INPROGRESS );
  10.133 +    do { smp_mb(); } while ( desc->status & IRQ_INPROGRESS );
  10.134  }
  10.135  
  10.136  int setup_irq(unsigned int irq, struct irqaction *new)
  10.137  {
  10.138 -    irq_desc_t   *desc = &irq_desc[irq];
  10.139 +    unsigned int  vector = irq_to_vector(irq);
  10.140 +    irq_desc_t   *desc = &irq_desc[vector];
  10.141      unsigned long flags;
  10.142   
  10.143      spin_lock_irqsave(&desc->lock,flags);
  10.144 @@ -167,7 +162,7 @@ int setup_irq(unsigned int irq, struct i
  10.145      desc->action  = new;
  10.146      desc->depth   = 0;
  10.147      desc->status &= ~IRQ_DISABLED;
  10.148 -    desc->handler->startup(irq);
  10.149 +    desc->handler->startup(vector);
  10.150  
  10.151      spin_unlock_irqrestore(&desc->lock,flags);
  10.152  
  10.153 @@ -187,9 +182,10 @@ typedef struct {
  10.154      struct domain *guest[IRQ_MAX_GUESTS];
  10.155  } irq_guest_action_t;
  10.156  
  10.157 -static void __do_IRQ_guest(int irq)
  10.158 +static void __do_IRQ_guest(int vector)
  10.159  {
  10.160 -    irq_desc_t         *desc = &irq_desc[irq];
  10.161 +    unsigned int        irq = vector_to_irq(vector);
  10.162 +    irq_desc_t         *desc = &irq_desc[vector];
  10.163      irq_guest_action_t *action = (irq_guest_action_t *)desc->action;
  10.164      struct domain      *d;
  10.165      int                 i;
  10.166 @@ -218,12 +214,12 @@ int pirq_guest_unmask(struct domain *d)
  10.167              j = find_first_set_bit(m);
  10.168              m &= ~(1 << j);
  10.169              pirq = (i << 5) + j;
  10.170 -            desc = &irq_desc[pirq];
  10.171 +            desc = &irq_desc[irq_to_vector(pirq)];
  10.172              spin_lock_irq(&desc->lock);
  10.173              if ( !test_bit(d->pirq_to_evtchn[pirq], &s->evtchn_mask[0]) &&
  10.174                   test_and_clear_bit(pirq, &d->pirq_mask) &&
  10.175                   (--((irq_guest_action_t *)desc->action)->in_flight == 0) )
  10.176 -                desc->handler->end(pirq);
  10.177 +                desc->handler->end(irq_to_vector(pirq));
  10.178              spin_unlock_irq(&desc->lock);
  10.179          }
  10.180      }
  10.181 @@ -233,8 +229,9 @@ int pirq_guest_unmask(struct domain *d)
  10.182  
  10.183  int pirq_guest_bind(struct vcpu *v, int irq, int will_share)
  10.184  {
  10.185 +    unsigned int        vector = irq_to_vector(irq);
  10.186      struct domain      *d = v->domain;
  10.187 -    irq_desc_t         *desc = &irq_desc[irq];
  10.188 +    irq_desc_t         *desc = &irq_desc[vector];
  10.189      irq_guest_action_t *action;
  10.190      unsigned long       flags;
  10.191      int                 rc = 0;
  10.192 @@ -243,6 +240,9 @@ int pirq_guest_bind(struct vcpu *v, int 
  10.193      if ( !IS_CAPABLE_PHYSDEV(d) )
  10.194          return -EPERM;
  10.195  
  10.196 +    if ( vector == 0 )
  10.197 +        return -EBUSY;
  10.198 +
  10.199      spin_lock_irqsave(&desc->lock, flags);
  10.200  
  10.201      action = (irq_guest_action_t *)desc->action;
  10.202 @@ -272,12 +272,12 @@ int pirq_guest_bind(struct vcpu *v, int 
  10.203          desc->depth = 0;
  10.204          desc->status |= IRQ_GUEST;
  10.205          desc->status &= ~IRQ_DISABLED;
  10.206 -        desc->handler->startup(irq);
  10.207 +        desc->handler->startup(vector);
  10.208  
  10.209          /* Attempt to bind the interrupt target to the correct CPU. */
  10.210          cpu_set(v->processor, cpumask);
  10.211          if ( desc->handler->set_affinity != NULL )
  10.212 -            desc->handler->set_affinity(irq, cpumask);
  10.213 +            desc->handler->set_affinity(vector, cpumask);
  10.214      }
  10.215      else if ( !will_share || !action->shareable )
  10.216      {
  10.217 @@ -303,18 +303,21 @@ int pirq_guest_bind(struct vcpu *v, int 
  10.218  
  10.219  int pirq_guest_unbind(struct domain *d, int irq)
  10.220  {
  10.221 -    irq_desc_t         *desc = &irq_desc[irq];
  10.222 +    unsigned int        vector = irq_to_vector(irq);
  10.223 +    irq_desc_t         *desc = &irq_desc[vector];
  10.224      irq_guest_action_t *action;
  10.225      unsigned long       flags;
  10.226      int                 i;
  10.227  
  10.228 +    BUG_ON(vector == 0);
  10.229 +
  10.230      spin_lock_irqsave(&desc->lock, flags);
  10.231  
  10.232      action = (irq_guest_action_t *)desc->action;
  10.233  
  10.234      if ( test_and_clear_bit(irq, &d->pirq_mask) &&
  10.235           (--action->in_flight == 0) )
  10.236 -        desc->handler->end(irq);
  10.237 +        desc->handler->end(vector);
  10.238  
  10.239      if ( action->nr_guests == 1 )
  10.240      {
  10.241 @@ -323,7 +326,7 @@ int pirq_guest_unbind(struct domain *d, 
  10.242          desc->depth   = 1;
  10.243          desc->status |= IRQ_DISABLED;
  10.244          desc->status &= ~IRQ_GUEST;
  10.245 -        desc->handler->shutdown(irq);
  10.246 +        desc->handler->shutdown(vector);
  10.247      }
  10.248      else
  10.249      {
  10.250 @@ -337,26 +340,3 @@ int pirq_guest_unbind(struct domain *d, 
  10.251      spin_unlock_irqrestore(&desc->lock, flags);    
  10.252      return 0;
  10.253  }
  10.254 -
  10.255 -int pirq_guest_bindable(int irq, int will_share)
  10.256 -{
  10.257 -    irq_desc_t         *desc = &irq_desc[irq];
  10.258 -    irq_guest_action_t *action;
  10.259 -    unsigned long       flags;
  10.260 -    int                 okay;
  10.261 -
  10.262 -    spin_lock_irqsave(&desc->lock, flags);
  10.263 -
  10.264 -    action = (irq_guest_action_t *)desc->action;
  10.265 -
  10.266 -    /*
  10.267 -     * To be bindable the IRQ must either be not currently bound (1), or
  10.268 -     * it must be shareable (2) and not at its share limit (3).
  10.269 -     */
  10.270 -    okay = ((!(desc->status & IRQ_GUEST) && (action == NULL)) || /* 1 */
  10.271 -            (action->shareable && will_share &&                  /* 2 */
  10.272 -             (action->nr_guests != IRQ_MAX_GUESTS)));            /* 3 */
  10.273 -
  10.274 -    spin_unlock_irqrestore(&desc->lock, flags);
  10.275 -    return okay;
  10.276 -}
    11.1 --- a/xen/arch/x86/mm.c	Wed Jun 08 12:48:07 2005 +0000
    11.2 +++ b/xen/arch/x86/mm.c	Thu Jun 09 09:20:02 2005 +0000
    11.3 @@ -1104,7 +1104,7 @@ static int mod_l3_entry(l3_pgentry_t *pl
    11.4          return 0;
    11.5      }
    11.6  
    11.7 -#ifdef CONFIG_PAE
    11.8 +#ifdef CONFIG_X86_PAE
    11.9      /*
   11.10       * Disallow updates to final L3 slot. It contains Xen mappings, and it
   11.11       * would be a pain to ensure they remain continuously valid throughout.
   11.12 @@ -1400,7 +1400,7 @@ int get_page_type(struct pfn_info *page,
   11.13                  else if ( ((type & PGT_va_mask) != PGT_va_mutable) &&
   11.14                            ((type & PGT_va_mask) != (x & PGT_va_mask)) )
   11.15                  {
   11.16 -#ifdef CONFIG_PAE
   11.17 +#ifdef CONFIG_X86_PAE
   11.18                      /* We use backptr as extra typing. Cannot be unknown. */
   11.19                      if ( (type & PGT_type_mask) == PGT_l2_page_table )
   11.20                          return 0;
   11.21 @@ -1671,7 +1671,7 @@ int do_mmuext_op(
   11.22              
   11.23              break;
   11.24  
   11.25 -#ifndef CONFIG_PAE /* Unsafe on PAE because of Xen-private mappings. */
   11.26 +#ifndef CONFIG_X86_PAE /* Unsafe on PAE because of Xen-private mappings. */
   11.27          case MMUEXT_PIN_L2_TABLE:
   11.28              type = PGT_l2_page_table;
   11.29              goto pin_page;
    12.1 --- a/xen/arch/x86/physdev.c	Wed Jun 08 12:48:07 2005 +0000
    12.2 +++ b/xen/arch/x86/physdev.c	Thu Jun 09 09:20:02 2005 +0000
    12.3 @@ -60,7 +60,7 @@ long do_physdev_op(physdev_op_t *uop)
    12.4              break;
    12.5          op.u.irq_status_query.flags = 0;
    12.6          /* Edge-triggered interrupts don't need an explicit unmask downcall. */
    12.7 -        if ( strstr(irq_desc[irq].handler->typename, "edge") == NULL )
    12.8 +        if ( strstr(irq_desc[irq_to_vector(irq)].handler->typename, "edge") == NULL )
    12.9              op.u.irq_status_query.flags |= PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY;
   12.10          ret = 0;
   12.11          break;
   12.12 @@ -89,7 +89,6 @@ long do_physdev_op(physdev_op_t *uop)
   12.13              return -EINVAL;
   12.14          
   12.15          op.u.irq_op.vector = assign_irq_vector(irq);
   12.16 -        set_intr_gate(op.u.irq_op.vector, interrupt[irq]);
   12.17          ret = 0;
   12.18          break;
   12.19  
    13.1 --- a/xen/arch/x86/setup.c	Wed Jun 08 12:48:07 2005 +0000
    13.2 +++ b/xen/arch/x86/setup.c	Thu Jun 09 09:20:02 2005 +0000
    13.3 @@ -33,10 +33,6 @@ static unsigned int opt_xenheap_megabyte
    13.4  integer_param("xenheap_megabytes", opt_xenheap_megabytes);
    13.5  #endif
    13.6  
    13.7 -/* opt_noht: If true, Hyperthreading is ignored. */
    13.8 -int opt_noht = 0;
    13.9 -boolean_param("noht", opt_noht);
   13.10 -
   13.11  /* opt_nosmp: If true, secondary processors are ignored. */
   13.12  static int opt_nosmp = 0;
   13.13  boolean_param("nosmp", opt_nosmp);
    14.1 --- a/xen/arch/x86/smpboot.c	Wed Jun 08 12:48:07 2005 +0000
    14.2 +++ b/xen/arch/x86/smpboot.c	Thu Jun 09 09:20:02 2005 +0000
    14.3 @@ -1178,12 +1178,6 @@ void __init smp_cpus_done(unsigned int m
    14.4  void __init smp_intr_init(void)
    14.5  {
    14.6  	/*
    14.7 -	 * IRQ0 must be given a fixed assignment and initialized,
    14.8 -	 * because it's used before the IO-APIC is set up.
    14.9 -	 */
   14.10 -	set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
   14.11 -
   14.12 -	/*
   14.13  	 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
   14.14  	 * IPI, driven by wakeup.
   14.15  	 */
    15.1 --- a/xen/arch/x86/vmx.c	Wed Jun 08 12:48:07 2005 +0000
    15.2 +++ b/xen/arch/x86/vmx.c	Thu Jun 09 09:20:02 2005 +0000
    15.3 @@ -1262,8 +1262,7 @@ asmlinkage void vmx_vmexit_handler(struc
    15.4          if (vector == LOCAL_TIMER_VECTOR) {
    15.5              smp_apic_timer_interrupt(&regs);
    15.6          } else {
    15.7 -            regs.entry_vector = (vector == FIRST_DEVICE_VECTOR?
    15.8 -                     0 : vector_irq[vector]);
    15.9 +            regs.entry_vector = vector;
   15.10              do_IRQ(&regs);
   15.11          }
   15.12          break;
    16.1 --- a/xen/arch/x86/vmx_vmcs.c	Wed Jun 08 12:48:07 2005 +0000
    16.2 +++ b/xen/arch/x86/vmx_vmcs.c	Thu Jun 09 09:20:02 2005 +0000
    16.3 @@ -445,12 +445,12 @@ int store_vmcs(struct arch_vmx_struct *a
    16.4  
    16.5  void vm_launch_fail(unsigned long eflags)
    16.6  {
    16.7 -    BUG();
    16.8 +    __vmx_bug(guest_cpu_user_regs());
    16.9  }
   16.10  
   16.11  void vm_resume_fail(unsigned long eflags)
   16.12  {
   16.13 -    BUG();
   16.14 +    __vmx_bug(guest_cpu_user_regs());
   16.15  }
   16.16  
   16.17  #endif /* CONFIG_VMX */
    17.1 --- a/xen/include/asm-ia64/config.h	Wed Jun 08 12:48:07 2005 +0000
    17.2 +++ b/xen/include/asm-ia64/config.h	Thu Jun 09 09:20:02 2005 +0000
    17.3 @@ -225,7 +225,6 @@ struct screen_info { };
    17.4  #define FORCE_CRASH()	asm("break 0;;");
    17.5  
    17.6  // these declarations got moved at some point, find a better place for them
    17.7 -extern int opt_noht;
    17.8  extern int ht_per_core;
    17.9  
   17.10  // needed for include/xen/smp.h
    18.1 --- a/xen/include/asm-x86/hardirq.h	Wed Jun 08 12:48:07 2005 +0000
    18.2 +++ b/xen/include/asm-x86/hardirq.h	Thu Jun 09 09:20:02 2005 +0000
    18.3 @@ -15,7 +15,7 @@ typedef struct {
    18.4  
    18.5  #define in_irq() (local_irq_count(smp_processor_id()) != 0)
    18.6  
    18.7 -#define irq_enter(cpu, irq)	(local_irq_count(cpu)++)
    18.8 -#define irq_exit(cpu, irq)	(local_irq_count(cpu)--)
    18.9 +#define irq_enter(cpu)	(local_irq_count(cpu)++)
   18.10 +#define irq_exit(cpu)	(local_irq_count(cpu)--)
   18.11  
   18.12  #endif /* __ASM_HARDIRQ_H */
    19.1 --- a/xen/include/asm-x86/io_apic.h	Wed Jun 08 12:48:07 2005 +0000
    19.2 +++ b/xen/include/asm-x86/io_apic.h	Thu Jun 09 09:20:02 2005 +0000
    19.3 @@ -14,44 +14,6 @@
    19.4  
    19.5  #ifdef CONFIG_X86_IO_APIC
    19.6  
    19.7 -#ifdef CONFIG_PCI_MSI
    19.8 -static inline int use_pci_vector(void)	{return 1;}
    19.9 -static inline void disable_edge_ioapic_vector(unsigned int vector) { }
   19.10 -static inline void end_edge_ioapic_vector (unsigned int vector) { }
   19.11 -#define startup_level_ioapic	startup_level_ioapic_vector
   19.12 -#define shutdown_level_ioapic	mask_IO_APIC_vector
   19.13 -#define enable_level_ioapic	unmask_IO_APIC_vector
   19.14 -#define disable_level_ioapic	mask_IO_APIC_vector
   19.15 -#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_vector
   19.16 -#define end_level_ioapic	end_level_ioapic_vector
   19.17 -#define set_ioapic_affinity	set_ioapic_affinity_vector
   19.18 -
   19.19 -#define startup_edge_ioapic 	startup_edge_ioapic_vector
   19.20 -#define shutdown_edge_ioapic 	disable_edge_ioapic_vector
   19.21 -#define enable_edge_ioapic 	unmask_IO_APIC_vector
   19.22 -#define disable_edge_ioapic 	disable_edge_ioapic_vector
   19.23 -#define ack_edge_ioapic 	ack_edge_ioapic_vector
   19.24 -#define end_edge_ioapic 	end_edge_ioapic_vector
   19.25 -#else
   19.26 -static inline int use_pci_vector(void)	{return 0;}
   19.27 -static inline void disable_edge_ioapic_irq(unsigned int irq) { }
   19.28 -static inline void end_edge_ioapic_irq (unsigned int irq) { }
   19.29 -#define startup_level_ioapic	startup_level_ioapic_irq
   19.30 -#define shutdown_level_ioapic	mask_IO_APIC_irq
   19.31 -#define enable_level_ioapic	unmask_IO_APIC_irq
   19.32 -#define disable_level_ioapic	mask_IO_APIC_irq
   19.33 -#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_irq
   19.34 -#define end_level_ioapic	end_level_ioapic_irq
   19.35 -#define set_ioapic_affinity	set_ioapic_affinity_irq
   19.36 -
   19.37 -#define startup_edge_ioapic 	startup_edge_ioapic_irq
   19.38 -#define shutdown_edge_ioapic 	disable_edge_ioapic_irq
   19.39 -#define enable_edge_ioapic 	unmask_IO_APIC_irq
   19.40 -#define disable_edge_ioapic 	disable_edge_ioapic_irq
   19.41 -#define ack_edge_ioapic 	ack_edge_ioapic_irq
   19.42 -#define end_edge_ioapic 	end_edge_ioapic_irq
   19.43 -#endif
   19.44 -
   19.45  #define IO_APIC_BASE(idx) \
   19.46  		((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
   19.47  		+ (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
    20.1 --- a/xen/include/asm-x86/irq.h	Wed Jun 08 12:48:07 2005 +0000
    20.2 +++ b/xen/include/asm-x86/irq.h	Thu Jun 09 09:20:02 2005 +0000
    20.3 @@ -8,17 +8,23 @@
    20.4  #include <asm/asm_defns.h>
    20.5  #include <irq_vectors.h>
    20.6  
    20.7 -extern void disable_irq(unsigned int);
    20.8 +#define IO_APIC_IRQ(irq)    (((irq) >= 16) || ((1<<(irq)) & io_apic_irqs))
    20.9 +#define IO_APIC_VECTOR(irq) (irq_vector[irq])
   20.10 +
   20.11 +#define LEGACY_VECTOR(irq)          ((irq) + FIRST_EXTERNAL_VECTOR)
   20.12 +#define LEGACY_IRQ_FROM_VECTOR(vec) ((vec) - FIRST_EXTERNAL_VECTOR)
   20.13 +
   20.14 +#define irq_to_vector(irq)  \
   20.15 +    (IO_APIC_IRQ(irq) ? IO_APIC_VECTOR(irq) : LEGACY_VECTOR(irq))
   20.16 +#define vector_to_irq(vec)  (vector_irq[vec])
   20.17 +
   20.18  extern void disable_irq_nosync(unsigned int);
   20.19  extern void enable_irq(unsigned int);
   20.20  
   20.21  extern int vector_irq[NR_VECTORS];
   20.22  extern u8 irq_vector[NR_IRQ_VECTORS];
   20.23 -#define IO_APIC_VECTOR(irq)     irq_vector[irq]
   20.24  #define AUTO_ASSIGN             -1
   20.25  
   20.26 -extern void (*interrupt[NR_IRQS])(void);
   20.27 -
   20.28  #define platform_legacy_irq(irq)	((irq) < 16)
   20.29  
   20.30  void disable_8259A_irq(unsigned int irq);
   20.31 @@ -26,13 +32,10 @@ void enable_8259A_irq(unsigned int irq);
   20.32  int i8259A_irq_pending(unsigned int irq);
   20.33  void make_8259A_irq(unsigned int irq);
   20.34  void init_8259A(int aeoi);
   20.35 -void send_IPI_self(int vector);
   20.36 -void init_VISWS_APIC_irqs(void);
   20.37 +
   20.38  void setup_IO_APIC(void);
   20.39  void disable_IO_APIC(void);
   20.40  void print_IO_APIC(void);
   20.41 -int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn);
   20.42 -void send_IPI(int dest, int vector);
   20.43  void setup_ioapic_dest(void);
   20.44  
   20.45  extern unsigned long io_apic_irqs;
   20.46 @@ -40,12 +43,4 @@ extern unsigned long io_apic_irqs;
   20.47  extern atomic_t irq_err_count;
   20.48  extern atomic_t irq_mis_count;
   20.49  
   20.50 -#define IO_APIC_IRQ(x) (((x) >= 16) || ((1<<(x)) & io_apic_irqs))
   20.51 -
   20.52 -static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i)
   20.53 -{
   20.54 -    if (IO_APIC_IRQ(i))
   20.55 -        send_IPI_self(IO_APIC_VECTOR(i));
   20.56 -}
   20.57 -
   20.58  #endif /* _ASM_HW_IRQ_H */
    21.1 --- a/xen/include/asm-x86/page.h	Wed Jun 08 12:48:07 2005 +0000
    21.2 +++ b/xen/include/asm-x86/page.h	Thu Jun 09 09:20:02 2005 +0000
    21.3 @@ -185,7 +185,7 @@ typedef struct { u64 pfn; } pagetable_t;
    21.4  #define pfn_valid(_pfn)     ((_pfn) < max_page)
    21.5  
    21.6  /* High table entries are reserved by the hypervisor. */
    21.7 -#if defined(CONFIG_X86_32) && !defined(CONFIG_PAE)
    21.8 +#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
    21.9  #define DOMAIN_ENTRIES_PER_L2_PAGETABLE     \
   21.10    (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
   21.11  #define HYPERVISOR_ENTRIES_PER_L2_PAGETABLE \
    22.1 --- a/xen/include/xen/irq.h	Wed Jun 08 12:48:07 2005 +0000
    22.2 +++ b/xen/include/xen/irq.h	Thu Jun 09 09:20:02 2005 +0000
    22.3 @@ -71,6 +71,5 @@ struct vcpu;
    22.4  extern int pirq_guest_unmask(struct domain *p);
    22.5  extern int pirq_guest_bind(struct vcpu *p, int irq, int will_share);
    22.6  extern int pirq_guest_unbind(struct domain *p, int irq);
    22.7 -extern int pirq_guest_bindable(int irq, int will_share);
    22.8  
    22.9  #endif /* __XEN_IRQ_H__ */
    23.1 --- a/xen/include/xen/smp.h	Wed Jun 08 12:48:07 2005 +0000
    23.2 +++ b/xen/include/xen/smp.h	Thu Jun 09 09:20:02 2005 +0000
    23.3 @@ -59,7 +59,6 @@ static inline int on_each_cpu(void (*fun
    23.4  }
    23.5  
    23.6  extern int ht_per_core;
    23.7 -extern int opt_noht;
    23.8  
    23.9  extern volatile unsigned long smp_msg_data;
   23.10  extern volatile int smp_src_cpu;