ia64/xen-unstable

changeset 16037:949664900fff

xentrace: Fix xentrace_format for new file format.
Signed-off-by: Atsushi SAKAI <sakaia@jp.fujitsu.com>
author Keir Fraser <keir@xensource.com>
date Tue Oct 02 09:31:40 2007 +0100 (2007-10-02)
parents 016cb0f193ba
children 60c898eeb17b
files tools/xentrace/xentrace_format
line diff
     1.1 --- a/tools/xentrace/xentrace_format	Tue Oct 02 09:30:36 2007 +0100
     1.2 +++ b/tools/xentrace/xentrace_format	Tue Oct 02 09:31:40 2007 +0100
     1.3 @@ -83,11 +83,24 @@ interrupted = 0
     1.4  
     1.5  defs = read_defs(arg[0])
     1.6  
     1.7 -# structure of trace record + prepended CPU id (as output by xentrace):
     1.8 -# CPU(I) TSC(Q) EVENT(L) D1(L) D2(L) D3(L) D4(L) D5(L)
     1.9 -# read CPU id separately to avoid structure packing problems on 64-bit arch.
    1.10 -CPUREC = "I"
    1.11 -TRCREC = "QLLLLLL"
    1.12 +# structure of trace record (as output by xentrace):
    1.13 +# HDR(I) {TSC(Q)} D1(I) D2(I) D3(I) D4(I) D5(I)
    1.14 +#
    1.15 +# HDR consists of EVENT:28:, n_data:3:, tsc_in:1:
    1.16 +# EVENT means Event ID
    1.17 +# n_data means number of data (like D1, D2, ...)
    1.18 +# tsc_in means TSC data exists(1) or not(0).
    1.19 +# if tsc_in == 0, TSC(Q) does not exists.
    1.20 +#
    1.21 +# CPU ID exists on trace data of EVENT=0x0001f003
    1.22 +#
    1.23 +HDRREC = "I"
    1.24 +TSCREC = "Q"
    1.25 +D1REC  = "I"
    1.26 +D2REC  = "II"
    1.27 +D3REC  = "III"
    1.28 +D4REC  = "IIII"
    1.29 +D5REC  = "IIIII"
    1.30  
    1.31  last_tsc = [0]
    1.32  
    1.33 @@ -96,19 +109,58 @@ i=0
    1.34  while not interrupted:
    1.35      try:
    1.36  	i=i+1
    1.37 -        line = sys.stdin.read(struct.calcsize(CPUREC))
    1.38 +        line = sys.stdin.read(struct.calcsize(HDRREC))
    1.39          if not line:
    1.40              break
    1.41 -        cpu = struct.unpack(CPUREC, line)[0]
    1.42 +        event = struct.unpack(HDRREC, line)[0]
    1.43 +        n_data = event >> 28 & 0x7
    1.44 +        tsc_in = event >> 31
    1.45  
    1.46 -        line = sys.stdin.read(struct.calcsize(TRCREC))
    1.47 -        if not line:
    1.48 -            break
    1.49 +        d1 = 0
    1.50 +        d2 = 0
    1.51 +        d3 = 0
    1.52 +        d4 = 0
    1.53 +        d5 = 0
    1.54 +  
    1.55 +        tsc = 0
    1.56  
    1.57 -        (tsc, event, d1, d2, d3, d4, d5) = struct.unpack(TRCREC, line)
    1.58 +        if tsc_in == 1:
    1.59 +            line = sys.stdin.read(struct.calcsize(TSCREC))
    1.60 +            if not line:
    1.61 +                break
    1.62 +            tsc = struct.unpack(TSCREC, line)[0]
    1.63  
    1.64 -        # Event field is 'uint32_t', not 'long'.
    1.65 -        event &= 0xffffffff
    1.66 +        if n_data == 1:
    1.67 +            line = sys.stdin.read(struct.calcsize(D1REC))
    1.68 +            if not line:
    1.69 +                break
    1.70 +            (d1) = struct.unpack(D1REC, line)
    1.71 +        if n_data == 2:
    1.72 +            line = sys.stdin.read(struct.calcsize(D2REC))
    1.73 +            if not line:
    1.74 +                break
    1.75 +            (d1, d2) = struct.unpack(D2REC, line)
    1.76 +        if n_data == 3:
    1.77 +            line = sys.stdin.read(struct.calcsize(D3REC))
    1.78 +            if not line:
    1.79 +                break
    1.80 +            (d1, d2, d3) = struct.unpack(D3REC, line)
    1.81 +        if n_data == 4:
    1.82 +            line = sys.stdin.read(struct.calcsize(D4REC))
    1.83 +            if not line:
    1.84 +                break
    1.85 +            (d1, d2, d3, d4) = struct.unpack(D4REC, line)
    1.86 +        if n_data == 5:
    1.87 +            line = sys.stdin.read(struct.calcsize(D5REC))
    1.88 +            if not line:
    1.89 +                break
    1.90 +            (d1, d2, d3, d4, d5) = struct.unpack(D5REC, line)
    1.91 +
    1.92 +        # Event field is 28bit of 'uint32_t' in header, not 'long'.
    1.93 +        event &= 0x0fffffff
    1.94 +        if event == 0x1f003:
    1.95 +            cpu = d1
    1.96 +
    1.97  
    1.98  	#tsc = (tscH<<32) | tscL
    1.99  
   1.100 @@ -116,16 +168,17 @@ while not interrupted:
   1.101  
   1.102          if cpu >= len(last_tsc):
   1.103              last_tsc += [0] * (cpu - len(last_tsc) + 1)
   1.104 -	elif tsc < last_tsc[cpu]:
   1.105 +	elif tsc < last_tsc[cpu] and tsc_in == 1:
   1.106  	    print "TSC stepped backward cpu %d !  %d %d" % (cpu,tsc,last_tsc[cpu])
   1.107  
   1.108  	# provide relative TSC
   1.109 -	if last_tsc[cpu] > 0:
   1.110 +	if last_tsc[cpu] > 0 and tsc_in == 1:
   1.111  		reltsc = tsc - last_tsc[cpu]
   1.112  	else:
   1.113  		reltsc = 0
   1.114  
   1.115 -	last_tsc[cpu] = tsc
   1.116 +	if tsc_in == 1:
   1.117 +	    last_tsc[cpu] = tsc
   1.118  
   1.119  	if mhz:
   1.120  	    tsc = tsc / (mhz*1000000.0)