ia64/xen-unstable

changeset 16283:9379c83e14b5

x86, hvm: Flush local TLB after any change to linear pagetable mapping.

This was not needed when vmenter/vmexit always had the side effect of
flushing host TLBs.

But, with SVM ASIDs, it is possible to:
(1) Update CR3 update,
(2) vmenter the guest, and
(3) and vmexit due to a page fault
all without an intervening host TLB flush.

Then the page fault code could use the linear pagetable
to read a top-level shadow page table entry.

But, without this change, it would fetch the wrong value
due to a stale TLB.

Signed-off-by: Robert Phillips <rphillips@virtualiron.com>
Signed-off-by: Ben Guthro <bguthro@virtualiron.com>
author Keir Fraser <keir@xensource.com>
date Tue Oct 30 16:15:17 2007 +0000 (2007-10-30)
parents 44dde35cb2a6
children 7eb68d995aa7
files xen/arch/x86/mm/shadow/multi.c
line diff
     1.1 --- a/xen/arch/x86/mm/shadow/multi.c	Tue Oct 30 16:11:47 2007 +0000
     1.2 +++ b/xen/arch/x86/mm/shadow/multi.c	Tue Oct 30 16:15:17 2007 +0000
     1.3 @@ -3399,6 +3399,21 @@ sh_update_linear_entries(struct vcpu *v)
     1.4  #else
     1.5  #error this should not happen
     1.6  #endif
     1.7 +
     1.8 +    if ( shadow_mode_external(d) )
     1.9 +    {
    1.10 +        /*
    1.11 +         * Having modified the linear pagetable mapping, flush local host TLBs.
    1.12 +         * This was not needed when vmenter/vmexit always had the side effect
    1.13 +         * of flushing host TLBs but, with ASIDs, it is possible to finish 
    1.14 +         * this CR3 update, vmenter the guest, vmexit due to a page fault, 
    1.15 +         * without an intervening host TLB flush. Then the page fault code 
    1.16 +         * could use the linear pagetable to read a top-level shadow page 
    1.17 +         * table entry. But, without this change, it would fetch the wrong 
    1.18 +         * value due to a stale TLB.
    1.19 +         */
    1.20 +        flush_tlb_local();
    1.21 +    }
    1.22  }
    1.23  
    1.24