ia64/xen-unstable

changeset 6444:9312a3e8a6f8

merge?
author kaf24@firebug.cl.cam.ac.uk
date Fri Aug 26 09:05:43 2005 +0000 (2005-08-26)
parents 48202c7c709a 8799d14bef77
children 83c73802f02a
files .hgignore Config.mk Makefile buildconfigs/Rules.mk buildconfigs/mk.linux-2.6-xen buildconfigs/mk.linux-2.6-xen0 buildconfigs/mk.linux-2.6-xenU docs/src/user.tex extras/mini-os/include/hypervisor.h extras/mini-os/include/mm.h extras/mini-os/include/time.h extras/mini-os/kernel.c extras/mini-os/mm.c extras/mini-os/time.c linux-2.4-xen-sparse/Makefile linux-2.4-xen-sparse/arch/xen/Makefile linux-2.4-xen-sparse/arch/xen/boot/Makefile linux-2.4-xen-sparse/arch/xen/config.in linux-2.4-xen-sparse/arch/xen/defconfig-xen0 linux-2.4-xen-sparse/arch/xen/defconfig-xenU linux-2.4-xen-sparse/arch/xen/drivers/balloon/Makefile linux-2.4-xen-sparse/arch/xen/drivers/blkif/Makefile linux-2.4-xen-sparse/arch/xen/drivers/blkif/backend/Makefile linux-2.4-xen-sparse/arch/xen/drivers/blkif/frontend/Makefile linux-2.4-xen-sparse/arch/xen/drivers/blkif/frontend/common.h linux-2.4-xen-sparse/arch/xen/drivers/blkif/frontend/vbd.c linux-2.4-xen-sparse/arch/xen/drivers/console/Makefile linux-2.4-xen-sparse/arch/xen/drivers/dom0/Makefile linux-2.4-xen-sparse/arch/xen/drivers/evtchn/Makefile linux-2.4-xen-sparse/arch/xen/drivers/netif/Makefile linux-2.4-xen-sparse/arch/xen/drivers/netif/backend/Makefile linux-2.4-xen-sparse/arch/xen/drivers/netif/frontend/Makefile linux-2.4-xen-sparse/arch/xen/kernel/Makefile linux-2.4-xen-sparse/arch/xen/kernel/entry.S linux-2.4-xen-sparse/arch/xen/kernel/head.S linux-2.4-xen-sparse/arch/xen/kernel/i386_ksyms.c linux-2.4-xen-sparse/arch/xen/kernel/irq.c linux-2.4-xen-sparse/arch/xen/kernel/ldt.c linux-2.4-xen-sparse/arch/xen/kernel/pci-pc.c linux-2.4-xen-sparse/arch/xen/kernel/process.c linux-2.4-xen-sparse/arch/xen/kernel/setup.c linux-2.4-xen-sparse/arch/xen/kernel/signal.c linux-2.4-xen-sparse/arch/xen/kernel/time.c linux-2.4-xen-sparse/arch/xen/kernel/traps.c linux-2.4-xen-sparse/arch/xen/lib/Makefile linux-2.4-xen-sparse/arch/xen/lib/delay.c linux-2.4-xen-sparse/arch/xen/mm/Makefile linux-2.4-xen-sparse/arch/xen/mm/fault.c linux-2.4-xen-sparse/arch/xen/mm/init.c linux-2.4-xen-sparse/arch/xen/mm/ioremap.c linux-2.4-xen-sparse/arch/xen/vmlinux.lds linux-2.4-xen-sparse/drivers/block/ll_rw_blk.c linux-2.4-xen-sparse/drivers/char/Makefile linux-2.4-xen-sparse/drivers/char/mem.c linux-2.4-xen-sparse/drivers/char/tty_io.c linux-2.4-xen-sparse/drivers/scsi/aic7xxx/Makefile linux-2.4-xen-sparse/include/asm-xen/bugs.h linux-2.4-xen-sparse/include/asm-xen/desc.h linux-2.4-xen-sparse/include/asm-xen/fixmap.h linux-2.4-xen-sparse/include/asm-xen/highmem.h linux-2.4-xen-sparse/include/asm-xen/hw_irq.h linux-2.4-xen-sparse/include/asm-xen/io.h linux-2.4-xen-sparse/include/asm-xen/irq.h linux-2.4-xen-sparse/include/asm-xen/keyboard.h linux-2.4-xen-sparse/include/asm-xen/mmu_context.h linux-2.4-xen-sparse/include/asm-xen/module.h linux-2.4-xen-sparse/include/asm-xen/page.h linux-2.4-xen-sparse/include/asm-xen/pci.h linux-2.4-xen-sparse/include/asm-xen/pgalloc.h linux-2.4-xen-sparse/include/asm-xen/pgtable-2level.h linux-2.4-xen-sparse/include/asm-xen/pgtable.h linux-2.4-xen-sparse/include/asm-xen/processor.h linux-2.4-xen-sparse/include/asm-xen/queues.h linux-2.4-xen-sparse/include/asm-xen/segment.h linux-2.4-xen-sparse/include/asm-xen/smp.h linux-2.4-xen-sparse/include/asm-xen/system.h linux-2.4-xen-sparse/include/asm-xen/vga.h linux-2.4-xen-sparse/include/asm-xen/xor.h linux-2.4-xen-sparse/include/linux/blk.h linux-2.4-xen-sparse/include/linux/highmem.h linux-2.4-xen-sparse/include/linux/irq.h linux-2.4-xen-sparse/include/linux/mm.h linux-2.4-xen-sparse/include/linux/sched.h linux-2.4-xen-sparse/include/linux/skbuff.h linux-2.4-xen-sparse/include/linux/timer.h linux-2.4-xen-sparse/kernel/time.c linux-2.4-xen-sparse/kernel/timer.c linux-2.4-xen-sparse/mkbuildtree linux-2.4-xen-sparse/mm/highmem.c linux-2.4-xen-sparse/mm/memory.c linux-2.4-xen-sparse/mm/mprotect.c linux-2.4-xen-sparse/mm/mremap.c linux-2.4-xen-sparse/mm/page_alloc.c linux-2.4-xen-sparse/net/core/skbuff.c linux-2.6-xen-sparse/arch/xen/Kconfig linux-2.6-xen-sparse/arch/xen/Kconfig.drivers linux-2.6-xen-sparse/arch/xen/Makefile linux-2.6-xen-sparse/arch/xen/boot/Makefile linux-2.6-xen-sparse/arch/xen/configs/xen0_defconfig_x86_32 linux-2.6-xen-sparse/arch/xen/configs/xen0_defconfig_x86_64 linux-2.6-xen-sparse/arch/xen/configs/xenU_defconfig_x86_32 linux-2.6-xen-sparse/arch/xen/configs/xenU_defconfig_x86_64 linux-2.6-xen-sparse/arch/xen/configs/xen_defconfig_x86_32 linux-2.6-xen-sparse/arch/xen/configs/xen_defconfig_x86_64 linux-2.6-xen-sparse/arch/xen/i386/Kconfig linux-2.6-xen-sparse/arch/xen/i386/Makefile linux-2.6-xen-sparse/arch/xen/i386/kernel/Makefile linux-2.6-xen-sparse/arch/xen/i386/kernel/acpi/Makefile linux-2.6-xen-sparse/arch/xen/i386/kernel/acpi/boot.c linux-2.6-xen-sparse/arch/xen/i386/kernel/apic.c linux-2.6-xen-sparse/arch/xen/i386/kernel/cpu/Makefile linux-2.6-xen-sparse/arch/xen/i386/kernel/cpu/common.c linux-2.6-xen-sparse/arch/xen/i386/kernel/cpu/mtrr/Makefile linux-2.6-xen-sparse/arch/xen/i386/kernel/cpu/mtrr/main.c linux-2.6-xen-sparse/arch/xen/i386/kernel/entry.S linux-2.6-xen-sparse/arch/xen/i386/kernel/head.S linux-2.6-xen-sparse/arch/xen/i386/kernel/i386_ksyms.c linux-2.6-xen-sparse/arch/xen/i386/kernel/init_task.c linux-2.6-xen-sparse/arch/xen/i386/kernel/io_apic.c linux-2.6-xen-sparse/arch/xen/i386/kernel/ioport.c linux-2.6-xen-sparse/arch/xen/i386/kernel/irq.c linux-2.6-xen-sparse/arch/xen/i386/kernel/ldt.c linux-2.6-xen-sparse/arch/xen/i386/kernel/microcode.c linux-2.6-xen-sparse/arch/xen/i386/kernel/mpparse.c linux-2.6-xen-sparse/arch/xen/i386/kernel/pci-dma.c linux-2.6-xen-sparse/arch/xen/i386/kernel/process.c linux-2.6-xen-sparse/arch/xen/i386/kernel/setup.c linux-2.6-xen-sparse/arch/xen/i386/kernel/signal.c linux-2.6-xen-sparse/arch/xen/i386/kernel/smp.c linux-2.6-xen-sparse/arch/xen/i386/kernel/smpboot.c linux-2.6-xen-sparse/arch/xen/i386/kernel/swiotlb.c linux-2.6-xen-sparse/arch/xen/i386/kernel/time.c linux-2.6-xen-sparse/arch/xen/i386/kernel/traps.c linux-2.6-xen-sparse/arch/xen/i386/kernel/vsyscall.S linux-2.6-xen-sparse/arch/xen/i386/mach-default/Makefile linux-2.6-xen-sparse/arch/xen/i386/mm/Makefile linux-2.6-xen-sparse/arch/xen/i386/mm/fault.c linux-2.6-xen-sparse/arch/xen/i386/mm/highmem.c linux-2.6-xen-sparse/arch/xen/i386/mm/hypervisor.c linux-2.6-xen-sparse/arch/xen/i386/mm/init.c linux-2.6-xen-sparse/arch/xen/i386/mm/ioremap.c linux-2.6-xen-sparse/arch/xen/i386/mm/pgtable.c linux-2.6-xen-sparse/arch/xen/i386/pci/Makefile linux-2.6-xen-sparse/arch/xen/i386/pci/irq.c linux-2.6-xen-sparse/arch/xen/kernel/Makefile linux-2.6-xen-sparse/arch/xen/kernel/ctrl_if.c linux-2.6-xen-sparse/arch/xen/kernel/devmem.c linux-2.6-xen-sparse/arch/xen/kernel/evtchn.c linux-2.6-xen-sparse/arch/xen/kernel/fixup.c linux-2.6-xen-sparse/arch/xen/kernel/gnttab.c linux-2.6-xen-sparse/arch/xen/kernel/reboot.c linux-2.6-xen-sparse/arch/xen/kernel/skbuff.c linux-2.6-xen-sparse/arch/xen/kernel/smp.c linux-2.6-xen-sparse/arch/xen/kernel/xen_proc.c linux-2.6-xen-sparse/arch/xen/x86_64/Kconfig linux-2.6-xen-sparse/arch/xen/x86_64/Makefile linux-2.6-xen-sparse/arch/xen/x86_64/ia32/Makefile linux-2.6-xen-sparse/arch/xen/x86_64/ia32/ia32entry.S linux-2.6-xen-sparse/arch/xen/x86_64/ia32/syscall32.c linux-2.6-xen-sparse/arch/xen/x86_64/ia32/vsyscall-int80.S linux-2.6-xen-sparse/arch/xen/x86_64/kernel/Makefile linux-2.6-xen-sparse/arch/xen/x86_64/kernel/acpi/Makefile linux-2.6-xen-sparse/arch/xen/x86_64/kernel/apic.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/e820.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/early_printk.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/entry.S linux-2.6-xen-sparse/arch/xen/x86_64/kernel/genapic.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/genapic_xen.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/head.S linux-2.6-xen-sparse/arch/xen/x86_64/kernel/head64.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/io_apic.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/ioport.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/irq.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/ldt.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/mpparse.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/pci-nommu.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/process.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/setup.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/setup64.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/signal.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/smp.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/smpboot.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/traps.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/vsyscall.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/x8664_ksyms.c linux-2.6-xen-sparse/arch/xen/x86_64/kernel/xen_entry.S linux-2.6-xen-sparse/arch/xen/x86_64/mm/Makefile linux-2.6-xen-sparse/arch/xen/x86_64/mm/fault.c linux-2.6-xen-sparse/arch/xen/x86_64/mm/init.c linux-2.6-xen-sparse/arch/xen/x86_64/mm/pageattr.c linux-2.6-xen-sparse/arch/xen/x86_64/pci/Makefile linux-2.6-xen-sparse/arch/xen/x86_64/pci/Makefile-BUS linux-2.6-xen-sparse/drivers/Makefile linux-2.6-xen-sparse/drivers/acpi/tables.c linux-2.6-xen-sparse/drivers/char/mem.c linux-2.6-xen-sparse/drivers/char/tty_io.c linux-2.6-xen-sparse/drivers/xen/Makefile linux-2.6-xen-sparse/drivers/xen/balloon/Makefile linux-2.6-xen-sparse/drivers/xen/balloon/balloon.c linux-2.6-xen-sparse/drivers/xen/blkback/Makefile linux-2.6-xen-sparse/drivers/xen/blkback/blkback.c linux-2.6-xen-sparse/drivers/xen/blkback/common.h linux-2.6-xen-sparse/drivers/xen/blkback/interface.c linux-2.6-xen-sparse/drivers/xen/blkback/vbd.c linux-2.6-xen-sparse/drivers/xen/blkback/xenbus.c linux-2.6-xen-sparse/drivers/xen/blkfront/Kconfig linux-2.6-xen-sparse/drivers/xen/blkfront/Makefile linux-2.6-xen-sparse/drivers/xen/blkfront/blkfront.c linux-2.6-xen-sparse/drivers/xen/blkfront/block.h linux-2.6-xen-sparse/drivers/xen/blkfront/vbd.c linux-2.6-xen-sparse/drivers/xen/blktap/Makefile linux-2.6-xen-sparse/drivers/xen/blktap/blktap.c linux-2.6-xen-sparse/drivers/xen/blktap/blktap.h linux-2.6-xen-sparse/drivers/xen/blktap/blktap_controlmsg.c linux-2.6-xen-sparse/drivers/xen/blktap/blktap_datapath.c linux-2.6-xen-sparse/drivers/xen/blktap/blktap_userdev.c linux-2.6-xen-sparse/drivers/xen/console/Makefile linux-2.6-xen-sparse/drivers/xen/console/console.c linux-2.6-xen-sparse/drivers/xen/evtchn/Makefile linux-2.6-xen-sparse/drivers/xen/evtchn/evtchn.c linux-2.6-xen-sparse/drivers/xen/netback/Makefile linux-2.6-xen-sparse/drivers/xen/netback/common.h linux-2.6-xen-sparse/drivers/xen/netback/interface.c linux-2.6-xen-sparse/drivers/xen/netback/loopback.c linux-2.6-xen-sparse/drivers/xen/netback/netback.c linux-2.6-xen-sparse/drivers/xen/netback/xenbus.c linux-2.6-xen-sparse/drivers/xen/netfront/Kconfig linux-2.6-xen-sparse/drivers/xen/netfront/Makefile linux-2.6-xen-sparse/drivers/xen/netfront/netfront.c linux-2.6-xen-sparse/drivers/xen/privcmd/Makefile linux-2.6-xen-sparse/drivers/xen/privcmd/privcmd.c linux-2.6-xen-sparse/drivers/xen/usbback/common.h linux-2.6-xen-sparse/drivers/xen/usbback/control.c linux-2.6-xen-sparse/drivers/xen/usbback/interface.c linux-2.6-xen-sparse/drivers/xen/usbback/usbback.c linux-2.6-xen-sparse/drivers/xen/usbfront/usbfront.c linux-2.6-xen-sparse/drivers/xen/usbfront/xhci.h linux-2.6-xen-sparse/drivers/xen/xenbus/Makefile linux-2.6-xen-sparse/drivers/xen/xenbus/xenbus_comms.c linux-2.6-xen-sparse/drivers/xen/xenbus/xenbus_comms.h linux-2.6-xen-sparse/drivers/xen/xenbus/xenbus_probe.c linux-2.6-xen-sparse/drivers/xen/xenbus/xenbus_xs.c linux-2.6-xen-sparse/include/asm-generic/pgtable.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/agp.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/desc.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/dma-mapping.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/fixmap.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/floppy.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/highmem.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/hw_irq.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/hypercall.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/io.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/kmap_types.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/mach-xen/irq_vectors.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/mach-xen/setup_arch_post.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/mach-xen/setup_arch_pre.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/mach-xen/smpboot_hooks.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/mmu.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/mmu_context.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/page.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/param.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/pci.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/pgalloc.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/pgtable-2level.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/pgtable-3level.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/pgtable.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/processor.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/ptrace.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/scatterlist.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/segment.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/setup.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/spinlock.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/swiotlb.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/synch_bitops.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/system.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/tlbflush.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/vga.h linux-2.6-xen-sparse/include/asm-xen/asm-x86_64/arch_hooks.h linux-2.6-xen-sparse/include/asm-xen/asm-x86_64/bootsetup.h linux-2.6-xen-sparse/include/asm-xen/asm-x86_64/desc.h linux-2.6-xen-sparse/include/asm-xen/asm-x86_64/dma-mapping.h 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xen/include/asm-ia64/linux/asm-generic/bug.h xen/include/asm-ia64/linux/asm-generic/div64.h xen/include/asm-ia64/linux/asm-generic/errno-base.h xen/include/asm-ia64/linux/asm-generic/errno.h xen/include/asm-ia64/linux/asm-generic/ide_iops.h xen/include/asm-ia64/linux/asm-generic/iomap.h xen/include/asm-ia64/linux/asm-generic/pci-dma-compat.h xen/include/asm-ia64/linux/asm-generic/pci.h xen/include/asm-ia64/linux/asm-generic/pgtable-nopud.h xen/include/asm-ia64/linux/asm-generic/pgtable.h xen/include/asm-ia64/linux/asm-generic/sections.h xen/include/asm-ia64/linux/asm-generic/topology.h xen/include/asm-ia64/linux/asm-generic/vmlinux.lds.h xen/include/asm-ia64/linux/asm/acpi.h xen/include/asm-ia64/linux/asm/asmmacro.h xen/include/asm-ia64/linux/asm/atomic.h xen/include/asm-ia64/linux/asm/bitops.h xen/include/asm-ia64/linux/asm/break.h xen/include/asm-ia64/linux/asm/bug.h xen/include/asm-ia64/linux/asm/byteorder.h xen/include/asm-ia64/linux/asm/cache.h xen/include/asm-ia64/linux/asm/cacheflush.h xen/include/asm-ia64/linux/asm/checksum.h xen/include/asm-ia64/linux/asm/current.h xen/include/asm-ia64/linux/asm/delay.h xen/include/asm-ia64/linux/asm/desc.h xen/include/asm-ia64/linux/asm/div64.h xen/include/asm-ia64/linux/asm/dma-mapping.h xen/include/asm-ia64/linux/asm/dma.h xen/include/asm-ia64/linux/asm/errno.h xen/include/asm-ia64/linux/asm/fpu.h xen/include/asm-ia64/linux/asm/hardirq.h xen/include/asm-ia64/linux/asm/hdreg.h xen/include/asm-ia64/linux/asm/hw_irq.h xen/include/asm-ia64/linux/asm/ia32.h xen/include/asm-ia64/linux/asm/intrinsics.h xen/include/asm-ia64/linux/asm/ioctl.h xen/include/asm-ia64/linux/asm/irq.h xen/include/asm-ia64/linux/asm/linkage.h xen/include/asm-ia64/linux/asm/machvec.h xen/include/asm-ia64/linux/asm/machvec_hpsim.h xen/include/asm-ia64/linux/asm/mca.h xen/include/asm-ia64/linux/asm/meminit.h xen/include/asm-ia64/linux/asm/mman.h xen/include/asm-ia64/linux/asm/module.h xen/include/asm-ia64/linux/asm/numa.h xen/include/asm-ia64/linux/asm/param.h xen/include/asm-ia64/linux/asm/patch.h xen/include/asm-ia64/linux/asm/pci.h xen/include/asm-ia64/linux/asm/pdb.h xen/include/asm-ia64/linux/asm/percpu.h xen/include/asm-ia64/linux/asm/pgtable.h xen/include/asm-ia64/linux/asm/ptrace_offsets.h xen/include/asm-ia64/linux/asm/rse.h xen/include/asm-ia64/linux/asm/rwsem.h xen/include/asm-ia64/linux/asm/sal.h xen/include/asm-ia64/linux/asm/scatterlist.h xen/include/asm-ia64/linux/asm/sections.h xen/include/asm-ia64/linux/asm/semaphore.h xen/include/asm-ia64/linux/asm/setup.h xen/include/asm-ia64/linux/asm/sigcontext.h xen/include/asm-ia64/linux/asm/signal.h xen/include/asm-ia64/linux/asm/smp.h xen/include/asm-ia64/linux/asm/sn/arch.h xen/include/asm-ia64/linux/asm/sn/geo.h xen/include/asm-ia64/linux/asm/sn/nodepda.h xen/include/asm-ia64/linux/asm/sn/sn_cpuid.h xen/include/asm-ia64/linux/asm/spinlock.h xen/include/asm-ia64/linux/asm/string.h xen/include/asm-ia64/linux/asm/thread_info.h xen/include/asm-ia64/linux/asm/timex.h xen/include/asm-ia64/linux/asm/tlbflush.h xen/include/asm-ia64/linux/asm/topology.h xen/include/asm-ia64/linux/asm/unaligned.h xen/include/asm-ia64/linux/asm/unistd.h xen/include/asm-ia64/linux/asm/unwind.h xen/include/asm-ia64/linux/asm/ustack.h xen/include/asm-ia64/linux/bcd.h xen/include/asm-ia64/linux/bitmap.h xen/include/asm-ia64/linux/bitops.h xen/include/asm-ia64/linux/bootmem.h xen/include/asm-ia64/linux/byteorder/generic.h xen/include/asm-ia64/linux/byteorder/little_endian.h xen/include/asm-ia64/linux/byteorder/swab.h xen/include/asm-ia64/linux/cpu.h xen/include/asm-ia64/linux/device.h xen/include/asm-ia64/linux/dma-mapping.h xen/include/asm-ia64/linux/efi.h xen/include/asm-ia64/linux/err.h xen/include/asm-ia64/linux/file.h xen/include/asm-ia64/linux/gfp.h xen/include/asm-ia64/linux/initrd.h xen/include/asm-ia64/linux/ioport.h xen/include/asm-ia64/linux/jiffies.h xen/include/asm-ia64/linux/kernel_stat.h xen/include/asm-ia64/linux/kmalloc_sizes.h xen/include/asm-ia64/linux/linkage.h xen/include/asm-ia64/linux/linuxtime.h xen/include/asm-ia64/linux/mmzone.h xen/include/asm-ia64/linux/module.h xen/include/asm-ia64/linux/numa.h xen/include/asm-ia64/linux/page-flags.h xen/include/asm-ia64/linux/percpu.h xen/include/asm-ia64/linux/preempt.h xen/include/asm-ia64/linux/proc_fs.h xen/include/asm-ia64/linux/profile.h xen/include/asm-ia64/linux/ptrace.h xen/include/asm-ia64/linux/random.h xen/include/asm-ia64/linux/rbtree.h xen/include/asm-ia64/linux/rtc.h xen/include/asm-ia64/linux/rwsem.h xen/include/asm-ia64/linux/seq_file.h xen/include/asm-ia64/linux/seqlock.h xen/include/asm-ia64/linux/serial.h xen/include/asm-ia64/linux/serial_core.h xen/include/asm-ia64/linux/signal.h xen/include/asm-ia64/linux/slab.h xen/include/asm-ia64/linux/smp_lock.h xen/include/asm-ia64/linux/stddef.h xen/include/asm-ia64/linux/swap.h xen/include/asm-ia64/linux/thread_info.h xen/include/asm-ia64/linux/threads.h xen/include/asm-ia64/linux/timex.h xen/include/asm-ia64/linux/topology.h xen/include/asm-ia64/linux/tty.h xen/include/asm-ia64/linux/wait.h xen/include/asm-ia64/mmu_context.h xen/include/asm-ia64/privop.h xen/include/asm-ia64/regionreg.h xen/include/asm-ia64/regs.h xen/include/asm-ia64/serial.h xen/include/asm-ia64/tlb.h xen/include/asm-ia64/vcpu.h xen/include/asm-ia64/vmmu.h xen/include/asm-ia64/vmx.h xen/include/asm-ia64/vmx_uaccess.h xen/include/asm-ia64/vmx_vcpu.h xen/include/asm-ia64/vmx_vpd.h xen/include/asm-ia64/xenprocessor.h xen/include/asm-ia64/xensystem.h xen/include/asm-x86/apicdef.h xen/include/asm-x86/config.h xen/include/asm-x86/e820.h xen/include/asm-x86/event.h xen/include/asm-x86/fixmap.h xen/include/asm-x86/genapic.h xen/include/asm-x86/hpet.h xen/include/asm-x86/io.h xen/include/asm-x86/mach-bigsmp/mach_apic.h xen/include/asm-x86/mach-default/mach_apic.h xen/include/asm-x86/mach-es7000/mach_apic.h xen/include/asm-x86/mach-generic/mach_apic.h xen/include/asm-x86/mach-summit/mach_apic.h xen/include/asm-x86/mach-summit/mach_mpparse.h xen/include/asm-x86/mm.h xen/include/asm-x86/page.h xen/include/asm-x86/shadow.h xen/include/asm-x86/shadow_64.h xen/include/asm-x86/shadow_public.h xen/include/asm-x86/time.h xen/include/asm-x86/types.h xen/include/asm-x86/uaccess.h xen/include/asm-x86/vmx.h xen/include/asm-x86/vmx_virpit.h xen/include/asm-x86/vmx_vmcs.h xen/include/asm-x86/x86_32/page-3level.h xen/include/asm-x86/x86_32/uaccess.h xen/include/asm-x86/x86_64/page.h xen/include/public/arch-ia64.h xen/include/public/arch-x86_32.h xen/include/public/arch-x86_64.h xen/include/public/dom0_ops.h xen/include/public/grant_table.h xen/include/public/io/blkif.h xen/include/public/io/domain_controller.h xen/include/public/io/netif.h xen/include/public/physdev.h xen/include/public/trace.h xen/include/public/xen.h xen/include/xen/ac_timer.h xen/include/xen/domain.h xen/include/xen/event.h xen/include/xen/grant_table.h xen/include/xen/mm.h xen/include/xen/perfc_defn.h xen/include/xen/sched.h xen/include/xen/serial.h xen/include/xen/symbols.h xen/include/xen/time.h xen/include/xen/trace.h xen/tools/Makefile xen/tools/symbols.c
line diff
     1.1 --- a/xen/arch/ia64/Makefile	Fri Aug 26 08:50:31 2005 +0000
     1.2 +++ b/xen/arch/ia64/Makefile	Fri Aug 26 09:05:43 2005 +0000
     1.3 @@ -1,5 +1,7 @@
     1.4  include $(BASEDIR)/Rules.mk
     1.5  
     1.6 +VPATH = linux linux-xen
     1.7 +
     1.8  # libs-y	+= arch/ia64/lib/lib.a
     1.9  
    1.10  OBJS = xensetup.o setup.o time.o irq.o ia64_ksyms.o process.o smp.o \
    1.11 @@ -12,8 +14,11 @@ OBJS = xensetup.o setup.o time.o irq.o i
    1.12  	irq_ia64.o irq_lsapic.o vhpt.o xenasm.o hyperprivop.o dom_fw.o \
    1.13  	grant_table.o sn_console.o
    1.14  
    1.15 +# TMP holder to contain *.0 moved out of CONFIG_VTI
    1.16 +OBJS += vmx_init.o
    1.17 +
    1.18  ifeq ($(CONFIG_VTI),y)
    1.19 -OBJS += vmx_init.o vmx_virt.o vmx_vcpu.o vmx_process.o vmx_vsa.o vmx_ivt.o \
    1.20 +OBJS += vmx_virt.o vmx_vcpu.o vmx_process.o vmx_vsa.o vmx_ivt.o\
    1.21  	vmx_phy_mode.o vmx_utility.o vmx_interrupt.o vmx_entry.o vmmu.o \
    1.22  	vtlb.o mmio.o vlsapic.o vmx_hypercall.o mm.o vmx_support.o pal_emul.o
    1.23  endif
    1.24 @@ -75,7 +80,7 @@ xen.lds.s: xen.lds.S
    1.25  		-o xen.lds.s xen.lds.S
    1.26  
    1.27  ia64lib.o:
    1.28 -	$(MAKE) -C lib && cp lib/ia64lib.o .
    1.29 +	$(MAKE) -C linux/lib && cp linux/lib/ia64lib.o .
    1.30  
    1.31  clean:
    1.32  	rm -f *.o *~ core  xen.lds.s $(BASEDIR)/include/asm-ia64/.offsets.h.stamp asm-offsets.s
     2.1 --- a/xen/arch/ia64/Rules.mk	Fri Aug 26 08:50:31 2005 +0000
     2.2 +++ b/xen/arch/ia64/Rules.mk	Fri Aug 26 09:05:43 2005 +0000
     2.3 @@ -6,14 +6,21 @@ ifneq ($(COMPILE_ARCH),$(TARGET_ARCH))
     2.4  CROSS_COMPILE ?= /usr/local/sp_env/v2.2.5/i686/bin/ia64-unknown-linux-
     2.5  endif
     2.6  AFLAGS  += -D__ASSEMBLY__
     2.7 -CPPFLAGS  += -I$(BASEDIR)/include -I$(BASEDIR)/include/asm-ia64
     2.8 +CPPFLAGS  += -I$(BASEDIR)/include -I$(BASEDIR)/include/asm-ia64 	\
     2.9 +             -I$(BASEDIR)/include/asm-ia64/linux 			\
    2.10 +	     -I$(BASEDIR)/include/asm-ia64/linux-xen 			\
    2.11 +             -I$(BASEDIR)/arch/ia64/linux -I$(BASEDIR)/arch/ia64/linux-xen
    2.12 +
    2.13  CFLAGS  := -nostdinc -fno-builtin -fno-common -fno-strict-aliasing
    2.14  #CFLAGS  += -O3		# -O3 over-inlines making debugging tough!
    2.15  CFLAGS  += -O2		# but no optimization causes compile errors!
    2.16  #CFLAGS  += -iwithprefix include -Wall -DMONITOR_BASE=$(MONITOR_BASE)
    2.17  CFLAGS  += -iwithprefix include -Wall
    2.18  CFLAGS  += -fomit-frame-pointer -I$(BASEDIR)/include -D__KERNEL__
    2.19 -CFLAGS  += -I$(BASEDIR)/include/asm-ia64
    2.20 +CFLAGS  += -I$(BASEDIR)/include/asm-ia64 -I$(BASEDIR)/include/asm-ia64/linux \
    2.21 +           -I$(BASEDIR)/include/asm-ia64/linux 				\
    2.22 +           -I$(BASEDIR)/include/asm-ia64/linux-xen 			\
    2.23 +           -I$(BASEDIR)/arch/ia64/linux -I$(BASEDIR)/arch/ia64/linux-xen
    2.24  CFLAGS  += -Wno-pointer-arith -Wredundant-decls
    2.25  CFLAGS  += -DIA64 -DXEN -DLINUX_2_6
    2.26  CFLAGS	+= -ffixed-r13 -mfixed-range=f12-f15,f32-f127
     3.1 --- a/xen/arch/ia64/asm-offsets.c	Fri Aug 26 08:50:31 2005 +0000
     3.2 +++ b/xen/arch/ia64/asm-offsets.c	Fri Aug 26 09:05:43 2005 +0000
     3.3 @@ -139,14 +139,14 @@ void foo(void)
     3.4  	DEFINE(IA64_PT_REGS_R2_OFFSET, offsetof (struct pt_regs, r2));
     3.5  	DEFINE(IA64_PT_REGS_R3_OFFSET, offsetof (struct pt_regs, r3));
     3.6  #ifdef CONFIG_VTI
     3.7 -	DEFINE(IA64_PT_REGS_R4_OFFSET, offsetof (struct xen_regs, r4));
     3.8 -	DEFINE(IA64_PT_REGS_R5_OFFSET, offsetof (struct xen_regs, r5));
     3.9 -	DEFINE(IA64_PT_REGS_R6_OFFSET, offsetof (struct xen_regs, r6));
    3.10 -	DEFINE(IA64_PT_REGS_R7_OFFSET, offsetof (struct xen_regs, r7));
    3.11 -	DEFINE(IA64_PT_REGS_CR_IIPA_OFFSET, offsetof (struct xen_regs, cr_iipa));
    3.12 -	DEFINE(IA64_PT_REGS_CR_ISR_OFFSET, offsetof (struct xen_regs, cr_isr));
    3.13 -	DEFINE(IA64_PT_REGS_EML_UNAT_OFFSET, offsetof (struct xen_regs, eml_unat));
    3.14 -	DEFINE(IA64_PT_REGS_RFI_PFS_OFFSET, offsetof (struct xen_regs, rfi_pfs));
    3.15 +	DEFINE(IA64_PT_REGS_R4_OFFSET, offsetof (struct pt_regs, r4));
    3.16 +	DEFINE(IA64_PT_REGS_R5_OFFSET, offsetof (struct pt_regs, r5));
    3.17 +	DEFINE(IA64_PT_REGS_R6_OFFSET, offsetof (struct pt_regs, r6));
    3.18 +	DEFINE(IA64_PT_REGS_R7_OFFSET, offsetof (struct pt_regs, r7));
    3.19 +	DEFINE(IA64_PT_REGS_CR_IIPA_OFFSET, offsetof (struct pt_regs, cr_iipa));
    3.20 +	DEFINE(IA64_PT_REGS_CR_ISR_OFFSET, offsetof (struct pt_regs, cr_isr));
    3.21 +	DEFINE(IA64_PT_REGS_EML_UNAT_OFFSET, offsetof (struct pt_regs, eml_unat));
    3.22 +	DEFINE(IA64_PT_REGS_RFI_PFS_OFFSET, offsetof (struct pt_regs, rfi_pfs));
    3.23  	DEFINE(RFI_IIP_OFFSET, offsetof(struct vcpu, arch.arch_vmx.rfi_iip));
    3.24  	DEFINE(RFI_IPSR_OFFSET, offsetof(struct vcpu, arch.arch_vmx.rfi_ipsr));
    3.25  	DEFINE(RFI_IFS_OFFSET,offsetof(struct vcpu ,arch.arch_vmx.rfi_ifs));
    3.26 @@ -296,4 +296,11 @@ void foo(void)
    3.27  	//DEFINE(IA64_TIME_SOURCE_MMIO64, TIME_SOURCE_MMIO64);
    3.28  	//DEFINE(IA64_TIME_SOURCE_MMIO32, TIME_SOURCE_MMIO32);
    3.29  	//DEFINE(IA64_TIMESPEC_TV_NSEC_OFFSET, offsetof (struct timespec, tv_nsec));
    3.30 +	DEFINE(IA64_KR_CURRENT_OFFSET, offsetof (cpu_kr_ia64_t, _kr[IA64_KR_CURRENT]));
    3.31 +	DEFINE(IA64_KR_PT_BASE_OFFSET, offsetof (cpu_kr_ia64_t, _kr[IA64_KR_PT_BASE]));
    3.32 +	DEFINE(IA64_KR_IO_BASE_OFFSET, offsetof (cpu_kr_ia64_t, _kr[IA64_KR_IO_BASE]));
    3.33 +	DEFINE(IA64_KR_PERCPU_DATA_OFFSET, offsetof (cpu_kr_ia64_t, _kr[IA64_KR_PER_CPU_DATA]));
    3.34 +	DEFINE(IA64_KR_IO_BASE_OFFSET, offsetof (cpu_kr_ia64_t, _kr[IA64_KR_IO_BASE]));
    3.35 +	DEFINE(IA64_KR_CURRENT_STACK_OFFSET, offsetof (cpu_kr_ia64_t, _kr[IA64_KR_CURRENT_STACK]));
    3.36 +
    3.37  }
     4.1 --- a/xen/arch/ia64/domain.c	Fri Aug 26 08:50:31 2005 +0000
     4.2 +++ b/xen/arch/ia64/domain.c	Fri Aug 26 09:05:43 2005 +0000
     4.3 @@ -38,25 +38,17 @@
     4.4  
     4.5  #include <asm/vcpu.h>   /* for function declarations */
     4.6  #include <public/arch-ia64.h>
     4.7 -#ifdef CONFIG_VTI
     4.8  #include <asm/vmx.h>
     4.9  #include <asm/vmx_vcpu.h>
    4.10  #include <asm/vmx_vpd.h>
    4.11  #include <asm/pal.h>
    4.12  #include <public/io/ioreq.h>
    4.13 -#endif // CONFIG_VTI
    4.14  
    4.15  #define CONFIG_DOMAIN0_CONTIGUOUS
    4.16  unsigned long dom0_start = -1L;
    4.17 -#ifdef CONFIG_VTI
    4.18  unsigned long dom0_size = 512*1024*1024; //FIXME: Should be configurable
    4.19  //FIXME: alignment should be 256MB, lest Linux use a 256MB page size
    4.20  unsigned long dom0_align = 256*1024*1024;
    4.21 -#else // CONFIG_VTI
    4.22 -unsigned long dom0_size = 512*1024*1024; //FIXME: Should be configurable
    4.23 -//FIXME: alignment should be 256MB, lest Linux use a 256MB page size
    4.24 -unsigned long dom0_align = 64*1024*1024;
    4.25 -#endif // CONFIG_VTI
    4.26  #ifdef DOMU_BUILD_STAGING
    4.27  unsigned long domU_staging_size = 32*1024*1024; //FIXME: Should be configurable
    4.28  unsigned long domU_staging_start;
    4.29 @@ -187,60 +179,6 @@ static void init_switch_stack(struct vcp
    4.30  	memset(v->arch._thread.fph,0,sizeof(struct ia64_fpreg)*96);
    4.31  }
    4.32  
    4.33 -#ifdef CONFIG_VTI
    4.34 -void arch_do_createdomain(struct vcpu *v)
    4.35 -{
    4.36 -	struct domain *d = v->domain;
    4.37 -	struct thread_info *ti = alloc_thread_info(v);
    4.38 -
    4.39 -	/* Clear thread_info to clear some important fields, like preempt_count */
    4.40 -	memset(ti, 0, sizeof(struct thread_info));
    4.41 -	init_switch_stack(v);
    4.42 -
    4.43 - 	/* Shared info area is required to be allocated at domain
    4.44 - 	 * creation, since control panel will write some I/O info
    4.45 - 	 * between front end and back end to that area. However for
    4.46 - 	 * vmx domain, our design is to let domain itself to allcoate
    4.47 - 	 * shared info area, to keep machine page contiguous. So this
    4.48 - 	 * page will be released later when domainN issues request
    4.49 - 	 * after up.
    4.50 - 	 */
    4.51 - 	d->shared_info = (void *)alloc_xenheap_page();
    4.52 -	/* Now assume all vcpu info and event indicators can be
    4.53 -	 * held in one shared page. Definitely later we need to
    4.54 -	 * consider more about it
    4.55 -	 */
    4.56 -
    4.57 -	memset(d->shared_info, 0, PAGE_SIZE);
    4.58 -	d->shared_info->vcpu_data[v->vcpu_id].arch.privregs = 
    4.59 -			alloc_xenheap_pages(get_order(sizeof(mapped_regs_t)));
    4.60 -	printf("arch_vcpu_info=%p\n", d->shared_info->vcpu_data[0].arch.privregs);
    4.61 -	memset(d->shared_info->vcpu_data[v->vcpu_id].arch.privregs, 0, PAGE_SIZE);
    4.62 -	v->vcpu_info = &d->shared_info->vcpu_data[v->vcpu_id];
    4.63 -	/* Mask all events, and specific port will be unmasked
    4.64 -	 * when customer subscribes to it.
    4.65 -	 */
    4.66 -	if(v == d->vcpu[0]) {
    4.67 -	    memset(&d->shared_info->evtchn_mask[0], 0xff,
    4.68 -		sizeof(d->shared_info->evtchn_mask));
    4.69 -	}
    4.70 -
    4.71 -	/* Allocate per-domain vTLB and vhpt */
    4.72 -	v->arch.vtlb = init_domain_tlb(v);
    4.73 -
    4.74 -	/* Physical->machine page table will be allocated when 
    4.75 -	 * final setup, since we have no the maximum pfn number in 
    4.76 -	 * this stage
    4.77 -	 */
    4.78 -
    4.79 -	/* FIXME: This is identity mapped address for xenheap. 
    4.80 -	 * Do we need it at all?
    4.81 -	 */
    4.82 -	d->xen_vastart = XEN_START_ADDR;
    4.83 -	d->xen_vaend = XEN_END_ADDR;
    4.84 -	d->arch.breakimm = 0x1000;
    4.85 -}
    4.86 -#else // CONFIG_VTI
    4.87  void arch_do_createdomain(struct vcpu *v)
    4.88  {
    4.89  	struct domain *d = v->domain;
    4.90 @@ -263,11 +201,26 @@ void arch_do_createdomain(struct vcpu *v
    4.91  	v->vcpu_info = &(d->shared_info->vcpu_data[0]);
    4.92  
    4.93  	d->max_pages = (128UL*1024*1024)/PAGE_SIZE; // 128MB default // FIXME
    4.94 -	if ((d->arch.metaphysical_rr0 = allocate_metaphysical_rr0()) == -1UL)
    4.95 +
    4.96 +#ifdef CONFIG_VTI
    4.97 +	/* Per-domain vTLB and vhpt implementation. Now vmx domain will stick
    4.98 +	 * to this solution. Maybe it can be deferred until we know created
    4.99 +	 * one as vmx domain */
   4.100 +	v->arch.vtlb = init_domain_tlb(v);
   4.101 +#endif
   4.102 +
   4.103 +	/* We may also need emulation rid for region4, though it's unlikely
   4.104 +	 * to see guest issue uncacheable access in metaphysical mode. But
   4.105 +	 * keep such info here may be more sane.
   4.106 +	 */
   4.107 +	if (((d->arch.metaphysical_rr0 = allocate_metaphysical_rr()) == -1UL)
   4.108 +	 || ((d->arch.metaphysical_rr4 = allocate_metaphysical_rr()) == -1UL))
   4.109  		BUG();
   4.110  	VCPU(v, metaphysical_mode) = 1;
   4.111  	v->arch.metaphysical_rr0 = d->arch.metaphysical_rr0;
   4.112 +	v->arch.metaphysical_rr4 = d->arch.metaphysical_rr4;
   4.113  	v->arch.metaphysical_saved_rr0 = d->arch.metaphysical_rr0;
   4.114 +	v->arch.metaphysical_saved_rr4 = d->arch.metaphysical_rr4;
   4.115  #define DOMAIN_RID_BITS_DEFAULT 18
   4.116  	if (!allocate_rid_range(d,DOMAIN_RID_BITS_DEFAULT)) // FIXME
   4.117  		BUG();
   4.118 @@ -292,7 +245,6 @@ void arch_do_createdomain(struct vcpu *v
   4.119  		return -ENOMEM;
   4.120  	}
   4.121  }
   4.122 -#endif // CONFIG_VTI
   4.123  
   4.124  void arch_getdomaininfo_ctxt(struct vcpu *v, struct vcpu_guest_context *c)
   4.125  {
   4.126 @@ -312,16 +264,28 @@ void arch_getdomaininfo_ctxt(struct vcpu
   4.127  	c->shared = v->domain->shared_info->arch;
   4.128  }
   4.129  
   4.130 -#ifndef CONFIG_VTI
   4.131  int arch_set_info_guest(struct vcpu *v, struct vcpu_guest_context *c)
   4.132  {
   4.133  	struct pt_regs *regs = (struct pt_regs *) ((unsigned long) v + IA64_STK_OFFSET) - 1;
   4.134 +	struct domain *d = v->domain;
   4.135 +	int i, rc, ret;
   4.136 +	unsigned long progress = 0;
   4.137  
   4.138  	printf("arch_set_info_guest\n");
   4.139 +	if ( test_bit(_VCPUF_initialised, &v->vcpu_flags) )
   4.140 +            return 0;
   4.141 +
   4.142 +	if (c->flags & VGCF_VMX_GUEST) {
   4.143 +	    if (!vmx_enabled) {
   4.144 +		printk("No VMX hardware feature for vmx domain.\n");
   4.145 +		return -EINVAL;
   4.146 +	    }
   4.147 +
   4.148 +	    vmx_setup_platform(v, c);
   4.149 +	}
   4.150 +
   4.151  	*regs = c->regs;
   4.152 -	regs->cr_ipsr = IA64_PSR_IT|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_IC|IA64_PSR_I|IA64_PSR_DFH|IA64_PSR_BN|IA64_PSR_SP|IA64_PSR_DI;
   4.153 -	regs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT;
   4.154 -	regs->ar_rsc |= (2 << 2); /* force PL2/3 */
   4.155 +	new_thread(v, regs->cr_iip, 0, 0);
   4.156  
   4.157   	v->vcpu_info->arch.evtchn_vector = c->vcpu.evtchn_vector;
   4.158  	if ( c->vcpu.privregs && copy_from_user(v->vcpu_info->arch.privregs,
   4.159 @@ -330,100 +294,13 @@ int arch_set_info_guest(struct vcpu *v, 
   4.160  	    return -EFAULT;
   4.161  	}
   4.162  
   4.163 -	init_all_rr(v);
   4.164 +	v->arch.domain_itm_last = -1L;
   4.165 +	d->shared_info->arch = c->shared;
   4.166  
   4.167 -	// this should be in userspace
   4.168 -	regs->r28 = dom_fw_setup(v->domain,"nomca nosmp xencons=tty0 console=tty0 root=/dev/hda1",256L);  //FIXME
   4.169 -	v->arch.domain_itm_last = -1L;
   4.170 - 	VCPU(v, banknum) = 1;
   4.171 - 	VCPU(v, metaphysical_mode) = 1;
   4.172 -
   4.173 -	v->domain->shared_info->arch = c->shared;
   4.174 +	/* Don't redo final setup */
   4.175 +	set_bit(_VCPUF_initialised, &v->vcpu_flags);
   4.176  	return 0;
   4.177  }
   4.178 -#else // CONFIG_VTI
   4.179 -int arch_set_info_guest(
   4.180 -    struct vcpu *v, struct vcpu_guest_context *c)
   4.181 -{
   4.182 -    struct domain *d = v->domain;
   4.183 -    int i, rc, ret;
   4.184 -    unsigned long progress = 0;
   4.185 -    shared_iopage_t *sp;
   4.186 -
   4.187 -    if ( test_bit(_VCPUF_initialised, &v->vcpu_flags) )
   4.188 -        return 0;
   4.189 -
   4.190 -    /* Lazy FP not implemented yet */
   4.191 -    clear_bit(_VCPUF_fpu_initialised, &v->vcpu_flags);
   4.192 -    if ( c->flags & VGCF_FPU_VALID )
   4.193 -        set_bit(_VCPUF_fpu_initialised, &v->vcpu_flags);
   4.194 -
   4.195 -    /* Sync d/i cache conservatively, after domain N is loaded */
   4.196 -    ret = ia64_pal_cache_flush(3, 0, &progress, NULL);
   4.197 -    if (ret != PAL_STATUS_SUCCESS)
   4.198 -            panic("PAL CACHE FLUSH failed for dom[%d].\n",
   4.199 -		v->domain->domain_id);
   4.200 -    DPRINTK("Sync i/d cache for dom%d image SUCC\n",
   4.201 -		v->domain->domain_id);
   4.202 -
   4.203 -    /* Physical mode emulation initialization, including
   4.204 -     * emulation ID allcation and related memory request
   4.205 -     */
   4.206 -    physical_mode_init(v);
   4.207 -
   4.208 -    /* FIXME: only support PMT table continuously by far */
   4.209 -    d->arch.pmt = __va(c->pt_base);
   4.210 -    d->arch.max_pfn = c->pt_max_pfn;
   4.211 -    d->arch.vmx_platform.shared_page_va = __va(c->share_io_pg);
   4.212 -    sp = get_sp(d);
   4.213 -    memset((char *)sp,0,PAGE_SIZE);
   4.214 -    /* FIXME: temp due to old CP */
   4.215 -    sp->sp_global.eport = 2;
   4.216 -#ifdef V_IOSAPIC_READY
   4.217 -    sp->vcpu_number = 1;
   4.218 -#endif
   4.219 -    /* TEMP */
   4.220 -    d->arch.vmx_platform.pib_base = 0xfee00000UL;
   4.221 -    
   4.222 -
   4.223 -    if (c->flags & VGCF_VMX_GUEST) {
   4.224 -	if (!vmx_enabled)
   4.225 -	    panic("No VMX hardware feature for vmx domain.\n");
   4.226 -
   4.227 -	vmx_final_setup_domain(d);
   4.228 -
   4.229 -	/* One more step to enable interrupt assist */
   4.230 -	set_bit(ARCH_VMX_INTR_ASSIST, &v->arch.arch_vmx.flags);
   4.231 -    }
   4.232 -
   4.233 -    vlsapic_reset(v);
   4.234 -    vtm_init(v);
   4.235 -
   4.236 -    /* Only open one port for I/O and interrupt emulation */
   4.237 -    if (v == d->vcpu[0]) {
   4.238 -	memset(&d->shared_info->evtchn_mask[0], 0xff,
   4.239 -		sizeof(d->shared_info->evtchn_mask));
   4.240 -	clear_bit(iopacket_port(d), &d->shared_info->evtchn_mask[0]);
   4.241 -    }
   4.242 -    /* Setup domain context. Actually IA-64 is a bit different with
   4.243 -     * x86, with almost all system resources better managed by HV
   4.244 -     * directly. CP only needs to provide start IP of guest, which
   4.245 -     * ideally is the load address of guest Firmware.
   4.246 -     */
   4.247 -    new_thread(v, c->guest_iip, 0, 0);
   4.248 -
   4.249 -
   4.250 -    d->xen_vastart = XEN_START_ADDR;
   4.251 -    d->xen_vaend = XEN_END_ADDR;
   4.252 -    d->arch.breakimm = 0x1000 + d->domain_id;
   4.253 -    v->arch._thread.on_ustack = 0;
   4.254 -
   4.255 -    /* Don't redo final setup */
   4.256 -    set_bit(_VCPUF_initialised, &v->vcpu_flags);
   4.257 -
   4.258 -    return 0;
   4.259 -}
   4.260 -#endif // CONFIG_VTI
   4.261  
   4.262  void arch_do_boot_vcpu(struct vcpu *v)
   4.263  {
   4.264 @@ -443,17 +320,17 @@ void domain_relinquish_resources(struct 
   4.265  	printf("domain_relinquish_resources: not implemented\n");
   4.266  }
   4.267  
   4.268 -#ifdef CONFIG_VTI
   4.269 +// heavily leveraged from linux/arch/ia64/kernel/process.c:copy_thread()
   4.270 +// and linux/arch/ia64/kernel/process.c:kernel_thread()
   4.271  void new_thread(struct vcpu *v,
   4.272                  unsigned long start_pc,
   4.273                  unsigned long start_stack,
   4.274                  unsigned long start_info)
   4.275  {
   4.276  	struct domain *d = v->domain;
   4.277 -	struct xen_regs *regs;
   4.278 +	struct pt_regs *regs;
   4.279  	struct ia64_boot_param *bp;
   4.280  	extern char saved_command_line[];
   4.281 -	//char *dom0_cmdline = "BOOT_IMAGE=scsi0:\EFI\redhat\xenlinux nomca root=/dev/sdb1 ro";
   4.282  
   4.283  
   4.284  #ifdef CONFIG_DOMAIN0_CONTIGUOUS
   4.285 @@ -471,61 +348,31 @@ void new_thread(struct vcpu *v,
   4.286  		regs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT; // domain runs at PL2
   4.287  	}
   4.288  	regs->cr_iip = start_pc;
   4.289 -	regs->cr_ifs = 0; /* why? - matthewc */
   4.290 +	regs->cr_ifs = 1UL << 63; /* or clear? */
   4.291  	regs->ar_fpsr = FPSR_DEFAULT;
   4.292 -	if (VMX_DOMAIN(v)) {
   4.293 -		vmx_init_all_rr(v);
   4.294 -	} else
   4.295 -		init_all_rr(v);
   4.296  
   4.297  	if (VMX_DOMAIN(v)) {
   4.298 -		if (d == dom0) {
   4.299 +#ifdef CONFIG_VTI
   4.300 +		vmx_init_all_rr(v);
   4.301 +		if (d == dom0)
   4.302  		    VMX_VPD(v,vgr[12]) = dom_fw_setup(d,saved_command_line,256L);
   4.303 -		    printk("new_thread, done with dom_fw_setup\n");
   4.304 -		}
   4.305  		/* Virtual processor context setup */
   4.306  		VMX_VPD(v, vpsr) = IA64_PSR_BN;
   4.307  		VPD_CR(v, dcr) = 0;
   4.308 +#endif
   4.309  	} else {
   4.310 -		regs->r28 = dom_fw_setup(d,saved_command_line,256L);
   4.311 +		init_all_rr(v);
   4.312 +		if (d == dom0) 
   4.313 +		    regs->r28 = dom_fw_setup(d,saved_command_line,256L);
   4.314 +		else {
   4.315 +		    regs->ar_rsc |= (2 << 2); /* force PL2/3 */
   4.316 +		    regs->r28 = dom_fw_setup(d,"nomca nosmp xencons=tty0 console=tty0 root=/dev/hda1",256L);  //FIXME
   4.317 +		}
   4.318  		VCPU(v, banknum) = 1;
   4.319  		VCPU(v, metaphysical_mode) = 1;
   4.320  		d->shared_info->arch.flags = (d == dom0) ? (SIF_INITDOMAIN|SIF_PRIVILEGED|SIF_BLK_BE_DOMAIN|SIF_NET_BE_DOMAIN|SIF_USB_BE_DOMAIN) : 0;
   4.321  	}
   4.322  }
   4.323 -#else // CONFIG_VTI
   4.324 -
   4.325 -// heavily leveraged from linux/arch/ia64/kernel/process.c:copy_thread()
   4.326 -// and linux/arch/ia64/kernel/process.c:kernel_thread()
   4.327 -void new_thread(struct vcpu *v,
   4.328 -	            unsigned long start_pc,
   4.329 -	            unsigned long start_stack,
   4.330 -	            unsigned long start_info)
   4.331 -{
   4.332 -	struct domain *d = v->domain;
   4.333 -	struct pt_regs *regs;
   4.334 -	struct ia64_boot_param *bp;
   4.335 -	extern char saved_command_line[];
   4.336 -
   4.337 -#ifdef CONFIG_DOMAIN0_CONTIGUOUS
   4.338 -	if (d == dom0) start_pc += dom0_start;
   4.339 -#endif
   4.340 -
   4.341 -	regs = (struct pt_regs *) ((unsigned long) v + IA64_STK_OFFSET) - 1;
   4.342 -	regs->cr_ipsr = ia64_getreg(_IA64_REG_PSR)
   4.343 -		| IA64_PSR_BITS_TO_SET | IA64_PSR_BN
   4.344 -		& ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS);
   4.345 -	regs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT; // domain runs at PL2
   4.346 -	regs->cr_iip = start_pc;
   4.347 -	regs->cr_ifs = 1UL << 63;
   4.348 -	regs->ar_fpsr = FPSR_DEFAULT;
   4.349 -	init_all_rr(v);
   4.350 -	regs->r28 = dom_fw_setup(d,saved_command_line,256L);  //FIXME
   4.351 -	VCPU(v, banknum) = 1;
   4.352 -	VCPU(v, metaphysical_mode) = 1;
   4.353 -	d->shared_info->arch.flags = (d == dom0) ? (SIF_INITDOMAIN|SIF_PRIVILEGED|SIF_BLK_BE_DOMAIN|SIF_NET_BE_DOMAIN|SIF_USB_BE_DOMAIN) : 0;
   4.354 -}
   4.355 -#endif // CONFIG_VTI
   4.356  
   4.357  static struct page * map_new_domain0_page(unsigned long mpaddr)
   4.358  {
   4.359 @@ -903,44 +750,6 @@ domU_staging_write_32(unsigned long at, 
   4.360  }
   4.361  #endif
   4.362  
   4.363 -#ifdef CONFIG_VTI
   4.364 -/* Up to whether domain is vmx one, different context may be setup
   4.365 - * here.
   4.366 - */
   4.367 -void
   4.368 -post_arch_do_create_domain(struct vcpu *v, int vmx_domain)
   4.369 -{
   4.370 -    struct domain *d = v->domain;
   4.371 -
   4.372 -    if (!vmx_domain) {
   4.373 -	d->shared_info = (void*)alloc_xenheap_page();
   4.374 -	if (!d->shared_info)
   4.375 -		panic("Allocate share info for non-vmx domain failed.\n");
   4.376 -	d->shared_info_va = 0xfffd000000000000;
   4.377 -
   4.378 -	printk("Build shared info for non-vmx domain\n");
   4.379 -	build_shared_info(d);
   4.380 -	/* Setup start info area */
   4.381 -    }
   4.382 -}
   4.383 -
   4.384 -/* For VMX domain, this is invoked when kernel model in domain
   4.385 - * request actively
   4.386 - */
   4.387 -void build_shared_info(struct domain *d)
   4.388 -{
   4.389 -    int i;
   4.390 -
   4.391 -    /* Set up shared-info area. */
   4.392 -    update_dom_time(d);
   4.393 -
   4.394 -    /* Mask all upcalls... */
   4.395 -    for ( i = 0; i < MAX_VIRT_CPUS; i++ )
   4.396 -        d->shared_info->vcpu_data[i].evtchn_upcall_mask = 1;
   4.397 -
   4.398 -    /* ... */
   4.399 -}
   4.400 -
   4.401  /*
   4.402   * Domain 0 has direct access to all devices absolutely. However
   4.403   * the major point of this stub here, is to allow alloc_dom_mem
   4.404 @@ -959,182 +768,12 @@ int construct_dom0(struct domain *d,
   4.405  	               unsigned long initrd_start, unsigned long initrd_len,
   4.406  	               char *cmdline)
   4.407  {
   4.408 -    char *dst;
   4.409 -    int i, rc;
   4.410 -    unsigned long pfn, mfn;
   4.411 -    unsigned long nr_pt_pages;
   4.412 -    unsigned long count;
   4.413 -    unsigned long alloc_start, alloc_end;
   4.414 -    struct pfn_info *page = NULL;
   4.415 -    start_info_t *si;
   4.416 -    struct vcpu *v = d->vcpu[0];
   4.417 -    struct domain_setup_info dsi;
   4.418 -    unsigned long p_start;
   4.419 -    unsigned long pkern_start;
   4.420 -    unsigned long pkern_entry;
   4.421 -    unsigned long pkern_end;
   4.422 -    unsigned long ret;
   4.423 -    unsigned long progress = 0;
   4.424 -
   4.425 -//printf("construct_dom0: starting\n");
   4.426 -    /* Sanity! */
   4.427 -#ifndef CLONE_DOMAIN0
   4.428 -    if ( d != dom0 ) 
   4.429 -        BUG();
   4.430 -    if ( test_bit(_DOMF_constructed, &d->domain_flags) ) 
   4.431 -        BUG();
   4.432 -#endif
   4.433 -
   4.434 -    printk("##Dom0: 0x%lx, domain: 0x%lx\n", (u64)dom0, (u64)d);
   4.435 -    memset(&dsi, 0, sizeof(struct domain_setup_info));
   4.436 -
   4.437 -    printk("*** LOADING DOMAIN 0 ***\n");
   4.438 -
   4.439 -    alloc_start = dom0_start;
   4.440 -    alloc_end = dom0_start + dom0_size;
   4.441 -    d->tot_pages = d->max_pages = (alloc_end - alloc_start)/PAGE_SIZE;
   4.442 -    image_start = __va(ia64_boot_param->initrd_start);
   4.443 -    image_len = ia64_boot_param->initrd_size;
   4.444 -
   4.445 -    dsi.image_addr = (unsigned long)image_start;
   4.446 -    dsi.image_len  = image_len;
   4.447 -    rc = parseelfimage(&dsi);
   4.448 -    if ( rc != 0 )
   4.449 -        return rc;
   4.450 -
   4.451 -    /* Temp workaround */
   4.452 -    if (running_on_sim)
   4.453 -	dsi.xen_section_string = (char *)1;
   4.454 -
   4.455 -    if ((!vmx_enabled) && !dsi.xen_section_string) {
   4.456 -	printk("Lack of hardware support for unmodified vmx dom0\n");
   4.457 -	panic("");
   4.458 -    }
   4.459 -
   4.460 -    if (vmx_enabled && !dsi.xen_section_string) {
   4.461 -	printk("Dom0 is vmx domain!\n");
   4.462 -	vmx_dom0 = 1;
   4.463 -    }
   4.464 -
   4.465 -    p_start = dsi.v_start;
   4.466 -    pkern_start = dsi.v_kernstart;
   4.467 -    pkern_end = dsi.v_kernend;
   4.468 -    pkern_entry = dsi.v_kernentry;
   4.469 -
   4.470 -    printk("p_start=%lx, pkern_start=%lx, pkern_end=%lx, pkern_entry=%lx\n",
   4.471 -	p_start,pkern_start,pkern_end,pkern_entry);
   4.472 -
   4.473 -    if ( (p_start & (PAGE_SIZE-1)) != 0 )
   4.474 -    {
   4.475 -        printk("Initial guest OS must load to a page boundary.\n");
   4.476 -        return -EINVAL;
   4.477 -    }
   4.478 -
   4.479 -    printk("METAPHYSICAL MEMORY ARRANGEMENT:\n"
   4.480 -           " Kernel image:  %lx->%lx\n"
   4.481 -           " Entry address: %lx\n"
   4.482 -           " Init. ramdisk:   (NOT IMPLEMENTED YET)\n",
   4.483 -           pkern_start, pkern_end, pkern_entry);
   4.484 -
   4.485 -    if ( (pkern_end - pkern_start) > (d->max_pages * PAGE_SIZE) )
   4.486 -    {
   4.487 -        printk("Initial guest OS requires too much space\n"
   4.488 -               "(%luMB is greater than %luMB limit)\n",
   4.489 -               (pkern_end-pkern_start)>>20, (d->max_pages<<PAGE_SHIFT)>>20);
   4.490 -        return -ENOMEM;
   4.491 -    }
   4.492 -
   4.493 -    // Other sanity check about Dom0 image
   4.494 -
   4.495 -    /* Construct a frame-allocation list for the initial domain, since these
   4.496 -     * pages are allocated by boot allocator and pfns are not set properly
   4.497 -     */
   4.498 -    for ( mfn = (alloc_start>>PAGE_SHIFT); 
   4.499 -          mfn < (alloc_end>>PAGE_SHIFT); 
   4.500 -          mfn++ )
   4.501 -    {
   4.502 -        page = &frame_table[mfn];
   4.503 -        page_set_owner(page, d);
   4.504 -        page->u.inuse.type_info = 0;
   4.505 -        page->count_info        = PGC_allocated | 1;
   4.506 -        list_add_tail(&page->list, &d->page_list);
   4.507 -
   4.508 -	/* Construct 1:1 mapping */
   4.509 -	machine_to_phys_mapping[mfn] = mfn;
   4.510 -    }
   4.511 -
   4.512 -    post_arch_do_create_domain(v, vmx_dom0);
   4.513 -
   4.514 -    /* Load Dom0 image to its own memory */
   4.515 -    loaddomainelfimage(d,image_start);
   4.516 -
   4.517 -    /* Copy the initial ramdisk. */
   4.518 -
   4.519 -    /* Sync d/i cache conservatively */
   4.520 -    ret = ia64_pal_cache_flush(4, 0, &progress, NULL);
   4.521 -    if (ret != PAL_STATUS_SUCCESS)
   4.522 -            panic("PAL CACHE FLUSH failed for dom0.\n");
   4.523 -    printk("Sync i/d cache for dom0 image SUCC\n");
   4.524 -
   4.525 -    /* Physical mode emulation initialization, including
   4.526 -     * emulation ID allcation and related memory request
   4.527 -     */
   4.528 -    physical_mode_init(v);
   4.529 -    /* Dom0's pfn is equal to mfn, so there's no need to allocate pmt
   4.530 -     * for dom0
   4.531 -     */
   4.532 -    d->arch.pmt = NULL;
   4.533 -
   4.534 -    /* Give up the VGA console if DOM0 is configured to grab it. */
   4.535 -    if (cmdline != NULL)
   4.536 -    	console_endboot(strstr(cmdline, "tty0") != NULL);
   4.537 -
   4.538 -    /* VMX specific construction for Dom0, if hardware supports VMX
   4.539 -     * and Dom0 is unmodified image
   4.540 -     */
   4.541 -    printk("Dom0: 0x%lx, domain: 0x%lx\n", (u64)dom0, (u64)d);
   4.542 -    if (vmx_dom0)
   4.543 -	vmx_final_setup_domain(dom0);
   4.544 -    
   4.545 -    /* vpd is ready now */
   4.546 -    vlsapic_reset(v);
   4.547 -    vtm_init(v);
   4.548 -
   4.549 -    set_bit(_DOMF_constructed, &d->domain_flags);
   4.550 -    new_thread(v, pkern_entry, 0, 0);
   4.551 -
   4.552 -    physdev_init_dom0(d);
   4.553 -    // FIXME: Hack for keyboard input
   4.554 -#ifdef CLONE_DOMAIN0
   4.555 -if (d == dom0)
   4.556 -#endif
   4.557 -    serial_input_init();
   4.558 -    if (d == dom0) {
   4.559 -    	VCPU(v, delivery_mask[0]) = -1L;
   4.560 -    	VCPU(v, delivery_mask[1]) = -1L;
   4.561 -    	VCPU(v, delivery_mask[2]) = -1L;
   4.562 -    	VCPU(v, delivery_mask[3]) = -1L;
   4.563 -    }
   4.564 -    else __set_bit(0x30,VCPU(v, delivery_mask));
   4.565 -
   4.566 -    return 0;
   4.567 -}
   4.568 -
   4.569 -
   4.570 -#else //CONFIG_VTI
   4.571 -
   4.572 -int construct_dom0(struct domain *d, 
   4.573 -	               unsigned long image_start, unsigned long image_len, 
   4.574 -	               unsigned long initrd_start, unsigned long initrd_len,
   4.575 -	               char *cmdline)
   4.576 -{
   4.577  	char *dst;
   4.578  	int i, rc;
   4.579  	unsigned long pfn, mfn;
   4.580  	unsigned long nr_pt_pages;
   4.581  	unsigned long count;
   4.582 -	//l2_pgentry_t *l2tab, *l2start;
   4.583 -	//l1_pgentry_t *l1tab = NULL, *l1start = NULL;
   4.584 +	unsigned long alloc_start, alloc_end;
   4.585  	struct pfn_info *page = NULL;
   4.586  	start_info_t *si;
   4.587  	struct vcpu *v = d->vcpu[0];
   4.588 @@ -1144,6 +783,7 @@ int construct_dom0(struct domain *d,
   4.589  	unsigned long pkern_start;
   4.590  	unsigned long pkern_entry;
   4.591  	unsigned long pkern_end;
   4.592 +	unsigned long ret, progress = 0;
   4.593  
   4.594  //printf("construct_dom0: starting\n");
   4.595  	/* Sanity! */
   4.596 @@ -1158,7 +798,9 @@ int construct_dom0(struct domain *d,
   4.597  
   4.598  	printk("*** LOADING DOMAIN 0 ***\n");
   4.599  
   4.600 -	d->max_pages = dom0_size/PAGE_SIZE;
   4.601 +	alloc_start = dom0_start;
   4.602 +	alloc_end = dom0_start + dom0_size;
   4.603 +	d->tot_pages = d->max_pages = dom0_size/PAGE_SIZE;
   4.604  	image_start = __va(ia64_boot_param->initrd_start);
   4.605  	image_len = ia64_boot_param->initrd_size;
   4.606  //printk("image_start=%lx, image_len=%lx\n",image_start,image_len);
   4.607 @@ -1171,6 +813,23 @@ int construct_dom0(struct domain *d,
   4.608  	if ( rc != 0 )
   4.609  	    return rc;
   4.610  
   4.611 +#ifdef CONFIG_VTI
   4.612 +	/* Temp workaround */
   4.613 +	if (running_on_sim)
   4.614 +	    dsi.xen_section_string = (char *)1;
   4.615 +
   4.616 +	/* Check whether dom0 is vti domain */
   4.617 +	if ((!vmx_enabled) && !dsi.xen_section_string) {
   4.618 +	    printk("Lack of hardware support for unmodified vmx dom0\n");
   4.619 +	    panic("");
   4.620 +	}
   4.621 +
   4.622 +	if (vmx_enabled && !dsi.xen_section_string) {
   4.623 +	    printk("Dom0 is vmx domain!\n");
   4.624 +	    vmx_dom0 = 1;
   4.625 +	}
   4.626 +#endif
   4.627 +
   4.628  	p_start = dsi.v_start;
   4.629  	pkern_start = dsi.v_kernstart;
   4.630  	pkern_end = dsi.v_kernend;
   4.631 @@ -1214,14 +873,43 @@ int construct_dom0(struct domain *d,
   4.632  	for ( i = 0; i < MAX_VIRT_CPUS; i++ )
   4.633  	    d->shared_info->vcpu_data[i].evtchn_upcall_mask = 1;
   4.634  
   4.635 +#ifdef CONFIG_VTI
   4.636 +	/* Construct a frame-allocation list for the initial domain, since these
   4.637 +	 * pages are allocated by boot allocator and pfns are not set properly
   4.638 +	 */
   4.639 +	for ( mfn = (alloc_start>>PAGE_SHIFT); 
   4.640 +	      mfn < (alloc_end>>PAGE_SHIFT); 
   4.641 +	      mfn++ )
   4.642 +	{
   4.643 +            page = &frame_table[mfn];
   4.644 +            page_set_owner(page, d);
   4.645 +            page->u.inuse.type_info = 0;
   4.646 +            page->count_info        = PGC_allocated | 1;
   4.647 +            list_add_tail(&page->list, &d->page_list);
   4.648 +
   4.649 +	    /* Construct 1:1 mapping */
   4.650 +	    machine_to_phys_mapping[mfn] = mfn;
   4.651 +	}
   4.652 +
   4.653 +	/* Dom0's pfn is equal to mfn, so there's no need to allocate pmt
   4.654 +	 * for dom0
   4.655 +	 */
   4.656 +	d->arch.pmt = NULL;
   4.657 +#endif
   4.658 +
   4.659  	/* Copy the OS image. */
   4.660 -	//(void)loadelfimage(image_start);
   4.661  	loaddomainelfimage(d,image_start);
   4.662  
   4.663  	/* Copy the initial ramdisk. */
   4.664  	//if ( initrd_len != 0 )
   4.665  	//    memcpy((void *)vinitrd_start, initrd_start, initrd_len);
   4.666  
   4.667 +	/* Sync d/i cache conservatively */
   4.668 +	ret = ia64_pal_cache_flush(4, 0, &progress, NULL);
   4.669 +	if (ret != PAL_STATUS_SUCCESS)
   4.670 +	    panic("PAL CACHE FLUSH failed for dom0.\n");
   4.671 +	printk("Sync i/d cache for dom0 image SUCC\n");
   4.672 +
   4.673  #if 0
   4.674  	/* Set up start info area. */
   4.675  	//si = (start_info_t *)vstartinfo_start;
   4.676 @@ -1257,14 +945,21 @@ int construct_dom0(struct domain *d,
   4.677  #endif
   4.678  	
   4.679  	/* Give up the VGA console if DOM0 is configured to grab it. */
   4.680 -#ifdef IA64
   4.681  	if (cmdline != NULL)
   4.682 -#endif
   4.683 -	console_endboot(strstr(cmdline, "tty0") != NULL);
   4.684 +	    console_endboot(strstr(cmdline, "tty0") != NULL);
   4.685 +
   4.686 +	/* VMX specific construction for Dom0, if hardware supports VMX
   4.687 +	 * and Dom0 is unmodified image
   4.688 +	 */
   4.689 +	printk("Dom0: 0x%lx, domain: 0x%lx\n", (u64)dom0, (u64)d);
   4.690 +	if (vmx_dom0)
   4.691 +	    vmx_final_setup_domain(dom0);
   4.692  
   4.693  	set_bit(_DOMF_constructed, &d->domain_flags);
   4.694  
   4.695  	new_thread(v, pkern_entry, 0, 0);
   4.696 +	physdev_init_dom0(d);
   4.697 +
   4.698  	// FIXME: Hack for keyboard input
   4.699  #ifdef CLONE_DOMAIN0
   4.700  if (d == dom0)
   4.701 @@ -1280,7 +975,6 @@ if (d == dom0)
   4.702  
   4.703  	return 0;
   4.704  }
   4.705 -#endif // CONFIG_VTI
   4.706  
   4.707  // FIXME: When dom0 can construct domains, this goes away (or is rewritten)
   4.708  int construct_domU(struct domain *d,
     5.1 --- a/xen/arch/ia64/hyperprivop.S	Fri Aug 26 08:50:31 2005 +0000
     5.2 +++ b/xen/arch/ia64/hyperprivop.S	Fri Aug 26 09:05:43 2005 +0000
     5.3 @@ -73,7 +73,8 @@ GLOBAL_ENTRY(fast_hyperprivop)
     5.4  	ld4 r20=[r20] ;;
     5.5  	cmp.eq p7,p0=r0,r20
     5.6  (p7)	br.cond.sptk.many 1f
     5.7 -	mov r20=IA64_KR(CURRENT);;
     5.8 +	movl r20=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
     5.9 +	ld8 r20=[r20];;
    5.10  	adds r21=IA64_VCPU_IRR0_OFFSET,r20;
    5.11  	adds r22=IA64_VCPU_IRR0_OFFSET+8,r20;;
    5.12  	ld8 r23=[r21],16; ld8 r24=[r22],16;;
    5.13 @@ -257,7 +258,8 @@ ENTRY(hyper_ssm_i)
    5.14  	st8 [r21]=r20 ;;
    5.15  	// leave cr.ifs alone for later rfi
    5.16  	// set iip to go to domain IVA break instruction vector
    5.17 -	mov r22=IA64_KR(CURRENT);;
    5.18 +	movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
    5.19 +	ld8 r22=[r22];;
    5.20  	adds r22=IA64_VCPU_IVA_OFFSET,r22;;
    5.21  	ld8 r23=[r22];;
    5.22  	movl r24=0x3000;;
    5.23 @@ -306,7 +308,7 @@ GLOBAL_ENTRY(fast_tick_reflect)
    5.24  	mov r28=IA64_TIMER_VECTOR;;
    5.25  	cmp.ne p6,p0=r28,r30
    5.26  (p6)	br.cond.spnt.few rp;;
    5.27 -	movl r20=(PERCPU_ADDR)+IA64_CPUINFO_ITM_NEXT_OFFSET;;
    5.28 +	movl r20=THIS_CPU(cpu_info)+IA64_CPUINFO_ITM_NEXT_OFFSET;;
    5.29  	ld8 r26=[r20];;
    5.30  	mov r27=ar.itc;;
    5.31  	adds r27=200,r27;;	// safety margin
    5.32 @@ -340,7 +342,8 @@ GLOBAL_ENTRY(fast_tick_reflect)
    5.33  (p6)	br.cond.spnt.few fast_tick_reflect_done;;
    5.34  	extr.u r27=r20,0,6	// r27 has low 6 bits of itv.vector
    5.35  	extr.u r26=r20,6,2;;	// r26 has irr index of itv.vector
    5.36 -	mov r19=IA64_KR(CURRENT);;
    5.37 +	movl r19=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
    5.38 +	ld8 r19=[r19];;
    5.39  	adds r22=IA64_VCPU_DOMAIN_ITM_LAST_OFFSET,r19
    5.40  	adds r23=IA64_VCPU_DOMAIN_ITM_OFFSET,r19;;
    5.41  	ld8 r24=[r22];;
    5.42 @@ -581,7 +584,8 @@ ENTRY(fast_reflect)
    5.43  	st8 [r18]=r0;;
    5.44  	// FIXME: need to save iipa and isr to be arch-compliant
    5.45  	// set iip to go to domain IVA break instruction vector
    5.46 -	mov r22=IA64_KR(CURRENT);;
    5.47 +	movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
    5.48 +	ld8 r22=[r22];;
    5.49  	adds r22=IA64_VCPU_IVA_OFFSET,r22;;
    5.50  	ld8 r23=[r22];;
    5.51  	add r20=r20,r23;;
    5.52 @@ -803,7 +807,8 @@ GLOBAL_ENTRY(rfi_check_extint)
    5.53  
    5.54  	// r18=&vpsr.i|vpsr.ic, r21==vpsr, r22=vcr.iip
    5.55  	// make sure none of these get trashed in case going to just_do_rfi
    5.56 -	mov r30=IA64_KR(CURRENT);;
    5.57 +	movl r30=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
    5.58 +	ld8 r30=[r30];;
    5.59  	adds r24=IA64_VCPU_INSVC3_OFFSET,r30;;
    5.60  	mov r25=192
    5.61  	adds r16=IA64_VCPU_IRR3_OFFSET,r30;;
    5.62 @@ -1010,7 +1015,8 @@ ENTRY(hyper_ssm_dt)
    5.63  	ld4 r21=[r20];;
    5.64  	cmp.eq p7,p0=r21,r0	// meta==0?
    5.65  (p7)	br.spnt.many	1f ;;	// already in virtual mode
    5.66 -	mov r22=IA64_KR(CURRENT);;
    5.67 +	movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
    5.68 +	ld8 r22=[r22];;
    5.69  	adds r22=IA64_VCPU_META_SAVED_RR0_OFFSET,r22;;
    5.70  	ld4 r23=[r22];;
    5.71  	mov rr[r0]=r23;;
    5.72 @@ -1045,7 +1051,8 @@ ENTRY(hyper_rsm_dt)
    5.73  	ld4 r21=[r20];;
    5.74  	cmp.ne p7,p0=r21,r0	// meta==0?
    5.75  (p7)	br.spnt.many	1f ;;	// already in metaphysical mode
    5.76 -	mov r22=IA64_KR(CURRENT);;
    5.77 +	movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
    5.78 +	ld8 r22=[r22];;
    5.79  	adds r22=IA64_VCPU_META_RR0_OFFSET,r22;;
    5.80  	ld4 r23=[r22];;
    5.81  	mov rr[r0]=r23;;
    5.82 @@ -1137,7 +1144,8 @@ ENTRY(hyper_get_ivr)
    5.83  (p7)	adds r20=XSI_PEND_OFS-XSI_PSR_IC_OFS,r18 ;;
    5.84  (p7)	st4 [r20]=r0;;
    5.85  (p7)	br.spnt.many 1f ;;
    5.86 -	mov r30=IA64_KR(CURRENT);;
    5.87 +	movl r30=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
    5.88 +	ld8 r30=[r30];;
    5.89  	adds r24=IA64_VCPU_INSVC3_OFFSET,r30;;
    5.90  	mov r25=192
    5.91  	adds r22=IA64_VCPU_IRR3_OFFSET,r30;;
    5.92 @@ -1242,7 +1250,8 @@ ENTRY(hyper_eoi)
    5.93  	adds r21=1,r21;;
    5.94  	st8 [r20]=r21;;
    5.95  #endif
    5.96 -	mov r22=IA64_KR(CURRENT);;
    5.97 +	movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
    5.98 +	ld8 r22=[r22];;
    5.99  	adds r22=IA64_VCPU_INSVC3_OFFSET,r22;;
   5.100  	ld8 r23=[r22];;
   5.101  	cmp.eq p6,p0=r23,r0;;
   5.102 @@ -1305,9 +1314,10 @@ ENTRY(hyper_set_itm)
   5.103  	adds r21=1,r21;;
   5.104  	st8 [r20]=r21;;
   5.105  #endif
   5.106 -	movl r20=(PERCPU_ADDR)+IA64_CPUINFO_ITM_NEXT_OFFSET;;
   5.107 +	movl r20=THIS_CPU(cpu_info)+IA64_CPUINFO_ITM_NEXT_OFFSET;;
   5.108  	ld8 r21=[r20];;
   5.109 -	mov r20=IA64_KR(CURRENT);;
   5.110 +	movl r20=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
   5.111 +	ld8 r20=[r20];;
   5.112  	adds r20=IA64_VCPU_DOMAIN_ITM_OFFSET,r20;;
   5.113  	st8 [r20]=r8;;
   5.114  	cmp.geu p6,p0=r21,r8;;
   5.115 @@ -1378,7 +1388,8 @@ ENTRY(hyper_set_rr)
   5.116  	st8 [r20]=r21;;
   5.117  #endif
   5.118  	extr.u r26=r9,8,24	// r26 = r9.rid
   5.119 -	mov r20=IA64_KR(CURRENT);;
   5.120 +	movl r20=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
   5.121 +	ld8 r20=[r20];;
   5.122  	adds r21=IA64_VCPU_STARTING_RID_OFFSET,r20;;
   5.123  	ld4 r22=[r21];;
   5.124  	adds r21=IA64_VCPU_ENDING_RID_OFFSET,r20;;
   5.125 @@ -1544,7 +1555,8 @@ 2:
   5.126  	mov ar.lc=r30 ;;
   5.127  	mov r29=cr.ipsr
   5.128  	mov r30=cr.iip;;
   5.129 -	mov r27=IA64_KR(CURRENT);;
   5.130 +	movl r27=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
   5.131 +	ld8 r27=[r27];;
   5.132  	adds r25=IA64_VCPU_DTLB_OFFSET,r27
   5.133  	adds r26=IA64_VCPU_ITLB_OFFSET,r27;;
   5.134  	ld8 r24=[r25]
     6.1 --- a/xen/arch/ia64/ivt.S	Fri Aug 26 08:50:31 2005 +0000
     6.2 +++ b/xen/arch/ia64/ivt.S	Fri Aug 26 09:05:43 2005 +0000
     6.3 @@ -136,7 +136,11 @@ ENTRY(vhpt_miss)
     6.4  	;;
     6.5  	rsm psr.dt				// use physical addressing for data
     6.6  	mov r31=pr				// save the predicate registers
     6.7 +#ifdef XEN
     6.8 +	movl r19=THIS_CPU(cpu_kr)+IA64_KR_PT_BASE_OFFSET;;
     6.9 +#else
    6.10  	mov r19=IA64_KR(PT_BASE)		// get page table base address
    6.11 +#endif
    6.12  	shl r21=r16,3				// shift bit 60 into sign bit
    6.13  	shr.u r17=r16,61			// get the region number into r17
    6.14  	;;
    6.15 @@ -503,7 +507,11 @@ ENTRY(nested_dtlb_miss)
    6.16  	 * Clobbered:	b0, r18, r19, r21, psr.dt (cleared)
    6.17  	 */
    6.18  	rsm psr.dt				// switch to using physical data addressing
    6.19 +#ifdef XEN
    6.20 +	movl r19=THIS_CPU(cpu_kr)+IA64_KR_PT_BASE_OFFSET;;
    6.21 +#else
    6.22  	mov r19=IA64_KR(PT_BASE)		// get the page table base address
    6.23 +#endif
    6.24  	shl r21=r16,3				// shift bit 60 into sign bit
    6.25  	;;
    6.26  	shr.u r17=r16,61			// get the region number into r17
    6.27 @@ -833,7 +841,9 @@ ENTRY(break_fault)
    6.28  	cmp4.eq p7,p0=r0,r19
    6.29  (p7)	br.sptk.many fast_hyperprivop
    6.30  	;;
    6.31 -	mov r22=IA64_KR(CURRENT);;
    6.32 +	movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
    6.33 +	ld8 r22 = [r22]
    6.34 +	;;
    6.35  	adds r22=IA64_VCPU_BREAKIMM_OFFSET,r22;;
    6.36  	ld4 r23=[r22];;
    6.37  	cmp4.eq p6,p7=r23,r17			// Xen-reserved breakimm?
    6.38 @@ -842,7 +852,8 @@ ENTRY(break_fault)
    6.39  	br.sptk.many fast_break_reflect
    6.40  	;;
    6.41  #endif
    6.42 -	mov r16=IA64_KR(CURRENT)		// r16 = current task; 12 cycle read lat.
    6.43 +	movl r16=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
    6.44 +	ld8 r16=[r16]
    6.45  	mov r17=cr.iim
    6.46  	mov r18=__IA64_BREAK_SYSCALL
    6.47  	mov r21=ar.fpsr
    6.48 @@ -934,7 +945,7 @@ ENTRY(interrupt)
    6.49  	// FIXME: this is a hack... use cpuinfo.ksoftirqd because its
    6.50  	// not used anywhere else and we need a place to stash ivr and
    6.51  	// there's no registers available unused by SAVE_MIN/REST
    6.52 -	movl r29=(PERCPU_ADDR)+IA64_CPUINFO_KSOFTIRQD_OFFSET;;
    6.53 +	movl r29=THIS_CPU(cpu_info)+IA64_CPUINFO_KSOFTIRQD_OFFSET;;
    6.54  	st8 [r29]=r30;;
    6.55  	movl r28=slow_interrupt;;
    6.56  	mov r29=rp;;
    6.57 @@ -954,7 +965,7 @@ slow_interrupt:
    6.58  	;;
    6.59  	alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
    6.60  #ifdef XEN
    6.61 -	movl out0=(PERCPU_ADDR)+IA64_CPUINFO_KSOFTIRQD_OFFSET;;
    6.62 +	movl out0=THIS_CPU(cpu_info)+IA64_CPUINFO_KSOFTIRQD_OFFSET;;
    6.63  	ld8 out0=[out0];;
    6.64  #else
    6.65  	mov out0=cr.ivr		// pass cr.ivr as first arg
     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/xen/arch/ia64/linux-xen/efi.c	Fri Aug 26 09:05:43 2005 +0000
     7.3 @@ -0,0 +1,866 @@
     7.4 +/*
     7.5 + * Extensible Firmware Interface
     7.6 + *
     7.7 + * Based on Extensible Firmware Interface Specification version 0.9 April 30, 1999
     7.8 + *
     7.9 + * Copyright (C) 1999 VA Linux Systems
    7.10 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
    7.11 + * Copyright (C) 1999-2003 Hewlett-Packard Co.
    7.12 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    7.13 + *	Stephane Eranian <eranian@hpl.hp.com>
    7.14 + *
    7.15 + * All EFI Runtime Services are not implemented yet as EFI only
    7.16 + * supports physical mode addressing on SoftSDV. This is to be fixed
    7.17 + * in a future version.  --drummond 1999-07-20
    7.18 + *
    7.19 + * Implemented EFI runtime services and virtual mode calls.  --davidm
    7.20 + *
    7.21 + * Goutham Rao: <goutham.rao@intel.com>
    7.22 + *	Skip non-WB memory and ignore empty memory ranges.
    7.23 + */
    7.24 +#include <linux/config.h>
    7.25 +#include <linux/module.h>
    7.26 +#include <linux/kernel.h>
    7.27 +#include <linux/init.h>
    7.28 +#include <linux/types.h>
    7.29 +#include <linux/time.h>
    7.30 +#include <linux/efi.h>
    7.31 +
    7.32 +#include <asm/io.h>
    7.33 +#include <asm/kregs.h>
    7.34 +#include <asm/meminit.h>
    7.35 +#include <asm/pgtable.h>
    7.36 +#include <asm/processor.h>
    7.37 +#include <asm/mca.h>
    7.38 +
    7.39 +#define EFI_DEBUG	0
    7.40 +
    7.41 +extern efi_status_t efi_call_phys (void *, ...);
    7.42 +
    7.43 +struct efi efi;
    7.44 +EXPORT_SYMBOL(efi);
    7.45 +static efi_runtime_services_t *runtime;
    7.46 +static unsigned long mem_limit = ~0UL, max_addr = ~0UL;
    7.47 +
    7.48 +#define efi_call_virt(f, args...)	(*(f))(args)
    7.49 +
    7.50 +#define STUB_GET_TIME(prefix, adjust_arg)							  \
    7.51 +static efi_status_t										  \
    7.52 +prefix##_get_time (efi_time_t *tm, efi_time_cap_t *tc)						  \
    7.53 +{												  \
    7.54 +	struct ia64_fpreg fr[6];								  \
    7.55 +	efi_time_cap_t *atc = NULL;								  \
    7.56 +	efi_status_t ret;									  \
    7.57 +												  \
    7.58 +	if (tc)											  \
    7.59 +		atc = adjust_arg(tc);								  \
    7.60 +	ia64_save_scratch_fpregs(fr);								  \
    7.61 +	ret = efi_call_##prefix((efi_get_time_t *) __va(runtime->get_time), adjust_arg(tm), atc); \
    7.62 +	ia64_load_scratch_fpregs(fr);								  \
    7.63 +	return ret;										  \
    7.64 +}
    7.65 +
    7.66 +#define STUB_SET_TIME(prefix, adjust_arg)							\
    7.67 +static efi_status_t										\
    7.68 +prefix##_set_time (efi_time_t *tm)								\
    7.69 +{												\
    7.70 +	struct ia64_fpreg fr[6];								\
    7.71 +	efi_status_t ret;									\
    7.72 +												\
    7.73 +	ia64_save_scratch_fpregs(fr);								\
    7.74 +	ret = efi_call_##prefix((efi_set_time_t *) __va(runtime->set_time), adjust_arg(tm));	\
    7.75 +	ia64_load_scratch_fpregs(fr);								\
    7.76 +	return ret;										\
    7.77 +}
    7.78 +
    7.79 +#define STUB_GET_WAKEUP_TIME(prefix, adjust_arg)						\
    7.80 +static efi_status_t										\
    7.81 +prefix##_get_wakeup_time (efi_bool_t *enabled, efi_bool_t *pending, efi_time_t *tm)		\
    7.82 +{												\
    7.83 +	struct ia64_fpreg fr[6];								\
    7.84 +	efi_status_t ret;									\
    7.85 +												\
    7.86 +	ia64_save_scratch_fpregs(fr);								\
    7.87 +	ret = efi_call_##prefix((efi_get_wakeup_time_t *) __va(runtime->get_wakeup_time),	\
    7.88 +				adjust_arg(enabled), adjust_arg(pending), adjust_arg(tm));	\
    7.89 +	ia64_load_scratch_fpregs(fr);								\
    7.90 +	return ret;										\
    7.91 +}
    7.92 +
    7.93 +#define STUB_SET_WAKEUP_TIME(prefix, adjust_arg)						\
    7.94 +static efi_status_t										\
    7.95 +prefix##_set_wakeup_time (efi_bool_t enabled, efi_time_t *tm)					\
    7.96 +{												\
    7.97 +	struct ia64_fpreg fr[6];								\
    7.98 +	efi_time_t *atm = NULL;									\
    7.99 +	efi_status_t ret;									\
   7.100 +												\
   7.101 +	if (tm)											\
   7.102 +		atm = adjust_arg(tm);								\
   7.103 +	ia64_save_scratch_fpregs(fr);								\
   7.104 +	ret = efi_call_##prefix((efi_set_wakeup_time_t *) __va(runtime->set_wakeup_time),	\
   7.105 +				enabled, atm);							\
   7.106 +	ia64_load_scratch_fpregs(fr);								\
   7.107 +	return ret;										\
   7.108 +}
   7.109 +
   7.110 +#define STUB_GET_VARIABLE(prefix, adjust_arg)						\
   7.111 +static efi_status_t									\
   7.112 +prefix##_get_variable (efi_char16_t *name, efi_guid_t *vendor, u32 *attr,		\
   7.113 +		       unsigned long *data_size, void *data)				\
   7.114 +{											\
   7.115 +	struct ia64_fpreg fr[6];							\
   7.116 +	u32 *aattr = NULL;									\
   7.117 +	efi_status_t ret;								\
   7.118 +											\
   7.119 +	if (attr)									\
   7.120 +		aattr = adjust_arg(attr);						\
   7.121 +	ia64_save_scratch_fpregs(fr);							\
   7.122 +	ret = efi_call_##prefix((efi_get_variable_t *) __va(runtime->get_variable),	\
   7.123 +				adjust_arg(name), adjust_arg(vendor), aattr,		\
   7.124 +				adjust_arg(data_size), adjust_arg(data));		\
   7.125 +	ia64_load_scratch_fpregs(fr);							\
   7.126 +	return ret;									\
   7.127 +}
   7.128 +
   7.129 +#define STUB_GET_NEXT_VARIABLE(prefix, adjust_arg)						\
   7.130 +static efi_status_t										\
   7.131 +prefix##_get_next_variable (unsigned long *name_size, efi_char16_t *name, efi_guid_t *vendor)	\
   7.132 +{												\
   7.133 +	struct ia64_fpreg fr[6];								\
   7.134 +	efi_status_t ret;									\
   7.135 +												\
   7.136 +	ia64_save_scratch_fpregs(fr);								\
   7.137 +	ret = efi_call_##prefix((efi_get_next_variable_t *) __va(runtime->get_next_variable),	\
   7.138 +				adjust_arg(name_size), adjust_arg(name), adjust_arg(vendor));	\
   7.139 +	ia64_load_scratch_fpregs(fr);								\
   7.140 +	return ret;										\
   7.141 +}
   7.142 +
   7.143 +#define STUB_SET_VARIABLE(prefix, adjust_arg)						\
   7.144 +static efi_status_t									\
   7.145 +prefix##_set_variable (efi_char16_t *name, efi_guid_t *vendor, unsigned long attr,	\
   7.146 +		       unsigned long data_size, void *data)				\
   7.147 +{											\
   7.148 +	struct ia64_fpreg fr[6];							\
   7.149 +	efi_status_t ret;								\
   7.150 +											\
   7.151 +	ia64_save_scratch_fpregs(fr);							\
   7.152 +	ret = efi_call_##prefix((efi_set_variable_t *) __va(runtime->set_variable),	\
   7.153 +				adjust_arg(name), adjust_arg(vendor), attr, data_size,	\
   7.154 +				adjust_arg(data));					\
   7.155 +	ia64_load_scratch_fpregs(fr);							\
   7.156 +	return ret;									\
   7.157 +}
   7.158 +
   7.159 +#define STUB_GET_NEXT_HIGH_MONO_COUNT(prefix, adjust_arg)					\
   7.160 +static efi_status_t										\
   7.161 +prefix##_get_next_high_mono_count (u32 *count)							\
   7.162 +{												\
   7.163 +	struct ia64_fpreg fr[6];								\
   7.164 +	efi_status_t ret;									\
   7.165 +												\
   7.166 +	ia64_save_scratch_fpregs(fr);								\
   7.167 +	ret = efi_call_##prefix((efi_get_next_high_mono_count_t *)				\
   7.168 +				__va(runtime->get_next_high_mono_count), adjust_arg(count));	\
   7.169 +	ia64_load_scratch_fpregs(fr);								\
   7.170 +	return ret;										\
   7.171 +}
   7.172 +
   7.173 +#define STUB_RESET_SYSTEM(prefix, adjust_arg)					\
   7.174 +static void									\
   7.175 +prefix##_reset_system (int reset_type, efi_status_t status,			\
   7.176 +		       unsigned long data_size, efi_char16_t *data)		\
   7.177 +{										\
   7.178 +	struct ia64_fpreg fr[6];						\
   7.179 +	efi_char16_t *adata = NULL;						\
   7.180 +										\
   7.181 +	if (data)								\
   7.182 +		adata = adjust_arg(data);					\
   7.183 +										\
   7.184 +	ia64_save_scratch_fpregs(fr);						\
   7.185 +	efi_call_##prefix((efi_reset_system_t *) __va(runtime->reset_system),	\
   7.186 +			  reset_type, status, data_size, adata);		\
   7.187 +	/* should not return, but just in case... */				\
   7.188 +	ia64_load_scratch_fpregs(fr);						\
   7.189 +}
   7.190 +
   7.191 +#define phys_ptr(arg)	((__typeof__(arg)) ia64_tpa(arg))
   7.192 +
   7.193 +STUB_GET_TIME(phys, phys_ptr)
   7.194 +STUB_SET_TIME(phys, phys_ptr)
   7.195 +STUB_GET_WAKEUP_TIME(phys, phys_ptr)
   7.196 +STUB_SET_WAKEUP_TIME(phys, phys_ptr)
   7.197 +STUB_GET_VARIABLE(phys, phys_ptr)
   7.198 +STUB_GET_NEXT_VARIABLE(phys, phys_ptr)
   7.199 +STUB_SET_VARIABLE(phys, phys_ptr)
   7.200 +STUB_GET_NEXT_HIGH_MONO_COUNT(phys, phys_ptr)
   7.201 +STUB_RESET_SYSTEM(phys, phys_ptr)
   7.202 +
   7.203 +#define id(arg)	arg
   7.204 +
   7.205 +STUB_GET_TIME(virt, id)
   7.206 +STUB_SET_TIME(virt, id)
   7.207 +STUB_GET_WAKEUP_TIME(virt, id)
   7.208 +STUB_SET_WAKEUP_TIME(virt, id)
   7.209 +STUB_GET_VARIABLE(virt, id)
   7.210 +STUB_GET_NEXT_VARIABLE(virt, id)
   7.211 +STUB_SET_VARIABLE(virt, id)
   7.212 +STUB_GET_NEXT_HIGH_MONO_COUNT(virt, id)
   7.213 +STUB_RESET_SYSTEM(virt, id)
   7.214 +
   7.215 +void
   7.216 +efi_gettimeofday (struct timespec *ts)
   7.217 +{
   7.218 +	efi_time_t tm;
   7.219 +
   7.220 +	memset(ts, 0, sizeof(ts));
   7.221 +	if ((*efi.get_time)(&tm, NULL) != EFI_SUCCESS)
   7.222 +		return;
   7.223 +
   7.224 +	ts->tv_sec = mktime(tm.year, tm.month, tm.day, tm.hour, tm.minute, tm.second);
   7.225 +	ts->tv_nsec = tm.nanosecond;
   7.226 +}
   7.227 +
   7.228 +static int
   7.229 +is_available_memory (efi_memory_desc_t *md)
   7.230 +{
   7.231 +	if (!(md->attribute & EFI_MEMORY_WB))
   7.232 +		return 0;
   7.233 +
   7.234 +	switch (md->type) {
   7.235 +	      case EFI_LOADER_CODE:
   7.236 +	      case EFI_LOADER_DATA:
   7.237 +	      case EFI_BOOT_SERVICES_CODE:
   7.238 +	      case EFI_BOOT_SERVICES_DATA:
   7.239 +	      case EFI_CONVENTIONAL_MEMORY:
   7.240 +		return 1;
   7.241 +	}
   7.242 +	return 0;
   7.243 +}
   7.244 +
   7.245 +/*
   7.246 + * Trim descriptor MD so its starts at address START_ADDR.  If the descriptor covers
   7.247 + * memory that is normally available to the kernel, issue a warning that some memory
   7.248 + * is being ignored.
   7.249 + */
   7.250 +static void
   7.251 +trim_bottom (efi_memory_desc_t *md, u64 start_addr)
   7.252 +{
   7.253 +	u64 num_skipped_pages;
   7.254 +
   7.255 +	if (md->phys_addr >= start_addr || !md->num_pages)
   7.256 +		return;
   7.257 +
   7.258 +	num_skipped_pages = (start_addr - md->phys_addr) >> EFI_PAGE_SHIFT;
   7.259 +	if (num_skipped_pages > md->num_pages)
   7.260 +		num_skipped_pages = md->num_pages;
   7.261 +
   7.262 +	if (is_available_memory(md))
   7.263 +		printk(KERN_NOTICE "efi.%s: ignoring %luKB of memory at 0x%lx due to granule hole "
   7.264 +		       "at 0x%lx\n", __FUNCTION__,
   7.265 +		       (num_skipped_pages << EFI_PAGE_SHIFT) >> 10,
   7.266 +		       md->phys_addr, start_addr - IA64_GRANULE_SIZE);
   7.267 +	/*
   7.268 +	 * NOTE: Don't set md->phys_addr to START_ADDR because that could cause the memory
   7.269 +	 * descriptor list to become unsorted.  In such a case, md->num_pages will be
   7.270 +	 * zero, so the Right Thing will happen.
   7.271 +	 */
   7.272 +	md->phys_addr += num_skipped_pages << EFI_PAGE_SHIFT;
   7.273 +	md->num_pages -= num_skipped_pages;
   7.274 +}
   7.275 +
   7.276 +static void
   7.277 +trim_top (efi_memory_desc_t *md, u64 end_addr)
   7.278 +{
   7.279 +	u64 num_dropped_pages, md_end_addr;
   7.280 +
   7.281 +	md_end_addr = md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT);
   7.282 +
   7.283 +	if (md_end_addr <= end_addr || !md->num_pages)
   7.284 +		return;
   7.285 +
   7.286 +	num_dropped_pages = (md_end_addr - end_addr) >> EFI_PAGE_SHIFT;
   7.287 +	if (num_dropped_pages > md->num_pages)
   7.288 +		num_dropped_pages = md->num_pages;
   7.289 +
   7.290 +	if (is_available_memory(md))
   7.291 +		printk(KERN_NOTICE "efi.%s: ignoring %luKB of memory at 0x%lx due to granule hole "
   7.292 +		       "at 0x%lx\n", __FUNCTION__,
   7.293 +		       (num_dropped_pages << EFI_PAGE_SHIFT) >> 10,
   7.294 +		       md->phys_addr, end_addr);
   7.295 +	md->num_pages -= num_dropped_pages;
   7.296 +}
   7.297 +
   7.298 +/*
   7.299 + * Walks the EFI memory map and calls CALLBACK once for each EFI memory descriptor that
   7.300 + * has memory that is available for OS use.
   7.301 + */
   7.302 +void
   7.303 +efi_memmap_walk (efi_freemem_callback_t callback, void *arg)
   7.304 +{
   7.305 +	int prev_valid = 0;
   7.306 +	struct range {
   7.307 +		u64 start;
   7.308 +		u64 end;
   7.309 +	} prev, curr;
   7.310 +	void *efi_map_start, *efi_map_end, *p, *q;
   7.311 +	efi_memory_desc_t *md, *check_md;
   7.312 +	u64 efi_desc_size, start, end, granule_addr, last_granule_addr, first_non_wb_addr = 0;
   7.313 +	unsigned long total_mem = 0;
   7.314 +
   7.315 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   7.316 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   7.317 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   7.318 +
   7.319 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   7.320 +		md = p;
   7.321 +
   7.322 +		/* skip over non-WB memory descriptors; that's all we're interested in... */
   7.323 +		if (!(md->attribute & EFI_MEMORY_WB))
   7.324 +			continue;
   7.325 +
   7.326 +#ifdef XEN
   7.327 +// this works around a problem in the ski bootloader
   7.328 +{
   7.329 +		extern long running_on_sim;
   7.330 +		if (running_on_sim && md->type != EFI_CONVENTIONAL_MEMORY)
   7.331 +			continue;
   7.332 +}
   7.333 +// this is a temporary hack to avoid CONFIG_VIRTUAL_MEM_MAP
   7.334 +		if (md->phys_addr >= 0x100000000) continue;
   7.335 +#endif
   7.336 +		/*
   7.337 +		 * granule_addr is the base of md's first granule.
   7.338 +		 * [granule_addr - first_non_wb_addr) is guaranteed to
   7.339 +		 * be contiguous WB memory.
   7.340 +		 */
   7.341 +		granule_addr = GRANULEROUNDDOWN(md->phys_addr);
   7.342 +		first_non_wb_addr = max(first_non_wb_addr, granule_addr);
   7.343 +
   7.344 +		if (first_non_wb_addr < md->phys_addr) {
   7.345 +			trim_bottom(md, granule_addr + IA64_GRANULE_SIZE);
   7.346 +			granule_addr = GRANULEROUNDDOWN(md->phys_addr);
   7.347 +			first_non_wb_addr = max(first_non_wb_addr, granule_addr);
   7.348 +		}
   7.349 +
   7.350 +		for (q = p; q < efi_map_end; q += efi_desc_size) {
   7.351 +			check_md = q;
   7.352 +
   7.353 +			if ((check_md->attribute & EFI_MEMORY_WB) &&
   7.354 +			    (check_md->phys_addr == first_non_wb_addr))
   7.355 +				first_non_wb_addr += check_md->num_pages << EFI_PAGE_SHIFT;
   7.356 +			else
   7.357 +				break;		/* non-WB or hole */
   7.358 +		}
   7.359 +
   7.360 +		last_granule_addr = GRANULEROUNDDOWN(first_non_wb_addr);
   7.361 +		if (last_granule_addr < md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT))
   7.362 +			trim_top(md, last_granule_addr);
   7.363 +
   7.364 +		if (is_available_memory(md)) {
   7.365 +			if (md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT) >= max_addr) {
   7.366 +				if (md->phys_addr >= max_addr)
   7.367 +					continue;
   7.368 +				md->num_pages = (max_addr - md->phys_addr) >> EFI_PAGE_SHIFT;
   7.369 +				first_non_wb_addr = max_addr;
   7.370 +			}
   7.371 +
   7.372 +			if (total_mem >= mem_limit)
   7.373 +				continue;
   7.374 +
   7.375 +			if (total_mem + (md->num_pages << EFI_PAGE_SHIFT) > mem_limit) {
   7.376 +				unsigned long limit_addr = md->phys_addr;
   7.377 +
   7.378 +				limit_addr += mem_limit - total_mem;
   7.379 +				limit_addr = GRANULEROUNDDOWN(limit_addr);
   7.380 +
   7.381 +				if (md->phys_addr > limit_addr)
   7.382 +					continue;
   7.383 +
   7.384 +				md->num_pages = (limit_addr - md->phys_addr) >>
   7.385 +				                EFI_PAGE_SHIFT;
   7.386 +				first_non_wb_addr = max_addr = md->phys_addr +
   7.387 +				              (md->num_pages << EFI_PAGE_SHIFT);
   7.388 +			}
   7.389 +			total_mem += (md->num_pages << EFI_PAGE_SHIFT);
   7.390 +
   7.391 +			if (md->num_pages == 0)
   7.392 +				continue;
   7.393 +
   7.394 +			curr.start = PAGE_OFFSET + md->phys_addr;
   7.395 +			curr.end   = curr.start + (md->num_pages << EFI_PAGE_SHIFT);
   7.396 +
   7.397 +			if (!prev_valid) {
   7.398 +				prev = curr;
   7.399 +				prev_valid = 1;
   7.400 +			} else {
   7.401 +				if (curr.start < prev.start)
   7.402 +					printk(KERN_ERR "Oops: EFI memory table not ordered!\n");
   7.403 +
   7.404 +				if (prev.end == curr.start) {
   7.405 +					/* merge two consecutive memory ranges */
   7.406 +					prev.end = curr.end;
   7.407 +				} else {
   7.408 +					start = PAGE_ALIGN(prev.start);
   7.409 +					end = prev.end & PAGE_MASK;
   7.410 +					if ((end > start) && (*callback)(start, end, arg) < 0)
   7.411 +						return;
   7.412 +					prev = curr;
   7.413 +				}
   7.414 +			}
   7.415 +		}
   7.416 +	}
   7.417 +	if (prev_valid) {
   7.418 +		start = PAGE_ALIGN(prev.start);
   7.419 +		end = prev.end & PAGE_MASK;
   7.420 +		if (end > start)
   7.421 +			(*callback)(start, end, arg);
   7.422 +	}
   7.423 +}
   7.424 +
   7.425 +/*
   7.426 + * Look for the PAL_CODE region reported by EFI and maps it using an
   7.427 + * ITR to enable safe PAL calls in virtual mode.  See IA-64 Processor
   7.428 + * Abstraction Layer chapter 11 in ADAG
   7.429 + */
   7.430 +
   7.431 +void *
   7.432 +efi_get_pal_addr (void)
   7.433 +{
   7.434 +	void *efi_map_start, *efi_map_end, *p;
   7.435 +	efi_memory_desc_t *md;
   7.436 +	u64 efi_desc_size;
   7.437 +	int pal_code_count = 0;
   7.438 +	u64 vaddr, mask;
   7.439 +
   7.440 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   7.441 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   7.442 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   7.443 +
   7.444 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   7.445 +		md = p;
   7.446 +		if (md->type != EFI_PAL_CODE)
   7.447 +			continue;
   7.448 +
   7.449 +		if (++pal_code_count > 1) {
   7.450 +			printk(KERN_ERR "Too many EFI Pal Code memory ranges, dropped @ %lx\n",
   7.451 +			       md->phys_addr);
   7.452 +			continue;
   7.453 +		}
   7.454 +		/*
   7.455 +		 * The only ITLB entry in region 7 that is used is the one installed by
   7.456 +		 * __start().  That entry covers a 64MB range.
   7.457 +		 */
   7.458 +		mask  = ~((1 << KERNEL_TR_PAGE_SHIFT) - 1);
   7.459 +		vaddr = PAGE_OFFSET + md->phys_addr;
   7.460 +
   7.461 +		/*
   7.462 +		 * We must check that the PAL mapping won't overlap with the kernel
   7.463 +		 * mapping.
   7.464 +		 *
   7.465 +		 * PAL code is guaranteed to be aligned on a power of 2 between 4k and
   7.466 +		 * 256KB and that only one ITR is needed to map it. This implies that the
   7.467 +		 * PAL code is always aligned on its size, i.e., the closest matching page
   7.468 +		 * size supported by the TLB. Therefore PAL code is guaranteed never to
   7.469 +		 * cross a 64MB unless it is bigger than 64MB (very unlikely!).  So for
   7.470 +		 * now the following test is enough to determine whether or not we need a
   7.471 +		 * dedicated ITR for the PAL code.
   7.472 +		 */
   7.473 +		if ((vaddr & mask) == (KERNEL_START & mask)) {
   7.474 +			printk(KERN_INFO "%s: no need to install ITR for PAL code\n",
   7.475 +			       __FUNCTION__);
   7.476 +			continue;
   7.477 +		}
   7.478 +
   7.479 +		if (md->num_pages << EFI_PAGE_SHIFT > IA64_GRANULE_SIZE)
   7.480 +			panic("Woah!  PAL code size bigger than a granule!");
   7.481 +
   7.482 +#if EFI_DEBUG
   7.483 +		mask  = ~((1 << IA64_GRANULE_SHIFT) - 1);
   7.484 +
   7.485 +		printk(KERN_INFO "CPU %d: mapping PAL code [0x%lx-0x%lx) into [0x%lx-0x%lx)\n",
   7.486 +			smp_processor_id(), md->phys_addr,
   7.487 +			md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT),
   7.488 +			vaddr & mask, (vaddr & mask) + IA64_GRANULE_SIZE);
   7.489 +#endif
   7.490 +		return __va(md->phys_addr);
   7.491 +	}
   7.492 +	printk(KERN_WARNING "%s: no PAL-code memory-descriptor found",
   7.493 +	       __FUNCTION__);
   7.494 +	return NULL;
   7.495 +}
   7.496 +
   7.497 +void
   7.498 +efi_map_pal_code (void)
   7.499 +{
   7.500 +	void *pal_vaddr = efi_get_pal_addr ();
   7.501 +	u64 psr;
   7.502 +
   7.503 +	if (!pal_vaddr)
   7.504 +		return;
   7.505 +
   7.506 +	/*
   7.507 +	 * Cannot write to CRx with PSR.ic=1
   7.508 +	 */
   7.509 +	psr = ia64_clear_ic();
   7.510 +	ia64_itr(0x1, IA64_TR_PALCODE, GRANULEROUNDDOWN((unsigned long) pal_vaddr),
   7.511 +		 pte_val(pfn_pte(__pa(pal_vaddr) >> PAGE_SHIFT, PAGE_KERNEL)),
   7.512 +		 IA64_GRANULE_SHIFT);
   7.513 +	ia64_set_psr(psr);		/* restore psr */
   7.514 +	ia64_srlz_i();
   7.515 +}
   7.516 +
   7.517 +void __init
   7.518 +efi_init (void)
   7.519 +{
   7.520 +	void *efi_map_start, *efi_map_end;
   7.521 +	efi_config_table_t *config_tables;
   7.522 +	efi_char16_t *c16;
   7.523 +	u64 efi_desc_size;
   7.524 +	char *cp, *end, vendor[100] = "unknown";
   7.525 +	extern char saved_command_line[];
   7.526 +	int i;
   7.527 +
   7.528 +	/* it's too early to be able to use the standard kernel command line support... */
   7.529 +	for (cp = saved_command_line; *cp; ) {
   7.530 +		if (memcmp(cp, "mem=", 4) == 0) {
   7.531 +			cp += 4;
   7.532 +			mem_limit = memparse(cp, &end);
   7.533 +			if (end != cp)
   7.534 +				break;
   7.535 +			cp = end;
   7.536 +		} else if (memcmp(cp, "max_addr=", 9) == 0) {
   7.537 +			cp += 9;
   7.538 +			max_addr = GRANULEROUNDDOWN(memparse(cp, &end));
   7.539 +			if (end != cp)
   7.540 +				break;
   7.541 +			cp = end;
   7.542 +		} else {
   7.543 +			while (*cp != ' ' && *cp)
   7.544 +				++cp;
   7.545 +			while (*cp == ' ')
   7.546 +				++cp;
   7.547 +		}
   7.548 +	}
   7.549 +	if (max_addr != ~0UL)
   7.550 +		printk(KERN_INFO "Ignoring memory above %luMB\n", max_addr >> 20);
   7.551 +
   7.552 +	efi.systab = __va(ia64_boot_param->efi_systab);
   7.553 +
   7.554 +	/*
   7.555 +	 * Verify the EFI Table
   7.556 +	 */
   7.557 +	if (efi.systab == NULL)
   7.558 +		panic("Woah! Can't find EFI system table.\n");
   7.559 +	if (efi.systab->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE)
   7.560 +		panic("Woah! EFI system table signature incorrect\n");
   7.561 +	if ((efi.systab->hdr.revision ^ EFI_SYSTEM_TABLE_REVISION) >> 16 != 0)
   7.562 +		printk(KERN_WARNING "Warning: EFI system table major version mismatch: "
   7.563 +		       "got %d.%02d, expected %d.%02d\n",
   7.564 +		       efi.systab->hdr.revision >> 16, efi.systab->hdr.revision & 0xffff,
   7.565 +		       EFI_SYSTEM_TABLE_REVISION >> 16, EFI_SYSTEM_TABLE_REVISION & 0xffff);
   7.566 +
   7.567 +	config_tables = __va(efi.systab->tables);
   7.568 +
   7.569 +	/* Show what we know for posterity */
   7.570 +	c16 = __va(efi.systab->fw_vendor);
   7.571 +	if (c16) {
   7.572 +		for (i = 0;i < (int) sizeof(vendor) && *c16; ++i)
   7.573 +			vendor[i] = *c16++;
   7.574 +		vendor[i] = '\0';
   7.575 +	}
   7.576 +
   7.577 +	printk(KERN_INFO "EFI v%u.%.02u by %s:",
   7.578 +	       efi.systab->hdr.revision >> 16, efi.systab->hdr.revision & 0xffff, vendor);
   7.579 +
   7.580 +	for (i = 0; i < (int) efi.systab->nr_tables; i++) {
   7.581 +		if (efi_guidcmp(config_tables[i].guid, MPS_TABLE_GUID) == 0) {
   7.582 +			efi.mps = __va(config_tables[i].table);
   7.583 +			printk(" MPS=0x%lx", config_tables[i].table);
   7.584 +		} else if (efi_guidcmp(config_tables[i].guid, ACPI_20_TABLE_GUID) == 0) {
   7.585 +			efi.acpi20 = __va(config_tables[i].table);
   7.586 +			printk(" ACPI 2.0=0x%lx", config_tables[i].table);
   7.587 +		} else if (efi_guidcmp(config_tables[i].guid, ACPI_TABLE_GUID) == 0) {
   7.588 +			efi.acpi = __va(config_tables[i].table);
   7.589 +			printk(" ACPI=0x%lx", config_tables[i].table);
   7.590 +		} else if (efi_guidcmp(config_tables[i].guid, SMBIOS_TABLE_GUID) == 0) {
   7.591 +			efi.smbios = __va(config_tables[i].table);
   7.592 +			printk(" SMBIOS=0x%lx", config_tables[i].table);
   7.593 +		} else if (efi_guidcmp(config_tables[i].guid, SAL_SYSTEM_TABLE_GUID) == 0) {
   7.594 +			efi.sal_systab = __va(config_tables[i].table);
   7.595 +			printk(" SALsystab=0x%lx", config_tables[i].table);
   7.596 +		} else if (efi_guidcmp(config_tables[i].guid, HCDP_TABLE_GUID) == 0) {
   7.597 +			efi.hcdp = __va(config_tables[i].table);
   7.598 +			printk(" HCDP=0x%lx", config_tables[i].table);
   7.599 +		}
   7.600 +	}
   7.601 +	printk("\n");
   7.602 +
   7.603 +	runtime = __va(efi.systab->runtime);
   7.604 +	efi.get_time = phys_get_time;
   7.605 +	efi.set_time = phys_set_time;
   7.606 +	efi.get_wakeup_time = phys_get_wakeup_time;
   7.607 +	efi.set_wakeup_time = phys_set_wakeup_time;
   7.608 +	efi.get_variable = phys_get_variable;
   7.609 +	efi.get_next_variable = phys_get_next_variable;
   7.610 +	efi.set_variable = phys_set_variable;
   7.611 +	efi.get_next_high_mono_count = phys_get_next_high_mono_count;
   7.612 +	efi.reset_system = phys_reset_system;
   7.613 +
   7.614 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   7.615 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   7.616 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   7.617 +
   7.618 +#if EFI_DEBUG
   7.619 +	/* print EFI memory map: */
   7.620 +	{
   7.621 +		efi_memory_desc_t *md;
   7.622 +		void *p;
   7.623 +
   7.624 +		for (i = 0, p = efi_map_start; p < efi_map_end; ++i, p += efi_desc_size) {
   7.625 +			md = p;
   7.626 +			printk("mem%02u: type=%u, attr=0x%lx, range=[0x%016lx-0x%016lx) (%luMB)\n",
   7.627 +			       i, md->type, md->attribute, md->phys_addr,
   7.628 +			       md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT),
   7.629 +			       md->num_pages >> (20 - EFI_PAGE_SHIFT));
   7.630 +		}
   7.631 +	}
   7.632 +#endif
   7.633 +
   7.634 +	efi_map_pal_code();
   7.635 +	efi_enter_virtual_mode();
   7.636 +}
   7.637 +
   7.638 +void
   7.639 +efi_enter_virtual_mode (void)
   7.640 +{
   7.641 +	void *efi_map_start, *efi_map_end, *p;
   7.642 +	efi_memory_desc_t *md;
   7.643 +	efi_status_t status;
   7.644 +	u64 efi_desc_size;
   7.645 +
   7.646 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   7.647 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   7.648 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   7.649 +
   7.650 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   7.651 +		md = p;
   7.652 +		if (md->attribute & EFI_MEMORY_RUNTIME) {
   7.653 +			/*
   7.654 +			 * Some descriptors have multiple bits set, so the order of
   7.655 +			 * the tests is relevant.
   7.656 +			 */
   7.657 +			if (md->attribute & EFI_MEMORY_WB) {
   7.658 +				md->virt_addr = (u64) __va(md->phys_addr);
   7.659 +			} else if (md->attribute & EFI_MEMORY_UC) {
   7.660 +				md->virt_addr = (u64) ioremap(md->phys_addr, 0);
   7.661 +			} else if (md->attribute & EFI_MEMORY_WC) {
   7.662 +#if 0
   7.663 +				md->virt_addr = ia64_remap(md->phys_addr, (_PAGE_A | _PAGE_P
   7.664 +									   | _PAGE_D
   7.665 +									   | _PAGE_MA_WC
   7.666 +									   | _PAGE_PL_0
   7.667 +									   | _PAGE_AR_RW));
   7.668 +#else
   7.669 +				printk(KERN_INFO "EFI_MEMORY_WC mapping\n");
   7.670 +				md->virt_addr = (u64) ioremap(md->phys_addr, 0);
   7.671 +#endif
   7.672 +			} else if (md->attribute & EFI_MEMORY_WT) {
   7.673 +#if 0
   7.674 +				md->virt_addr = ia64_remap(md->phys_addr, (_PAGE_A | _PAGE_P
   7.675 +									   | _PAGE_D | _PAGE_MA_WT
   7.676 +									   | _PAGE_PL_0
   7.677 +									   | _PAGE_AR_RW));
   7.678 +#else
   7.679 +				printk(KERN_INFO "EFI_MEMORY_WT mapping\n");
   7.680 +				md->virt_addr = (u64) ioremap(md->phys_addr, 0);
   7.681 +#endif
   7.682 +			}
   7.683 +		}
   7.684 +	}
   7.685 +
   7.686 +	status = efi_call_phys(__va(runtime->set_virtual_address_map),
   7.687 +			       ia64_boot_param->efi_memmap_size,
   7.688 +			       efi_desc_size, ia64_boot_param->efi_memdesc_version,
   7.689 +			       ia64_boot_param->efi_memmap);
   7.690 +	if (status != EFI_SUCCESS) {
   7.691 +		printk(KERN_WARNING "warning: unable to switch EFI into virtual mode "
   7.692 +		       "(status=%lu)\n", status);
   7.693 +		return;
   7.694 +	}
   7.695 +
   7.696 +	/*
   7.697 +	 * Now that EFI is in virtual mode, we call the EFI functions more efficiently:
   7.698 +	 */
   7.699 +	efi.get_time = virt_get_time;
   7.700 +	efi.set_time = virt_set_time;
   7.701 +	efi.get_wakeup_time = virt_get_wakeup_time;
   7.702 +	efi.set_wakeup_time = virt_set_wakeup_time;
   7.703 +	efi.get_variable = virt_get_variable;
   7.704 +	efi.get_next_variable = virt_get_next_variable;
   7.705 +	efi.set_variable = virt_set_variable;
   7.706 +	efi.get_next_high_mono_count = virt_get_next_high_mono_count;
   7.707 +	efi.reset_system = virt_reset_system;
   7.708 +}
   7.709 +
   7.710 +/*
   7.711 + * Walk the EFI memory map looking for the I/O port range.  There can only be one entry of
   7.712 + * this type, other I/O port ranges should be described via ACPI.
   7.713 + */
   7.714 +u64
   7.715 +efi_get_iobase (void)
   7.716 +{
   7.717 +	void *efi_map_start, *efi_map_end, *p;
   7.718 +	efi_memory_desc_t *md;
   7.719 +	u64 efi_desc_size;
   7.720 +
   7.721 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   7.722 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   7.723 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   7.724 +
   7.725 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   7.726 +		md = p;
   7.727 +		if (md->type == EFI_MEMORY_MAPPED_IO_PORT_SPACE) {
   7.728 +			if (md->attribute & EFI_MEMORY_UC)
   7.729 +				return md->phys_addr;
   7.730 +		}
   7.731 +	}
   7.732 +	return 0;
   7.733 +}
   7.734 +
   7.735 +#ifdef XEN
   7.736 +// variation of efi_get_iobase which returns entire memory descriptor
   7.737 +efi_memory_desc_t *
   7.738 +efi_get_io_md (void)
   7.739 +{
   7.740 +	void *efi_map_start, *efi_map_end, *p;
   7.741 +	efi_memory_desc_t *md;
   7.742 +	u64 efi_desc_size;
   7.743 +
   7.744 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   7.745 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   7.746 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   7.747 +
   7.748 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   7.749 +		md = p;
   7.750 +		if (md->type == EFI_MEMORY_MAPPED_IO_PORT_SPACE) {
   7.751 +			if (md->attribute & EFI_MEMORY_UC)
   7.752 +				return md;
   7.753 +		}
   7.754 +	}
   7.755 +	return 0;
   7.756 +}
   7.757 +#endif
   7.758 +
   7.759 +u32
   7.760 +efi_mem_type (unsigned long phys_addr)
   7.761 +{
   7.762 +	void *efi_map_start, *efi_map_end, *p;
   7.763 +	efi_memory_desc_t *md;
   7.764 +	u64 efi_desc_size;
   7.765 +
   7.766 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   7.767 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   7.768 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   7.769 +
   7.770 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   7.771 +		md = p;
   7.772 +
   7.773 +		if (phys_addr - md->phys_addr < (md->num_pages << EFI_PAGE_SHIFT))
   7.774 +			 return md->type;
   7.775 +	}
   7.776 +	return 0;
   7.777 +}
   7.778 +
   7.779 +u64
   7.780 +efi_mem_attributes (unsigned long phys_addr)
   7.781 +{
   7.782 +	void *efi_map_start, *efi_map_end, *p;
   7.783 +	efi_memory_desc_t *md;
   7.784 +	u64 efi_desc_size;
   7.785 +
   7.786 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   7.787 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   7.788 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   7.789 +
   7.790 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   7.791 +		md = p;
   7.792 +
   7.793 +		if (phys_addr - md->phys_addr < (md->num_pages << EFI_PAGE_SHIFT))
   7.794 +			return md->attribute;
   7.795 +	}
   7.796 +	return 0;
   7.797 +}
   7.798 +EXPORT_SYMBOL(efi_mem_attributes);
   7.799 +
   7.800 +int
   7.801 +valid_phys_addr_range (unsigned long phys_addr, unsigned long *size)
   7.802 +{
   7.803 +	void *efi_map_start, *efi_map_end, *p;
   7.804 +	efi_memory_desc_t *md;
   7.805 +	u64 efi_desc_size;
   7.806 +
   7.807 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   7.808 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   7.809 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   7.810 +
   7.811 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   7.812 +		md = p;
   7.813 +
   7.814 +		if (phys_addr - md->phys_addr < (md->num_pages << EFI_PAGE_SHIFT)) {
   7.815 +			if (!(md->attribute & EFI_MEMORY_WB))
   7.816 +				return 0;
   7.817 +
   7.818 +			if (*size > md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT) - phys_addr)
   7.819 +				*size = md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT) - phys_addr;
   7.820 +			return 1;
   7.821 +		}
   7.822 +	}
   7.823 +	return 0;
   7.824 +}
   7.825 +
   7.826 +int __init
   7.827 +efi_uart_console_only(void)
   7.828 +{
   7.829 +	efi_status_t status;
   7.830 +	char *s, name[] = "ConOut";
   7.831 +	efi_guid_t guid = EFI_GLOBAL_VARIABLE_GUID;
   7.832 +	efi_char16_t *utf16, name_utf16[32];
   7.833 +	unsigned char data[1024];
   7.834 +	unsigned long size = sizeof(data);
   7.835 +	struct efi_generic_dev_path *hdr, *end_addr;
   7.836 +	int uart = 0;
   7.837 +
   7.838 +	/* Convert to UTF-16 */
   7.839 +	utf16 = name_utf16;
   7.840 +	s = name;
   7.841 +	while (*s)
   7.842 +		*utf16++ = *s++ & 0x7f;
   7.843 +	*utf16 = 0;
   7.844 +
   7.845 +	status = efi.get_variable(name_utf16, &guid, NULL, &size, data);
   7.846 +	if (status != EFI_SUCCESS) {
   7.847 +		printk(KERN_ERR "No EFI %s variable?\n", name);
   7.848 +		return 0;
   7.849 +	}
   7.850 +
   7.851 +	hdr = (struct efi_generic_dev_path *) data;
   7.852 +	end_addr = (struct efi_generic_dev_path *) ((u8 *) data + size);
   7.853 +	while (hdr < end_addr) {
   7.854 +		if (hdr->type == EFI_DEV_MSG &&
   7.855 +		    hdr->sub_type == EFI_DEV_MSG_UART)
   7.856 +			uart = 1;
   7.857 +		else if (hdr->type == EFI_DEV_END_PATH ||
   7.858 +			  hdr->type == EFI_DEV_END_PATH2) {
   7.859 +			if (!uart)
   7.860 +				return 0;
   7.861 +			if (hdr->sub_type == EFI_DEV_END_ENTIRE)
   7.862 +				return 1;
   7.863 +			uart = 0;
   7.864 +		}
   7.865 +		hdr = (struct efi_generic_dev_path *) ((u8 *) hdr + hdr->length);
   7.866 +	}
   7.867 +	printk(KERN_ERR "Malformed %s value\n", name);
   7.868 +	return 0;
   7.869 +}
     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/xen/arch/ia64/linux-xen/entry.S	Fri Aug 26 09:05:43 2005 +0000
     8.3 @@ -0,0 +1,1657 @@
     8.4 +/*
     8.5 + * ia64/kernel/entry.S
     8.6 + *
     8.7 + * Kernel entry points.
     8.8 + *
     8.9 + * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
    8.10 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    8.11 + * Copyright (C) 1999, 2002-2003
    8.12 + *	Asit Mallick <Asit.K.Mallick@intel.com>
    8.13 + * 	Don Dugger <Don.Dugger@intel.com>
    8.14 + *	Suresh Siddha <suresh.b.siddha@intel.com>
    8.15 + *	Fenghua Yu <fenghua.yu@intel.com>
    8.16 + * Copyright (C) 1999 VA Linux Systems
    8.17 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
    8.18 + */
    8.19 +/*
    8.20 + * ia64_switch_to now places correct virtual mapping in in TR2 for
    8.21 + * kernel stack. This allows us to handle interrupts without changing
    8.22 + * to physical mode.
    8.23 + *
    8.24 + * Jonathan Nicklin	<nicklin@missioncriticallinux.com>
    8.25 + * Patrick O'Rourke	<orourke@missioncriticallinux.com>
    8.26 + * 11/07/2000
    8.27 + */
    8.28 +/*
    8.29 + * Global (preserved) predicate usage on syscall entry/exit path:
    8.30 + *
    8.31 + *	pKStk:		See entry.h.
    8.32 + *	pUStk:		See entry.h.
    8.33 + *	pSys:		See entry.h.
    8.34 + *	pNonSys:	!pSys
    8.35 + */
    8.36 +
    8.37 +#include <linux/config.h>
    8.38 +
    8.39 +#include <asm/asmmacro.h>
    8.40 +#include <asm/cache.h>
    8.41 +#include <asm/errno.h>
    8.42 +#include <asm/kregs.h>
    8.43 +#include <asm/offsets.h>
    8.44 +#include <asm/pgtable.h>
    8.45 +#include <asm/percpu.h>
    8.46 +#include <asm/processor.h>
    8.47 +#include <asm/thread_info.h>
    8.48 +#include <asm/unistd.h>
    8.49 +
    8.50 +#include "minstate.h"
    8.51 +
    8.52 +#ifndef XEN
    8.53 +	/*
    8.54 +	 * execve() is special because in case of success, we need to
    8.55 +	 * setup a null register window frame.
    8.56 +	 */
    8.57 +ENTRY(ia64_execve)
    8.58 +	/*
    8.59 +	 * Allocate 8 input registers since ptrace() may clobber them
    8.60 +	 */
    8.61 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
    8.62 +	alloc loc1=ar.pfs,8,2,4,0
    8.63 +	mov loc0=rp
    8.64 +	.body
    8.65 +	mov out0=in0			// filename
    8.66 +	;;				// stop bit between alloc and call
    8.67 +	mov out1=in1			// argv
    8.68 +	mov out2=in2			// envp
    8.69 +	add out3=16,sp			// regs
    8.70 +	br.call.sptk.many rp=sys_execve
    8.71 +.ret0:
    8.72 +#ifdef CONFIG_IA32_SUPPORT
    8.73 +	/*
    8.74 +	 * Check if we're returning to ia32 mode. If so, we need to restore ia32 registers
    8.75 +	 * from pt_regs.
    8.76 +	 */
    8.77 +	adds r16=PT(CR_IPSR)+16,sp
    8.78 +	;;
    8.79 +	ld8 r16=[r16]
    8.80 +#endif
    8.81 +	cmp4.ge p6,p7=r8,r0
    8.82 +	mov ar.pfs=loc1			// restore ar.pfs
    8.83 +	sxt4 r8=r8			// return 64-bit result
    8.84 +	;;
    8.85 +	stf.spill [sp]=f0
    8.86 +(p6)	cmp.ne pKStk,pUStk=r0,r0	// a successful execve() lands us in user-mode...
    8.87 +	mov rp=loc0
    8.88 +(p6)	mov ar.pfs=r0			// clear ar.pfs on success
    8.89 +(p7)	br.ret.sptk.many rp
    8.90 +
    8.91 +	/*
    8.92 +	 * In theory, we'd have to zap this state only to prevent leaking of
    8.93 +	 * security sensitive state (e.g., if current->mm->dumpable is zero).  However,
    8.94 +	 * this executes in less than 20 cycles even on Itanium, so it's not worth
    8.95 +	 * optimizing for...).
    8.96 +	 */
    8.97 +	mov ar.unat=0; 		mov ar.lc=0
    8.98 +	mov r4=0;		mov f2=f0;		mov b1=r0
    8.99 +	mov r5=0;		mov f3=f0;		mov b2=r0
   8.100 +	mov r6=0;		mov f4=f0;		mov b3=r0
   8.101 +	mov r7=0;		mov f5=f0;		mov b4=r0
   8.102 +	ldf.fill f12=[sp];	mov f13=f0;		mov b5=r0
   8.103 +	ldf.fill f14=[sp];	ldf.fill f15=[sp];	mov f16=f0
   8.104 +	ldf.fill f17=[sp];	ldf.fill f18=[sp];	mov f19=f0
   8.105 +	ldf.fill f20=[sp];	ldf.fill f21=[sp];	mov f22=f0
   8.106 +	ldf.fill f23=[sp];	ldf.fill f24=[sp];	mov f25=f0
   8.107 +	ldf.fill f26=[sp];	ldf.fill f27=[sp];	mov f28=f0
   8.108 +	ldf.fill f29=[sp];	ldf.fill f30=[sp];	mov f31=f0
   8.109 +#ifdef CONFIG_IA32_SUPPORT
   8.110 +	tbit.nz p6,p0=r16, IA64_PSR_IS_BIT
   8.111 +	movl loc0=ia64_ret_from_ia32_execve
   8.112 +	;;
   8.113 +(p6)	mov rp=loc0
   8.114 +#endif
   8.115 +	br.ret.sptk.many rp
   8.116 +END(ia64_execve)
   8.117 +
   8.118 +/*
   8.119 + * sys_clone2(u64 flags, u64 ustack_base, u64 ustack_size, u64 parent_tidptr, u64 child_tidptr,
   8.120 + *	      u64 tls)
   8.121 + */
   8.122 +GLOBAL_ENTRY(sys_clone2)
   8.123 +	/*
   8.124 +	 * Allocate 8 input registers since ptrace() may clobber them
   8.125 +	 */
   8.126 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
   8.127 +	alloc r16=ar.pfs,8,2,6,0
   8.128 +	DO_SAVE_SWITCH_STACK
   8.129 +	adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
   8.130 +	mov loc0=rp
   8.131 +	mov loc1=r16				// save ar.pfs across do_fork
   8.132 +	.body
   8.133 +	mov out1=in1
   8.134 +	mov out3=in2
   8.135 +	tbit.nz p6,p0=in0,CLONE_SETTLS_BIT
   8.136 +	mov out4=in3	// parent_tidptr: valid only w/CLONE_PARENT_SETTID
   8.137 +	;;
   8.138 +(p6)	st8 [r2]=in5				// store TLS in r16 for copy_thread()
   8.139 +	mov out5=in4	// child_tidptr:  valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID
   8.140 +	adds out2=IA64_SWITCH_STACK_SIZE+16,sp	// out2 = &regs
   8.141 +	mov out0=in0				// out0 = clone_flags
   8.142 +	br.call.sptk.many rp=do_fork
   8.143 +.ret1:	.restore sp
   8.144 +	adds sp=IA64_SWITCH_STACK_SIZE,sp	// pop the switch stack
   8.145 +	mov ar.pfs=loc1
   8.146 +	mov rp=loc0
   8.147 +	br.ret.sptk.many rp
   8.148 +END(sys_clone2)
   8.149 +
   8.150 +/*
   8.151 + * sys_clone(u64 flags, u64 ustack_base, u64 parent_tidptr, u64 child_tidptr, u64 tls)
   8.152 + *	Deprecated.  Use sys_clone2() instead.
   8.153 + */
   8.154 +GLOBAL_ENTRY(sys_clone)
   8.155 +	/*
   8.156 +	 * Allocate 8 input registers since ptrace() may clobber them
   8.157 +	 */
   8.158 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
   8.159 +	alloc r16=ar.pfs,8,2,6,0
   8.160 +	DO_SAVE_SWITCH_STACK
   8.161 +	adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
   8.162 +	mov loc0=rp
   8.163 +	mov loc1=r16				// save ar.pfs across do_fork
   8.164 +	.body
   8.165 +	mov out1=in1
   8.166 +	mov out3=16				// stacksize (compensates for 16-byte scratch area)
   8.167 +	tbit.nz p6,p0=in0,CLONE_SETTLS_BIT
   8.168 +	mov out4=in2	// parent_tidptr: valid only w/CLONE_PARENT_SETTID
   8.169 +	;;
   8.170 +(p6)	st8 [r2]=in4				// store TLS in r13 (tp)
   8.171 +	mov out5=in3	// child_tidptr:  valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID
   8.172 +	adds out2=IA64_SWITCH_STACK_SIZE+16,sp	// out2 = &regs
   8.173 +	mov out0=in0				// out0 = clone_flags
   8.174 +	br.call.sptk.many rp=do_fork
   8.175 +.ret2:	.restore sp
   8.176 +	adds sp=IA64_SWITCH_STACK_SIZE,sp	// pop the switch stack
   8.177 +	mov ar.pfs=loc1
   8.178 +	mov rp=loc0
   8.179 +	br.ret.sptk.many rp
   8.180 +END(sys_clone)
   8.181 +#endif /* !XEN */
   8.182 +
   8.183 +/*
   8.184 + * prev_task <- ia64_switch_to(struct task_struct *next)
   8.185 + *	With Ingo's new scheduler, interrupts are disabled when this routine gets
   8.186 + *	called.  The code starting at .map relies on this.  The rest of the code
   8.187 + *	doesn't care about the interrupt masking status.
   8.188 + */
   8.189 +GLOBAL_ENTRY(ia64_switch_to)
   8.190 +	.prologue
   8.191 +	alloc r16=ar.pfs,1,0,0,0
   8.192 +	DO_SAVE_SWITCH_STACK
   8.193 +	.body
   8.194 +
   8.195 +	adds r22=IA64_TASK_THREAD_KSP_OFFSET,r13
   8.196 +	movl r25=init_task
   8.197 +	movl r27=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_STACK_OFFSET;;
   8.198 +	ld8 r27=[r27]
   8.199 +	adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0
   8.200 +#ifdef XEN
   8.201 +	dep r20=0,in0,60,4		// physical address of "next"
   8.202 +#else
   8.203 +	dep r20=0,in0,61,3		// physical address of "next"
   8.204 +#endif
   8.205 +	;;
   8.206 +	st8 [r22]=sp			// save kernel stack pointer of old task
   8.207 +	shr.u r26=r20,IA64_GRANULE_SHIFT
   8.208 +	cmp.eq p7,p6=r25,in0
   8.209 +	;;
   8.210 +	/*
   8.211 +	 * If we've already mapped this task's page, we can skip doing it again.
   8.212 +	 */
   8.213 +(p6)	cmp.eq p7,p6=r26,r27
   8.214 +(p6)	br.cond.dpnt .map
   8.215 +	;;
   8.216 +.done:
   8.217 +(p6)	ssm psr.ic			// if we had to map, reenable the psr.ic bit FIRST!!!
   8.218 +	;;
   8.219 +(p6)	srlz.d
   8.220 +	ld8 sp=[r21]			// load kernel stack pointer of new task
   8.221 +	movl r8=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
   8.222 +	st8 [r8]=in0
   8.223 +	mov r8=r13			// return pointer to previously running task
   8.224 +	mov r13=in0			// set "current" pointer
   8.225 +	;;
   8.226 +	DO_LOAD_SWITCH_STACK
   8.227 +
   8.228 +#ifdef CONFIG_SMP
   8.229 +	sync.i				// ensure "fc"s done by this CPU are visible on other CPUs
   8.230 +#endif
   8.231 +	br.ret.sptk.many rp		// boogie on out in new context
   8.232 +
   8.233 +.map:
   8.234 +#ifdef XEN
   8.235 +	// avoid overlapping with kernel TR
   8.236 +	movl r25=KERNEL_START
   8.237 +	dep  r23=0,in0,0,KERNEL_TR_PAGE_SHIFT
   8.238 +	;;
   8.239 +	cmp.eq p7,p0=r25,r23
   8.240 +	;;
   8.241 +(p7)	movl r8=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_STACK_OFFSET;;
   8.242 +(p7)	st8 [r8]=r26
   8.243 +(p7)	br.cond.sptk .done
   8.244 +#endif
   8.245 +	rsm psr.ic			// interrupts (psr.i) are already disabled here
   8.246 +	movl r25=PAGE_KERNEL
   8.247 +	;;
   8.248 +	srlz.d
   8.249 +	or r23=r25,r20			// construct PA | page properties
   8.250 +	mov r25=IA64_GRANULE_SHIFT<<2
   8.251 +	;;
   8.252 +	mov cr.itir=r25
   8.253 +	mov cr.ifa=in0			// VA of next task...
   8.254 +	;;
   8.255 +	mov r25=IA64_TR_CURRENT_STACK
   8.256 +	movl r8=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_STACK_OFFSET;;
   8.257 +	st8 [r8]=r26
   8.258 +	itr.d dtr[r25]=r23		// wire in new mapping...
   8.259 +	br.cond.sptk .done
   8.260 +END(ia64_switch_to)
   8.261 +
   8.262 +/*
   8.263 + * Note that interrupts are enabled during save_switch_stack and load_switch_stack.  This
   8.264 + * means that we may get an interrupt with "sp" pointing to the new kernel stack while
   8.265 + * ar.bspstore is still pointing to the old kernel backing store area.  Since ar.rsc,
   8.266 + * ar.rnat, ar.bsp, and ar.bspstore are all preserved by interrupts, this is not a
   8.267 + * problem.  Also, we don't need to specify unwind information for preserved registers
   8.268 + * that are not modified in save_switch_stack as the right unwind information is already
   8.269 + * specified at the call-site of save_switch_stack.
   8.270 + */
   8.271 +
   8.272 +/*
   8.273 + * save_switch_stack:
   8.274 + *	- r16 holds ar.pfs
   8.275 + *	- b7 holds address to return to
   8.276 + *	- rp (b0) holds return address to save
   8.277 + */
   8.278 +GLOBAL_ENTRY(save_switch_stack)
   8.279 +	.prologue
   8.280 +	.altrp b7
   8.281 +	flushrs			// flush dirty regs to backing store (must be first in insn group)
   8.282 +	.save @priunat,r17
   8.283 +	mov r17=ar.unat		// preserve caller's
   8.284 +	.body
   8.285 +#ifdef CONFIG_ITANIUM
   8.286 +	adds r2=16+128,sp
   8.287 +	adds r3=16+64,sp
   8.288 +	adds r14=SW(R4)+16,sp
   8.289 +	;;
   8.290 +	st8.spill [r14]=r4,16		// spill r4
   8.291 +	lfetch.fault.excl.nt1 [r3],128
   8.292 +	;;
   8.293 +	lfetch.fault.excl.nt1 [r2],128
   8.294 +	lfetch.fault.excl.nt1 [r3],128
   8.295 +	;;
   8.296 +	lfetch.fault.excl [r2]
   8.297 +	lfetch.fault.excl [r3]
   8.298 +	adds r15=SW(R5)+16,sp
   8.299 +#else
   8.300 +	add r2=16+3*128,sp
   8.301 +	add r3=16,sp
   8.302 +	add r14=SW(R4)+16,sp
   8.303 +	;;
   8.304 +	st8.spill [r14]=r4,SW(R6)-SW(R4)	// spill r4 and prefetch offset 0x1c0
   8.305 +	lfetch.fault.excl.nt1 [r3],128	//		prefetch offset 0x010
   8.306 +	;;
   8.307 +	lfetch.fault.excl.nt1 [r3],128	//		prefetch offset 0x090
   8.308 +	lfetch.fault.excl.nt1 [r2],128	//		prefetch offset 0x190
   8.309 +	;;
   8.310 +	lfetch.fault.excl.nt1 [r3]	//		prefetch offset 0x110
   8.311 +	lfetch.fault.excl.nt1 [r2]	//		prefetch offset 0x210
   8.312 +	adds r15=SW(R5)+16,sp
   8.313 +#endif
   8.314 +	;;
   8.315 +	st8.spill [r15]=r5,SW(R7)-SW(R5)	// spill r5
   8.316 +	mov.m ar.rsc=0			// put RSE in mode: enforced lazy, little endian, pl 0
   8.317 +	add r2=SW(F2)+16,sp		// r2 = &sw->f2
   8.318 +	;;
   8.319 +	st8.spill [r14]=r6,SW(B0)-SW(R6)	// spill r6
   8.320 +	mov.m r18=ar.fpsr		// preserve fpsr
   8.321 +	add r3=SW(F3)+16,sp		// r3 = &sw->f3
   8.322 +	;;
   8.323 +	stf.spill [r2]=f2,32
   8.324 +	mov.m r19=ar.rnat
   8.325 +	mov r21=b0
   8.326 +
   8.327 +	stf.spill [r3]=f3,32
   8.328 +	st8.spill [r15]=r7,SW(B2)-SW(R7)	// spill r7
   8.329 +	mov r22=b1
   8.330 +	;;
   8.331 +	// since we're done with the spills, read and save ar.unat:
   8.332 +	mov.m r29=ar.unat
   8.333 +	mov.m r20=ar.bspstore
   8.334 +	mov r23=b2
   8.335 +	stf.spill [r2]=f4,32
   8.336 +	stf.spill [r3]=f5,32
   8.337 +	mov r24=b3
   8.338 +	;;
   8.339 +	st8 [r14]=r21,SW(B1)-SW(B0)		// save b0
   8.340 +	st8 [r15]=r23,SW(B3)-SW(B2)		// save b2
   8.341 +	mov r25=b4
   8.342 +	mov r26=b5
   8.343 +	;;
   8.344 +	st8 [r14]=r22,SW(B4)-SW(B1)		// save b1
   8.345 +	st8 [r15]=r24,SW(AR_PFS)-SW(B3)		// save b3
   8.346 +	mov r21=ar.lc		// I-unit
   8.347 +	stf.spill [r2]=f12,32
   8.348 +	stf.spill [r3]=f13,32
   8.349 +	;;
   8.350 +	st8 [r14]=r25,SW(B5)-SW(B4)		// save b4
   8.351 +	st8 [r15]=r16,SW(AR_LC)-SW(AR_PFS)	// save ar.pfs
   8.352 +	stf.spill [r2]=f14,32
   8.353 +	stf.spill [r3]=f15,32
   8.354 +	;;
   8.355 +	st8 [r14]=r26				// save b5
   8.356 +	st8 [r15]=r21				// save ar.lc
   8.357 +	stf.spill [r2]=f16,32
   8.358 +	stf.spill [r3]=f17,32
   8.359 +	;;
   8.360 +	stf.spill [r2]=f18,32
   8.361 +	stf.spill [r3]=f19,32
   8.362 +	;;
   8.363 +	stf.spill [r2]=f20,32
   8.364 +	stf.spill [r3]=f21,32
   8.365 +	;;
   8.366 +	stf.spill [r2]=f22,32
   8.367 +	stf.spill [r3]=f23,32
   8.368 +	;;
   8.369 +	stf.spill [r2]=f24,32
   8.370 +	stf.spill [r3]=f25,32
   8.371 +	;;
   8.372 +	stf.spill [r2]=f26,32
   8.373 +	stf.spill [r3]=f27,32
   8.374 +	;;
   8.375 +	stf.spill [r2]=f28,32
   8.376 +	stf.spill [r3]=f29,32
   8.377 +	;;
   8.378 +	stf.spill [r2]=f30,SW(AR_UNAT)-SW(F30)
   8.379 +	stf.spill [r3]=f31,SW(PR)-SW(F31)
   8.380 +	add r14=SW(CALLER_UNAT)+16,sp
   8.381 +	;;
   8.382 +	st8 [r2]=r29,SW(AR_RNAT)-SW(AR_UNAT)	// save ar.unat
   8.383 +	st8 [r14]=r17,SW(AR_FPSR)-SW(CALLER_UNAT) // save caller_unat
   8.384 +	mov r21=pr
   8.385 +	;;
   8.386 +	st8 [r2]=r19,SW(AR_BSPSTORE)-SW(AR_RNAT) // save ar.rnat
   8.387 +	st8 [r3]=r21				// save predicate registers
   8.388 +	;;
   8.389 +	st8 [r2]=r20				// save ar.bspstore
   8.390 +	st8 [r14]=r18				// save fpsr
   8.391 +	mov ar.rsc=3		// put RSE back into eager mode, pl 0
   8.392 +	br.cond.sptk.many b7
   8.393 +END(save_switch_stack)
   8.394 +
   8.395 +/*
   8.396 + * load_switch_stack:
   8.397 + *	- "invala" MUST be done at call site (normally in DO_LOAD_SWITCH_STACK)
   8.398 + *	- b7 holds address to return to
   8.399 + *	- must not touch r8-r11
   8.400 + */
   8.401 +#ifdef XEN
   8.402 +GLOBAL_ENTRY(load_switch_stack)
   8.403 +#else
   8.404 +ENTRY(load_switch_stack)
   8.405 +#endif
   8.406 +	.prologue
   8.407 +	.altrp b7
   8.408 +
   8.409 +	.body
   8.410 +	lfetch.fault.nt1 [sp]
   8.411 +	adds r2=SW(AR_BSPSTORE)+16,sp
   8.412 +	adds r3=SW(AR_UNAT)+16,sp
   8.413 +	mov ar.rsc=0						// put RSE into enforced lazy mode
   8.414 +	adds r14=SW(CALLER_UNAT)+16,sp
   8.415 +	adds r15=SW(AR_FPSR)+16,sp
   8.416 +	;;
   8.417 +	ld8 r27=[r2],(SW(B0)-SW(AR_BSPSTORE))	// bspstore
   8.418 +	ld8 r29=[r3],(SW(B1)-SW(AR_UNAT))	// unat
   8.419 +	;;
   8.420 +	ld8 r21=[r2],16		// restore b0
   8.421 +	ld8 r22=[r3],16		// restore b1
   8.422 +	;;
   8.423 +	ld8 r23=[r2],16		// restore b2
   8.424 +	ld8 r24=[r3],16		// restore b3
   8.425 +	;;
   8.426 +	ld8 r25=[r2],16		// restore b4
   8.427 +	ld8 r26=[r3],16		// restore b5
   8.428 +	;;
   8.429 +	ld8 r16=[r2],(SW(PR)-SW(AR_PFS))	// ar.pfs
   8.430 +	ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC))	// ar.lc
   8.431 +	;;
   8.432 +	ld8 r28=[r2]		// restore pr
   8.433 +	ld8 r30=[r3]		// restore rnat
   8.434 +	;;
   8.435 +	ld8 r18=[r14],16	// restore caller's unat
   8.436 +	ld8 r19=[r15],24	// restore fpsr
   8.437 +	;;
   8.438 +	ldf.fill f2=[r14],32
   8.439 +	ldf.fill f3=[r15],32
   8.440 +	;;
   8.441 +	ldf.fill f4=[r14],32
   8.442 +	ldf.fill f5=[r15],32
   8.443 +	;;
   8.444 +	ldf.fill f12=[r14],32
   8.445 +	ldf.fill f13=[r15],32
   8.446 +	;;
   8.447 +	ldf.fill f14=[r14],32
   8.448 +	ldf.fill f15=[r15],32
   8.449 +	;;
   8.450 +	ldf.fill f16=[r14],32
   8.451 +	ldf.fill f17=[r15],32
   8.452 +	;;
   8.453 +	ldf.fill f18=[r14],32
   8.454 +	ldf.fill f19=[r15],32
   8.455 +	mov b0=r21
   8.456 +	;;
   8.457 +	ldf.fill f20=[r14],32
   8.458 +	ldf.fill f21=[r15],32
   8.459 +	mov b1=r22
   8.460 +	;;
   8.461 +	ldf.fill f22=[r14],32
   8.462 +	ldf.fill f23=[r15],32
   8.463 +	mov b2=r23
   8.464 +	;;
   8.465 +	mov ar.bspstore=r27
   8.466 +	mov ar.unat=r29		// establish unat holding the NaT bits for r4-r7
   8.467 +	mov b3=r24
   8.468 +	;;
   8.469 +	ldf.fill f24=[r14],32
   8.470 +	ldf.fill f25=[r15],32
   8.471 +	mov b4=r25
   8.472 +	;;
   8.473 +	ldf.fill f26=[r14],32
   8.474 +	ldf.fill f27=[r15],32
   8.475 +	mov b5=r26
   8.476 +	;;
   8.477 +	ldf.fill f28=[r14],32
   8.478 +	ldf.fill f29=[r15],32
   8.479 +	mov ar.pfs=r16
   8.480 +	;;
   8.481 +	ldf.fill f30=[r14],32
   8.482 +	ldf.fill f31=[r15],24
   8.483 +	mov ar.lc=r17
   8.484 +	;;
   8.485 +	ld8.fill r4=[r14],16
   8.486 +	ld8.fill r5=[r15],16
   8.487 +	mov pr=r28,-1
   8.488 +	;;
   8.489 +	ld8.fill r6=[r14],16
   8.490 +	ld8.fill r7=[r15],16
   8.491 +
   8.492 +	mov ar.unat=r18				// restore caller's unat
   8.493 +	mov ar.rnat=r30				// must restore after bspstore but before rsc!
   8.494 +	mov ar.fpsr=r19				// restore fpsr
   8.495 +	mov ar.rsc=3				// put RSE back into eager mode, pl 0
   8.496 +	br.cond.sptk.many b7
   8.497 +END(load_switch_stack)
   8.498 +
   8.499 +#ifndef XEN
   8.500 +GLOBAL_ENTRY(__ia64_syscall)
   8.501 +	.regstk 6,0,0,0
   8.502 +	mov r15=in5				// put syscall number in place
   8.503 +	break __BREAK_SYSCALL
   8.504 +	movl r2=errno
   8.505 +	cmp.eq p6,p7=-1,r10
   8.506 +	;;
   8.507 +(p6)	st4 [r2]=r8
   8.508 +(p6)	mov r8=-1
   8.509 +	br.ret.sptk.many rp
   8.510 +END(__ia64_syscall)
   8.511 +
   8.512 +GLOBAL_ENTRY(execve)
   8.513 +	mov r15=__NR_execve			// put syscall number in place
   8.514 +	break __BREAK_SYSCALL
   8.515 +	br.ret.sptk.many rp
   8.516 +END(execve)
   8.517 +
   8.518 +GLOBAL_ENTRY(clone)
   8.519 +	mov r15=__NR_clone			// put syscall number in place
   8.520 +	break __BREAK_SYSCALL
   8.521 +	br.ret.sptk.many rp
   8.522 +END(clone)
   8.523 +
   8.524 +	/*
   8.525 +	 * Invoke a system call, but do some tracing before and after the call.
   8.526 +	 * We MUST preserve the current register frame throughout this routine
   8.527 +	 * because some system calls (such as ia64_execve) directly
   8.528 +	 * manipulate ar.pfs.
   8.529 +	 */
   8.530 +GLOBAL_ENTRY(ia64_trace_syscall)
   8.531 +	PT_REGS_UNWIND_INFO(0)
   8.532 +	/*
   8.533 +	 * We need to preserve the scratch registers f6-f11 in case the system
   8.534 +	 * call is sigreturn.
   8.535 +	 */
   8.536 +	adds r16=PT(F6)+16,sp
   8.537 +	adds r17=PT(F7)+16,sp
   8.538 +	;;
   8.539 + 	stf.spill [r16]=f6,32
   8.540 + 	stf.spill [r17]=f7,32
   8.541 +	;;
   8.542 + 	stf.spill [r16]=f8,32
   8.543 + 	stf.spill [r17]=f9,32
   8.544 +	;;
   8.545 + 	stf.spill [r16]=f10
   8.546 + 	stf.spill [r17]=f11
   8.547 +	br.call.sptk.many rp=syscall_trace_enter // give parent a chance to catch syscall args
   8.548 +	adds r16=PT(F6)+16,sp
   8.549 +	adds r17=PT(F7)+16,sp
   8.550 +	;;
   8.551 +	ldf.fill f6=[r16],32
   8.552 +	ldf.fill f7=[r17],32
   8.553 +	;;
   8.554 +	ldf.fill f8=[r16],32
   8.555 +	ldf.fill f9=[r17],32
   8.556 +	;;
   8.557 +	ldf.fill f10=[r16]
   8.558 +	ldf.fill f11=[r17]
   8.559 +	// the syscall number may have changed, so re-load it and re-calculate the
   8.560 +	// syscall entry-point:
   8.561 +	adds r15=PT(R15)+16,sp			// r15 = &pt_regs.r15 (syscall #)
   8.562 +	;;
   8.563 +	ld8 r15=[r15]
   8.564 +	mov r3=NR_syscalls - 1
   8.565 +	;;
   8.566 +	adds r15=-1024,r15
   8.567 +	movl r16=sys_call_table
   8.568 +	;;
   8.569 +	shladd r20=r15,3,r16			// r20 = sys_call_table + 8*(syscall-1024)
   8.570 +	cmp.leu p6,p7=r15,r3
   8.571 +	;;
   8.572 +(p6)	ld8 r20=[r20]				// load address of syscall entry point
   8.573 +(p7)	movl r20=sys_ni_syscall
   8.574 +	;;
   8.575 +	mov b6=r20
   8.576 +	br.call.sptk.many rp=b6			// do the syscall
   8.577 +.strace_check_retval:
   8.578 +	cmp.lt p6,p0=r8,r0			// syscall failed?
   8.579 +	adds r2=PT(R8)+16,sp			// r2 = &pt_regs.r8
   8.580 +	adds r3=PT(R10)+16,sp			// r3 = &pt_regs.r10
   8.581 +	mov r10=0
   8.582 +(p6)	br.cond.sptk strace_error		// syscall failed ->
   8.583 +	;;					// avoid RAW on r10
   8.584 +.strace_save_retval:
   8.585 +.mem.offset 0,0; st8.spill [r2]=r8		// store return value in slot for r8
   8.586 +.mem.offset 8,0; st8.spill [r3]=r10		// clear error indication in slot for r10
   8.587 +	br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
   8.588 +.ret3:	br.cond.sptk .work_pending_syscall_end
   8.589 +
   8.590 +strace_error:
   8.591 +	ld8 r3=[r2]				// load pt_regs.r8
   8.592 +	sub r9=0,r8				// negate return value to get errno value
   8.593 +	;;
   8.594 +	cmp.ne p6,p0=r3,r0			// is pt_regs.r8!=0?
   8.595 +	adds r3=16,r2				// r3=&pt_regs.r10
   8.596 +	;;
   8.597 +(p6)	mov r10=-1
   8.598 +(p6)	mov r8=r9
   8.599 +	br.cond.sptk .strace_save_retval
   8.600 +END(ia64_trace_syscall)
   8.601 +
   8.602 +	/*
   8.603 +	 * When traced and returning from sigreturn, we invoke syscall_trace but then
   8.604 +	 * go straight to ia64_leave_kernel rather than ia64_leave_syscall.
   8.605 +	 */
   8.606 +GLOBAL_ENTRY(ia64_strace_leave_kernel)
   8.607 +	PT_REGS_UNWIND_INFO(0)
   8.608 +{	/*
   8.609 +	 * Some versions of gas generate bad unwind info if the first instruction of a
   8.610 +	 * procedure doesn't go into the first slot of a bundle.  This is a workaround.
   8.611 +	 */
   8.612 +	nop.m 0
   8.613 +	nop.i 0
   8.614 +	br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
   8.615 +}
   8.616 +.ret4:	br.cond.sptk ia64_leave_kernel
   8.617 +END(ia64_strace_leave_kernel)
   8.618 +#endif
   8.619 +
   8.620 +GLOBAL_ENTRY(ia64_ret_from_clone)
   8.621 +	PT_REGS_UNWIND_INFO(0)
   8.622 +{	/*
   8.623 +	 * Some versions of gas generate bad unwind info if the first instruction of a
   8.624 +	 * procedure doesn't go into the first slot of a bundle.  This is a workaround.
   8.625 +	 */
   8.626 +	nop.m 0
   8.627 +	nop.i 0
   8.628 +	/*
   8.629 +	 * We need to call schedule_tail() to complete the scheduling process.
   8.630 +	 * Called by ia64_switch_to() after do_fork()->copy_thread().  r8 contains the
   8.631 +	 * address of the previously executing task.
   8.632 +	 */
   8.633 +	br.call.sptk.many rp=ia64_invoke_schedule_tail
   8.634 +}
   8.635 +#ifdef XEN
   8.636 +	// new domains are cloned but not exec'ed so switch to user mode here
   8.637 +	cmp.ne pKStk,pUStk=r0,r0
   8.638 +#ifdef CONFIG_VTI
   8.639 +	br.cond.spnt ia64_leave_hypervisor
   8.640 +#else // CONFIG_VTI
   8.641 +	br.cond.spnt ia64_leave_kernel
   8.642 +#endif // CONFIG_VTI
   8.643 +#else
   8.644 +.ret8:
   8.645 +	adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
   8.646 +	;;
   8.647 +	ld4 r2=[r2]
   8.648 +	;;
   8.649 +	mov r8=0
   8.650 +	and r2=_TIF_SYSCALL_TRACEAUDIT,r2
   8.651 +	;;
   8.652 +	cmp.ne p6,p0=r2,r0
   8.653 +(p6)	br.cond.spnt .strace_check_retval
   8.654 +#endif
   8.655 +	;;					// added stop bits to prevent r8 dependency
   8.656 +END(ia64_ret_from_clone)
   8.657 +	// fall through
   8.658 +GLOBAL_ENTRY(ia64_ret_from_syscall)
   8.659 +	PT_REGS_UNWIND_INFO(0)
   8.660 +	cmp.ge p6,p7=r8,r0			// syscall executed successfully?
   8.661 +	adds r2=PT(R8)+16,sp			// r2 = &pt_regs.r8
   8.662 +	mov r10=r0				// clear error indication in r10
   8.663 +(p7)	br.cond.spnt handle_syscall_error	// handle potential syscall failure
   8.664 +END(ia64_ret_from_syscall)
   8.665 +	// fall through
   8.666 +/*
   8.667 + * ia64_leave_syscall(): Same as ia64_leave_kernel, except that it doesn't
   8.668 + *	need to switch to bank 0 and doesn't restore the scratch registers.
   8.669 + *	To avoid leaking kernel bits, the scratch registers are set to
   8.670 + *	the following known-to-be-safe values:
   8.671 + *
   8.672 + *		  r1: restored (global pointer)
   8.673 + *		  r2: cleared
   8.674 + *		  r3: 1 (when returning to user-level)
   8.675 + *	      r8-r11: restored (syscall return value(s))
   8.676 + *		 r12: restored (user-level stack pointer)
   8.677 + *		 r13: restored (user-level thread pointer)
   8.678 + *		 r14: cleared
   8.679 + *		 r15: restored (syscall #)
   8.680 + *	     r16-r17: cleared
   8.681 + *		 r18: user-level b6
   8.682 + *		 r19: cleared
   8.683 + *		 r20: user-level ar.fpsr
   8.684 + *		 r21: user-level b0
   8.685 + *		 r22: cleared
   8.686 + *		 r23: user-level ar.bspstore
   8.687 + *		 r24: user-level ar.rnat
   8.688 + *		 r25: user-level ar.unat
   8.689 + *		 r26: user-level ar.pfs
   8.690 + *		 r27: user-level ar.rsc
   8.691 + *		 r28: user-level ip
   8.692 + *		 r29: user-level psr
   8.693 + *		 r30: user-level cfm
   8.694 + *		 r31: user-level pr
   8.695 + *	      f6-f11: cleared
   8.696 + *		  pr: restored (user-level pr)
   8.697 + *		  b0: restored (user-level rp)
   8.698 + *	          b6: restored
   8.699 + *		  b7: cleared
   8.700 + *	     ar.unat: restored (user-level ar.unat)
   8.701 + *	      ar.pfs: restored (user-level ar.pfs)
   8.702 + *	      ar.rsc: restored (user-level ar.rsc)
   8.703 + *	     ar.rnat: restored (user-level ar.rnat)
   8.704 + *	 ar.bspstore: restored (user-level ar.bspstore)
   8.705 + *	     ar.fpsr: restored (user-level ar.fpsr)
   8.706 + *	      ar.ccv: cleared
   8.707 + *	      ar.csd: cleared
   8.708 + *	      ar.ssd: cleared
   8.709 + */
   8.710 +ENTRY(ia64_leave_syscall)
   8.711 +	PT_REGS_UNWIND_INFO(0)
   8.712 +	/*
   8.713 +	 * work.need_resched etc. mustn't get changed by this CPU before it returns to
   8.714 +	 * user- or fsys-mode, hence we disable interrupts early on.
   8.715 +	 *
   8.716 +	 * p6 controls whether current_thread_info()->flags needs to be check for
   8.717 +	 * extra work.  We always check for extra work when returning to user-level.
   8.718 +	 * With CONFIG_PREEMPT, we also check for extra work when the preempt_count
   8.719 +	 * is 0.  After extra work processing has been completed, execution
   8.720 +	 * resumes at .work_processed_syscall with p6 set to 1 if the extra-work-check
   8.721 +	 * needs to be redone.
   8.722 +	 */
   8.723 +#ifdef CONFIG_PREEMPT
   8.724 +	rsm psr.i				// disable interrupts
   8.725 +	cmp.eq pLvSys,p0=r0,r0			// pLvSys=1: leave from syscall
   8.726 +(pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
   8.727 +	;;
   8.728 +	.pred.rel.mutex pUStk,pKStk
   8.729 +(pKStk) ld4 r21=[r20]			// r21 <- preempt_count
   8.730 +(pUStk)	mov r21=0			// r21 <- 0
   8.731 +	;;
   8.732 +	cmp.eq p6,p0=r21,r0		// p6 <- pUStk || (preempt_count == 0)
   8.733 +#else /* !CONFIG_PREEMPT */
   8.734 +(pUStk)	rsm psr.i
   8.735 +	cmp.eq pLvSys,p0=r0,r0		// pLvSys=1: leave from syscall
   8.736 +(pUStk)	cmp.eq.unc p6,p0=r0,r0		// p6 <- pUStk
   8.737 +#endif
   8.738 +.work_processed_syscall:
   8.739 +	adds r2=PT(LOADRS)+16,r12
   8.740 +	adds r3=PT(AR_BSPSTORE)+16,r12
   8.741 +#ifdef XEN
   8.742 +	;;
   8.743 +#else
   8.744 +	adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
   8.745 +	;;
   8.746 +(p6)	ld4 r31=[r18]				// load current_thread_info()->flags
   8.747 +#endif
   8.748 +	ld8 r19=[r2],PT(B6)-PT(LOADRS)		// load ar.rsc value for "loadrs"
   8.749 +	mov b7=r0		// clear b7
   8.750 +	;;
   8.751 +	ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE)	// load ar.bspstore (may be garbage)
   8.752 +	ld8 r18=[r2],PT(R9)-PT(B6)		// load b6
   8.753 +#ifndef XEN
   8.754 +(p6)	and r15=TIF_WORK_MASK,r31		// any work other than TIF_SYSCALL_TRACE?
   8.755 +#endif
   8.756 +	;;
   8.757 +	mov r16=ar.bsp				// M2  get existing backing store pointer
   8.758 +#ifndef XEN
   8.759 +(p6)	cmp4.ne.unc p6,p0=r15, r0		// any special work pending?
   8.760 +(p6)	br.cond.spnt .work_pending_syscall
   8.761 +#endif
   8.762 +	;;
   8.763 +	// start restoring the state saved on the kernel stack (struct pt_regs):
   8.764 +	ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
   8.765 +	ld8 r11=[r3],PT(CR_IIP)-PT(R11)
   8.766 +	mov f6=f0		// clear f6
   8.767 +	;;
   8.768 +	invala			// M0|1 invalidate ALAT
   8.769 +	rsm psr.i | psr.ic	// M2 initiate turning off of interrupt and interruption collection
   8.770 +	mov f9=f0		// clear f9
   8.771 +
   8.772 +	ld8 r29=[r2],16		// load cr.ipsr
   8.773 +	ld8 r28=[r3],16			// load cr.iip
   8.774 +	mov f8=f0		// clear f8
   8.775 +	;;
   8.776 +	ld8 r30=[r2],16		// M0|1 load cr.ifs
   8.777 +	mov.m ar.ssd=r0		// M2 clear ar.ssd
   8.778 +	cmp.eq p9,p0=r0,r0	// set p9 to indicate that we should restore cr.ifs
   8.779 +	;;
   8.780 +	ld8 r25=[r3],16		// M0|1 load ar.unat
   8.781 +	mov.m ar.csd=r0		// M2 clear ar.csd
   8.782 +	mov r22=r0		// clear r22
   8.783 +	;;
   8.784 +	ld8 r26=[r2],PT(B0)-PT(AR_PFS)	// M0|1 load ar.pfs
   8.785 +(pKStk)	mov r22=psr		// M2 read PSR now that interrupts are disabled
   8.786 +	mov f10=f0		// clear f10
   8.787 +	;;
   8.788 +	ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // load b0
   8.789 +	ld8 r27=[r3],PT(PR)-PT(AR_RSC)	// load ar.rsc
   8.790 +	mov f11=f0		// clear f11
   8.791 +	;;
   8.792 +	ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT)	// load ar.rnat (may be garbage)
   8.793 +	ld8 r31=[r3],PT(R1)-PT(PR)		// load predicates
   8.794 +(pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
   8.795 +	;;
   8.796 +	ld8 r20=[r2],PT(R12)-PT(AR_FPSR)	// load ar.fpsr
   8.797 +	ld8.fill r1=[r3],16	// load r1
   8.798 +(pUStk) mov r17=1
   8.799 +	;;
   8.800 +	srlz.d			// M0  ensure interruption collection is off
   8.801 +	ld8.fill r13=[r3],16
   8.802 +	mov f7=f0		// clear f7
   8.803 +	;;
   8.804 +	ld8.fill r12=[r2]	// restore r12 (sp)
   8.805 +	ld8.fill r15=[r3]	// restore r15
   8.806 +#ifdef XEN
   8.807 +	movl r3=THIS_CPU(ia64_phys_stacked_size_p8)
   8.808 +#else
   8.809 +	addl r3=THIS_CPU(ia64_phys_stacked_size_p8),r0
   8.810 +#endif
   8.811 +	;;
   8.812 +(pUStk)	ld4 r3=[r3]		// r3 = cpu_data->phys_stacked_size_p8
   8.813 +(pUStk) st1 [r14]=r17
   8.814 +	mov b6=r18		// I0  restore b6
   8.815 +	;;
   8.816 +	mov r14=r0		// clear r14
   8.817 +	shr.u r18=r19,16	// I0|1 get byte size of existing "dirty" partition
   8.818 +(pKStk) br.cond.dpnt.many skip_rbs_switch
   8.819 +
   8.820 +	mov.m ar.ccv=r0		// clear ar.ccv
   8.821 +(pNonSys) br.cond.dpnt.many dont_preserve_current_frame
   8.822 +	br.cond.sptk.many rbs_switch
   8.823 +END(ia64_leave_syscall)
   8.824 +
   8.825 +#ifdef CONFIG_IA32_SUPPORT
   8.826 +GLOBAL_ENTRY(ia64_ret_from_ia32_execve)
   8.827 +	PT_REGS_UNWIND_INFO(0)
   8.828 +	adds r2=PT(R8)+16,sp			// r2 = &pt_regs.r8
   8.829 +	adds r3=PT(R10)+16,sp			// r3 = &pt_regs.r10
   8.830 +	;;
   8.831 +	.mem.offset 0,0
   8.832 +	st8.spill [r2]=r8	// store return value in slot for r8 and set unat bit
   8.833 +	.mem.offset 8,0
   8.834 +	st8.spill [r3]=r0	// clear error indication in slot for r10 and set unat bit
   8.835 +END(ia64_ret_from_ia32_execve_syscall)
   8.836 +	// fall through
   8.837 +#endif /* CONFIG_IA32_SUPPORT */
   8.838 +GLOBAL_ENTRY(ia64_leave_kernel)
   8.839 +	PT_REGS_UNWIND_INFO(0)
   8.840 +	/*
   8.841 +	 * work.need_resched etc. mustn't get changed by this CPU before it returns to
   8.842 +	 * user- or fsys-mode, hence we disable interrupts early on.
   8.843 +	 *
   8.844 +	 * p6 controls whether current_thread_info()->flags needs to be check for
   8.845 +	 * extra work.  We always check for extra work when returning to user-level.
   8.846 +	 * With CONFIG_PREEMPT, we also check for extra work when the preempt_count
   8.847 +	 * is 0.  After extra work processing has been completed, execution
   8.848 +	 * resumes at .work_processed_syscall with p6 set to 1 if the extra-work-check
   8.849 +	 * needs to be redone.
   8.850 +	 */
   8.851 +#ifdef CONFIG_PREEMPT
   8.852 +	rsm psr.i				// disable interrupts
   8.853 +	cmp.eq p0,pLvSys=r0,r0			// pLvSys=0: leave from kernel
   8.854 +(pKStk)	adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
   8.855 +	;;
   8.856 +	.pred.rel.mutex pUStk,pKStk
   8.857 +(pKStk)	ld4 r21=[r20]			// r21 <- preempt_count
   8.858 +(pUStk)	mov r21=0			// r21 <- 0
   8.859 +	;;
   8.860 +	cmp.eq p6,p0=r21,r0		// p6 <- pUStk || (preempt_count == 0)
   8.861 +#else
   8.862 +(pUStk)	rsm psr.i
   8.863 +	cmp.eq p0,pLvSys=r0,r0		// pLvSys=0: leave from kernel
   8.864 +(pUStk)	cmp.eq.unc p6,p0=r0,r0		// p6 <- pUStk
   8.865 +#endif
   8.866 +.work_processed_kernel:
   8.867 +#ifdef XEN
   8.868 +	alloc loc0=ar.pfs,0,1,1,0
   8.869 +	adds out0=16,r12
   8.870 +	;;
   8.871 +(p6)	br.call.sptk.many b0=deliver_pending_interrupt
   8.872 +	mov ar.pfs=loc0
   8.873 +	mov r31=r0
   8.874 +#else
   8.875 +	adds r17=TI_FLAGS+IA64_TASK_SIZE,r13
   8.876 +	;;
   8.877 +(p6)	ld4 r31=[r17]				// load current_thread_info()->flags
   8.878 +#endif
   8.879 +	adds r21=PT(PR)+16,r12
   8.880 +	;;
   8.881 +
   8.882 +	lfetch [r21],PT(CR_IPSR)-PT(PR)
   8.883 +	adds r2=PT(B6)+16,r12
   8.884 +	adds r3=PT(R16)+16,r12
   8.885 +	;;
   8.886 +	lfetch [r21]
   8.887 +	ld8 r28=[r2],8		// load b6
   8.888 +	adds r29=PT(R24)+16,r12
   8.889 +
   8.890 +	ld8.fill r16=[r3]
   8.891 +	adds r30=PT(AR_CCV)+16,r12
   8.892 +(p6)	and r19=TIF_WORK_MASK,r31		// any work other than TIF_SYSCALL_TRACE?
   8.893 +	;;
   8.894 +	adds r3=PT(AR_CSD)-PT(R16),r3
   8.895 +	ld8.fill r24=[r29]
   8.896 +	ld8 r15=[r30]		// load ar.ccv
   8.897 +(p6)	cmp4.ne.unc p6,p0=r19, r0		// any special work pending?
   8.898 +	;;
   8.899 +	ld8 r29=[r2],16		// load b7
   8.900 +	ld8 r30=[r3],16		// load ar.csd
   8.901 +#ifndef XEN
   8.902 +(p6)	br.cond.spnt .work_pending
   8.903 +#endif
   8.904 +	;;
   8.905 +	ld8 r31=[r2],16		// load ar.ssd
   8.906 +	ld8.fill r8=[r3],16
   8.907 +	;;
   8.908 +	ld8.fill r9=[r2],16
   8.909 +	ld8.fill r10=[r3],PT(R17)-PT(R10)
   8.910 +	;;
   8.911 +	ld8.fill r11=[r2],PT(R18)-PT(R11)
   8.912 +	ld8.fill r17=[r3],16
   8.913 +	;;
   8.914 +	ld8.fill r18=[r2],16
   8.915 +	ld8.fill r19=[r3],16
   8.916 +	;;
   8.917 +	ld8.fill r20=[r2],16
   8.918 +	ld8.fill r21=[r3],16
   8.919 +	mov ar.csd=r30
   8.920 +	mov ar.ssd=r31
   8.921 +	;;
   8.922 +	rsm psr.i | psr.ic	// initiate turning off of interrupt and interruption collection
   8.923 +	invala			// invalidate ALAT
   8.924 +	;;
   8.925 +	ld8.fill r22=[r2],24
   8.926 +	ld8.fill r23=[r3],24
   8.927 +	mov b6=r28
   8.928 +	;;
   8.929 +	ld8.fill r25=[r2],16
   8.930 +	ld8.fill r26=[r3],16
   8.931 +	mov b7=r29
   8.932 +	;;
   8.933 +	ld8.fill r27=[r2],16
   8.934 +	ld8.fill r28=[r3],16
   8.935 +	;;
   8.936 +	ld8.fill r29=[r2],16
   8.937 +	ld8.fill r30=[r3],24
   8.938 +	;;
   8.939 +	ld8.fill r31=[r2],PT(F9)-PT(R31)
   8.940 +	adds r3=PT(F10)-PT(F6),r3
   8.941 +	;;
   8.942 +	ldf.fill f9=[r2],PT(F6)-PT(F9)
   8.943 +	ldf.fill f10=[r3],PT(F8)-PT(F10)
   8.944 +	;;
   8.945 +	ldf.fill f6=[r2],PT(F7)-PT(F6)
   8.946 +	;;
   8.947 +	ldf.fill f7=[r2],PT(F11)-PT(F7)
   8.948 +	ldf.fill f8=[r3],32
   8.949 +	;;
   8.950 +	srlz.i			// ensure interruption collection is off
   8.951 +	mov ar.ccv=r15
   8.952 +	;;
   8.953 +	ldf.fill f11=[r2]
   8.954 +	bsw.0			// switch back to bank 0 (no stop bit required beforehand...)
   8.955 +	;;
   8.956 +(pUStk) movl r18=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
   8.957 +(pUStk) ld8 r18=[r18]
   8.958 +	adds r16=PT(CR_IPSR)+16,r12
   8.959 +	adds r17=PT(CR_IIP)+16,r12
   8.960 +
   8.961 +(pKStk)	mov r22=psr		// M2 read PSR now that interrupts are disabled
   8.962 +	nop.i 0
   8.963 +	nop.i 0
   8.964 +	;;
   8.965 +	ld8 r29=[r16],16	// load cr.ipsr
   8.966 +	ld8 r28=[r17],16	// load cr.iip
   8.967 +	;;
   8.968 +	ld8 r30=[r16],16	// load cr.ifs
   8.969 +	ld8 r25=[r17],16	// load ar.unat
   8.970 +	;;
   8.971 +	ld8 r26=[r16],16	// load ar.pfs
   8.972 +	ld8 r27=[r17],16	// load ar.rsc
   8.973 +	cmp.eq p9,p0=r0,r0	// set p9 to indicate that we should restore cr.ifs
   8.974 +	;;
   8.975 +	ld8 r24=[r16],16	// load ar.rnat (may be garbage)
   8.976 +	ld8 r23=[r17],16	// load ar.bspstore (may be garbage)
   8.977 +	;;
   8.978 +	ld8 r31=[r16],16	// load predicates
   8.979 +	ld8 r21=[r17],16	// load b0
   8.980 +	;;
   8.981 +	ld8 r19=[r16],16	// load ar.rsc value for "loadrs"
   8.982 +	ld8.fill r1=[r17],16	// load r1
   8.983 +	;;
   8.984 +	ld8.fill r12=[r16],16
   8.985 +	ld8.fill r13=[r17],16
   8.986 +(pUStk)	adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18
   8.987 +	;;
   8.988 +	ld8 r20=[r16],16	// ar.fpsr
   8.989 +	ld8.fill r15=[r17],16
   8.990 +	;;
   8.991 +	ld8.fill r14=[r16],16
   8.992 +	ld8.fill r2=[r17]
   8.993 +(pUStk)	mov r17=1
   8.994 +	;;
   8.995 +	ld8.fill r3=[r16]
   8.996 +(pUStk)	st1 [r18]=r17		// restore current->thread.on_ustack
   8.997 +	shr.u r18=r19,16	// get byte size of existing "dirty" partition
   8.998 +	;;
   8.999 +	mov r16=ar.bsp		// get existing backing store pointer
  8.1000 +#ifdef XEN
  8.1001 +	movl r17=THIS_CPU(ia64_phys_stacked_size_p8)
  8.1002 +#else
  8.1003 +	addl r17=THIS_CPU(ia64_phys_stacked_size_p8),r0
  8.1004 +#endif
  8.1005 +	;;
  8.1006 +	ld4 r17=[r17]		// r17 = cpu_data->phys_stacked_size_p8
  8.1007 +(pKStk)	br.cond.dpnt skip_rbs_switch
  8.1008 +
  8.1009 +	/*
  8.1010 +	 * Restore user backing store.
  8.1011 +	 *
  8.1012 +	 * NOTE: alloc, loadrs, and cover can't be predicated.
  8.1013 +	 */
  8.1014 +(pNonSys) br.cond.dpnt dont_preserve_current_frame
  8.1015 +
  8.1016 +rbs_switch:
  8.1017 +	cover				// add current frame into dirty partition and set cr.ifs
  8.1018 +	;;
  8.1019 +	mov r19=ar.bsp			// get new backing store pointer
  8.1020 +	sub r16=r16,r18			// krbs = old bsp - size of dirty partition
  8.1021 +	cmp.ne p9,p0=r0,r0		// clear p9 to skip restore of cr.ifs
  8.1022 +	;;
  8.1023 +	sub r19=r19,r16			// calculate total byte size of dirty partition
  8.1024 +	add r18=64,r18			// don't force in0-in7 into memory...
  8.1025 +	;;
  8.1026 +	shl r19=r19,16			// shift size of dirty partition into loadrs position
  8.1027 +	;;
  8.1028 +dont_preserve_current_frame:
  8.1029 +	/*
  8.1030 +	 * To prevent leaking bits between the kernel and user-space,
  8.1031 +	 * we must clear the stacked registers in the "invalid" partition here.
  8.1032 +	 * Not pretty, but at least it's fast (3.34 registers/cycle on Itanium,
  8.1033 +	 * 5 registers/cycle on McKinley).
  8.1034 +	 */
  8.1035 +#	define pRecurse	p6
  8.1036 +#	define pReturn	p7
  8.1037 +#ifdef CONFIG_ITANIUM
  8.1038 +#	define Nregs	10
  8.1039 +#else
  8.1040 +#	define Nregs	14
  8.1041 +#endif
  8.1042 +	alloc loc0=ar.pfs,2,Nregs-2,2,0
  8.1043 +	shr.u loc1=r18,9		// RNaTslots <= floor(dirtySize / (64*8))
  8.1044 +	sub r17=r17,r18			// r17 = (physStackedSize + 8) - dirtySize
  8.1045 +	;;
  8.1046 +	mov ar.rsc=r19			// load ar.rsc to be used for "loadrs"
  8.1047 +	shladd in0=loc1,3,r17
  8.1048 +	mov in1=0
  8.1049 +	;;
  8.1050 +	TEXT_ALIGN(32)
  8.1051 +rse_clear_invalid:
  8.1052 +#ifdef CONFIG_ITANIUM
  8.1053 +	// cycle 0
  8.1054 + { .mii
  8.1055 +	alloc loc0=ar.pfs,2,Nregs-2,2,0
  8.1056 +	cmp.lt pRecurse,p0=Nregs*8,in0	// if more than Nregs regs left to clear, (re)curse
  8.1057 +	add out0=-Nregs*8,in0
  8.1058 +}{ .mfb
  8.1059 +	add out1=1,in1			// increment recursion count
  8.1060 +	nop.f 0
  8.1061 +	nop.b 0				// can't do br.call here because of alloc (WAW on CFM)
  8.1062 +	;;
  8.1063 +}{ .mfi	// cycle 1
  8.1064 +	mov loc1=0
  8.1065 +	nop.f 0
  8.1066 +	mov loc2=0
  8.1067 +}{ .mib
  8.1068 +	mov loc3=0
  8.1069 +	mov loc4=0
  8.1070 +(pRecurse) br.call.sptk.many b0=rse_clear_invalid
  8.1071 +
  8.1072 +}{ .mfi	// cycle 2
  8.1073 +	mov loc5=0
  8.1074 +	nop.f 0
  8.1075 +	cmp.ne pReturn,p0=r0,in1	// if recursion count != 0, we need to do a br.ret
  8.1076 +}{ .mib
  8.1077 +	mov loc6=0
  8.1078 +	mov loc7=0
  8.1079 +(pReturn) br.ret.sptk.many b0
  8.1080 +}
  8.1081 +#else /* !CONFIG_ITANIUM */
  8.1082 +	alloc loc0=ar.pfs,2,Nregs-2,2,0
  8.1083 +	cmp.lt pRecurse,p0=Nregs*8,in0	// if more than Nregs regs left to clear, (re)curse
  8.1084 +	add out0=-Nregs*8,in0
  8.1085 +	add out1=1,in1			// increment recursion count
  8.1086 +	mov loc1=0
  8.1087 +	mov loc2=0
  8.1088 +	;;
  8.1089 +	mov loc3=0
  8.1090 +	mov loc4=0
  8.1091 +	mov loc5=0
  8.1092 +	mov loc6=0
  8.1093 +	mov loc7=0
  8.1094 +(pRecurse) br.call.sptk.few b0=rse_clear_invalid
  8.1095 +	;;
  8.1096 +	mov loc8=0
  8.1097 +	mov loc9=0
  8.1098 +	cmp.ne pReturn,p0=r0,in1	// if recursion count != 0, we need to do a br.ret
  8.1099 +	mov loc10=0
  8.1100 +	mov loc11=0
  8.1101 +(pReturn) br.ret.sptk.many b0
  8.1102 +#endif /* !CONFIG_ITANIUM */
  8.1103 +#	undef pRecurse
  8.1104 +#	undef pReturn
  8.1105 +	;;
  8.1106 +	alloc r17=ar.pfs,0,0,0,0	// drop current register frame
  8.1107 +	;;
  8.1108 +	loadrs
  8.1109 +	;;
  8.1110 +skip_rbs_switch:
  8.1111 +	mov ar.unat=r25		// M2
  8.1112 +(pKStk)	extr.u r22=r22,21,1	// I0 extract current value of psr.pp from r22
  8.1113 +(pLvSys)mov r19=r0		// A  clear r19 for leave_syscall, no-op otherwise
  8.1114 +	;;
  8.1115 +(pUStk)	mov ar.bspstore=r23	// M2
  8.1116 +(pKStk)	dep r29=r22,r29,21,1	// I0 update ipsr.pp with psr.pp
  8.1117 +(pLvSys)mov r16=r0		// A  clear r16 for leave_syscall, no-op otherwise
  8.1118 +	;;
  8.1119 +	mov cr.ipsr=r29		// M2
  8.1120 +	mov ar.pfs=r26		// I0
  8.1121 +(pLvSys)mov r17=r0		// A  clear r17 for leave_syscall, no-op otherwise
  8.1122 +
  8.1123 +(p9)	mov cr.ifs=r30		// M2
  8.1124 +	mov b0=r21		// I0
  8.1125 +(pLvSys)mov r18=r0		// A  clear r18 for leave_syscall, no-op otherwise
  8.1126 +
  8.1127 +	mov ar.fpsr=r20		// M2
  8.1128 +	mov cr.iip=r28		// M2
  8.1129 +	nop 0
  8.1130 +	;;
  8.1131 +(pUStk)	mov ar.rnat=r24		// M2 must happen with RSE in lazy mode
  8.1132 +	nop 0
  8.1133 +(pLvSys)mov r2=r0
  8.1134 +
  8.1135 +	mov ar.rsc=r27		// M2
  8.1136 +	mov pr=r31,-1		// I0
  8.1137 +	rfi			// B
  8.1138 +
  8.1139 +#ifndef XEN
  8.1140 +	/*
  8.1141 +	 * On entry:
  8.1142 +	 *	r20 = &current->thread_info->pre_count (if CONFIG_PREEMPT)
  8.1143 +	 *	r31 = current->thread_info->flags
  8.1144 +	 * On exit:
  8.1145 +	 *	p6 = TRUE if work-pending-check needs to be redone
  8.1146 +	 */
  8.1147 +.work_pending_syscall:
  8.1148 +	add r2=-8,r2
  8.1149 +	add r3=-8,r3
  8.1150 +	;;
  8.1151 +	st8 [r2]=r8
  8.1152 +	st8 [r3]=r10
  8.1153 +.work_pending:
  8.1154 +	tbit.nz p6,p0=r31,TIF_SIGDELAYED		// signal delayed from  MCA/INIT/NMI/PMI context?
  8.1155 +(p6)	br.cond.sptk.few .sigdelayed
  8.1156 +	;;
  8.1157 +	tbit.z p6,p0=r31,TIF_NEED_RESCHED		// current_thread_info()->need_resched==0?
  8.1158 +(p6)	br.cond.sptk.few .notify
  8.1159 +#ifdef CONFIG_PREEMPT
  8.1160 +(pKStk) dep r21=-1,r0,PREEMPT_ACTIVE_BIT,1
  8.1161 +	;;
  8.1162 +(pKStk) st4 [r20]=r21
  8.1163 +	ssm psr.i		// enable interrupts
  8.1164 +#endif
  8.1165 +	br.call.spnt.many rp=schedule
  8.1166 +.ret9:	cmp.eq p6,p0=r0,r0				// p6 <- 1
  8.1167 +	rsm psr.i		// disable interrupts
  8.1168 +	;;
  8.1169 +#ifdef CONFIG_PREEMPT
  8.1170 +(pKStk)	adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
  8.1171 +	;;
  8.1172 +(pKStk)	st4 [r20]=r0		// preempt_count() <- 0
  8.1173 +#endif
  8.1174 +(pLvSys)br.cond.sptk.few  .work_pending_syscall_end
  8.1175 +	br.cond.sptk.many .work_processed_kernel	// re-check
  8.1176 +
  8.1177 +.notify:
  8.1178 +(pUStk)	br.call.spnt.many rp=notify_resume_user
  8.1179 +.ret10:	cmp.ne p6,p0=r0,r0				// p6 <- 0
  8.1180 +(pLvSys)br.cond.sptk.few  .work_pending_syscall_end
  8.1181 +	br.cond.sptk.many .work_processed_kernel	// don't re-check
  8.1182 +
  8.1183 +// There is a delayed signal that was detected in MCA/INIT/NMI/PMI context where
  8.1184 +// it could not be delivered.  Deliver it now.  The signal might be for us and
  8.1185 +// may set TIF_SIGPENDING, so redrive ia64_leave_* after processing the delayed
  8.1186 +// signal.
  8.1187 +
  8.1188 +.sigdelayed:
  8.1189 +	br.call.sptk.many rp=do_sigdelayed
  8.1190 +	cmp.eq p6,p0=r0,r0				// p6 <- 1, always re-check
  8.1191 +(pLvSys)br.cond.sptk.few  .work_pending_syscall_end
  8.1192 +	br.cond.sptk.many .work_processed_kernel	// re-check
  8.1193 +
  8.1194 +.work_pending_syscall_end:
  8.1195 +	adds r2=PT(R8)+16,r12
  8.1196 +	adds r3=PT(R10)+16,r12
  8.1197 +	;;
  8.1198 +	ld8 r8=[r2]
  8.1199 +	ld8 r10=[r3]
  8.1200 +	br.cond.sptk.many .work_processed_syscall	// re-check
  8.1201 +#endif
  8.1202 +
  8.1203 +END(ia64_leave_kernel)
  8.1204 +
  8.1205 +ENTRY(handle_syscall_error)
  8.1206 +	/*
  8.1207 +	 * Some system calls (e.g., ptrace, mmap) can return arbitrary values which could
  8.1208 +	 * lead us to mistake a negative return value as a failed syscall.  Those syscall
  8.1209 +	 * must deposit a non-zero value in pt_regs.r8 to indicate an error.  If
  8.1210 +	 * pt_regs.r8 is zero, we assume that the call completed successfully.
  8.1211 +	 */
  8.1212 +	PT_REGS_UNWIND_INFO(0)
  8.1213 +	ld8 r3=[r2]		// load pt_regs.r8
  8.1214 +	;;
  8.1215 +	cmp.eq p6,p7=r3,r0	// is pt_regs.r8==0?
  8.1216 +	;;
  8.1217 +(p7)	mov r10=-1
  8.1218 +(p7)	sub r8=0,r8		// negate return value to get errno
  8.1219 +	br.cond.sptk ia64_leave_syscall
  8.1220 +END(handle_syscall_error)
  8.1221 +
  8.1222 +	/*
  8.1223 +	 * Invoke schedule_tail(task) while preserving in0-in7, which may be needed
  8.1224 +	 * in case a system call gets restarted.
  8.1225 +	 */
  8.1226 +GLOBAL_ENTRY(ia64_invoke_schedule_tail)
  8.1227 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
  8.1228 +	alloc loc1=ar.pfs,8,2,1,0
  8.1229 +	mov loc0=rp
  8.1230 +	mov out0=r8				// Address of previous task
  8.1231 +	;;
  8.1232 +	br.call.sptk.many rp=schedule_tail
  8.1233 +.ret11:	mov ar.pfs=loc1
  8.1234 +	mov rp=loc0
  8.1235 +	br.ret.sptk.many rp
  8.1236 +END(ia64_invoke_schedule_tail)
  8.1237 +
  8.1238 +#ifndef XEN
  8.1239 +	/*
  8.1240 +	 * Setup stack and call do_notify_resume_user().  Note that pSys and pNonSys need to
  8.1241 +	 * be set up by the caller.  We declare 8 input registers so the system call
  8.1242 +	 * args get preserved, in case we need to restart a system call.
  8.1243 +	 */
  8.1244 +ENTRY(notify_resume_user)
  8.1245 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
  8.1246 +	alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart!
  8.1247 +	mov r9=ar.unat
  8.1248 +	mov loc0=rp				// save return address
  8.1249 +	mov out0=0				// there is no "oldset"
  8.1250 +	adds out1=8,sp				// out1=&sigscratch->ar_pfs
  8.1251 +(pSys)	mov out2=1				// out2==1 => we're in a syscall
  8.1252 +	;;
  8.1253 +(pNonSys) mov out2=0				// out2==0 => not a syscall
  8.1254 +	.fframe 16
  8.1255 +	.spillpsp ar.unat, 16			// (note that offset is relative to psp+0x10!)
  8.1256 +	st8 [sp]=r9,-16				// allocate space for ar.unat and save it
  8.1257 +	st8 [out1]=loc1,-8			// save ar.pfs, out1=&sigscratch
  8.1258 +	.body
  8.1259 +	br.call.sptk.many rp=do_notify_resume_user
  8.1260 +.ret15:	.restore sp
  8.1261 +	adds sp=16,sp				// pop scratch stack space
  8.1262 +	;;
  8.1263 +	ld8 r9=[sp]				// load new unat from sigscratch->scratch_unat
  8.1264 +	mov rp=loc0
  8.1265 +	;;
  8.1266 +	mov ar.unat=r9
  8.1267 +	mov ar.pfs=loc1
  8.1268 +	br.ret.sptk.many rp
  8.1269 +END(notify_resume_user)
  8.1270 +
  8.1271 +GLOBAL_ENTRY(sys_rt_sigsuspend)
  8.1272 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
  8.1273 +	alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart!
  8.1274 +	mov r9=ar.unat
  8.1275 +	mov loc0=rp				// save return address
  8.1276 +	mov out0=in0				// mask
  8.1277 +	mov out1=in1				// sigsetsize
  8.1278 +	adds out2=8,sp				// out2=&sigscratch->ar_pfs
  8.1279 +	;;
  8.1280 +	.fframe 16
  8.1281 +	.spillpsp ar.unat, 16			// (note that offset is relative to psp+0x10!)
  8.1282 +	st8 [sp]=r9,-16				// allocate space for ar.unat and save it
  8.1283 +	st8 [out2]=loc1,-8			// save ar.pfs, out2=&sigscratch
  8.1284 +	.body
  8.1285 +	br.call.sptk.many rp=ia64_rt_sigsuspend
  8.1286 +.ret17:	.restore sp
  8.1287 +	adds sp=16,sp				// pop scratch stack space
  8.1288 +	;;
  8.1289 +	ld8 r9=[sp]				// load new unat from sw->caller_unat
  8.1290 +	mov rp=loc0
  8.1291 +	;;
  8.1292 +	mov ar.unat=r9
  8.1293 +	mov ar.pfs=loc1
  8.1294 +	br.ret.sptk.many rp
  8.1295 +END(sys_rt_sigsuspend)
  8.1296 +
  8.1297 +ENTRY(sys_rt_sigreturn)
  8.1298 +	PT_REGS_UNWIND_INFO(0)
  8.1299 +	/*
  8.1300 +	 * Allocate 8 input registers since ptrace() may clobber them
  8.1301 +	 */
  8.1302 +	alloc r2=ar.pfs,8,0,1,0
  8.1303 +	.prologue
  8.1304 +	PT_REGS_SAVES(16)
  8.1305 +	adds sp=-16,sp
  8.1306 +	.body
  8.1307 +	cmp.eq pNonSys,pSys=r0,r0		// sigreturn isn't a normal syscall...
  8.1308 +	;;
  8.1309 +	/*
  8.1310 +	 * leave_kernel() restores f6-f11 from pt_regs, but since the streamlined
  8.1311 +	 * syscall-entry path does not save them we save them here instead.  Note: we
  8.1312 +	 * don't need to save any other registers that are not saved by the stream-lined
  8.1313 +	 * syscall path, because restore_sigcontext() restores them.
  8.1314 +	 */
  8.1315 +	adds r16=PT(F6)+32,sp
  8.1316 +	adds r17=PT(F7)+32,sp
  8.1317 +	;;
  8.1318 + 	stf.spill [r16]=f6,32
  8.1319 + 	stf.spill [r17]=f7,32
  8.1320 +	;;
  8.1321 + 	stf.spill [r16]=f8,32
  8.1322 + 	stf.spill [r17]=f9,32
  8.1323 +	;;
  8.1324 + 	stf.spill [r16]=f10
  8.1325 + 	stf.spill [r17]=f11
  8.1326 +	adds out0=16,sp				// out0 = &sigscratch
  8.1327 +	br.call.sptk.many rp=ia64_rt_sigreturn
  8.1328 +.ret19:	.restore sp 0
  8.1329 +	adds sp=16,sp
  8.1330 +	;;
  8.1331 +	ld8 r9=[sp]				// load new ar.unat
  8.1332 +	mov.sptk b7=r8,ia64_leave_kernel
  8.1333 +	;;
  8.1334 +	mov ar.unat=r9
  8.1335 +	br.many b7
  8.1336 +END(sys_rt_sigreturn)
  8.1337 +#endif
  8.1338 +
  8.1339 +GLOBAL_ENTRY(ia64_prepare_handle_unaligned)
  8.1340 +	.prologue
  8.1341 +	/*
  8.1342 +	 * r16 = fake ar.pfs, we simply need to make sure privilege is still 0
  8.1343 +	 */
  8.1344 +	mov r16=r0
  8.1345 +	DO_SAVE_SWITCH_STACK
  8.1346 +	br.call.sptk.many rp=ia64_handle_unaligned	// stack frame setup in ivt
  8.1347 +.ret21:	.body
  8.1348 +	DO_LOAD_SWITCH_STACK
  8.1349 +	br.cond.sptk.many rp				// goes to ia64_leave_kernel
  8.1350 +END(ia64_prepare_handle_unaligned)
  8.1351 +
  8.1352 +#ifndef XEN
  8.1353 +	//
  8.1354 +	// unw_init_running(void (*callback)(info, arg), void *arg)
  8.1355 +	//
  8.1356 +#	define EXTRA_FRAME_SIZE	((UNW_FRAME_INFO_SIZE+15)&~15)
  8.1357 +
  8.1358 +GLOBAL_ENTRY(unw_init_running)
  8.1359 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
  8.1360 +	alloc loc1=ar.pfs,2,3,3,0
  8.1361 +	;;
  8.1362 +	ld8 loc2=[in0],8
  8.1363 +	mov loc0=rp
  8.1364 +	mov r16=loc1
  8.1365 +	DO_SAVE_SWITCH_STACK
  8.1366 +	.body
  8.1367 +
  8.1368 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
  8.1369 +	.fframe IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE
  8.1370 +	SWITCH_STACK_SAVES(EXTRA_FRAME_SIZE)
  8.1371 +	adds sp=-EXTRA_FRAME_SIZE,sp
  8.1372 +	.body
  8.1373 +	;;
  8.1374 +	adds out0=16,sp				// &info
  8.1375 +	mov out1=r13				// current
  8.1376 +	adds out2=16+EXTRA_FRAME_SIZE,sp	// &switch_stack
  8.1377 +	br.call.sptk.many rp=unw_init_frame_info
  8.1378 +1:	adds out0=16,sp				// &info
  8.1379 +	mov b6=loc2
  8.1380 +	mov loc2=gp				// save gp across indirect function call
  8.1381 +	;;
  8.1382 +	ld8 gp=[in0]
  8.1383 +	mov out1=in1				// arg
  8.1384 +	br.call.sptk.many rp=b6			// invoke the callback function
  8.1385 +1:	mov gp=loc2				// restore gp
  8.1386 +
  8.1387 +	// For now, we don't allow changing registers from within
  8.1388 +	// unw_init_running; if we ever want to allow that, we'd
  8.1389 +	// have to do a load_switch_stack here:
  8.1390 +	.restore sp
  8.1391 +	adds sp=IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE,sp
  8.1392 +
  8.1393 +	mov ar.pfs=loc1
  8.1394 +	mov rp=loc0
  8.1395 +	br.ret.sptk.many rp
  8.1396 +END(unw_init_running)
  8.1397 +
  8.1398 +	.rodata
  8.1399 +	.align 8
  8.1400 +	.globl sys_call_table
  8.1401 +sys_call_table:
  8.1402 +	data8 sys_ni_syscall		//  This must be sys_ni_syscall!  See ivt.S.
  8.1403 +	data8 sys_exit				// 1025
  8.1404 +	data8 sys_read
  8.1405 +	data8 sys_write
  8.1406 +	data8 sys_open
  8.1407 +	data8 sys_close
  8.1408 +	data8 sys_creat				// 1030
  8.1409 +	data8 sys_link
  8.1410 +	data8 sys_unlink
  8.1411 +	data8 ia64_execve
  8.1412 +	data8 sys_chdir
  8.1413 +	data8 sys_fchdir			// 1035
  8.1414 +	data8 sys_utimes
  8.1415 +	data8 sys_mknod
  8.1416 +	data8 sys_chmod
  8.1417 +	data8 sys_chown
  8.1418 +	data8 sys_lseek				// 1040
  8.1419 +	data8 sys_getpid
  8.1420 +	data8 sys_getppid
  8.1421 +	data8 sys_mount
  8.1422 +	data8 sys_umount
  8.1423 +	data8 sys_setuid			// 1045
  8.1424 +	data8 sys_getuid
  8.1425 +	data8 sys_geteuid
  8.1426 +	data8 sys_ptrace
  8.1427 +	data8 sys_access
  8.1428 +	data8 sys_sync				// 1050
  8.1429 +	data8 sys_fsync
  8.1430 +	data8 sys_fdatasync
  8.1431 +	data8 sys_kill
  8.1432 +	data8 sys_rename
  8.1433 +	data8 sys_mkdir				// 1055
  8.1434 +	data8 sys_rmdir
  8.1435 +	data8 sys_dup
  8.1436 +	data8 sys_pipe
  8.1437 +	data8 sys_times
  8.1438 +	data8 ia64_brk				// 1060
  8.1439 +	data8 sys_setgid
  8.1440 +	data8 sys_getgid
  8.1441 +	data8 sys_getegid
  8.1442 +	data8 sys_acct
  8.1443 +	data8 sys_ioctl				// 1065
  8.1444 +	data8 sys_fcntl
  8.1445 +	data8 sys_umask
  8.1446 +	data8 sys_chroot
  8.1447 +	data8 sys_ustat
  8.1448 +	data8 sys_dup2				// 1070
  8.1449 +	data8 sys_setreuid
  8.1450 +	data8 sys_setregid
  8.1451 +	data8 sys_getresuid
  8.1452 +	data8 sys_setresuid
  8.1453 +	data8 sys_getresgid			// 1075
  8.1454 +	data8 sys_setresgid
  8.1455 +	data8 sys_getgroups
  8.1456 +	data8 sys_setgroups
  8.1457 +	data8 sys_getpgid
  8.1458 +	data8 sys_setpgid			// 1080
  8.1459 +	data8 sys_setsid
  8.1460 +	data8 sys_getsid
  8.1461 +	data8 sys_sethostname
  8.1462 +	data8 sys_setrlimit
  8.1463 +	data8 sys_getrlimit			// 1085
  8.1464 +	data8 sys_getrusage
  8.1465 +	data8 sys_gettimeofday
  8.1466 +	data8 sys_settimeofday
  8.1467 +	data8 sys_select
  8.1468 +	data8 sys_poll				// 1090
  8.1469 +	data8 sys_symlink
  8.1470 +	data8 sys_readlink
  8.1471 +	data8 sys_uselib
  8.1472 +	data8 sys_swapon
  8.1473 +	data8 sys_swapoff			// 1095
  8.1474 +	data8 sys_reboot
  8.1475 +	data8 sys_truncate
  8.1476 +	data8 sys_ftruncate
  8.1477 +	data8 sys_fchmod
  8.1478 +	data8 sys_fchown			// 1100
  8.1479 +	data8 ia64_getpriority
  8.1480 +	data8 sys_setpriority
  8.1481 +	data8 sys_statfs
  8.1482 +	data8 sys_fstatfs
  8.1483 +	data8 sys_gettid			// 1105
  8.1484 +	data8 sys_semget
  8.1485 +	data8 sys_semop
  8.1486 +	data8 sys_semctl
  8.1487 +	data8 sys_msgget
  8.1488 +	data8 sys_msgsnd			// 1110
  8.1489 +	data8 sys_msgrcv
  8.1490 +	data8 sys_msgctl
  8.1491 +	data8 sys_shmget
  8.1492 +	data8 ia64_shmat
  8.1493 +	data8 sys_shmdt				// 1115
  8.1494 +	data8 sys_shmctl
  8.1495 +	data8 sys_syslog
  8.1496 +	data8 sys_setitimer
  8.1497 +	data8 sys_getitimer
  8.1498 +	data8 sys_ni_syscall			// 1120		/* was: ia64_oldstat */
  8.1499 +	data8 sys_ni_syscall					/* was: ia64_oldlstat */
  8.1500 +	data8 sys_ni_syscall					/* was: ia64_oldfstat */
  8.1501 +	data8 sys_vhangup
  8.1502 +	data8 sys_lchown
  8.1503 +	data8 sys_remap_file_pages		// 1125
  8.1504 +	data8 sys_wait4
  8.1505 +	data8 sys_sysinfo
  8.1506 +	data8 sys_clone
  8.1507 +	data8 sys_setdomainname
  8.1508 +	data8 sys_newuname			// 1130
  8.1509 +	data8 sys_adjtimex
  8.1510 +	data8 sys_ni_syscall					/* was: ia64_create_module */
  8.1511 +	data8 sys_init_module
  8.1512 +	data8 sys_delete_module
  8.1513 +	data8 sys_ni_syscall			// 1135		/* was: sys_get_kernel_syms */
  8.1514 +	data8 sys_ni_syscall					/* was: sys_query_module */
  8.1515 +	data8 sys_quotactl
  8.1516 +	data8 sys_bdflush
  8.1517 +	data8 sys_sysfs
  8.1518 +	data8 sys_personality			// 1140
  8.1519 +	data8 sys_ni_syscall		// sys_afs_syscall
  8.1520 +	data8 sys_setfsuid
  8.1521 +	data8 sys_setfsgid
  8.1522 +	data8 sys_getdents
  8.1523 +	data8 sys_flock				// 1145
  8.1524 +	data8 sys_readv
  8.1525 +	data8 sys_writev
  8.1526 +	data8 sys_pread64
  8.1527 +	data8 sys_pwrite64
  8.1528 +	data8 sys_sysctl			// 1150
  8.1529 +	data8 sys_mmap
  8.1530 +	data8 sys_munmap
  8.1531 +	data8 sys_mlock
  8.1532 +	data8 sys_mlockall
  8.1533 +	data8 sys_mprotect			// 1155
  8.1534 +	data8 ia64_mremap
  8.1535 +	data8 sys_msync
  8.1536 +	data8 sys_munlock
  8.1537 +	data8 sys_munlockall
  8.1538 +	data8 sys_sched_getparam		// 1160
  8.1539 +	data8 sys_sched_setparam
  8.1540 +	data8 sys_sched_getscheduler
  8.1541 +	data8 sys_sched_setscheduler
  8.1542 +	data8 sys_sched_yield
  8.1543 +	data8 sys_sched_get_priority_max	// 1165
  8.1544 +	data8 sys_sched_get_priority_min
  8.1545 +	data8 sys_sched_rr_get_interval
  8.1546 +	data8 sys_nanosleep
  8.1547 +	data8 sys_nfsservctl
  8.1548 +	data8 sys_prctl				// 1170
  8.1549 +	data8 sys_getpagesize
  8.1550 +	data8 sys_mmap2
  8.1551 +	data8 sys_pciconfig_read
  8.1552 +	data8 sys_pciconfig_write
  8.1553 +	data8 sys_perfmonctl			// 1175
  8.1554 +	data8 sys_sigaltstack
  8.1555 +	data8 sys_rt_sigaction
  8.1556 +	data8 sys_rt_sigpending
  8.1557 +	data8 sys_rt_sigprocmask
  8.1558 +	data8 sys_rt_sigqueueinfo		// 1180
  8.1559 +	data8 sys_rt_sigreturn
  8.1560 +	data8 sys_rt_sigsuspend
  8.1561 +	data8 sys_rt_sigtimedwait
  8.1562 +	data8 sys_getcwd
  8.1563 +	data8 sys_capget			// 1185
  8.1564 +	data8 sys_capset
  8.1565 +	data8 sys_sendfile64
  8.1566 +	data8 sys_ni_syscall		// sys_getpmsg (STREAMS)
  8.1567 +	data8 sys_ni_syscall		// sys_putpmsg (STREAMS)
  8.1568 +	data8 sys_socket			// 1190
  8.1569 +	data8 sys_bind
  8.1570 +	data8 sys_connect
  8.1571 +	data8 sys_listen
  8.1572 +	data8 sys_accept
  8.1573 +	data8 sys_getsockname			// 1195
  8.1574 +	data8 sys_getpeername
  8.1575 +	data8 sys_socketpair
  8.1576 +	data8 sys_send
  8.1577 +	data8 sys_sendto
  8.1578 +	data8 sys_recv				// 1200
  8.1579 +	data8 sys_recvfrom
  8.1580 +	data8 sys_shutdown
  8.1581 +	data8 sys_setsockopt
  8.1582 +	data8 sys_getsockopt
  8.1583 +	data8 sys_sendmsg			// 1205
  8.1584 +	data8 sys_recvmsg
  8.1585 +	data8 sys_pivot_root
  8.1586 +	data8 sys_mincore
  8.1587 +	data8 sys_madvise
  8.1588 +	data8 sys_newstat			// 1210
  8.1589 +	data8 sys_newlstat
  8.1590 +	data8 sys_newfstat
  8.1591 +	data8 sys_clone2
  8.1592 +	data8 sys_getdents64
  8.1593 +	data8 sys_getunwind			// 1215
  8.1594 +	data8 sys_readahead
  8.1595 +	data8 sys_setxattr
  8.1596 +	data8 sys_lsetxattr
  8.1597 +	data8 sys_fsetxattr
  8.1598 +	data8 sys_getxattr			// 1220
  8.1599 +	data8 sys_lgetxattr
  8.1600 +	data8 sys_fgetxattr
  8.1601 +	data8 sys_listxattr
  8.1602 +	data8 sys_llistxattr
  8.1603 +	data8 sys_flistxattr			// 1225
  8.1604 +	data8 sys_removexattr
  8.1605 +	data8 sys_lremovexattr
  8.1606 +	data8 sys_fremovexattr
  8.1607 +	data8 sys_tkill
  8.1608 +	data8 sys_futex				// 1230
  8.1609 +	data8 sys_sched_setaffinity
  8.1610 +	data8 sys_sched_getaffinity
  8.1611 +	data8 sys_set_tid_address
  8.1612 +	data8 sys_fadvise64_64
  8.1613 +	data8 sys_tgkill 			// 1235
  8.1614 +	data8 sys_exit_group
  8.1615 +	data8 sys_lookup_dcookie
  8.1616 +	data8 sys_io_setup
  8.1617 +	data8 sys_io_destroy
  8.1618 +	data8 sys_io_getevents			// 1240
  8.1619 +	data8 sys_io_submit
  8.1620 +	data8 sys_io_cancel
  8.1621 +	data8 sys_epoll_create
  8.1622 +	data8 sys_epoll_ctl
  8.1623 +	data8 sys_epoll_wait			// 1245
  8.1624 +	data8 sys_restart_syscall
  8.1625 +	data8 sys_semtimedop
  8.1626 +	data8 sys_timer_create
  8.1627 +	data8 sys_timer_settime
  8.1628 +	data8 sys_timer_gettime			// 1250
  8.1629 +	data8 sys_timer_getoverrun
  8.1630 +	data8 sys_timer_delete
  8.1631 +	data8 sys_clock_settime
  8.1632 +	data8 sys_clock_gettime
  8.1633 +	data8 sys_clock_getres			// 1255
  8.1634 +	data8 sys_clock_nanosleep
  8.1635 +	data8 sys_fstatfs64
  8.1636 +	data8 sys_statfs64
  8.1637 +	data8 sys_mbind
  8.1638 +	data8 sys_get_mempolicy			// 1260
  8.1639 +	data8 sys_set_mempolicy
  8.1640 +	data8 sys_mq_open
  8.1641 +	data8 sys_mq_unlink
  8.1642 +	data8 sys_mq_timedsend
  8.1643 +	data8 sys_mq_timedreceive		// 1265
  8.1644 +	data8 sys_mq_notify
  8.1645 +	data8 sys_mq_getsetattr
  8.1646 +	data8 sys_ni_syscall			// reserved for kexec_load
  8.1647 +	data8 sys_ni_syscall			// reserved for vserver
  8.1648 +	data8 sys_waitid			// 1270
  8.1649 +	data8 sys_add_key
  8.1650 +	data8 sys_request_key
  8.1651 +	data8 sys_keyctl
  8.1652 +	data8 sys_ni_syscall
  8.1653 +	data8 sys_ni_syscall			// 1275
  8.1654 +	data8 sys_ni_syscall
  8.1655 +	data8 sys_ni_syscall
  8.1656 +	data8 sys_ni_syscall
  8.1657 +	data8 sys_ni_syscall
  8.1658 +
  8.1659 +	.org sys_call_table + 8*NR_syscalls	// guard against failures to increase NR_syscalls
  8.1660 +#endif
     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/xen/arch/ia64/linux-xen/entry.h	Fri Aug 26 09:05:43 2005 +0000
     9.3 @@ -0,0 +1,97 @@
     9.4 +#include <linux/config.h>
     9.5 +
     9.6 +/*
     9.7 + * Preserved registers that are shared between code in ivt.S and
     9.8 + * entry.S.  Be careful not to step on these!
     9.9 + */
    9.10 +#define PRED_LEAVE_SYSCALL	1 /* TRUE iff leave from syscall */
    9.11 +#define PRED_KERNEL_STACK	2 /* returning to kernel-stacks? */
    9.12 +#define PRED_USER_STACK		3 /* returning to user-stacks? */
    9.13 +#ifdef CONFIG_VTI
    9.14 +#define PRED_EMUL		2 /* Need to save r4-r7 for inst emulation */
    9.15 +#define PRED_NON_EMUL		3 /* No need to save r4-r7 for normal path */
    9.16 +#define PRED_BN0		6 /* Guest is in bank 0 */
    9.17 +#define PRED_BN1		7 /* Guest is in bank 1 */
    9.18 +#endif // CONFIG_VTI
    9.19 +#define PRED_SYSCALL		4 /* inside a system call? */
    9.20 +#define PRED_NON_SYSCALL	5 /* complement of PRED_SYSCALL */
    9.21 +
    9.22 +#ifdef __ASSEMBLY__
    9.23 +# define PASTE2(x,y)	x##y
    9.24 +# define PASTE(x,y)	PASTE2(x,y)
    9.25 +
    9.26 +# define pLvSys		PASTE(p,PRED_LEAVE_SYSCALL)
    9.27 +# define pKStk		PASTE(p,PRED_KERNEL_STACK)
    9.28 +# define pUStk		PASTE(p,PRED_USER_STACK)
    9.29 +#ifdef CONFIG_VTI
    9.30 +# define pEml		PASTE(p,PRED_EMUL)
    9.31 +# define pNonEml	PASTE(p,PRED_NON_EMUL)
    9.32 +# define pBN0		PASTE(p,PRED_BN0)
    9.33 +# define pBN1		PASTE(p,PRED_BN1)
    9.34 +#endif // CONFIG_VTI
    9.35 +# define pSys		PASTE(p,PRED_SYSCALL)
    9.36 +# define pNonSys	PASTE(p,PRED_NON_SYSCALL)
    9.37 +#endif
    9.38 +
    9.39 +#define PT(f)		(IA64_PT_REGS_##f##_OFFSET)
    9.40 +#define SW(f)		(IA64_SWITCH_STACK_##f##_OFFSET)
    9.41 +#ifdef CONFIG_VTI
    9.42 +#define VPD(f)      (VPD_##f##_START_OFFSET)
    9.43 +#endif // CONFIG_VTI
    9.44 +
    9.45 +#define PT_REGS_SAVES(off)			\
    9.46 +	.unwabi 3, 'i';				\
    9.47 +	.fframe IA64_PT_REGS_SIZE+16+(off);	\
    9.48 +	.spillsp rp, PT(CR_IIP)+16+(off);	\
    9.49 +	.spillsp ar.pfs, PT(CR_IFS)+16+(off);	\
    9.50 +	.spillsp ar.unat, PT(AR_UNAT)+16+(off);	\
    9.51 +	.spillsp ar.fpsr, PT(AR_FPSR)+16+(off);	\
    9.52 +	.spillsp pr, PT(PR)+16+(off);
    9.53 +
    9.54 +#define PT_REGS_UNWIND_INFO(off)		\
    9.55 +	.prologue;				\
    9.56 +	PT_REGS_SAVES(off);			\
    9.57 +	.body
    9.58 +
    9.59 +#define SWITCH_STACK_SAVES(off)							\
    9.60 +	.savesp ar.unat,SW(CALLER_UNAT)+16+(off);				\
    9.61 +	.savesp ar.fpsr,SW(AR_FPSR)+16+(off);					\
    9.62 +	.spillsp f2,SW(F2)+16+(off); .spillsp f3,SW(F3)+16+(off);		\
    9.63 +	.spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off);		\
    9.64 +	.spillsp f16,SW(F16)+16+(off); .spillsp f17,SW(F17)+16+(off);		\
    9.65 +	.spillsp f18,SW(F18)+16+(off); .spillsp f19,SW(F19)+16+(off);		\
    9.66 +	.spillsp f20,SW(F20)+16+(off); .spillsp f21,SW(F21)+16+(off);		\
    9.67 +	.spillsp f22,SW(F22)+16+(off); .spillsp f23,SW(F23)+16+(off);		\
    9.68 +	.spillsp f24,SW(F24)+16+(off); .spillsp f25,SW(F25)+16+(off);		\
    9.69 +	.spillsp f26,SW(F26)+16+(off); .spillsp f27,SW(F27)+16+(off);		\
    9.70 +	.spillsp f28,SW(F28)+16+(off); .spillsp f29,SW(F29)+16+(off);		\
    9.71 +	.spillsp f30,SW(F30)+16+(off); .spillsp f31,SW(F31)+16+(off);		\
    9.72 +	.spillsp r4,SW(R4)+16+(off); .spillsp r5,SW(R5)+16+(off);		\
    9.73 +	.spillsp r6,SW(R6)+16+(off); .spillsp r7,SW(R7)+16+(off);		\
    9.74 +	.spillsp b0,SW(B0)+16+(off); .spillsp b1,SW(B1)+16+(off);		\
    9.75 +	.spillsp b2,SW(B2)+16+(off); .spillsp b3,SW(B3)+16+(off);		\
    9.76 +	.spillsp b4,SW(B4)+16+(off); .spillsp b5,SW(B5)+16+(off);		\
    9.77 +	.spillsp ar.pfs,SW(AR_PFS)+16+(off); .spillsp ar.lc,SW(AR_LC)+16+(off);	\
    9.78 +	.spillsp @priunat,SW(AR_UNAT)+16+(off);					\
    9.79 +	.spillsp ar.rnat,SW(AR_RNAT)+16+(off);					\
    9.80 +	.spillsp ar.bspstore,SW(AR_BSPSTORE)+16+(off);				\
    9.81 +	.spillsp pr,SW(PR)+16+(off))
    9.82 +
    9.83 +#define DO_SAVE_SWITCH_STACK			\
    9.84 +	movl r28=1f;				\
    9.85 +	;;					\
    9.86 +	.fframe IA64_SWITCH_STACK_SIZE;		\
    9.87 +	adds sp=-IA64_SWITCH_STACK_SIZE,sp;	\
    9.88 +	mov.ret.sptk b7=r28,1f;			\
    9.89 +	SWITCH_STACK_SAVES(0);			\
    9.90 +	br.cond.sptk.many save_switch_stack;	\
    9.91 +1:
    9.92 +
    9.93 +#define DO_LOAD_SWITCH_STACK			\
    9.94 +	movl r28=1f;				\
    9.95 +	;;					\
    9.96 +	invala;					\
    9.97 +	mov.ret.sptk b7=r28,1f;			\
    9.98 +	br.cond.sptk.many load_switch_stack;	\
    9.99 +1:	.restore sp;				\
   9.100 +	adds sp=IA64_SWITCH_STACK_SIZE,sp
    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/xen/arch/ia64/linux-xen/head.S	Fri Aug 26 09:05:43 2005 +0000
    10.3 @@ -0,0 +1,1026 @@
    10.4 +/*
    10.5 + * Here is where the ball gets rolling as far as the kernel is concerned.
    10.6 + * When control is transferred to _start, the bootload has already
    10.7 + * loaded us to the correct address.  All that's left to do here is
    10.8 + * to set up the kernel's global pointer and jump to the kernel
    10.9 + * entry point.
   10.10 + *
   10.11 + * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
   10.12 + *	David Mosberger-Tang <davidm@hpl.hp.com>
   10.13 + *	Stephane Eranian <eranian@hpl.hp.com>
   10.14 + * Copyright (C) 1999 VA Linux Systems
   10.15 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
   10.16 + * Copyright (C) 1999 Intel Corp.
   10.17 + * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
   10.18 + * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
   10.19 + * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
   10.20 + *   -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
   10.21 + */
   10.22 +
   10.23 +#include <linux/config.h>
   10.24 +
   10.25 +#include <asm/asmmacro.h>
   10.26 +#include <asm/fpu.h>
   10.27 +#include <asm/kregs.h>
   10.28 +#include <asm/mmu_context.h>
   10.29 +#include <asm/offsets.h>
   10.30 +#include <asm/pal.h>
   10.31 +#include <asm/pgtable.h>
   10.32 +#include <asm/processor.h>
   10.33 +#include <asm/ptrace.h>
   10.34 +#include <asm/system.h>
   10.35 +
   10.36 +	.section __special_page_section,"ax"
   10.37 +
   10.38 +	.global empty_zero_page
   10.39 +empty_zero_page:
   10.40 +	.skip PAGE_SIZE
   10.41 +
   10.42 +	.global swapper_pg_dir
   10.43 +swapper_pg_dir:
   10.44 +	.skip PAGE_SIZE
   10.45 +
   10.46 +	.rodata
   10.47 +halt_msg:
   10.48 +	stringz "Halting kernel\n"
   10.49 +
   10.50 +	.text
   10.51 +
   10.52 +	.global start_ap
   10.53 +
   10.54 +	/*
   10.55 +	 * Start the kernel.  When the bootloader passes control to _start(), r28
   10.56 +	 * points to the address of the boot parameter area.  Execution reaches
   10.57 +	 * here in physical mode.
   10.58 +	 */
   10.59 +GLOBAL_ENTRY(_start)
   10.60 +start_ap:
   10.61 +	.prologue
   10.62 +	.save rp, r0		// terminate unwind chain with a NULL rp
   10.63 +	.body
   10.64 +
   10.65 +	rsm psr.i | psr.ic
   10.66 +	;;
   10.67 +	srlz.i
   10.68 +	;;
   10.69 +	/*
   10.70 +	 * Initialize kernel region registers:
   10.71 +	 *	rr[0]: VHPT enabled, page size = PAGE_SHIFT
   10.72 +	 *	rr[1]: VHPT enabled, page size = PAGE_SHIFT
   10.73 +	 *	rr[2]: VHPT enabled, page size = PAGE_SHIFT
   10.74 +	 *	rr[3]: VHPT enabled, page size = PAGE_SHIFT
   10.75 +	 *	rr[4]: VHPT enabled, page size = PAGE_SHIFT
   10.76 +	 *	rr[5]: VHPT enabled, page size = PAGE_SHIFT
   10.77 +	 *	rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
   10.78 +	 *	rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
   10.79 +	 * We initialize all of them to prevent inadvertently assuming
   10.80 +	 * something about the state of address translation early in boot.
   10.81 +	 */
   10.82 +	movl r6=((ia64_rid(IA64_REGION_ID_KERNEL, (0<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
   10.83 +	movl r7=(0<<61)
   10.84 +	movl r8=((ia64_rid(IA64_REGION_ID_KERNEL, (1<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
   10.85 +	movl r9=(1<<61)
   10.86 +	movl r10=((ia64_rid(IA64_REGION_ID_KERNEL, (2<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
   10.87 +	movl r11=(2<<61)
   10.88 +	movl r12=((ia64_rid(IA64_REGION_ID_KERNEL, (3<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
   10.89 +	movl r13=(3<<61)
   10.90 +	movl r14=((ia64_rid(IA64_REGION_ID_KERNEL, (4<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
   10.91 +	movl r15=(4<<61)
   10.92 +	movl r16=((ia64_rid(IA64_REGION_ID_KERNEL, (5<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
   10.93 +	movl r17=(5<<61)
   10.94 +	movl r18=((ia64_rid(IA64_REGION_ID_KERNEL, (6<<61)) << 8) | (IA64_GRANULE_SHIFT << 2))
   10.95 +	movl r19=(6<<61)
   10.96 +	movl r20=((ia64_rid(IA64_REGION_ID_KERNEL, (7<<61)) << 8) | (IA64_GRANULE_SHIFT << 2))
   10.97 +	movl r21=(7<<61)
   10.98 +	;;
   10.99 +	mov rr[r7]=r6
  10.100 +	mov rr[r9]=r8
  10.101 +	mov rr[r11]=r10
  10.102 +	mov rr[r13]=r12
  10.103 +	mov rr[r15]=r14
  10.104 +	mov rr[r17]=r16
  10.105 +	mov rr[r19]=r18
  10.106 +	mov rr[r21]=r20
  10.107 +	;;
  10.108 +	/*
  10.109 +	 * Now pin mappings into the TLB for kernel text and data
  10.110 +	 */
  10.111 +	mov r18=KERNEL_TR_PAGE_SHIFT<<2
  10.112 +	movl r17=KERNEL_START
  10.113 +	;;
  10.114 +	mov cr.itir=r18
  10.115 +	mov cr.ifa=r17
  10.116 +	mov r16=IA64_TR_KERNEL
  10.117 +	mov r3=ip
  10.118 +	movl r18=PAGE_KERNEL
  10.119 +	;;
  10.120 +	dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
  10.121 +	;;
  10.122 +	or r18=r2,r18
  10.123 +	;;
  10.124 +	srlz.i
  10.125 +	;;
  10.126 +	itr.i itr[r16]=r18
  10.127 +	;;
  10.128 +	itr.d dtr[r16]=r18
  10.129 +	;;
  10.130 +	srlz.i
  10.131 +
  10.132 +	/*
  10.133 +	 * Switch into virtual mode:
  10.134 +	 */
  10.135 +#ifdef CONFIG_VTI
  10.136 +	movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH \
  10.137 +		  |IA64_PSR_DI)
  10.138 +#else // CONFIG_VTI
  10.139 +	movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
  10.140 +		  |IA64_PSR_DI)
  10.141 +#endif // CONFIG_VTI
  10.142 +	;;
  10.143 +	mov cr.ipsr=r16
  10.144 +	movl r17=1f
  10.145 +	;;
  10.146 +	mov cr.iip=r17
  10.147 +	mov cr.ifs=r0
  10.148 +	;;
  10.149 +	rfi
  10.150 +	;;
  10.151 +1:	// now we are in virtual mode
  10.152 +
  10.153 +	// set IVT entry point---can't access I/O ports without it
  10.154 +#ifdef CONFIG_VTI
  10.155 +    movl r3=vmx_ia64_ivt
  10.156 +#else // CONFIG_VTI
  10.157 +	movl r3=ia64_ivt
  10.158 +#endif // CONFIG_VTI
  10.159 +	;;
  10.160 +	mov cr.iva=r3
  10.161 +	movl r2=FPSR_DEFAULT
  10.162 +	;;
  10.163 +	srlz.i
  10.164 +	movl gp=__gp
  10.165 +
  10.166 +	mov ar.fpsr=r2
  10.167 +	;;
  10.168 +
  10.169 +#define isAP	p2	// are we an Application Processor?
  10.170 +#define isBP	p3	// are we the Bootstrap Processor?
  10.171 +
  10.172 +#ifdef CONFIG_SMP
  10.173 +	/*
  10.174 +	 * Find the init_task for the currently booting CPU.  At poweron, and in
  10.175 +	 * UP mode, task_for_booting_cpu is NULL.
  10.176 +	 */
  10.177 +	movl r3=task_for_booting_cpu
  10.178 + 	;;
  10.179 +	ld8 r3=[r3]
  10.180 +	movl r2=init_task
  10.181 +	;;
  10.182 +	cmp.eq isBP,isAP=r3,r0
  10.183 +	;;
  10.184 +(isAP)	mov r2=r3
  10.185 +#else
  10.186 +	movl r2=init_task
  10.187 +	cmp.eq isBP,isAP=r0,r0
  10.188 +#endif
  10.189 +	;;
  10.190 +	tpa r3=r2		// r3 == phys addr of task struct
  10.191 +	mov r16=-1
  10.192 +(isBP)	br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
  10.193 +
  10.194 +	// load mapping for stack (virtaddr in r2, physaddr in r3)
  10.195 +	rsm psr.ic
  10.196 +	movl r17=PAGE_KERNEL
  10.197 +	;;
  10.198 +	srlz.d
  10.199 +	dep r18=0,r3,0,12
  10.200 +	;;
  10.201 +	or r18=r17,r18
  10.202 +#ifdef XEN
  10.203 +	dep r2=-1,r3,60,4	// IMVA of task
  10.204 +#else
  10.205 +	dep r2=-1,r3,61,3	// IMVA of task
  10.206 +#endif
  10.207 +	;;
  10.208 +	mov r17=rr[r2]
  10.209 +	shr.u r16=r3,IA64_GRANULE_SHIFT
  10.210 +	;;
  10.211 +	dep r17=0,r17,8,24
  10.212 +	;;
  10.213 +	mov cr.itir=r17
  10.214 +	mov cr.ifa=r2
  10.215 +
  10.216 +	mov r19=IA64_TR_CURRENT_STACK
  10.217 +	;;
  10.218 +	itr.d dtr[r19]=r18
  10.219 +	;;
  10.220 +	ssm psr.ic
  10.221 +	srlz.d
  10.222 +  	;;
  10.223 +
  10.224 +.load_current:
  10.225 +	// load the "current" pointer (r13) and ar.k6 with the current task
  10.226 +#ifdef CONFIG_VTI
  10.227 +	mov r21=r2		// virtual address
  10.228 +	;;
  10.229 +	bsw.1
  10.230 +	;;
  10.231 +#else // CONFIG_VTI
  10.232 +	mov IA64_KR(CURRENT)=r2
  10.233 +	mov IA64_KR(CURRENT_STACK)=r16
  10.234 +#endif // CONFIG_VTI
  10.235 +	mov r13=r2
  10.236 +	/*
  10.237 +	 * Reserve space at the top of the stack for "struct pt_regs".  Kernel threads
  10.238 +	 * don't store interesting values in that structure, but the space still needs
  10.239 +	 * to be there because time-critical stuff such as the context switching can
  10.240 +	 * be implemented more efficiently (for example, __switch_to()
  10.241 +	 * always sets the psr.dfh bit of the task it is switching to).
  10.242 +	 */
  10.243 +	addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
  10.244 +	addl r2=IA64_RBS_OFFSET,r2	// initialize the RSE
  10.245 +	mov ar.rsc=0		// place RSE in enforced lazy mode
  10.246 +	;;
  10.247 +	loadrs			// clear the dirty partition
  10.248 +	;;
  10.249 +	mov ar.bspstore=r2	// establish the new RSE stack
  10.250 +	;;
  10.251 +	mov ar.rsc=0x3		// place RSE in eager mode
  10.252 +
  10.253 +#ifdef XEN
  10.254 +(isBP)	dep r28=-1,r28,60,4	// make address virtual
  10.255 +#else
  10.256 +(isBP)	dep r28=-1,r28,61,3	// make address virtual
  10.257 +#endif
  10.258 +(isBP)	movl r2=ia64_boot_param
  10.259 +	;;
  10.260 +(isBP)	st8 [r2]=r28		// save the address of the boot param area passed by the bootloader
  10.261 +
  10.262 +#ifdef CONFIG_SMP
  10.263 +(isAP)	br.call.sptk.many rp=start_secondary
  10.264 +.ret0:
  10.265 +(isAP)	br.cond.sptk self
  10.266 +#endif
  10.267 +
  10.268 +	// This is executed by the bootstrap processor (bsp) only:
  10.269 +
  10.270 +#ifdef CONFIG_IA64_FW_EMU
  10.271 +	// initialize PAL & SAL emulator:
  10.272 +	br.call.sptk.many rp=sys_fw_init
  10.273 +.ret1:
  10.274 +#endif
  10.275 +	br.call.sptk.many rp=start_kernel
  10.276 +.ret2:	addl r3=@ltoff(halt_msg),gp
  10.277 +	;;
  10.278 +	alloc r2=ar.pfs,8,0,2,0
  10.279 +	;;
  10.280 +	ld8 out0=[r3]
  10.281 +	br.call.sptk.many b0=console_print
  10.282 +
  10.283 +self:	hint @pause
  10.284 +	;;
  10.285 +	br.sptk.many self		// endless loop
  10.286 +	;;
  10.287 +END(_start)
  10.288 +
  10.289 +GLOBAL_ENTRY(ia64_save_debug_regs)
  10.290 +	alloc r16=ar.pfs,1,0,0,0
  10.291 +	mov r20=ar.lc			// preserve ar.lc
  10.292 +	mov ar.lc=IA64_NUM_DBG_REGS-1
  10.293 +	mov r18=0
  10.294 +	add r19=IA64_NUM_DBG_REGS*8,in0
  10.295 +	;;
  10.296 +1:	mov r16=dbr[r18]
  10.297 +#ifdef CONFIG_ITANIUM
  10.298 +	;;
  10.299 +	srlz.d
  10.300 +#endif
  10.301 +	mov r17=ibr[r18]
  10.302 +	add r18=1,r18
  10.303 +	;;
  10.304 +	st8.nta [in0]=r16,8
  10.305 +	st8.nta [r19]=r17,8
  10.306 +	br.cloop.sptk.many 1b
  10.307 +	;;
  10.308 +	mov ar.lc=r20			// restore ar.lc
  10.309 +	br.ret.sptk.many rp
  10.310 +END(ia64_save_debug_regs)
  10.311 +
  10.312 +GLOBAL_ENTRY(ia64_load_debug_regs)
  10.313 +	alloc r16=ar.pfs,1,0,0,0
  10.314 +	lfetch.nta [in0]
  10.315 +	mov r20=ar.lc			// preserve ar.lc
  10.316 +	add r19=IA64_NUM_DBG_REGS*8,in0
  10.317 +	mov ar.lc=IA64_NUM_DBG_REGS-1
  10.318 +	mov r18=-1
  10.319 +	;;
  10.320 +1:	ld8.nta r16=[in0],8
  10.321 +	ld8.nta r17=[r19],8
  10.322 +	add r18=1,r18
  10.323 +	;;
  10.324 +	mov dbr[r18]=r16
  10.325 +#ifdef CONFIG_ITANIUM
  10.326 +	;;
  10.327 +	srlz.d				// Errata 132 (NoFix status)
  10.328 +#endif
  10.329 +	mov ibr[r18]=r17
  10.330 +	br.cloop.sptk.many 1b
  10.331 +	;;
  10.332 +	mov ar.lc=r20			// restore ar.lc
  10.333 +	br.ret.sptk.many rp
  10.334 +END(ia64_load_debug_regs)
  10.335 +
  10.336 +GLOBAL_ENTRY(__ia64_save_fpu)
  10.337 +	alloc r2=ar.pfs,1,4,0,0
  10.338 +	adds loc0=96*16-16,in0
  10.339 +	adds loc1=96*16-16-128,in0
  10.340 +	;;
  10.341 +	stf.spill.nta [loc0]=f127,-256
  10.342 +	stf.spill.nta [loc1]=f119,-256
  10.343 +	;;
  10.344 +	stf.spill.nta [loc0]=f111,-256
  10.345 +	stf.spill.nta [loc1]=f103,-256
  10.346 +	;;
  10.347 +	stf.spill.nta [loc0]=f95,-256
  10.348 +	stf.spill.nta [loc1]=f87,-256
  10.349 +	;;
  10.350 +	stf.spill.nta [loc0]=f79,-256
  10.351 +	stf.spill.nta [loc1]=f71,-256
  10.352 +	;;
  10.353 +	stf.spill.nta [loc0]=f63,-256
  10.354 +	stf.spill.nta [loc1]=f55,-256
  10.355 +	adds loc2=96*16-32,in0
  10.356 +	;;
  10.357 +	stf.spill.nta [loc0]=f47,-256
  10.358 +	stf.spill.nta [loc1]=f39,-256
  10.359 +	adds loc3=96*16-32-128,in0
  10.360 +	;;
  10.361 +	stf.spill.nta [loc2]=f126,-256
  10.362 +	stf.spill.nta [loc3]=f118,-256
  10.363 +	;;
  10.364 +	stf.spill.nta [loc2]=f110,-256
  10.365 +	stf.spill.nta [loc3]=f102,-256
  10.366 +	;;
  10.367 +	stf.spill.nta [loc2]=f94,-256
  10.368 +	stf.spill.nta [loc3]=f86,-256
  10.369 +	;;
  10.370 +	stf.spill.nta [loc2]=f78,-256
  10.371 +	stf.spill.nta [loc3]=f70,-256
  10.372 +	;;
  10.373 +	stf.spill.nta [loc2]=f62,-256
  10.374 +	stf.spill.nta [loc3]=f54,-256
  10.375 +	adds loc0=96*16-48,in0
  10.376 +	;;
  10.377 +	stf.spill.nta [loc2]=f46,-256
  10.378 +	stf.spill.nta [loc3]=f38,-256
  10.379 +	adds loc1=96*16-48-128,in0
  10.380 +	;;
  10.381 +	stf.spill.nta [loc0]=f125,-256
  10.382 +	stf.spill.nta [loc1]=f117,-256
  10.383 +	;;
  10.384 +	stf.spill.nta [loc0]=f109,-256
  10.385 +	stf.spill.nta [loc1]=f101,-256
  10.386 +	;;
  10.387 +	stf.spill.nta [loc0]=f93,-256
  10.388 +	stf.spill.nta [loc1]=f85,-256
  10.389 +	;;
  10.390 +	stf.spill.nta [loc0]=f77,-256
  10.391 +	stf.spill.nta [loc1]=f69,-256
  10.392 +	;;
  10.393 +	stf.spill.nta [loc0]=f61,-256
  10.394 +	stf.spill.nta [loc1]=f53,-256
  10.395 +	adds loc2=96*16-64,in0
  10.396 +	;;
  10.397 +	stf.spill.nta [loc0]=f45,-256
  10.398 +	stf.spill.nta [loc1]=f37,-256
  10.399 +	adds loc3=96*16-64-128,in0
  10.400 +	;;
  10.401 +	stf.spill.nta [loc2]=f124,-256
  10.402 +	stf.spill.nta [loc3]=f116,-256
  10.403 +	;;
  10.404 +	stf.spill.nta [loc2]=f108,-256
  10.405 +	stf.spill.nta [loc3]=f100,-256
  10.406 +	;;
  10.407 +	stf.spill.nta [loc2]=f92,-256
  10.408 +	stf.spill.nta [loc3]=f84,-256
  10.409 +	;;
  10.410 +	stf.spill.nta [loc2]=f76,-256
  10.411 +	stf.spill.nta [loc3]=f68,-256
  10.412 +	;;
  10.413 +	stf.spill.nta [loc2]=f60,-256
  10.414 +	stf.spill.nta [loc3]=f52,-256
  10.415 +	adds loc0=96*16-80,in0
  10.416 +	;;
  10.417 +	stf.spill.nta [loc2]=f44,-256
  10.418 +	stf.spill.nta [loc3]=f36,-256
  10.419 +	adds loc1=96*16-80-128,in0
  10.420 +	;;
  10.421 +	stf.spill.nta [loc0]=f123,-256
  10.422 +	stf.spill.nta [loc1]=f115,-256
  10.423 +	;;
  10.424 +	stf.spill.nta [loc0]=f107,-256
  10.425 +	stf.spill.nta [loc1]=f99,-256
  10.426 +	;;
  10.427 +	stf.spill.nta [loc0]=f91,-256
  10.428 +	stf.spill.nta [loc1]=f83,-256
  10.429 +	;;
  10.430 +	stf.spill.nta [loc0]=f75,-256
  10.431 +	stf.spill.nta [loc1]=f67,-256
  10.432 +	;;
  10.433 +	stf.spill.nta [loc0]=f59,-256
  10.434 +	stf.spill.nta [loc1]=f51,-256
  10.435 +	adds loc2=96*16-96,in0
  10.436 +	;;
  10.437 +	stf.spill.nta [loc0]=f43,-256
  10.438 +	stf.spill.nta [loc1]=f35,-256
  10.439 +	adds loc3=96*16-96-128,in0
  10.440 +	;;
  10.441 +	stf.spill.nta [loc2]=f122,-256
  10.442 +	stf.spill.nta [loc3]=f114,-256
  10.443 +	;;
  10.444 +	stf.spill.nta [loc2]=f106,-256
  10.445 +	stf.spill.nta [loc3]=f98,-256
  10.446 +	;;
  10.447 +	stf.spill.nta [loc2]=f90,-256
  10.448 +	stf.spill.nta [loc3]=f82,-256
  10.449 +	;;
  10.450 +	stf.spill.nta [loc2]=f74,-256
  10.451 +	stf.spill.nta [loc3]=f66,-256
  10.452 +	;;
  10.453 +	stf.spill.nta [loc2]=f58,-256
  10.454 +	stf.spill.nta [loc3]=f50,-256
  10.455 +	adds loc0=96*16-112,in0
  10.456 +	;;
  10.457 +	stf.spill.nta [loc2]=f42,-256
  10.458 +	stf.spill.nta [loc3]=f34,-256
  10.459 +	adds loc1=96*16-112-128,in0
  10.460 +	;;
  10.461 +	stf.spill.nta [loc0]=f121,-256
  10.462 +	stf.spill.nta [loc1]=f113,-256
  10.463 +	;;
  10.464 +	stf.spill.nta [loc0]=f105,-256
  10.465 +	stf.spill.nta [loc1]=f97,-256
  10.466 +	;;
  10.467 +	stf.spill.nta [loc0]=f89,-256
  10.468 +	stf.spill.nta [loc1]=f81,-256
  10.469 +	;;
  10.470 +	stf.spill.nta [loc0]=f73,-256
  10.471 +	stf.spill.nta [loc1]=f65,-256
  10.472 +	;;
  10.473 +	stf.spill.nta [loc0]=f57,-256
  10.474 +	stf.spill.nta [loc1]=f49,-256
  10.475 +	adds loc2=96*16-128,in0
  10.476 +	;;
  10.477 +	stf.spill.nta [loc0]=f41,-256
  10.478 +	stf.spill.nta [loc1]=f33,-256
  10.479 +	adds loc3=96*16-128-128,in0
  10.480 +	;;
  10.481 +	stf.spill.nta [loc2]=f120,-256
  10.482 +	stf.spill.nta [loc3]=f112,-256
  10.483 +	;;
  10.484 +	stf.spill.nta [loc2]=f104,-256
  10.485 +	stf.spill.nta [loc3]=f96,-256
  10.486 +	;;
  10.487 +	stf.spill.nta [loc2]=f88,-256
  10.488 +	stf.spill.nta [loc3]=f80,-256
  10.489 +	;;
  10.490 +	stf.spill.nta [loc2]=f72,-256
  10.491 +	stf.spill.nta [loc3]=f64,-256
  10.492 +	;;
  10.493 +	stf.spill.nta [loc2]=f56,-256
  10.494 +	stf.spill.nta [loc3]=f48,-256
  10.495 +	;;
  10.496 +	stf.spill.nta [loc2]=f40
  10.497 +	stf.spill.nta [loc3]=f32
  10.498 +	br.ret.sptk.many rp
  10.499 +END(__ia64_save_fpu)
  10.500 +
  10.501 +GLOBAL_ENTRY(__ia64_load_fpu)
  10.502 +	alloc r2=ar.pfs,1,2,0,0
  10.503 +	adds r3=128,in0
  10.504 +	adds r14=256,in0
  10.505 +	adds r15=384,in0
  10.506 +	mov loc0=512
  10.507 +	mov loc1=-1024+16
  10.508 +	;;
  10.509 +	ldf.fill.nta f32=[in0],loc0
  10.510 +	ldf.fill.nta f40=[ r3],loc0
  10.511 +	ldf.fill.nta f48=[r14],loc0
  10.512 +	ldf.fill.nta f56=[r15],loc0
  10.513 +	;;
  10.514 +	ldf.fill.nta f64=[in0],loc0
  10.515 +	ldf.fill.nta f72=[ r3],loc0
  10.516 +	ldf.fill.nta f80=[r14],loc0
  10.517 +	ldf.fill.nta f88=[r15],loc0
  10.518 +	;;
  10.519 +	ldf.fill.nta f96=[in0],loc1
  10.520 +	ldf.fill.nta f104=[ r3],loc1
  10.521 +	ldf.fill.nta f112=[r14],loc1
  10.522 +	ldf.fill.nta f120=[r15],loc1
  10.523 +	;;
  10.524 +	ldf.fill.nta f33=[in0],loc0
  10.525 +	ldf.fill.nta f41=[ r3],loc0
  10.526 +	ldf.fill.nta f49=[r14],loc0
  10.527 +	ldf.fill.nta f57=[r15],loc0
  10.528 +	;;
  10.529 +	ldf.fill.nta f65=[in0],loc0
  10.530 +	ldf.fill.nta f73=[ r3],loc0
  10.531 +	ldf.fill.nta f81=[r14],loc0
  10.532 +	ldf.fill.nta f89=[r15],loc0
  10.533 +	;;
  10.534 +	ldf.fill.nta f97=[in0],loc1
  10.535 +	ldf.fill.nta f105=[ r3],loc1
  10.536 +	ldf.fill.nta f113=[r14],loc1
  10.537 +	ldf.fill.nta f121=[r15],loc1
  10.538 +	;;
  10.539 +	ldf.fill.nta f34=[in0],loc0
  10.540 +	ldf.fill.nta f42=[ r3],loc0
  10.541 +	ldf.fill.nta f50=[r14],loc0
  10.542 +	ldf.fill.nta f58=[r15],loc0
  10.543 +	;;
  10.544 +	ldf.fill.nta f66=[in0],loc0
  10.545 +	ldf.fill.nta f74=[ r3],loc0
  10.546 +	ldf.fill.nta f82=[r14],loc0
  10.547 +	ldf.fill.nta f90=[r15],loc0
  10.548 +	;;
  10.549 +	ldf.fill.nta f98=[in0],loc1
  10.550 +	ldf.fill.nta f106=[ r3],loc1
  10.551 +	ldf.fill.nta f114=[r14],loc1
  10.552 +	ldf.fill.nta f122=[r15],loc1
  10.553 +	;;
  10.554 +	ldf.fill.nta f35=[in0],loc0
  10.555 +	ldf.fill.nta f43=[ r3],loc0
  10.556 +	ldf.fill.nta f51=[r14],loc0
  10.557 +	ldf.fill.nta f59=[r15],loc0
  10.558 +	;;
  10.559 +	ldf.fill.nta f67=[in0],loc0
  10.560 +	ldf.fill.nta f75=[ r3],loc0
  10.561 +	ldf.fill.nta f83=[r14],loc0
  10.562 +	ldf.fill.nta f91=[r15],loc0
  10.563 +	;;
  10.564 +	ldf.fill.nta f99=[in0],loc1
  10.565 +	ldf.fill.nta f107=[ r3],loc1
  10.566 +	ldf.fill.nta f115=[r14],loc1
  10.567 +	ldf.fill.nta f123=[r15],loc1
  10.568 +	;;
  10.569 +	ldf.fill.nta f36=[in0],loc0
  10.570 +	ldf.fill.nta f44=[ r3],loc0
  10.571 +	ldf.fill.nta f52=[r14],loc0
  10.572 +	ldf.fill.nta f60=[r15],loc0
  10.573 +	;;
  10.574 +	ldf.fill.nta f68=[in0],loc0
  10.575 +	ldf.fill.nta f76=[ r3],loc0
  10.576 +	ldf.fill.nta f84=[r14],loc0
  10.577 +	ldf.fill.nta f92=[r15],loc0
  10.578 +	;;
  10.579 +	ldf.fill.nta f100=[in0],loc1
  10.580 +	ldf.fill.nta f108=[ r3],loc1
  10.581 +	ldf.fill.nta f116=[r14],loc1
  10.582 +	ldf.fill.nta f124=[r15],loc1
  10.583 +	;;
  10.584 +	ldf.fill.nta f37=[in0],loc0
  10.585 +	ldf.fill.nta f45=[ r3],loc0
  10.586 +	ldf.fill.nta f53=[r14],loc0
  10.587 +	ldf.fill.nta f61=[r15],loc0
  10.588 +	;;
  10.589 +	ldf.fill.nta f69=[in0],loc0
  10.590 +	ldf.fill.nta f77=[ r3],loc0
  10.591 +	ldf.fill.nta f85=[r14],loc0
  10.592 +	ldf.fill.nta f93=[r15],loc0
  10.593 +	;;
  10.594 +	ldf.fill.nta f101=[in0],loc1
  10.595 +	ldf.fill.nta f109=[ r3],loc1
  10.596 +	ldf.fill.nta f117=[r14],loc1
  10.597 +	ldf.fill.nta f125=[r15],loc1
  10.598 +	;;
  10.599 +	ldf.fill.nta f38 =[in0],loc0
  10.600 +	ldf.fill.nta f46 =[ r3],loc0
  10.601 +	ldf.fill.nta f54 =[r14],loc0
  10.602 +	ldf.fill.nta f62 =[r15],loc0
  10.603 +	;;
  10.604 +	ldf.fill.nta f70 =[in0],loc0
  10.605 +	ldf.fill.nta f78 =[ r3],loc0
  10.606 +	ldf.fill.nta f86 =[r14],loc0
  10.607 +	ldf.fill.nta f94 =[r15],loc0
  10.608 +	;;
  10.609 +	ldf.fill.nta f102=[in0],loc1
  10.610 +	ldf.fill.nta f110=[ r3],loc1
  10.611 +	ldf.fill.nta f118=[r14],loc1
  10.612 +	ldf.fill.nta f126=[r15],loc1
  10.613 +	;;
  10.614 +	ldf.fill.nta f39 =[in0],loc0
  10.615 +	ldf.fill.nta f47 =[ r3],loc0
  10.616 +	ldf.fill.nta f55 =[r14],loc0
  10.617 +	ldf.fill.nta f63 =[r15],loc0
  10.618 +	;;
  10.619 +	ldf.fill.nta f71 =[in0],loc0
  10.620 +	ldf.fill.nta f79 =[ r3],loc0
  10.621 +	ldf.fill.nta f87 =[r14],loc0
  10.622 +	ldf.fill.nta f95 =[r15],loc0
  10.623 +	;;
  10.624 +	ldf.fill.nta f103=[in0]
  10.625 +	ldf.fill.nta f111=[ r3]
  10.626 +	ldf.fill.nta f119=[r14]
  10.627 +	ldf.fill.nta f127=[r15]
  10.628 +	br.ret.sptk.many rp
  10.629 +END(__ia64_load_fpu)
  10.630 +
  10.631 +GLOBAL_ENTRY(__ia64_init_fpu)
  10.632 +	stf.spill [sp]=f0		// M3
  10.633 +	mov	 f32=f0			// F
  10.634 +	nop.b	 0
  10.635 +
  10.636 +	ldfps	 f33,f34=[sp]		// M0
  10.637 +	ldfps	 f35,f36=[sp]		// M1
  10.638 +	mov      f37=f0			// F
  10.639 +	;;
  10.640 +
  10.641 +	setf.s	 f38=r0			// M2
  10.642 +	setf.s	 f39=r0			// M3
  10.643 +	mov      f40=f0			// F
  10.644 +
  10.645 +	ldfps	 f41,f42=[sp]		// M0
  10.646 +	ldfps	 f43,f44=[sp]		// M1
  10.647 +	mov      f45=f0			// F
  10.648 +
  10.649 +	setf.s	 f46=r0			// M2
  10.650 +	setf.s	 f47=r0			// M3
  10.651 +	mov      f48=f0			// F
  10.652 +
  10.653 +	ldfps	 f49,f50=[sp]		// M0
  10.654 +	ldfps	 f51,f52=[sp]		// M1
  10.655 +	mov      f53=f0			// F
  10.656 +
  10.657 +	setf.s	 f54=r0			// M2
  10.658 +	setf.s	 f55=r0			// M3
  10.659 +	mov      f56=f0			// F
  10.660 +
  10.661 +	ldfps	 f57,f58=[sp]		// M0
  10.662 +	ldfps	 f59,f60=[sp]		// M1
  10.663 +	mov      f61=f0			// F
  10.664 +
  10.665 +	setf.s	 f62=r0			// M2
  10.666 +	setf.s	 f63=r0			// M3
  10.667 +	mov      f64=f0			// F
  10.668 +
  10.669 +	ldfps	 f65,f66=[sp]		// M0
  10.670 +	ldfps	 f67,f68=[sp]		// M1
  10.671 +	mov      f69=f0			// F
  10.672 +
  10.673 +	setf.s	 f70=r0			// M2
  10.674 +	setf.s	 f71=r0			// M3
  10.675 +	mov      f72=f0			// F
  10.676 +
  10.677 +	ldfps	 f73,f74=[sp]		// M0
  10.678 +	ldfps	 f75,f76=[sp]		// M1
  10.679 +	mov      f77=f0			// F
  10.680 +
  10.681 +	setf.s	 f78=r0			// M2
  10.682 +	setf.s	 f79=r0			// M3
  10.683 +	mov      f80=f0			// F
  10.684 +
  10.685 +	ldfps	 f81,f82=[sp]		// M0
  10.686 +	ldfps	 f83,f84=[sp]		// M1
  10.687 +	mov      f85=f0			// F
  10.688 +
  10.689 +	setf.s	 f86=r0			// M2
  10.690 +	setf.s	 f87=r0			// M3
  10.691 +	mov      f88=f0			// F
  10.692 +
  10.693 +	/*
  10.694 +	 * When the instructions are cached, it would be faster to initialize
  10.695 +	 * the remaining registers with simply mov instructions (F-unit).
  10.696 +	 * This gets the time down to ~29 cycles.  However, this would use up
  10.697 +	 * 33 bundles, whereas continuing with the above pattern yields
  10.698 +	 * 10 bundles and ~30 cycles.
  10.699 +	 */
  10.700 +
  10.701 +	ldfps	 f89,f90=[sp]		// M0
  10.702 +	ldfps	 f91,f92=[sp]		// M1
  10.703 +	mov      f93=f0			// F
  10.704 +
  10.705 +	setf.s	 f94=r0			// M2
  10.706 +	setf.s	 f95=r0			// M3
  10.707 +	mov      f96=f0			// F
  10.708 +
  10.709 +	ldfps	 f97,f98=[sp]		// M0
  10.710 +	ldfps	 f99,f100=[sp]		// M1
  10.711 +	mov      f101=f0		// F
  10.712 +
  10.713 +	setf.s	 f102=r0		// M2
  10.714 +	setf.s	 f103=r0		// M3
  10.715 +	mov      f104=f0		// F
  10.716 +
  10.717 +	ldfps	 f105,f106=[sp]		// M0
  10.718 +	ldfps	 f107,f108=[sp]		// M1
  10.719 +	mov      f109=f0		// F
  10.720 +
  10.721 +	setf.s	 f110=r0		// M2
  10.722 +	setf.s	 f111=r0		// M3
  10.723 +	mov      f112=f0		// F
  10.724 +
  10.725 +	ldfps	 f113,f114=[sp]		// M0
  10.726 +	ldfps	 f115,f116=[sp]		// M1
  10.727 +	mov      f117=f0		// F
  10.728 +
  10.729 +	setf.s	 f118=r0		// M2
  10.730 +	setf.s	 f119=r0		// M3
  10.731 +	mov      f120=f0		// F
  10.732 +
  10.733 +	ldfps	 f121,f122=[sp]		// M0
  10.734 +	ldfps	 f123,f124=[sp]		// M1
  10.735 +	mov      f125=f0		// F
  10.736 +
  10.737 +	setf.s	 f126=r0		// M2
  10.738 +	setf.s	 f127=r0		// M3
  10.739 +	br.ret.sptk.many rp		// F
  10.740 +END(__ia64_init_fpu)
  10.741 +
  10.742 +/*
  10.743 + * Switch execution mode from virtual to physical
  10.744 + *
  10.745 + * Inputs:
  10.746 + *	r16 = new psr to establish
  10.747 + * Output:
  10.748 + *	r19 = old virtual address of ar.bsp
  10.749 + *	r20 = old virtual address of sp
  10.750 + *
  10.751 + * Note: RSE must already be in enforced lazy mode
  10.752 + */
  10.753 +GLOBAL_ENTRY(ia64_switch_mode_phys)
  10.754 + {
  10.755 +	alloc r2=ar.pfs,0,0,0,0
  10.756 +	rsm psr.i | psr.ic		// disable interrupts and interrupt collection
  10.757 +	mov r15=ip
  10.758 + }
  10.759 +	;;
  10.760 + {
  10.761 +	flushrs				// must be first insn in group
  10.762 +	srlz.i
  10.763 + }
  10.764 +	;;
  10.765 +	mov cr.ipsr=r16			// set new PSR
  10.766 +	add r3=1f-ia64_switch_mode_phys,r15
  10.767 +
  10.768 +	mov r19=ar.bsp
  10.769 +	mov r20=sp
  10.770 +	mov r14=rp			// get return address into a general register
  10.771 +	;;
  10.772 +
  10.773 +	// going to physical mode, use tpa to translate virt->phys
  10.774 +	tpa r17=r19
  10.775 +	tpa r3=r3
  10.776 +	tpa sp=sp
  10.777 +	tpa r14=r14
  10.778 +	;;
  10.779 +
  10.780 +	mov r18=ar.rnat			// save ar.rnat
  10.781 +	mov ar.bspstore=r17		// this steps on ar.rnat
  10.782 +	mov cr.iip=r3
  10.783 +	mov cr.ifs=r0
  10.784 +	;;
  10.785 +	mov ar.rnat=r18			// restore ar.rnat
  10.786 +	rfi				// must be last insn in group
  10.787 +	;;
  10.788 +1:	mov rp=r14
  10.789 +	br.ret.sptk.many rp
  10.790 +END(ia64_switch_mode_phys)
  10.791 +
  10.792 +/*
  10.793 + * Switch execution mode from physical to virtual
  10.794 + *
  10.795 + * Inputs:
  10.796 + *	r16 = new psr to establish
  10.797 + *	r19 = new bspstore to establish
  10.798 + *	r20 = new sp to establish
  10.799 + *
  10.800 + * Note: RSE must already be in enforced lazy mode
  10.801 + */
  10.802 +GLOBAL_ENTRY(ia64_switch_mode_virt)
  10.803 + {
  10.804 +	alloc r2=ar.pfs,0,0,0,0
  10.805 +	rsm psr.i | psr.ic		// disable interrupts and interrupt collection
  10.806 +	mov r15=ip
  10.807 + }
  10.808 +	;;
  10.809 + {
  10.810 +	flushrs				// must be first insn in group
  10.811 +	srlz.i
  10.812 + }
  10.813 +	;;
  10.814 +	mov cr.ipsr=r16			// set new PSR
  10.815 +	add r3=1f-ia64_switch_mode_virt,r15
  10.816 +
  10.817 +	mov r14=rp			// get return address into a general register
  10.818 +	;;
  10.819 +
  10.820 +	// going to virtual
  10.821 +	//   - for code addresses, set upper bits of addr to KERNEL_START
  10.822 +	//   - for stack addresses, copy from input argument
  10.823 +	movl r18=KERNEL_START
  10.824 +	dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
  10.825 +	dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
  10.826 +	mov sp=r20
  10.827 +	;;
  10.828 +	or r3=r3,r18
  10.829 +	or r14=r14,r18
  10.830 +	;;
  10.831 +
  10.832 +	mov r18=ar.rnat			// save ar.rnat
  10.833 +	mov ar.bspstore=r19		// this steps on ar.rnat
  10.834 +	mov cr.iip=r3
  10.835 +	mov cr.ifs=r0
  10.836 +	;;
  10.837 +	mov ar.rnat=r18			// restore ar.rnat
  10.838 +	rfi				// must be last insn in group
  10.839 +	;;
  10.840 +1:	mov rp=r14
  10.841 +	br.ret.sptk.many rp
  10.842 +END(ia64_switch_mode_virt)
  10.843 +
  10.844 +GLOBAL_ENTRY(ia64_delay_loop)
  10.845 +	.prologue
  10.846 +{	nop 0			// work around GAS unwind info generation bug...
  10.847 +	.save ar.lc,r2
  10.848 +	mov r2=ar.lc
  10.849 +	.body
  10.850 +	;;
  10.851 +	mov ar.lc=r32
  10.852 +}
  10.853 +	;;
  10.854 +	// force loop to be 32-byte aligned (GAS bug means we cannot use .align
  10.855 +	// inside function body without corrupting unwind info).
  10.856 +{	nop 0 }
  10.857 +1:	br.cloop.sptk.few 1b
  10.858 +	;;
  10.859 +	mov ar.lc=r2
  10.860 +	br.ret.sptk.many rp
  10.861 +END(ia64_delay_loop)
  10.862 +
  10.863 +/*
  10.864 + * Return a CPU-local timestamp in nano-seconds.  This timestamp is
  10.865 + * NOT synchronized across CPUs its return value must never be
  10.866 + * compared against the values returned on another CPU.  The usage in
  10.867 + * kernel/sched.c ensures that.
  10.868 + *
  10.869 + * The return-value of sched_clock() is NOT supposed to wrap-around.
  10.870 + * If it did, it would cause some scheduling hiccups (at the worst).
  10.871 + * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
  10.872 + * that would happen only once every 5+ years.
  10.873 + *
  10.874 + * The code below basically calculates:
  10.875 + *
  10.876 + *   (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
  10.877 + *
  10.878 + * except that the multiplication and the shift are done with 128-bit
  10.879 + * intermediate precision so that we can produce a full 64-bit result.
  10.880 + */
  10.881 +GLOBAL_ENTRY(sched_clock)
  10.882 +#ifdef XEN
  10.883 +	movl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET
  10.884 +#else
  10.885 +	addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
  10.886 +#endif
  10.887 +	mov.m r9=ar.itc		// fetch cycle-counter				(35 cyc)
  10.888 +	;;
  10.889 +	ldf8 f8=[r8]
  10.890 +	;;
  10.891 +	setf.sig f9=r9		// certain to stall, so issue it _after_ ldf8...
  10.892 +	;;
  10.893 +	xmpy.lu f10=f9,f8	// calculate low 64 bits of 128-bit product	(4 cyc)
  10.894 +	xmpy.hu f11=f9,f8	// calculate high 64 bits of 128-bit product
  10.895 +	;;
  10.896 +	getf.sig r8=f10		//						(5 cyc)
  10.897 +	getf.sig r9=f11
  10.898 +	;;
  10.899 +	shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
  10.900 +	br.ret.sptk.many rp
  10.901 +END(sched_clock)
  10.902 +
  10.903 +GLOBAL_ENTRY(start_kernel_thread)
  10.904 +	.prologue
  10.905 +	.save rp, r0				// this is the end of the call-chain
  10.906 +	.body
  10.907 +	alloc r2 = ar.pfs, 0, 0, 2, 0
  10.908 +	mov out0 = r9
  10.909 +	mov out1 = r11;;
  10.910 +	br.call.sptk.many rp = kernel_thread_helper;;
  10.911 +	mov out0 = r8
  10.912 +	br.call.sptk.many rp = sys_exit;;
  10.913 +1:	br.sptk.few 1b				// not reached
  10.914 +END(start_kernel_thread)
  10.915 +
  10.916 +#ifdef CONFIG_IA64_BRL_EMU
  10.917 +
  10.918 +/*
  10.919 + *  Assembly routines used by brl_emu.c to set preserved register state.
  10.920 + */
  10.921 +
  10.922 +#define SET_REG(reg)				\
  10.923 + GLOBAL_ENTRY(ia64_set_##reg);			\
  10.924 +	alloc r16=ar.pfs,1,0,0,0;		\
  10.925 +	mov reg=r32;				\
  10.926 +	;;					\
  10.927 +	br.ret.sptk.many rp;			\
  10.928 + END(ia64_set_##reg)
  10.929 +
  10.930 +SET_REG(b1);
  10.931 +SET_REG(b2);
  10.932 +SET_REG(b3);
  10.933 +SET_REG(b4);
  10.934 +SET_REG(b5);
  10.935 +
  10.936 +#endif /* CONFIG_IA64_BRL_EMU */
  10.937 +
  10.938 +#ifdef CONFIG_SMP
  10.939 +	/*
  10.940 +	 * This routine handles spinlock contention.  It uses a non-standard calling
  10.941 +	 * convention to avoid converting leaf routines into interior routines.  Because
  10.942 +	 * of this special convention, there are several restrictions:
  10.943 +	 *
  10.944 +	 * - do not use gp relative variables, this code is called from the kernel
  10.945 +	 *   and from modules, r1 is undefined.
  10.946 +	 * - do not use stacked registers, the caller owns them.
  10.947 +	 * - do not use the scratch stack space, the caller owns it.
  10.948 +	 * - do not use any registers other than the ones listed below
  10.949 +	 *
  10.950 +	 * Inputs:
  10.951 +	 *   ar.pfs - saved CFM of caller
  10.952 +	 *   ar.ccv - 0 (and available for use)
  10.953 +	 *   r27    - flags from spin_lock_irqsave or 0.  Must be preserved.
  10.954 +	 *   r28    - available for use.
  10.955 +	 *   r29    - available for use.
  10.956 +	 *   r30    - available for use.
  10.957 +	 *   r31    - address of lock, available for use.
  10.958 +	 *   b6     - return address
  10.959 +	 *   p14    - available for use.
  10.960 +	 *   p15    - used to track flag status.
  10.961 +	 *
  10.962 +	 * If you patch this code to use more registers, do not forget to update
  10.963 +	 * the clobber lists for spin_lock() in include/asm-ia64/spinlock.h.
  10.964 +	 */
  10.965 +
  10.966 +#if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
  10.967 +
  10.968 +GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4)
  10.969 +	.prologue
  10.970 +	.save ar.pfs, r0	// this code effectively has a zero frame size
  10.971 +	.save rp, r28
  10.972 +	.body
  10.973 +	nop 0
  10.974 +	tbit.nz p15,p0=r27,IA64_PSR_I_BIT
  10.975 +	.restore sp		// pop existing prologue after next insn
  10.976 +	mov b6 = r28
  10.977 +	.prologue
  10.978 +	.save ar.pfs, r0
  10.979 +	.altrp b6
  10.980 +	.body
  10.981 +	;;
  10.982 +(p15)	ssm psr.i		// reenable interrupts if they were on
  10.983 +				// DavidM says that srlz.d is slow and is not required in this case
  10.984 +.wait:
  10.985 +	// exponential backoff, kdb, lockmeter etc. go in here
  10.986 +	hint @pause
  10.987 +	ld4 r30=[r31]		// don't use ld4.bias; if it's contended, we won't write the word
  10.988 +	nop 0
  10.989 +	;;
  10.990 +	cmp4.ne p14,p0=r30,r0
  10.991 +(p14)	br.cond.sptk.few .wait
  10.992 +(p15)	rsm psr.i		// disable interrupts if we reenabled them
  10.993 +	br.cond.sptk.few b6	// lock is now free, try to acquire
  10.994 +	.global ia64_spinlock_contention_pre3_4_end	// for kernprof
  10.995 +ia64_spinlock_contention_pre3_4_end:
  10.996 +END(ia64_spinlock_contention_pre3_4)
  10.997 +
  10.998 +#else
  10.999 +
 10.1000 +GLOBAL_ENTRY(ia64_spinlock_contention)
 10.1001 +	.prologue
 10.1002 +	.altrp b6
 10.1003 +	.body
 10.1004 +	tbit.nz p15,p0=r27,IA64_PSR_I_BIT
 10.1005 +	;;
 10.1006 +.wait:
 10.1007 +(p15)	ssm psr.i		// reenable interrupts if they were on
 10.1008 +				// DavidM says that srlz.d is slow and is not required in this case
 10.1009 +.wait2:
 10.1010 +	// exponential backoff, kdb, lockmeter etc. go in here
 10.1011 +	hint @pause
 10.1012 +	ld4 r30=[r31]		// don't use ld4.bias; if it's contended, we won't write the word
 10.1013 +	;;
 10.1014 +	cmp4.ne p14,p0=r30,r0
 10.1015 +	mov r30 = 1
 10.1016 +(p14)	br.cond.sptk.few .wait2
 10.1017 +(p15)	rsm psr.i		// disable interrupts if we reenabled them
 10.1018 +	;;
 10.1019 +	cmpxchg4.acq r30=[r31], r30, ar.ccv
 10.1020 +	;;
 10.1021 +	cmp4.ne p14,p0=r0,r30
 10.1022 +(p14)	br.cond.sptk.few .wait
 10.1023 +
 10.1024 +	br.ret.sptk.many b6	// lock is now taken
 10.1025 +END(ia64_spinlock_contention)
 10.1026 +
 10.1027 +#endif
 10.1028 +
 10.1029 +#endif /* CONFIG_SMP */
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/xen/arch/ia64/linux-xen/irq_ia64.c	Fri Aug 26 09:05:43 2005 +0000
    11.3 @@ -0,0 +1,381 @@
    11.4 +/*
    11.5 + * linux/arch/ia64/kernel/irq.c
    11.6 + *
    11.7 + * Copyright (C) 1998-2001 Hewlett-Packard Co
    11.8 + *	Stephane Eranian <eranian@hpl.hp.com>
    11.9 + *	David Mosberger-Tang <davidm@hpl.hp.com>
   11.10 + *
   11.11 + *  6/10/99: Updated to bring in sync with x86 version to facilitate
   11.12 + *	     support for SMP and different interrupt controllers.
   11.13 + *
   11.14 + * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
   11.15 + *                      PCI to vector allocation routine.
   11.16 + * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
   11.17 + *						Added CPU Hotplug handling for IPF.
   11.18 + */
   11.19 +
   11.20 +#include <linux/config.h>
   11.21 +#include <linux/module.h>
   11.22 +
   11.23 +#include <linux/jiffies.h>
   11.24 +#include <linux/errno.h>
   11.25 +#include <linux/init.h>
   11.26 +#include <linux/interrupt.h>
   11.27 +#include <linux/ioport.h>
   11.28 +#include <linux/kernel_stat.h>
   11.29 +#include <linux/slab.h>
   11.30 +#include <linux/ptrace.h>
   11.31 +#include <linux/random.h>	/* for rand_initialize_irq() */
   11.32 +#include <linux/signal.h>
   11.33 +#include <linux/smp.h>
   11.34 +#include <linux/smp_lock.h>
   11.35 +#include <linux/threads.h>
   11.36 +#include <linux/bitops.h>
   11.37 +
   11.38 +#include <asm/delay.h>
   11.39 +#include <asm/intrinsics.h>
   11.40 +#include <asm/io.h>
   11.41 +#include <asm/hw_irq.h>
   11.42 +#include <asm/machvec.h>
   11.43 +#include <asm/pgtable.h>
   11.44 +#include <asm/system.h>
   11.45 +
   11.46 +#ifdef CONFIG_PERFMON
   11.47 +# include <asm/perfmon.h>
   11.48 +#endif
   11.49 +
   11.50 +#define IRQ_DEBUG	0
   11.51 +
   11.52 +/* default base addr of IPI table */
   11.53 +void __iomem *ipi_base_addr = ((void __iomem *)
   11.54 +			       (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));
   11.55 +
   11.56 +/*
   11.57 + * Legacy IRQ to IA-64 vector translation table.
   11.58 + */
   11.59 +__u8 isa_irq_to_vector_map[16] = {
   11.60 +	/* 8259 IRQ translation, first 16 entries */
   11.61 +	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
   11.62 +	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
   11.63 +};
   11.64 +EXPORT_SYMBOL(isa_irq_to_vector_map);
   11.65 +
   11.66 +static unsigned long ia64_vector_mask[BITS_TO_LONGS(IA64_NUM_DEVICE_VECTORS)];
   11.67 +
   11.68 +int
   11.69 +assign_irq_vector (int irq)
   11.70 +{
   11.71 +	int pos, vector;
   11.72 + again:
   11.73 +	pos = find_first_zero_bit(ia64_vector_mask, IA64_NUM_DEVICE_VECTORS);
   11.74 +	vector = IA64_FIRST_DEVICE_VECTOR + pos;
   11.75 +	if (vector > IA64_LAST_DEVICE_VECTOR)
   11.76 +		/* XXX could look for sharable vectors instead of panic'ing... */
   11.77 +		panic("assign_irq_vector: out of interrupt vectors!");
   11.78 +	if (test_and_set_bit(pos, ia64_vector_mask))
   11.79 +		goto again;
   11.80 +	return vector;
   11.81 +}
   11.82 +
   11.83 +void
   11.84 +free_irq_vector (int vector)
   11.85 +{
   11.86 +	int pos;
   11.87 +
   11.88 +	if (vector < IA64_FIRST_DEVICE_VECTOR || vector > IA64_LAST_DEVICE_VECTOR)
   11.89 +		return;
   11.90 +
   11.91 +	pos = vector - IA64_FIRST_DEVICE_VECTOR;
   11.92 +	if (!test_and_clear_bit(pos, ia64_vector_mask))
   11.93 +		printk(KERN_WARNING "%s: double free!\n", __FUNCTION__);
   11.94 +}
   11.95 +
   11.96 +#ifdef CONFIG_SMP
   11.97 +#	define IS_RESCHEDULE(vec)	(vec == IA64_IPI_RESCHEDULE)
   11.98 +#else
   11.99 +#	define IS_RESCHEDULE(vec)	(0)
  11.100 +#endif
  11.101 +/*
  11.102 + * That's where the IVT branches when we get an external
  11.103 + * interrupt. This branches to the correct hardware IRQ handler via
  11.104 + * function ptr.
  11.105 + */
  11.106 +void
  11.107 +ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
  11.108 +{
  11.109 +	unsigned long saved_tpr;
  11.110 +
  11.111 +#if IRQ_DEBUG
  11.112 +#ifdef XEN
  11.113 +	xen_debug_irq(vector, regs);
  11.114 +#endif
  11.115 +	{
  11.116 +		unsigned long bsp, sp;
  11.117 +
  11.118 +		/*
  11.119 +		 * Note: if the interrupt happened while executing in
  11.120 +		 * the context switch routine (ia64_switch_to), we may
  11.121 +		 * get a spurious stack overflow here.  This is
  11.122 +		 * because the register and the memory stack are not
  11.123 +		 * switched atomically.
  11.124 +		 */
  11.125 +		bsp = ia64_getreg(_IA64_REG_AR_BSP);
  11.126 +		sp = ia64_getreg(_IA64_REG_SP);
  11.127 +
  11.128 +		if ((sp - bsp) < 1024) {
  11.129 +			static unsigned char count;
  11.130 +			static long last_time;
  11.131 +
  11.132 +			if (jiffies - last_time > 5*HZ)
  11.133 +				count = 0;
  11.134 +			if (++count < 5) {
  11.135 +				last_time = jiffies;
  11.136 +				printk("ia64_handle_irq: DANGER: less than "
  11.137 +				       "1KB of free stack space!!\n"
  11.138 +				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
  11.139 +			}
  11.140 +		}
  11.141 +	}
  11.142 +#endif /* IRQ_DEBUG */
  11.143 +
  11.144 +	/*
  11.145 +	 * Always set TPR to limit maximum interrupt nesting depth to
  11.146 +	 * 16 (without this, it would be ~240, which could easily lead
  11.147 +	 * to kernel stack overflows).
  11.148 +	 */
  11.149 +	irq_enter();
  11.150 +	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
  11.151 +	ia64_srlz_d();
  11.152 +	while (vector != IA64_SPURIOUS_INT_VECTOR) {
  11.153 +		if (!IS_RESCHEDULE(vector)) {
  11.154 +			ia64_setreg(_IA64_REG_CR_TPR, vector);
  11.155 +			ia64_srlz_d();
  11.156 +
  11.157 +#ifdef XEN
  11.158 +			if (!xen_do_IRQ(vector))
  11.159 +#endif
  11.160 +			__do_IRQ(local_vector_to_irq(vector), regs);
  11.161 +
  11.162 +			/*
  11.163 +			 * Disable interrupts and send EOI:
  11.164 +			 */
  11.165 +			local_irq_disable();
  11.166 +			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
  11.167 +		}
  11.168 +		ia64_eoi();
  11.169 +		vector = ia64_get_ivr();
  11.170 +	}
  11.171 +	/*
  11.172 +	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
  11.173 +	 * handler needs to be able to wait for further keyboard interrupts, which can't
  11.174 +	 * come through until ia64_eoi() has been done.
  11.175 +	 */
  11.176 +	irq_exit();
  11.177 +}
  11.178 +
  11.179 +#ifdef  CONFIG_VTI
  11.180 +#define vmx_irq_enter()		\
  11.181 +	add_preempt_count(HARDIRQ_OFFSET);
  11.182 +
  11.183 +/* Now softirq will be checked when leaving hypervisor, or else
  11.184 + * scheduler irq will be executed too early.
  11.185 + */
  11.186 +#define vmx_irq_exit(void)	\
  11.187 +	sub_preempt_count(HARDIRQ_OFFSET);
  11.188 +/*
  11.189 + * That's where the IVT branches when we get an external
  11.190 + * interrupt. This branches to the correct hardware IRQ handler via
  11.191 + * function ptr.
  11.192 + */
  11.193 +void
  11.194 +vmx_ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
  11.195 +{
  11.196 +	unsigned long saved_tpr;
  11.197 +	int	wake_dom0 = 0;
  11.198 +
  11.199 +
  11.200 +#if IRQ_DEBUG
  11.201 +	{
  11.202 +		unsigned long bsp, sp;
  11.203 +
  11.204 +		/*
  11.205 +		 * Note: if the interrupt happened while executing in
  11.206 +		 * the context switch routine (ia64_switch_to), we may
  11.207 +		 * get a spurious stack overflow here.  This is
  11.208 +		 * because the register and the memory stack are not
  11.209 +		 * switched atomically.
  11.210 +		 */
  11.211 +		bsp = ia64_getreg(_IA64_REG_AR_BSP);
  11.212 +		sp = ia64_getreg(_IA64_REG_AR_SP);
  11.213 +
  11.214 +		if ((sp - bsp) < 1024) {
  11.215 +			static unsigned char count;
  11.216 +			static long last_time;
  11.217 +
  11.218 +			if (jiffies - last_time > 5*HZ)
  11.219 +				count = 0;
  11.220 +			if (++count < 5) {
  11.221 +				last_time = jiffies;
  11.222 +				printk("ia64_handle_irq: DANGER: less than "
  11.223 +				       "1KB of free stack space!!\n"
  11.224 +				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
  11.225 +			}
  11.226 +		}
  11.227 +	}
  11.228 +#endif /* IRQ_DEBUG */
  11.229 +
  11.230 +	/*
  11.231 +	 * Always set TPR to limit maximum interrupt nesting depth to
  11.232 +	 * 16 (without this, it would be ~240, which could easily lead
  11.233 +	 * to kernel stack overflows).
  11.234 +	 */
  11.235 +	vmx_irq_enter();
  11.236 +	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
  11.237 +	ia64_srlz_d();
  11.238 +	while (vector != IA64_SPURIOUS_INT_VECTOR) {
  11.239 +	    if (!IS_RESCHEDULE(vector)) {
  11.240 +		ia64_setreg(_IA64_REG_CR_TPR, vector);
  11.241 +		ia64_srlz_d();
  11.242 +
  11.243 +		if (vector != IA64_TIMER_VECTOR) {
  11.244 +			/* FIXME: Leave IRQ re-route later */
  11.245 +			vmx_vcpu_pend_interrupt(dom0->vcpu[0],vector);
  11.246 +			wake_dom0 = 1;
  11.247 +		}
  11.248 +		else {	// FIXME: Handle Timer only now
  11.249 +			__do_IRQ(local_vector_to_irq(vector), regs);
  11.250 +		}
  11.251 +		
  11.252 +		/*
  11.253 +		 * Disable interrupts and send EOI:
  11.254 +		 */
  11.255 +		local_irq_disable();
  11.256 +		ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
  11.257 +	    }
  11.258 +	    else {
  11.259 +                printf("Oops: RESCHEDULE IPI absorbed by HV\n");
  11.260 +            }
  11.261 +	    ia64_eoi();
  11.262 +	    vector = ia64_get_ivr();
  11.263 +	}
  11.264 +	/*
  11.265 +	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
  11.266 +	 * handler needs to be able to wait for further keyboard interrupts, which can't
  11.267 +	 * come through until ia64_eoi() has been done.
  11.268 +	 */
  11.269 +	vmx_irq_exit();
  11.270 +	if ( wake_dom0 && current != dom0 ) 
  11.271 +		domain_wake(dom0->vcpu[0]);
  11.272 +}
  11.273 +#endif
  11.274 +
  11.275 +
  11.276 +#ifdef CONFIG_HOTPLUG_CPU
  11.277 +/*
  11.278 + * This function emulates a interrupt processing when a cpu is about to be
  11.279 + * brought down.
  11.280 + */
  11.281 +void ia64_process_pending_intr(void)
  11.282 +{
  11.283 +	ia64_vector vector;
  11.284 +	unsigned long saved_tpr;
  11.285 +	extern unsigned int vectors_in_migration[NR_IRQS];
  11.286 +
  11.287 +	vector = ia64_get_ivr();
  11.288 +
  11.289 +	 irq_enter();
  11.290 +	 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
  11.291 +	 ia64_srlz_d();
  11.292 +
  11.293 +	 /*
  11.294 +	  * Perform normal interrupt style processing
  11.295 +	  */
  11.296 +	while (vector != IA64_SPURIOUS_INT_VECTOR) {
  11.297 +		if (!IS_RESCHEDULE(vector)) {
  11.298 +			ia64_setreg(_IA64_REG_CR_TPR, vector);
  11.299 +			ia64_srlz_d();
  11.300 +
  11.301 +			/*
  11.302 +			 * Now try calling normal ia64_handle_irq as it would have got called
  11.303 +			 * from a real intr handler. Try passing null for pt_regs, hopefully
  11.304 +			 * it will work. I hope it works!.
  11.305 +			 * Probably could shared code.
  11.306 +			 */
  11.307 +			vectors_in_migration[local_vector_to_irq(vector)]=0;
  11.308 +			__do_IRQ(local_vector_to_irq(vector), NULL);
  11.309 +
  11.310 +			/*
  11.311 +			 * Disable interrupts and send EOI
  11.312 +			 */
  11.313 +			local_irq_disable();
  11.314 +			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
  11.315 +		}
  11.316 +		ia64_eoi();
  11.317 +		vector = ia64_get_ivr();
  11.318 +	}
  11.319 +	irq_exit();
  11.320 +}
  11.321 +#endif
  11.322 +
  11.323 +
  11.324 +#ifdef CONFIG_SMP
  11.325 +extern irqreturn_t handle_IPI (int irq, void *dev_id, struct pt_regs *regs);
  11.326 +
  11.327 +static struct irqaction ipi_irqaction = {
  11.328 +	.handler =	handle_IPI,
  11.329 +	.flags =	SA_INTERRUPT,
  11.330 +	.name =		"IPI"
  11.331 +};
  11.332 +#endif
  11.333 +
  11.334 +void
  11.335 +register_percpu_irq (ia64_vector vec, struct irqaction *action)
  11.336 +{
  11.337 +	irq_desc_t *desc;
  11.338 +	unsigned int irq;
  11.339 +
  11.340 +	for (irq = 0; irq < NR_IRQS; ++irq)
  11.341 +		if (irq_to_vector(irq) == vec) {
  11.342 +			desc = irq_descp(irq);
  11.343 +			desc->status |= IRQ_PER_CPU;
  11.344 +			desc->handler = &irq_type_ia64_lsapic;
  11.345 +			if (action)
  11.346 +				setup_irq(irq, action);
  11.347 +		}
  11.348 +}
  11.349 +
  11.350 +void __init
  11.351 +init_IRQ (void)
  11.352 +{
  11.353 +	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
  11.354 +#ifdef CONFIG_SMP
  11.355 +	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
  11.356 +#endif
  11.357 +#ifdef CONFIG_PERFMON
  11.358 +	pfm_init_percpu();
  11.359 +#endif
  11.360 +	platform_irq_init();
  11.361 +}
  11.362 +
  11.363 +void
  11.364 +ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
  11.365 +{
  11.366 +	void __iomem *ipi_addr;
  11.367 +	unsigned long ipi_data;
  11.368 +	unsigned long phys_cpu_id;
  11.369 +
  11.370 +#ifdef CONFIG_SMP
  11.371 +	phys_cpu_id = cpu_physical_id(cpu);
  11.372 +#else
  11.373 +	phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
  11.374 +#endif
  11.375 +
  11.376 +	/*
  11.377 +	 * cpu number is in 8bit ID and 8bit EID
  11.378 +	 */
  11.379 +
  11.380 +	ipi_data = (delivery_mode << 8) | (vector & 0xff);
  11.381 +	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));
  11.382 +
  11.383 +	writeq(ipi_data, ipi_addr);
  11.384 +}
    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/xen/arch/ia64/linux-xen/mm_contig.c	Fri Aug 26 09:05:43 2005 +0000
    12.3 @@ -0,0 +1,305 @@
    12.4 +/*
    12.5 + * This file is subject to the terms and conditions of the GNU General Public
    12.6 + * License.  See the file "COPYING" in the main directory of this archive
    12.7 + * for more details.
    12.8 + *
    12.9 + * Copyright (C) 1998-2003 Hewlett-Packard Co
   12.10 + *	David Mosberger-Tang <davidm@hpl.hp.com>
   12.11 + *	Stephane Eranian <eranian@hpl.hp.com>
   12.12 + * Copyright (C) 2000, Rohit Seth <rohit.seth@intel.com>
   12.13 + * Copyright (C) 1999 VA Linux Systems
   12.14 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
   12.15 + * Copyright (C) 2003 Silicon Graphics, Inc. All rights reserved.
   12.16 + *
   12.17 + * Routines used by ia64 machines with contiguous (or virtually contiguous)
   12.18 + * memory.
   12.19 + */
   12.20 +#include <linux/config.h>
   12.21 +#include <linux/bootmem.h>
   12.22 +#include <linux/efi.h>
   12.23 +#include <linux/mm.h>
   12.24 +#include <linux/swap.h>
   12.25 +
   12.26 +#include <asm/meminit.h>
   12.27 +#include <asm/pgalloc.h>
   12.28 +#include <asm/pgtable.h>
   12.29 +#include <asm/sections.h>
   12.30 +#include <asm/mca.h>
   12.31 +
   12.32 +#ifdef CONFIG_VIRTUAL_MEM_MAP
   12.33 +static unsigned long num_dma_physpages;
   12.34 +#endif
   12.35 +
   12.36 +/**
   12.37 + * show_mem - display a memory statistics summary
   12.38 + *
   12.39 + * Just walks the pages in the system and describes where they're allocated.
   12.40 + */
   12.41 +#ifndef XEN
   12.42 +void
   12.43 +show_mem (void)
   12.44 +{
   12.45 +	int i, total = 0, reserved = 0;
   12.46 +	int shared = 0, cached = 0;
   12.47 +
   12.48 +	printk("Mem-info:\n");
   12.49 +	show_free_areas();
   12.50 +
   12.51 +	printk("Free swap:       %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
   12.52 +	i = max_mapnr;
   12.53 +	while (i-- > 0) {
   12.54 +		if (!pfn_valid(i))
   12.55 +			continue;
   12.56 +		total++;
   12.57 +		if (PageReserved(mem_map+i))
   12.58 +			reserved++;
   12.59 +		else if (PageSwapCache(mem_map+i))
   12.60 +			cached++;
   12.61 +		else if (page_count(mem_map + i))
   12.62 +			shared += page_count(mem_map + i) - 1;
   12.63 +	}
   12.64 +	printk("%d pages of RAM\n", total);
   12.65 +	printk("%d reserved pages\n", reserved);
   12.66 +	printk("%d pages shared\n", shared);
   12.67 +	printk("%d pages swap cached\n", cached);
   12.68 +	printk("%ld pages in page table cache\n", pgtable_cache_size);
   12.69 +}
   12.70 +#endif
   12.71 +
   12.72 +/* physical address where the bootmem map is located */
   12.73 +unsigned long bootmap_start;
   12.74 +
   12.75 +/**
   12.76 + * find_max_pfn - adjust the maximum page number callback
   12.77 + * @start: start of range
   12.78 + * @end: end of range
   12.79 + * @arg: address of pointer to global max_pfn variable
   12.80 + *
   12.81 + * Passed as a callback function to efi_memmap_walk() to determine the highest
   12.82 + * available page frame number in the system.
   12.83 + */
   12.84 +int
   12.85 +find_max_pfn (unsigned long start, unsigned long end, void *arg)
   12.86 +{
   12.87 +	unsigned long *max_pfnp = arg, pfn;
   12.88 +
   12.89 +	pfn = (PAGE_ALIGN(end - 1) - PAGE_OFFSET) >> PAGE_SHIFT;
   12.90 +	if (pfn > *max_pfnp)
   12.91 +		*max_pfnp = pfn;
   12.92 +	return 0;
   12.93 +}
   12.94 +
   12.95 +/**
   12.96 + * find_bootmap_location - callback to find a memory area for the bootmap
   12.97 + * @start: start of region
   12.98 + * @end: end of region
   12.99 + * @arg: unused callback data
  12.100 + *
  12.101 + * Find a place to put the bootmap and return its starting address in
  12.102 + * bootmap_start.  This address must be page-aligned.
  12.103 + */
  12.104 +int
  12.105 +find_bootmap_location (unsigned long start, unsigned long end, void *arg)
  12.106 +{
  12.107 +	unsigned long needed = *(unsigned long *)arg;
  12.108 +	unsigned long range_start, range_end, free_start;
  12.109 +	int i;
  12.110 +
  12.111 +#if IGNORE_PFN0
  12.112 +	if (start == PAGE_OFFSET) {
  12.113 +		start += PAGE_SIZE;
  12.114 +		if (start >= end)
  12.115 +			return 0;
  12.116 +	}
  12.117 +#endif
  12.118 +
  12.119 +	free_start = PAGE_OFFSET;
  12.120 +
  12.121 +	for (i = 0; i < num_rsvd_regions; i++) {
  12.122 +		range_start = max(start, free_start);
  12.123 +		range_end   = min(end, rsvd_region[i].start & PAGE_MASK);
  12.124 +
  12.125 +		free_start = PAGE_ALIGN(rsvd_region[i].end);
  12.126 +
  12.127 +		if (range_end <= range_start)
  12.128 +			continue; /* skip over empty range */
  12.129 +
  12.130 +		if (range_end - range_start >= needed) {
  12.131 +			bootmap_start = __pa(range_start);
  12.132 +			return -1;	/* done */
  12.133 +		}
  12.134 +
  12.135 +		/* nothing more available in this segment */
  12.136 +		if (range_end == end)
  12.137 +			return 0;
  12.138 +	}
  12.139 +	return 0;
  12.140 +}
  12.141 +
  12.142 +/**
  12.143 + * find_memory - setup memory map
  12.144 + *
  12.145 + * Walk the EFI memory map and find usable memory for the system, taking
  12.146 + * into account reserved areas.
  12.147 + */
  12.148 +#ifndef XEN
  12.149 +void
  12.150 +find_memory (void)
  12.151 +{
  12.152 +	unsigned long bootmap_size;
  12.153 +
  12.154 +	reserve_memory();
  12.155 +
  12.156 +	/* first find highest page frame number */
  12.157 +	max_pfn = 0;
  12.158 +	efi_memmap_walk(find_max_pfn, &max_pfn);
  12.159 +
  12.160 +	/* how many bytes to cover all the pages */
  12.161 +	bootmap_size = bootmem_bootmap_pages(max_pfn) << PAGE_SHIFT;
  12.162 +
  12.163 +	/* look for a location to hold the bootmap */
  12.164 +	bootmap_start = ~0UL;
  12.165 +	efi_memmap_walk(find_bootmap_location, &bootmap_size);
  12.166 +	if (bootmap_start == ~0UL)
  12.167 +		panic("Cannot find %ld bytes for bootmap\n", bootmap_size);
  12.168 +
  12.169 +	bootmap_size = init_bootmem(bootmap_start >> PAGE_SHIFT, max_pfn);
  12.170 +
  12.171 +	/* Free all available memory, then mark bootmem-map as being in use. */
  12.172 +	efi_memmap_walk(filter_rsvd_memory, free_bootmem);
  12.173 +	reserve_bootmem(bootmap_start, bootmap_size);
  12.174 +
  12.175 +	find_initrd();
  12.176 +}
  12.177 +#endif
  12.178 +
  12.179 +#ifdef CONFIG_SMP
  12.180 +/**
  12.181 + * per_cpu_init - setup per-cpu variables
  12.182 + *
  12.183 + * Allocate and setup per-cpu data areas.
  12.184 + */
  12.185 +void *
  12.186 +per_cpu_init (void)
  12.187 +{
  12.188 +	void *cpu_data;
  12.189 +	int cpu;
  12.190 +
  12.191 +	/*
  12.192 +	 * get_free_pages() cannot be used before cpu_init() done.  BSP
  12.193 +	 * allocates "NR_CPUS" pages for all CPUs to avoid that AP calls
  12.194 +	 * get_zeroed_page().
  12.195 +	 */
  12.196 +	if (smp_processor_id() == 0) {
  12.197 +		cpu_data = __alloc_bootmem(PERCPU_PAGE_SIZE * NR_CPUS,
  12.198 +					   PERCPU_PAGE_SIZE, __pa(MAX_DMA_ADDRESS));
  12.199 +		for (cpu = 0; cpu < NR_CPUS; cpu++) {
  12.200 +			memcpy(cpu_data, __phys_per_cpu_start, __per_cpu_end - __per_cpu_start);
  12.201 +			__per_cpu_offset[cpu] = (char *) cpu_data - __per_cpu_start;
  12.202 +			cpu_data += PERCPU_PAGE_SIZE;
  12.203 +			per_cpu(local_per_cpu_offset, cpu) = __per_cpu_offset[cpu];
  12.204 +		}
  12.205 +	}
  12.206 +	return __per_cpu_start + __per_cpu_offset[smp_processor_id()];
  12.207 +}
  12.208 +#endif /* CONFIG_SMP */
  12.209 +
  12.210 +static int
  12.211 +count_pages (u64 start, u64 end, void *arg)
  12.212 +{
  12.213 +	unsigned long *count = arg;
  12.214 +
  12.215 +	*count += (end - start) >> PAGE_SHIFT;
  12.216 +	return 0;
  12.217 +}
  12.218 +
  12.219 +#ifdef CONFIG_VIRTUAL_MEM_MAP
  12.220 +static int
  12.221 +count_dma_pages (u64 start, u64 end, void *arg)
  12.222 +{
  12.223 +	unsigned long *count = arg;
  12.224 +
  12.225 +	if (start < MAX_DMA_ADDRESS)
  12.226 +		*count += (min(end, MAX_DMA_ADDRESS) - start) >> PAGE_SHIFT;
  12.227 +	return 0;
  12.228 +}
  12.229 +#endif
  12.230 +
  12.231 +/*
  12.232 + * Set up the page tables.
  12.233 + */
  12.234 +
  12.235 +#ifndef XEN
  12.236 +void
  12.237 +paging_init (void)
  12.238 +{
  12.239 +	unsigned long max_dma;
  12.240 +	unsigned long zones_size[MAX_NR_ZONES];
  12.241 +#ifdef CONFIG_VIRTUAL_MEM_MAP
  12.242 +	unsigned long zholes_size[MAX_NR_ZONES];
  12.243 +	unsigned long max_gap;
  12.244 +#endif
  12.245 +
  12.246 +	/* initialize mem_map[] */
  12.247 +
  12.248 +	memset(zones_size, 0, sizeof(zones_size));
  12.249 +
  12.250 +	num_physpages = 0;
  12.251 +	efi_memmap_walk(count_pages, &num_physpages);
  12.252 +
  12.253 +	max_dma = virt_to_phys((void *) MAX_DMA_ADDRESS) >> PAGE_SHIFT;
  12.254 +
  12.255 +#ifdef CONFIG_VIRTUAL_MEM_MAP
  12.256 +	memset(zholes_size, 0, sizeof(zholes_size));
  12.257 +
  12.258 +	num_dma_physpages = 0;
  12.259 +	efi_memmap_walk(count_dma_pages, &num_dma_physpages);
  12.260 +
  12.261 +	if (max_low_pfn < max_dma) {
  12.262 +		zones_size[ZONE_DMA] = max_low_pfn;
  12.263 +		zholes_size[ZONE_DMA] = max_low_pfn - num_dma_physpages;
  12.264 +	} else {
  12.265 +		zones_size[ZONE_DMA] = max_dma;
  12.266 +		zholes_size[ZONE_DMA] = max_dma - num_dma_physpages;
  12.267 +		if (num_physpages > num_dma_physpages) {
  12.268 +			zones_size[ZONE_NORMAL] = max_low_pfn - max_dma;
  12.269 +			zholes_size[ZONE_NORMAL] =
  12.270 +				((max_low_pfn - max_dma) -
  12.271 +				 (num_physpages - num_dma_physpages));
  12.272 +		}
  12.273 +	}
  12.274 +
  12.275 +	max_gap = 0;
  12.276 +	efi_memmap_walk(find_largest_hole, (u64 *)&max_gap);
  12.277 +	if (max_gap < LARGE_GAP) {
  12.278 +		vmem_map = (struct page *) 0;
  12.279 +		free_area_init_node(0, &contig_page_data, zones_size, 0,
  12.280 +				    zholes_size);
  12.281 +	} else {
  12.282 +		unsigned long map_size;
  12.283 +
  12.284 +		/* allocate virtual_mem_map */
  12.285 +
  12.286 +		map_size = PAGE_ALIGN(max_low_pfn * sizeof(struct page));
  12.287 +		vmalloc_end -= map_size;
  12.288 +		vmem_map = (struct page *) vmalloc_end;
  12.289 +		efi_memmap_walk(create_mem_map_page_table, NULL);
  12.290 +
  12.291 +		mem_map = contig_page_data.node_mem_map = vmem_map;
  12.292 +		free_area_init_node(0, &contig_page_data, zones_size,
  12.293 +				    0, zholes_size);
  12.294 +
  12.295 +		printk("Virtual mem_map starts at 0x%p\n", mem_map);
  12.296 +	}
  12.297 +#else /* !CONFIG_VIRTUAL_MEM_MAP */
  12.298 +	if (max_low_pfn < max_dma)
  12.299 +		zones_size[ZONE_DMA] = max_low_pfn;
  12.300 +	else {
  12.301 +		zones_size[ZONE_DMA] = max_dma;
  12.302 +		zones_size[ZONE_NORMAL] = max_low_pfn - max_dma;
  12.303 +	}
  12.304 +	free_area_init(zones_size);
  12.305 +#endif /* !CONFIG_VIRTUAL_MEM_MAP */
  12.306 +	zero_page_memmap_ptr = virt_to_page(ia64_imva(empty_zero_page));
  12.307 +}
  12.308 +#endif /* !CONFIG_XEN */
    13.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.2 +++ b/xen/arch/ia64/linux-xen/pal.S	Fri Aug 26 09:05:43 2005 +0000
    13.3 @@ -0,0 +1,310 @@
    13.4 +/*
    13.5 + * PAL Firmware support
    13.6 + * IA-64 Processor Programmers Reference Vol 2
    13.7 + *
    13.8 + * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
    13.9 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
   13.10 + * Copyright (C) 1999-2001, 2003 Hewlett-Packard Co
   13.11 + *	David Mosberger <davidm@hpl.hp.com>
   13.12 + *	Stephane Eranian <eranian@hpl.hp.com>
   13.13 + *
   13.14 + * 05/22/2000 eranian Added support for stacked register calls
   13.15 + * 05/24/2000 eranian Added support for physical mode static calls
   13.16 + */
   13.17 +
   13.18 +#include <asm/asmmacro.h>
   13.19 +#include <asm/processor.h>
   13.20 +
   13.21 +	.data
   13.22 +pal_entry_point:
   13.23 +	data8 ia64_pal_default_handler
   13.24 +	.text
   13.25 +
   13.26 +/*
   13.27 + * Set the PAL entry point address.  This could be written in C code, but we do it here
   13.28 + * to keep it all in one module (besides, it's so trivial that it's
   13.29 + * not a big deal).
   13.30 + *
   13.31 + * in0		Address of the PAL entry point (text address, NOT a function descriptor).
   13.32 + */
   13.33 +GLOBAL_ENTRY(ia64_pal_handler_init)
   13.34 +	alloc r3=ar.pfs,1,0,0,0
   13.35 +	movl r2=pal_entry_point
   13.36 +	;;
   13.37 +	st8 [r2]=in0
   13.38 +	br.ret.sptk.many rp
   13.39 +END(ia64_pal_handler_init)
   13.40 +
   13.41 +/*
   13.42 + * Default PAL call handler.  This needs to be coded in assembly because it uses
   13.43 + * the static calling convention, i.e., the RSE may not be used and calls are
   13.44 + * done via "br.cond" (not "br.call").
   13.45 + */
   13.46 +GLOBAL_ENTRY(ia64_pal_default_handler)
   13.47 +	mov r8=-1
   13.48 +	br.cond.sptk.many rp
   13.49 +END(ia64_pal_default_handler)
   13.50 +
   13.51 +/*
   13.52 + * Make a PAL call using the static calling convention.
   13.53 + *
   13.54 + * in0         Index of PAL service
   13.55 + * in1 - in3   Remaining PAL arguments
   13.56 + * in4	       1 ==> clear psr.ic,  0 ==> don't clear psr.ic
   13.57 + *
   13.58 + */
   13.59 +GLOBAL_ENTRY(ia64_pal_call_static)
   13.60 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
   13.61 +	alloc loc1 = ar.pfs,5,5,0,0
   13.62 +	movl loc2 = pal_entry_point
   13.63 +1:	{
   13.64 +	  mov r28 = in0
   13.65 +	  mov r29 = in1
   13.66 +	  mov r8 = ip
   13.67 +	}
   13.68 +	;;
   13.69 +	ld8 loc2 = [loc2]		// loc2 <- entry point
   13.70 +	tbit.nz p6,p7 = in4, 0
   13.71 +	adds r8 = 1f-1b,r8
   13.72 +	mov loc4=ar.rsc			// save RSE configuration
   13.73 +	;;
   13.74 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   13.75 +	mov loc3 = psr
   13.76 +	mov loc0 = rp
   13.77 +	.body
   13.78 +	mov r30 = in2
   13.79 +
   13.80 +(p6)	rsm psr.i | psr.ic
   13.81 +	mov r31 = in3
   13.82 +	mov b7 = loc2
   13.83 +
   13.84 +(p7)	rsm psr.i
   13.85 +	;;
   13.86 +(p6)	srlz.i
   13.87 +	mov rp = r8
   13.88 +	br.cond.sptk.many b7
   13.89 +1:	mov psr.l = loc3
   13.90 +	mov ar.rsc = loc4		// restore RSE configuration
   13.91 +	mov ar.pfs = loc1
   13.92 +	mov rp = loc0
   13.93 +	;;
   13.94 +	srlz.d				// seralize restoration of psr.l
   13.95 +	br.ret.sptk.many b0
   13.96 +END(ia64_pal_call_static)
   13.97 +
   13.98 +/*
   13.99 + * Make a PAL call using the stacked registers calling convention.
  13.100 + *
  13.101 + * Inputs:
  13.102 + * 	in0         Index of PAL service
  13.103 + * 	in2 - in3   Remaning PAL arguments
  13.104 + */
  13.105 +GLOBAL_ENTRY(ia64_pal_call_stacked)
  13.106 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
  13.107 +	alloc loc1 = ar.pfs,4,4,4,0
  13.108 +	movl loc2 = pal_entry_point
  13.109 +
  13.110 +	mov r28  = in0			// Index MUST be copied to r28
  13.111 +	mov out0 = in0			// AND in0 of PAL function
  13.112 +	mov loc0 = rp
  13.113 +	.body
  13.114 +	;;
  13.115 +	ld8 loc2 = [loc2]		// loc2 <- entry point
  13.116 +	mov out1 = in1
  13.117 +	mov out2 = in2
  13.118 +	mov out3 = in3
  13.119 +	mov loc3 = psr
  13.120 +	;;
  13.121 +	rsm psr.i
  13.122 +	mov b7 = loc2
  13.123 +	;;
  13.124 +	br.call.sptk.many rp=b7		// now make the call
  13.125 +.ret0:	mov psr.l  = loc3
  13.126 +	mov ar.pfs = loc1
  13.127 +	mov rp = loc0
  13.128 +	;;
  13.129 +	srlz.d				// serialize restoration of psr.l
  13.130 +	br.ret.sptk.many b0
  13.131 +END(ia64_pal_call_stacked)
  13.132 +
  13.133 +/*
  13.134 + * Make a physical mode PAL call using the static registers calling convention.
  13.135 + *
  13.136 + * Inputs:
  13.137 + * 	in0         Index of PAL service
  13.138 + * 	in2 - in3   Remaning PAL arguments
  13.139 + *
  13.140 + * PSR_LP, PSR_TB, PSR_ID, PSR_DA are never set by the kernel.
  13.141 + * So we don't need to clear them.
  13.142 + */
  13.143 +#define PAL_PSR_BITS_TO_CLEAR							\
  13.144 +	(IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT  | IA64_PSR_DB | IA64_PSR_RT |	\
  13.145 +	 IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED |		\
  13.146 +	 IA64_PSR_DFL | IA64_PSR_DFH)
  13.147 +
  13.148 +#define PAL_PSR_BITS_TO_SET							\
  13.149 +	(IA64_PSR_BN)
  13.150 +
  13.151 +
  13.152 +GLOBAL_ENTRY(ia64_pal_call_phys_static)
  13.153 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
  13.154 +	alloc loc1 = ar.pfs,4,7,0,0
  13.155 +	movl loc2 = pal_entry_point
  13.156 +1:	{
  13.157 +	  mov r28  = in0		// copy procedure index
  13.158 +	  mov r8   = ip			// save ip to compute branch
  13.159 +	  mov loc0 = rp			// save rp
  13.160 +	}
  13.161 +	.body
  13.162 +	;;
  13.163 +	ld8 loc2 = [loc2]		// loc2 <- entry point
  13.164 +	mov r29  = in1			// first argument
  13.165 +	mov r30  = in2			// copy arg2
  13.166 +	mov r31  = in3			// copy arg3
  13.167 +	;;
  13.168 +	mov loc3 = psr			// save psr
  13.169 +	adds r8  = 1f-1b,r8		// calculate return address for call
  13.170 +	;;
  13.171 +	mov loc4=ar.rsc			// save RSE configuration
  13.172 +#ifdef XEN
  13.173 +	dep.z loc2=loc2,0,60		// convert pal entry point to physical
  13.174 +#else // XEN
  13.175 +	dep.z loc2=loc2,0,61		// convert pal entry point to physical
  13.176 +#endif // XEN
  13.177 +	tpa r8=r8			// convert rp to physical
  13.178 +	;;
  13.179 +	mov b7 = loc2			// install target to branch reg
  13.180 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
  13.181 +	movl r16=PAL_PSR_BITS_TO_CLEAR
  13.182 +	movl r17=PAL_PSR_BITS_TO_SET
  13.183 +	;;
  13.184 +	or loc3=loc3,r17		// add in psr the bits to set
  13.185 +	;;
  13.186 +	andcm r16=loc3,r16		// removes bits to clear from psr
  13.187 +	br.call.sptk.many rp=ia64_switch_mode_phys
  13.188 +.ret1:	mov rp = r8			// install return address (physical)
  13.189 +	mov loc5 = r19
  13.190 +	mov loc6 = r20
  13.191 +	br.cond.sptk.many b7
  13.192 +1:
  13.193 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
  13.194 +	mov r16=loc3			// r16= original psr
  13.195 +	mov r19=loc5
  13.196 +	mov r20=loc6
  13.197 +	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
  13.198 +.ret2:
  13.199 +	mov psr.l = loc3		// restore init PSR
  13.200 +
  13.201 +	mov ar.pfs = loc1
  13.202 +	mov rp = loc0
  13.203 +	;;
  13.204 +	mov ar.rsc=loc4			// restore RSE configuration
  13.205 +	srlz.d				// seralize restoration of psr.l
  13.206 +	br.ret.sptk.many b0
  13.207 +END(ia64_pal_call_phys_static)
  13.208 +
  13.209 +/*
  13.210 + * Make a PAL call using the stacked registers in physical mode.
  13.211 + *
  13.212 + * Inputs:
  13.213 + * 	in0         Index of PAL service
  13.214 + * 	in2 - in3   Remaning PAL arguments
  13.215 + */
  13.216 +GLOBAL_ENTRY(ia64_pal_call_phys_stacked)
  13.217 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
  13.218 +	alloc	loc1 = ar.pfs,5,7,4,0
  13.219 +	movl	loc2 = pal_entry_point
  13.220 +1:	{
  13.221 +	  mov r28  = in0		// copy procedure index
  13.222 +	  mov loc0 = rp		// save rp
  13.223 +	}
  13.224 +	.body
  13.225 +	;;
  13.226 +	ld8 loc2 = [loc2]		// loc2 <- entry point
  13.227 +	mov out0 = in0		// first argument
  13.228 +	mov out1 = in1		// copy arg2
  13.229 +	mov out2 = in2		// copy arg3
  13.230 +	mov out3 = in3		// copy arg3
  13.231 +	;;
  13.232 +	mov loc3 = psr		// save psr
  13.233 +	;;
  13.234 +	mov loc4=ar.rsc			// save RSE configuration
  13.235 +#ifdef XEN
  13.236 +	dep.z loc2=loc2,0,60		// convert pal entry point to physical
  13.237 +#else // XEN
  13.238 +	dep.z loc2=loc2,0,61		// convert pal entry point to physical
  13.239 +#endif // XEN
  13.240 +	;;
  13.241 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
  13.242 +	movl r16=PAL_PSR_BITS_TO_CLEAR
  13.243 +	movl r17=PAL_PSR_BITS_TO_SET
  13.244 +	;;
  13.245 +	or loc3=loc3,r17		// add in psr the bits to set
  13.246 +	mov b7 = loc2			// install target to branch reg
  13.247 +	;;
  13.248 +	andcm r16=loc3,r16		// removes bits to clear from psr
  13.249 +	br.call.sptk.many rp=ia64_switch_mode_phys
  13.250 +.ret6:
  13.251 +	mov loc5 = r19
  13.252 +	mov loc6 = r20
  13.253 +	br.call.sptk.many rp=b7		// now make the call
  13.254 +.ret7:
  13.255 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
  13.256 +	mov r16=loc3			// r16= original psr
  13.257 +	mov r19=loc5
  13.258 +	mov r20=loc6
  13.259 +	br.call.sptk.many rp=ia64_switch_mode_virt	// return to virtual mode
  13.260 +
  13.261 +.ret8:	mov psr.l  = loc3		// restore init PSR
  13.262 +	mov ar.pfs = loc1
  13.263 +	mov rp = loc0
  13.264 +	;;
  13.265 +	mov ar.rsc=loc4			// restore RSE configuration
  13.266 +	srlz.d				// seralize restoration of psr.l
  13.267 +	br.ret.sptk.many b0
  13.268 +END(ia64_pal_call_phys_stacked)
  13.269 +
  13.270 +/*
  13.271 + * Save scratch fp scratch regs which aren't saved in pt_regs already (fp10-fp15).
  13.272 + *
  13.273 + * NOTE: We need to do this since firmware (SAL and PAL) may use any of the scratch
  13.274 + * regs fp-low partition.
  13.275 + *
  13.276 + * Inputs:
  13.277 + *      in0	Address of stack storage for fp regs
  13.278 + */
  13.279 +GLOBAL_ENTRY(ia64_save_scratch_fpregs)
  13.280 +	alloc r3=ar.pfs,1,0,0,0
  13.281 +	add r2=16,in0
  13.282 +	;;
  13.283 +	stf.spill [in0] = f10,32
  13.284 +	stf.spill [r2]  = f11,32
  13.285 +	;;
  13.286 +	stf.spill [in0] = f12,32
  13.287 +	stf.spill [r2]  = f13,32
  13.288 +	;;
  13.289 +	stf.spill [in0] = f14,32
  13.290 +	stf.spill [r2]  = f15,32
  13.291 +	br.ret.sptk.many rp
  13.292 +END(ia64_save_scratch_fpregs)
  13.293 +
  13.294 +/*
  13.295 + * Load scratch fp scratch regs (fp10-fp15)
  13.296 + *
  13.297 + * Inputs:
  13.298 + *      in0	Address of stack storage for fp regs
  13.299 + */
  13.300 +GLOBAL_ENTRY(ia64_load_scratch_fpregs)
  13.301 +	alloc r3=ar.pfs,1,0,0,0
  13.302 +	add r2=16,in0
  13.303 +	;;
  13.304 +	ldf.fill  f10 = [in0],32
  13.305 +	ldf.fill  f11 = [r2],32
  13.306 +	;;
  13.307 +	ldf.fill  f12 = [in0],32
  13.308 +	ldf.fill  f13 = [r2],32
  13.309 +	;;
  13.310 +	ldf.fill  f14 = [in0],32
  13.311 +	ldf.fill  f15 = [r2],32
  13.312 +	br.ret.sptk.many rp
  13.313 +END(ia64_load_scratch_fpregs)
    14.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.2 +++ b/xen/arch/ia64/linux-xen/setup.c	Fri Aug 26 09:05:43 2005 +0000
    14.3 @@ -0,0 +1,772 @@
    14.4 +/*
    14.5 + * Architecture-specific setup.
    14.6 + *
    14.7 + * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
    14.8 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    14.9 + *	Stephane Eranian <eranian@hpl.hp.com>
   14.10 + * Copyright (C) 2000, Rohit Seth <rohit.seth@intel.com>
   14.11 + * Copyright (C) 1999 VA Linux Systems
   14.12 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
   14.13 + *
   14.14 + * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
   14.15 + * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
   14.16 + * 03/31/00 R.Seth	cpu_initialized and current->processor fixes
   14.17 + * 02/04/00 D.Mosberger	some more get_cpuinfo fixes...
   14.18 + * 02/01/00 R.Seth	fixed get_cpuinfo for SMP
   14.19 + * 01/07/99 S.Eranian	added the support for command line argument
   14.20 + * 06/24/99 W.Drummond	added boot_cpu_data.
   14.21 + */
   14.22 +#include <linux/config.h>
   14.23 +#include <linux/module.h>
   14.24 +#include <linux/init.h>
   14.25 +
   14.26 +#include <linux/acpi.h>
   14.27 +#include <linux/bootmem.h>
   14.28 +#include <linux/console.h>
   14.29 +#include <linux/delay.h>
   14.30 +#include <linux/kernel.h>
   14.31 +#include <linux/reboot.h>
   14.32 +#include <linux/sched.h>
   14.33 +#include <linux/seq_file.h>
   14.34 +#include <linux/string.h>
   14.35 +#include <linux/threads.h>
   14.36 +#include <linux/tty.h>
   14.37 +#include <linux/serial.h>
   14.38 +#include <linux/serial_core.h>
   14.39 +#include <linux/efi.h>
   14.40 +#include <linux/initrd.h>
   14.41 +
   14.42 +#include <asm/ia32.h>
   14.43 +#include <asm/machvec.h>
   14.44 +#include <asm/mca.h>
   14.45 +#include <asm/meminit.h>
   14.46 +#include <asm/page.h>
   14.47 +#include <asm/patch.h>
   14.48 +#include <asm/pgtable.h>
   14.49 +#include <asm/processor.h>
   14.50 +#include <asm/sal.h>
   14.51 +#include <asm/sections.h>
   14.52 +#include <asm/serial.h>
   14.53 +#include <asm/setup.h>
   14.54 +#include <asm/smp.h>
   14.55 +#include <asm/system.h>
   14.56 +#include <asm/unistd.h>
   14.57 +#include <asm/vmx.h>
   14.58 +#include <asm/io.h>
   14.59 +
   14.60 +#if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
   14.61 +# error "struct cpuinfo_ia64 too big!"
   14.62 +#endif
   14.63 +
   14.64 +#ifdef CONFIG_SMP
   14.65 +unsigned long __per_cpu_offset[NR_CPUS];
   14.66 +EXPORT_SYMBOL(__per_cpu_offset);
   14.67 +#endif
   14.68 +
   14.69 +DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
   14.70 +DEFINE_PER_CPU(cpu_kr_ia64_t, cpu_kr);
   14.71 +DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
   14.72 +DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
   14.73 +unsigned long ia64_cycles_per_usec;
   14.74 +struct ia64_boot_param *ia64_boot_param;
   14.75 +struct screen_info screen_info;
   14.76 +
   14.77 +unsigned long ia64_max_cacheline_size;
   14.78 +unsigned long ia64_iobase;	/* virtual address for I/O accesses */
   14.79 +EXPORT_SYMBOL(ia64_iobase);
   14.80 +struct io_space io_space[MAX_IO_SPACES];
   14.81 +EXPORT_SYMBOL(io_space);
   14.82 +unsigned int num_io_spaces;
   14.83 +
   14.84 +unsigned char aux_device_present = 0xaa;        /* XXX remove this when legacy I/O is gone */
   14.85 +
   14.86 +/*
   14.87 + * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1).  This
   14.88 + * mask specifies a mask of address bits that must be 0 in order for two buffers to be
   14.89 + * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
   14.90 + * address of the second buffer must be aligned to (merge_mask+1) in order to be
   14.91 + * mergeable).  By default, we assume there is no I/O MMU which can merge physically
   14.92 + * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
   14.93 + * page-size of 2^64.
   14.94 + */
   14.95 +unsigned long ia64_max_iommu_merge_mask = ~0UL;
   14.96 +EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
   14.97 +
   14.98 +/*
   14.99 + * We use a special marker for the end of memory and it uses the extra (+1) slot
  14.100 + */
  14.101 +struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
  14.102 +int num_rsvd_regions;
  14.103 +
  14.104 +
  14.105 +/*
  14.106 + * Filter incoming memory segments based on the primitive map created from the boot
  14.107 + * parameters. Segments contained in the map are removed from the memory ranges. A
  14.108 + * caller-specified function is called with the memory ranges that remain after filtering.
  14.109 + * This routine does not assume the incoming segments are sorted.
  14.110 + */
  14.111 +int
  14.112 +filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
  14.113 +{
  14.114 +	unsigned long range_start, range_end, prev_start;
  14.115 +	void (*func)(unsigned long, unsigned long, int);
  14.116 +	int i;
  14.117 +
  14.118 +#if IGNORE_PFN0
  14.119 +	if (start == PAGE_OFFSET) {
  14.120 +		printk(KERN_WARNING "warning: skipping physical page 0\n");
  14.121 +		start += PAGE_SIZE;
  14.122 +		if (start >= end) return 0;
  14.123 +	}
  14.124 +#endif
  14.125 +	/*
  14.126 +	 * lowest possible address(walker uses virtual)
  14.127 +	 */
  14.128 +	prev_start = PAGE_OFFSET;
  14.129 +	func = arg;
  14.130 +
  14.131 +	for (i = 0; i < num_rsvd_regions; ++i) {
  14.132 +		range_start = max(start, prev_start);
  14.133 +		range_end   = min(end, rsvd_region[i].start);
  14.134 +
  14.135 +		if (range_start < range_end)
  14.136 +#ifdef XEN
  14.137 +		{
  14.138 +		/* init_boot_pages requires "ps, pe" */
  14.139 +			printk("Init boot pages: 0x%lx -> 0x%lx.\n",
  14.140 +				__pa(range_start), __pa(range_end));
  14.141 +			(*func)(__pa(range_start), __pa(range_end), 0);
  14.142 +		}
  14.143 +#else
  14.144 +			call_pernode_memory(__pa(range_start), range_end - range_start, func);
  14.145 +#endif
  14.146 +
  14.147 +		/* nothing more available in this segment */
  14.148 +		if (range_end == end) return 0;
  14.149 +
  14.150 +		prev_start = rsvd_region[i].end;
  14.151 +	}
  14.152 +	/* end of memory marker allows full processing inside loop body */
  14.153 +	return 0;
  14.154 +}
  14.155 +
  14.156 +static void
  14.157 +sort_regions (struct rsvd_region *rsvd_region, int max)
  14.158 +{
  14.159 +	int j;
  14.160 +
  14.161 +	/* simple bubble sorting */
  14.162 +	while (max--) {
  14.163 +		for (j = 0; j < max; ++j) {
  14.164 +			if (rsvd_region[j].start > rsvd_region[j+1].start) {
  14.165 +				struct rsvd_region tmp;
  14.166 +				tmp = rsvd_region[j];
  14.167 +				rsvd_region[j] = rsvd_region[j + 1];
  14.168 +				rsvd_region[j + 1] = tmp;
  14.169 +			}
  14.170 +		}
  14.171 +	}
  14.172 +}
  14.173 +
  14.174 +/**
  14.175 + * reserve_memory - setup reserved memory areas
  14.176 + *
  14.177 + * Setup the reserved memory areas set aside for the boot parameters,
  14.178 + * initrd, etc.  There are currently %IA64_MAX_RSVD_REGIONS defined,
  14.179 + * see include/asm-ia64/meminit.h if you need to define more.
  14.180 + */
  14.181 +void
  14.182 +reserve_memory (void)
  14.183 +{
  14.184 +	int n = 0;
  14.185 +
  14.186 +	/*
  14.187 +	 * none of the entries in this table overlap
  14.188 +	 */
  14.189 +	rsvd_region[n].start = (unsigned long) ia64_boot_param;
  14.190 +	rsvd_region[n].end   = rsvd_region[n].start + sizeof(*ia64_boot_param);
  14.191 +	n++;
  14.192 +
  14.193 +	rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
  14.194 +	rsvd_region[n].end   = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
  14.195 +	n++;
  14.196 +
  14.197 +	rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
  14.198 +	rsvd_region[n].end   = (rsvd_region[n].start
  14.199 +				+ strlen(__va(ia64_boot_param->command_line)) + 1);
  14.200 +	n++;
  14.201 +
  14.202 +	rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
  14.203 +#ifdef XEN
  14.204 +	/* Reserve xen image/bitmap/xen-heap */
  14.205 +	rsvd_region[n].end   = rsvd_region[n].start + xenheap_size;
  14.206 +#else
  14.207 +	rsvd_region[n].end   = (unsigned long) ia64_imva(_end);
  14.208 +#endif
  14.209 +	n++;
  14.210 +
  14.211 +#ifdef CONFIG_BLK_DEV_INITRD
  14.212 +	if (ia64_boot_param->initrd_start) {
  14.213 +		rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
  14.214 +		rsvd_region[n].end   = rsvd_region[n].start + ia64_boot_param->initrd_size;
  14.215 +		n++;
  14.216 +	}
  14.217 +#endif
  14.218 +
  14.219 +	/* end of memory marker */
  14.220 +	rsvd_region[n].start = ~0UL;
  14.221 +	rsvd_region[n].end   = ~0UL;
  14.222 +	n++;
  14.223 +
  14.224 +	num_rsvd_regions = n;
  14.225 +
  14.226 +	sort_regions(rsvd_region, num_rsvd_regions);
  14.227 +}
  14.228 +
  14.229 +/**
  14.230 + * find_initrd - get initrd parameters from the boot parameter structure
  14.231 + *
  14.232 + * Grab the initrd start and end from the boot parameter struct given us by
  14.233 + * the boot loader.
  14.234 + */
  14.235 +void
  14.236 +find_initrd (void)
  14.237 +{
  14.238 +#ifdef CONFIG_BLK_DEV_INITRD
  14.239 +	if (ia64_boot_param->initrd_start) {
  14.240 +		initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
  14.241 +		initrd_end   = initrd_start+ia64_boot_param->initrd_size;
  14.242 +
  14.243 +		printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
  14.244 +		       initrd_start, ia64_boot_param->initrd_size);
  14.245 +	}
  14.246 +#endif
  14.247 +}
  14.248 +
  14.249 +static void __init
  14.250 +io_port_init (void)
  14.251 +{
  14.252 +	extern unsigned long ia64_iobase;
  14.253 +	unsigned long phys_iobase;
  14.254 +
  14.255 +	/*
  14.256 +	 *  Set `iobase' to the appropriate address in region 6 (uncached access range).
  14.257 +	 *
  14.258 +	 *  The EFI memory map is the "preferred" location to get the I/O port space base,
  14.259 +	 *  rather the relying on AR.KR0. This should become more clear in future SAL
  14.260 +	 *  specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
  14.261 +	 *  found in the memory map.
  14.262 +	 */
  14.263 +	phys_iobase = efi_get_iobase();
  14.264 +	if (phys_iobase)
  14.265 +		/* set AR.KR0 since this is all we use it for anyway */
  14.266 +		ia64_set_kr(IA64_KR_IO_BASE, phys_iobase);
  14.267 +	else {
  14.268 +		phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
  14.269 +		printk(KERN_INFO "No I/O port range found in EFI memory map, falling back "
  14.270 +		       "to AR.KR0\n");
  14.271 +		printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase);
  14.272 +	}
  14.273 +	ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
  14.274 +
  14.275 +	/* setup legacy IO port space */
  14.276 +	io_space[0].mmio_base = ia64_iobase;
  14.277 +	io_space[0].sparse = 1;
  14.278 +	num_io_spaces = 1;
  14.279 +}
  14.280 +
  14.281 +/**
  14.282 + * early_console_setup - setup debugging console
  14.283 + *
  14.284 + * Consoles started here require little enough setup that we can start using
  14.285 + * them very early in the boot process, either right after the machine
  14.286 + * vector initialization, or even before if the drivers can detect their hw.
  14.287 + *
  14.288 + * Returns non-zero if a console couldn't be setup.
  14.289 + */
  14.290 +static inline int __init
  14.291 +early_console_setup (char *cmdline)
  14.292 +{
  14.293 +#ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
  14.294 +	{
  14.295 +		extern int sn_serial_console_early_setup(void);
  14.296 +		if (!sn_serial_console_early_setup())
  14.297 +			return 0;
  14.298 +	}
  14.299 +#endif
  14.300 +#ifdef CONFIG_EFI_PCDP
  14.301 +	if (!efi_setup_pcdp_console(cmdline))
  14.302 +		return 0;
  14.303 +#endif
  14.304 +#ifdef CONFIG_SERIAL_8250_CONSOLE
  14.305 +	if (!early_serial_console_init(cmdline))
  14.306 +		return 0;
  14.307 +#endif
  14.308 +
  14.309 +	return -1;
  14.310 +}
  14.311 +
  14.312 +static inline void
  14.313 +mark_bsp_online (void)
  14.314 +{
  14.315 +#ifdef CONFIG_SMP
  14.316 +	/* If we register an early console, allow CPU 0 to printk */
  14.317 +	cpu_set(smp_processor_id(), cpu_online_map);
  14.318 +#endif
  14.319 +}
  14.320 +
  14.321 +void __init
  14.322 +#ifdef XEN
  14.323 +early_setup_arch (char **cmdline_p)
  14.324 +#else
  14.325 +setup_arch (char **cmdline_p)
  14.326 +#endif
  14.327 +{
  14.328 +	unw_init();
  14.329 +
  14.330 +	ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
  14.331 +
  14.332 +	*cmdline_p = __va(ia64_boot_param->command_line);
  14.333 +#ifdef XEN
  14.334 +	efi_init();
  14.335 +#else
  14.336 +	strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
  14.337 +
  14.338 +	efi_init();
  14.339 +	io_port_init();
  14.340 +#endif
  14.341 +
  14.342 +#ifdef CONFIG_IA64_GENERIC
  14.343 +	{
  14.344 +		const char *mvec_name = strstr (*cmdline_p, "machvec=");
  14.345 +		char str[64];
  14.346 +
  14.347 +		if (mvec_name) {
  14.348 +			const char *end;
  14.349 +			size_t len;
  14.350 +
  14.351 +			mvec_name += 8;
  14.352 +			end = strchr (mvec_name, ' ');
  14.353 +			if (end)
  14.354 +				len = end - mvec_name;
  14.355 +			else
  14.356 +				len = strlen (mvec_name);
  14.357 +			len = min(len, sizeof (str) - 1);
  14.358 +			strncpy (str, mvec_name, len);
  14.359 +			str[len] = '\0';
  14.360 +			mvec_name = str;
  14.361 +		} else
  14.362 +			mvec_name = acpi_get_sysname();
  14.363 +		machvec_init(mvec_name);
  14.364 +	}
  14.365 +#endif
  14.366 +
  14.367 +#ifdef XEN
  14.368 +	early_cmdline_parse(cmdline_p);
  14.369 +	cmdline_parse(*cmdline_p);
  14.370 +#undef CONFIG_ACPI_BOOT
  14.371 +#endif
  14.372 +	if (early_console_setup(*cmdline_p) == 0)
  14.373 +		mark_bsp_online();
  14.374 +
  14.375 +#ifdef CONFIG_ACPI_BOOT
  14.376 +	/* Initialize the ACPI boot-time table parser */
  14.377 +	acpi_table_init();
  14.378 +# ifdef CONFIG_ACPI_NUMA
  14.379 +	acpi_numa_init();
  14.380 +# endif
  14.381 +#else
  14.382 +# ifdef CONFIG_SMP
  14.383 +	smp_build_cpu_map();	/* happens, e.g., with the Ski simulator */
  14.384 +# endif
  14.385 +#endif /* CONFIG_APCI_BOOT */
  14.386 +
  14.387 +#ifndef XEN
  14.388 +	find_memory();
  14.389 +#else
  14.390 +	io_port_init();
  14.391 +}
  14.392 +
  14.393 +void __init
  14.394 +late_setup_arch (char **cmdline_p)
  14.395 +{
  14.396 +#undef CONFIG_ACPI_BOOT
  14.397 +	acpi_table_init();
  14.398 +#endif
  14.399 +	/* process SAL system table: */
  14.400 +	ia64_sal_init(efi.sal_systab);
  14.401 +
  14.402 +#ifdef CONFIG_SMP
  14.403 +	cpu_physical_id(0) = hard_smp_processor_id();
  14.404 +#endif
  14.405 +
  14.406 +#ifdef XEN
  14.407 +	identify_vmx_feature();
  14.408 +#endif
  14.409 +
  14.410 +	cpu_init();	/* initialize the bootstrap CPU */
  14.411 +
  14.412 +#ifdef CONFIG_ACPI_BOOT
  14.413 +	acpi_boot_init();
  14.414 +#endif
  14.415 +
  14.416 +#ifdef CONFIG_VT
  14.417 +	if (!conswitchp) {
  14.418 +# if defined(CONFIG_DUMMY_CONSOLE)
  14.419 +		conswitchp = &dummy_con;
  14.420 +# endif
  14.421 +# if defined(CONFIG_VGA_CONSOLE)
  14.422 +		/*
  14.423 +		 * Non-legacy systems may route legacy VGA MMIO range to system
  14.424 +		 * memory.  vga_con probes the MMIO hole, so memory looks like
  14.425 +		 * a VGA device to it.  The EFI memory map can tell us if it's
  14.426 +		 * memory so we can avoid this problem.
  14.427 +		 */
  14.428 +		if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
  14.429 +			conswitchp = &vga_con;
  14.430 +# endif
  14.431 +	}
  14.432 +#endif
  14.433 +
  14.434 +	/* enable IA-64 Machine Check Abort Handling unless disabled */
  14.435 +	if (!strstr(saved_command_line, "nomca"))
  14.436 +		ia64_mca_init();
  14.437 +
  14.438 +	platform_setup(cmdline_p);
  14.439 +	paging_init();
  14.440 +}
  14.441 +
  14.442 +/*
  14.443 + * Display cpu info for all cpu's.
  14.444 + */
  14.445 +static int
  14.446 +show_cpuinfo (struct seq_file *m, void *v)
  14.447 +{
  14.448 +#ifdef CONFIG_SMP
  14.449 +#	define lpj	c->loops_per_jiffy
  14.450 +#	define cpunum	c->cpu
  14.451 +#else
  14.452 +#	define lpj	loops_per_jiffy
  14.453 +#	define cpunum	0
  14.454 +#endif
  14.455 +	static struct {
  14.456 +		unsigned long mask;
  14.457 +		const char *feature_name;
  14.458 +	} feature_bits[] = {
  14.459 +		{ 1UL << 0, "branchlong" },
  14.460 +		{ 1UL << 1, "spontaneous deferral"},
  14.461 +		{ 1UL << 2, "16-byte atomic ops" }
  14.462 +	};
  14.463 +	char family[32], features[128], *cp, sep;
  14.464 +	struct cpuinfo_ia64 *c = v;
  14.465 +	unsigned long mask;
  14.466 +	int i;
  14.467 +
  14.468 +	mask = c->features;
  14.469 +
  14.470 +	switch (c->family) {
  14.471 +	      case 0x07:	memcpy(family, "Itanium", 8); break;
  14.472 +	      case 0x1f:	memcpy(family, "Itanium 2", 10); break;
  14.473 +	      default:		sprintf(family, "%u", c->family); break;
  14.474 +	}
  14.475 +
  14.476 +	/* build the feature string: */
  14.477 +	memcpy(features, " standard", 10);
  14.478 +	cp = features;
  14.479 +	sep = 0;
  14.480 +	for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
  14.481 +		if (mask & feature_bits[i].mask) {
  14.482 +			if (sep)
  14.483 +				*cp++ = sep;
  14.484 +			sep = ',';
  14.485 +			*cp++ = ' ';
  14.486 +			strcpy(cp, feature_bits[i].feature_name);
  14.487 +			cp += strlen(feature_bits[i].feature_name);
  14.488 +			mask &= ~feature_bits[i].mask;
  14.489 +		}
  14.490 +	}
  14.491 +	if (mask) {
  14.492 +		/* print unknown features as a hex value: */
  14.493 +		if (sep)
  14.494 +			*cp++ = sep;
  14.495 +		sprintf(cp, " 0x%lx", mask);
  14.496 +	}
  14.497 +
  14.498 +	seq_printf(m,
  14.499 +		   "processor  : %d\n"
  14.500 +		   "vendor     : %s\n"
  14.501 +		   "arch       : IA-64\n"
  14.502 +		   "family     : %s\n"
  14.503 +		   "model      : %u\n"
  14.504 +		   "revision   : %u\n"
  14.505 +		   "archrev    : %u\n"
  14.506 +		   "features   :%s\n"	/* don't change this---it _is_ right! */
  14.507 +		   "cpu number : %lu\n"
  14.508 +		   "cpu regs   : %u\n"
  14.509 +		   "cpu MHz    : %lu.%06lu\n"
  14.510 +		   "itc MHz    : %lu.%06lu\n"
  14.511 +		   "BogoMIPS   : %lu.%02lu\n\n",
  14.512 +		   cpunum, c->vendor, family, c->model, c->revision, c->archrev,
  14.513 +		   features, c->ppn, c->number,
  14.514 +		   c->proc_freq / 1000000, c->proc_freq % 1000000,
  14.515 +		   c->itc_freq / 1000000, c->itc_freq % 1000000,
  14.516 +		   lpj*HZ/500000, (lpj*HZ/5000) % 100);
  14.517 +	return 0;
  14.518 +}
  14.519 +
  14.520 +static void *
  14.521 +c_start (struct seq_file *m, loff_t *pos)
  14.522 +{
  14.523 +#ifdef CONFIG_SMP
  14.524 +	while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
  14.525 +		++*pos;
  14.526 +#endif
  14.527 +	return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
  14.528 +}
  14.529 +
  14.530 +static void *
  14.531 +c_next (struct seq_file *m, void *v, loff_t *pos)
  14.532 +{
  14.533 +	++*pos;
  14.534 +	return c_start(m, pos);
  14.535 +}
  14.536 +
  14.537 +static void
  14.538 +c_stop (struct seq_file *m, void *v)
  14.539 +{
  14.540 +}
  14.541 +
  14.542 +#ifndef XEN
  14.543 +struct seq_operations cpuinfo_op = {
  14.544 +	.start =	c_start,
  14.545 +	.next =		c_next,
  14.546 +	.stop =		c_stop,
  14.547 +	.show =		show_cpuinfo
  14.548 +};
  14.549 +#endif
  14.550 +
  14.551 +void
  14.552 +identify_cpu (struct cpuinfo_ia64 *c)
  14.553 +{
  14.554 +	union {
  14.555 +		unsigned long bits[5];
  14.556 +		struct {
  14.557 +			/* id 0 & 1: */
  14.558 +			char vendor[16];
  14.559 +
  14.560 +			/* id 2 */
  14.561 +			u64 ppn;		/* processor serial number */
  14.562 +
  14.563 +			/* id 3: */
  14.564 +			unsigned number		:  8;
  14.565 +			unsigned revision	:  8;
  14.566 +			unsigned model		:  8;
  14.567 +			unsigned family		:  8;
  14.568 +			unsigned archrev	:  8;
  14.569 +			unsigned reserved	: 24;
  14.570 +
  14.571 +			/* id 4: */
  14.572 +			u64 features;
  14.573 +		} field;
  14.574 +	} cpuid;
  14.575 +	pal_vm_info_1_u_t vm1;
  14.576 +	pal_vm_info_2_u_t vm2;
  14.577 +	pal_status_t status;
  14.578 +	unsigned long impl_va_msb = 50, phys_addr_size = 44;	/* Itanium defaults */
  14.579 +	int i;
  14.580 +
  14.581 +	for (i = 0; i < 5; ++i)
  14.582 +		cpuid.bits[i] = ia64_get_cpuid(i);
  14.583 +
  14.584 +	memcpy(c->vendor, cpuid.field.vendor, 16);
  14.585 +#ifdef CONFIG_SMP
  14.586 +	c->cpu = smp_processor_id();
  14.587 +#endif
  14.588 +	c->ppn = cpuid.field.ppn;
  14.589 +	c->number = cpuid.field.number;
  14.590 +	c->revision = cpuid.field.revision;
  14.591 +	c->model = cpuid.field.model;
  14.592 +	c->family = cpuid.field.family;
  14.593 +	c->archrev = cpuid.field.archrev;
  14.594 +	c->features = cpuid.field.features;
  14.595 +
  14.596 +	status = ia64_pal_vm_summary(&vm1, &vm2);
  14.597 +	if (status == PAL_STATUS_SUCCESS) {
  14.598 +		impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
  14.599 +		phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
  14.600 +	}
  14.601 +	c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
  14.602 +	c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
  14.603 +
  14.604 +#ifdef XEN
  14.605 +	/* If vmx feature is on, do necessary initialization for vmx */
  14.606 +	if (vmx_enabled)
  14.607 +		vmx_init_env();
  14.608 +#endif
  14.609 +}
  14.610 +
  14.611 +void
  14.612 +setup_per_cpu_areas (void)
  14.613 +{
  14.614 +	/* start_kernel() requires this... */
  14.615 +}
  14.616 +
  14.617 +static void
  14.618 +get_max_cacheline_size (void)
  14.619 +{
  14.620 +	unsigned long line_size, max = 1;
  14.621 +	u64 l, levels, unique_caches;
  14.622 +        pal_cache_config_info_t cci;
  14.623 +        s64 status;
  14.624 +
  14.625 +        status = ia64_pal_cache_summary(&levels, &unique_caches);
  14.626 +        if (status != 0) {
  14.627 +                printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
  14.628 +                       __FUNCTION__, status);
  14.629 +                max = SMP_CACHE_BYTES;
  14.630 +		goto out;
  14.631 +        }
  14.632 +
  14.633 +	for (l = 0; l < levels; ++l) {
  14.634 +		status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
  14.635 +						    &cci);
  14.636 +		if (status != 0) {
  14.637 +			printk(KERN_ERR
  14.638 +			       "%s: ia64_pal_cache_config_info(l=%lu) failed (status=%ld)\n",
  14.639 +			       __FUNCTION__, l, status);
  14.640 +			max = SMP_CACHE_BYTES;
  14.641 +		}
  14.642 +		line_size = 1 << cci.pcci_line_size;
  14.643 +		if (line_size > max)
  14.644 +			max = line_size;
  14.645 +        }
  14.646 +  out:
  14.647 +	if (max > ia64_max_cacheline_size)
  14.648 +		ia64_max_cacheline_size = max;
  14.649 +}
  14.650 +
  14.651 +/*
  14.652 + * cpu_init() initializes state that is per-CPU.  This function acts
  14.653 + * as a 'CPU state barrier', nothing should get across.
  14.654 + */
  14.655 +void
  14.656 +cpu_init (void)
  14.657 +{
  14.658 +	extern void __devinit ia64_mmu_init (void *);
  14.659 +	unsigned long num_phys_stacked;
  14.660 +	pal_vm_info_2_u_t vmi;
  14.661 +	unsigned int max_ctx;
  14.662 +	struct cpuinfo_ia64 *cpu_info;
  14.663 +	void *cpu_data;
  14.664 +
  14.665 +	cpu_data = per_cpu_init();
  14.666 +
  14.667 +	/*
  14.668 +	 * We set ar.k3 so that assembly code in MCA handler can compute
  14.669 +	 * physical addresses of per cpu variables with a simple:
  14.670 +	 *   phys = ar.k3 + &per_cpu_var
  14.671 +	 */
  14.672 +	ia64_set_kr(IA64_KR_PER_CPU_DATA,
  14.673 +		    ia64_tpa(cpu_data) - (long) __per_cpu_start);
  14.674 +
  14.675 +	get_max_cacheline_size();
  14.676 +
  14.677 +	/*
  14.678 +	 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
  14.679 +	 * ia64_mmu_init() yet.  And we can't call ia64_mmu_init() first because it
  14.680 +	 * depends on the data returned by identify_cpu().  We break the dependency by
  14.681 +	 * accessing cpu_data() through the canonical per-CPU address.
  14.682 +	 */
  14.683 +	cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
  14.684 +	identify_cpu(cpu_info);
  14.685 +
  14.686 +#ifdef CONFIG_MCKINLEY
  14.687 +	{
  14.688 +#		define FEATURE_SET 16
  14.689 +		struct ia64_pal_retval iprv;
  14.690 +
  14.691 +		if (cpu_info->family == 0x1f) {
  14.692 +			PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
  14.693 +			if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
  14.694 +				PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
  14.695 +				              (iprv.v1 | 0x80), FEATURE_SET, 0);
  14.696 +		}
  14.697 +	}
  14.698 +#endif
  14.699 +
  14.700 +	/* Clear the stack memory reserved for pt_regs: */
  14.701 +	memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
  14.702 +
  14.703 +	ia64_set_kr(IA64_KR_FPU_OWNER, 0);
  14.704 +
  14.705 +	/*
  14.706 +	 * Initialize default control register to defer all speculative faults.  The
  14.707 +	 * kernel MUST NOT depend on a particular setting of these bits (in other words,
  14.708 +	 * the kernel must have recovery code for all speculative accesses).  Turn on
  14.709 +	 * dcr.lc as per recommendation by the architecture team.  Most IA-32 apps
  14.710 +	 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
  14.711 +	 * be fine).
  14.712 +	 */
  14.713 +	ia64_setreg(_IA64_REG_CR_DCR,  (  IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
  14.714 +					| IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
  14.715 +	atomic_inc(&init_mm.mm_count);
  14.716 +	current->active_mm = &init_mm;
  14.717 +#ifdef XEN
  14.718 +	if (current->domain->arch.mm)
  14.719 +#else
  14.720 +	if (current->mm)
  14.721 +#endif
  14.722 +		BUG();
  14.723 +
  14.724 +	ia64_mmu_init(ia64_imva(cpu_data));
  14.725 +	ia64_mca_cpu_init(ia64_imva(cpu_data));
  14.726 +
  14.727 +#ifdef CONFIG_IA32_SUPPORT
  14.728 +	ia32_cpu_init();
  14.729 +#endif
  14.730 +
  14.731 +	/* Clear ITC to eliminiate sched_clock() overflows in human time.  */
  14.732 +	ia64_set_itc(0);
  14.733 +
  14.734 +	/* disable all local interrupt sources: */
  14.735 +	ia64_set_itv(1 << 16);
  14.736 +	ia64_set_lrr0(1 << 16);
  14.737 +	ia64_set_lrr1(1 << 16);
  14.738 +	ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
  14.739 +	ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
  14.740 +
  14.741 +	/* clear TPR & XTP to enable all interrupt classes: */
  14.742 +	ia64_setreg(_IA64_REG_CR_TPR, 0);
  14.743 +#ifdef CONFIG_SMP
  14.744 +	normal_xtp();
  14.745 +#endif
  14.746 +
  14.747 +	/* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
  14.748 +	if (ia64_pal_vm_summary(NULL, &vmi) == 0)
  14.749 +		max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
  14.750 +	else {
  14.751 +		printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
  14.752 +		max_ctx = (1U << 15) - 1;	/* use architected minimum */
  14.753 +	}
  14.754 +	while (max_ctx < ia64_ctx.max_ctx) {
  14.755 +		unsigned int old = ia64_ctx.max_ctx;
  14.756 +		if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
  14.757 +			break;
  14.758 +	}
  14.759 +
  14.760 +	if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
  14.761 +		printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
  14.762 +		       "stacked regs\n");
  14.763 +		num_phys_stacked = 96;
  14.764 +	}
  14.765 +	/* size of physical stacked register partition plus 8 bytes: */
  14.766 +	__get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
  14.767 +	platform_cpu_init();
  14.768 +}
  14.769 +
  14.770 +void
  14.771 +check_bugs (void)
  14.772 +{
  14.773 +	ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
  14.774 +			       (unsigned long) __end___mckinley_e9_bundles);
  14.775 +}
    15.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.2 +++ b/xen/arch/ia64/linux-xen/time.c	Fri Aug 26 09:05:43 2005 +0000
    15.3 @@ -0,0 +1,264 @@
    15.4 +/*
    15.5 + * linux/arch/ia64/kernel/time.c
    15.6 + *
    15.7 + * Copyright (C) 1998-2003 Hewlett-Packard Co
    15.8 + *	Stephane Eranian <eranian@hpl.hp.com>
    15.9 + *	David Mosberger <davidm@hpl.hp.com>
   15.10 + * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
   15.11 + * Copyright (C) 1999-2000 VA Linux Systems
   15.12 + * Copyright (C) 1999-2000 Walt Drummond <drummond@valinux.com>
   15.13 + */
   15.14 +#include <linux/config.h>
   15.15 +
   15.16 +#include <linux/cpu.h>
   15.17 +#include <linux/init.h>
   15.18 +#include <linux/kernel.h>
   15.19 +#include <linux/module.h>
   15.20 +#include <linux/profile.h>
   15.21 +#include <linux/sched.h>
   15.22 +#include <linux/time.h>
   15.23 +#include <linux/interrupt.h>
   15.24 +#include <linux/efi.h>
   15.25 +#include <linux/profile.h>
   15.26 +#include <linux/timex.h>
   15.27 +
   15.28 +#include <asm/machvec.h>
   15.29 +#include <asm/delay.h>
   15.30 +#include <asm/hw_irq.h>
   15.31 +#include <asm/ptrace.h>
   15.32 +#include <asm/sal.h>
   15.33 +#include <asm/sections.h>
   15.34 +#include <asm/system.h>
   15.35 +#ifdef XEN
   15.36 +#include <linux/jiffies.h>	// not included by xen/sched.h
   15.37 +#endif
   15.38 +
   15.39 +extern unsigned long wall_jiffies;
   15.40 +
   15.41 +u64 jiffies_64 __cacheline_aligned_in_smp = INITIAL_JIFFIES;
   15.42 +
   15.43 +EXPORT_SYMBOL(jiffies_64);
   15.44 +
   15.45 +#define TIME_KEEPER_ID	0	/* smp_processor_id() of time-keeper */
   15.46 +
   15.47 +#ifdef CONFIG_IA64_DEBUG_IRQ
   15.48 +
   15.49 +unsigned long last_cli_ip;
   15.50 +EXPORT_SYMBOL(last_cli_ip);
   15.51 +
   15.52 +#endif
   15.53 +
   15.54 +#ifndef XEN
   15.55 +static struct time_interpolator itc_interpolator = {
   15.56 +	.shift = 16,
   15.57 +	.mask = 0xffffffffffffffffLL,
   15.58 +	.source = TIME_SOURCE_CPU
   15.59 +};
   15.60 +
   15.61 +static irqreturn_t
   15.62 +timer_interrupt (int irq, void *dev_id, struct pt_regs *regs)
   15.63 +{
   15.64 +	unsigned long new_itm;
   15.65 +
   15.66 +	if (unlikely(cpu_is_offline(smp_processor_id()))) {
   15.67 +		return IRQ_HANDLED;
   15.68 +	}
   15.69 +
   15.70 +	platform_timer_interrupt(irq, dev_id, regs);
   15.71 +
   15.72 +	new_itm = local_cpu_data->itm_next;
   15.73 +
   15.74 +	if (!time_after(ia64_get_itc(), new_itm))
   15.75 +		printk(KERN_ERR "Oops: timer tick before it's due (itc=%lx,itm=%lx)\n",
   15.76 +		       ia64_get_itc(), new_itm);
   15.77 +
   15.78 +	profile_tick(CPU_PROFILING, regs);
   15.79 +
   15.80 +	while (1) {
   15.81 +		update_process_times(user_mode(regs));
   15.82 +
   15.83 +		new_itm += local_cpu_data->itm_delta;
   15.84 +
   15.85 +		if (smp_processor_id() == TIME_KEEPER_ID) {
   15.86 +			/*
   15.87 +			 * Here we are in the timer irq handler. We have irqs locally
   15.88 +			 * disabled, but we don't know if the timer_bh is running on
   15.89 +			 * another CPU. We need to avoid to SMP race by acquiring the
   15.90 +			 * xtime_lock.
   15.91 +			 */
   15.92 +			write_seqlock(&xtime_lock);
   15.93 +			do_timer(regs);
   15.94 +			local_cpu_data->itm_next = new_itm;
   15.95 +			write_sequnlock(&xtime_lock);
   15.96 +		} else
   15.97 +			local_cpu_data->itm_next = new_itm;
   15.98 +
   15.99 +		if (time_after(new_itm, ia64_get_itc()))
  15.100 +			break;
  15.101 +	}
  15.102 +
  15.103 +	do {
  15.104 +		/*
  15.105 +		 * If we're too close to the next clock tick for
  15.106 +		 * comfort, we increase the safety margin by
  15.107 +		 * intentionally dropping the next tick(s).  We do NOT
  15.108 +		 * update itm.next because that would force us to call
  15.109 +		 * do_timer() which in turn would let our clock run
  15.110 +		 * too fast (with the potentially devastating effect
  15.111 +		 * of losing monotony of time).
  15.112 +		 */
  15.113 +		while (!time_after(new_itm, ia64_get_itc() + local_cpu_data->itm_delta/2))
  15.114 +			new_itm += local_cpu_data->itm_delta;
  15.115 +		ia64_set_itm(new_itm);
  15.116 +		/* double check, in case we got hit by a (slow) PMI: */
  15.117 +	} while (time_after_eq(ia64_get_itc(), new_itm));
  15.118 +	return IRQ_HANDLED;
  15.119 +}
  15.120 +#endif
  15.121 +
  15.122 +/*
  15.123 + * Encapsulate access to the itm structure for SMP.
  15.124 + */
  15.125 +void
  15.126 +ia64_cpu_local_tick (void)
  15.127 +{
  15.128 +	int cpu = smp_processor_id();
  15.129 +	unsigned long shift = 0, delta;
  15.130 +
  15.131 +	/* arrange for the cycle counter to generate a timer interrupt: */
  15.132 +	ia64_set_itv(IA64_TIMER_VECTOR);
  15.133 +
  15.134 +	delta = local_cpu_data->itm_delta;
  15.135 +	/*
  15.136 +	 * Stagger the timer tick for each CPU so they don't occur all at (almost) the
  15.137 +	 * same time:
  15.138 +	 */
  15.139 +	if (cpu) {
  15.140 +		unsigned long hi = 1UL << ia64_fls(cpu);
  15.141 +		shift = (2*(cpu - hi) + 1) * delta/hi/2;
  15.142 +	}
  15.143 +	local_cpu_data->itm_next = ia64_get_itc() + delta + shift;
  15.144 +	ia64_set_itm(local_cpu_data->itm_next);
  15.145 +}
  15.146 +
  15.147 +static int nojitter;
  15.148 +
  15.149 +static int __init nojitter_setup(char *str)
  15.150 +{
  15.151 +	nojitter = 1;
  15.152 +	printk("Jitter checking for ITC timers disabled\n");
  15.153 +	return 1;
  15.154 +}
  15.155 +
  15.156 +__setup("nojitter", nojitter_setup);
  15.157 +
  15.158 +
  15.159 +void __devinit
  15.160 +ia64_init_itm (void)
  15.161 +{
  15.162 +	unsigned long platform_base_freq, itc_freq;
  15.163 +	struct pal_freq_ratio itc_ratio, proc_ratio;
  15.164 +	long status, platform_base_drift, itc_drift;
  15.165 +
  15.166 +	/*
  15.167 +	 * According to SAL v2.6, we need to use a SAL call to determine the platform base
  15.168 +	 * frequency and then a PAL call to determine the frequency ratio between the ITC
  15.169 +	 * and the base frequency.
  15.170 +	 */
  15.171 +	status = ia64_sal_freq_base(SAL_FREQ_BASE_PLATFORM,
  15.172 +				    &platform_base_freq, &platform_base_drift);
  15.173 +	if (status != 0) {
  15.174 +		printk(KERN_ERR "SAL_FREQ_BASE_PLATFORM failed: %s\n", ia64_sal_strerror(status));
  15.175 +	} else {
  15.176 +		status = ia64_pal_freq_ratios(&proc_ratio, NULL, &itc_ratio);
  15.177 +		if (status != 0)
  15.178 +			printk(KERN_ERR "PAL_FREQ_RATIOS failed with status=%ld\n", status);
  15.179 +	}
  15.180 +	if (status != 0) {
  15.181 +		/* invent "random" values */
  15.182 +		printk(KERN_ERR
  15.183 +		       "SAL/PAL failed to obtain frequency info---inventing reasonable values\n");
  15.184 +		platform_base_freq = 100000000;
  15.185 +		platform_base_drift = -1;	/* no drift info */
  15.186 +		itc_ratio.num = 3;
  15.187 +		itc_ratio.den = 1;
  15.188 +	}
  15.189 +	if (platform_base_freq < 40000000) {
  15.190 +		printk(KERN_ERR "Platform base frequency %lu bogus---resetting to 75MHz!\n",
  15.191 +		       platform_base_freq);
  15.192 +		platform_base_freq = 75000000;
  15.193 +		platform_base_drift = -1;
  15.194 +	}
  15.195 +	if (!proc_ratio.den)
  15.196 +		proc_ratio.den = 1;	/* avoid division by zero */
  15.197 +	if (!itc_ratio.den)
  15.198 +		itc_ratio.den = 1;	/* avoid division by zero */
  15.199 +
  15.200 +	itc_freq = (platform_base_freq*itc_ratio.num)/itc_ratio.den;
  15.201 +
  15.202 +	local_cpu_data->itm_delta = (itc_freq + HZ/2) / HZ;
  15.203 +	printk(KERN_DEBUG "CPU %d: base freq=%lu.%03luMHz, ITC ratio=%lu/%lu, "
  15.204 +	       "ITC freq=%lu.%03luMHz", smp_processor_id(),
  15.205 +	       platform_base_freq / 1000000, (platform_base_freq / 1000) % 1000,
  15.206 +	       itc_ratio.num, itc_ratio.den, itc_freq / 1000000, (itc_freq / 1000) % 1000);
  15.207 +
  15.208 +	if (platform_base_drift != -1) {
  15.209 +		itc_drift = platform_base_drift*itc_ratio.num/itc_ratio.den;
  15.210 +		printk("+/-%ldppm\n", itc_drift);
  15.211 +	} else {
  15.212 +		itc_drift = -1;
  15.213 +		printk("\n");
  15.214 +	}
  15.215 +
  15.216 +	local_cpu_data->proc_freq = (platform_base_freq*proc_ratio.num)/proc_ratio.den;
  15.217 +	local_cpu_data->itc_freq = itc_freq;
  15.218 +	local_cpu_data->cyc_per_usec = (itc_freq + USEC_PER_SEC/2) / USEC_PER_SEC;
  15.219 +	local_cpu_data->nsec_per_cyc = ((NSEC_PER_SEC<<IA64_NSEC_PER_CYC_SHIFT)
  15.220 +					+ itc_freq/2)/itc_freq;
  15.221 +
  15.222 +	if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) {
  15.223 +#ifndef XEN
  15.224 +		itc_interpolator.frequency = local_cpu_data->itc_freq;
  15.225 +		itc_interpolator.drift = itc_drift;
  15.226 +#ifdef CONFIG_SMP
  15.227 +		/* On IA64 in an SMP configuration ITCs are never accurately synchronized.
  15.228 +		 * Jitter compensation requires a cmpxchg which may limit
  15.229 +		 * the scalability of the syscalls for retrieving time.
  15.230 +		 * The ITC synchronization is usually successful to within a few
  15.231 +		 * ITC ticks but this is not a sure thing. If you need to improve
  15.232 +		 * timer performance in SMP situations then boot the kernel with the
  15.233 +		 * "nojitter" option. However, doing so may result in time fluctuating (maybe
  15.234 +		 * even going backward) if the ITC offsets between the individual CPUs
  15.235 +		 * are too large.
  15.236 +		 */
  15.237 +		if (!nojitter) itc_interpolator.jitter = 1;
  15.238 +#endif
  15.239 +		register_time_interpolator(&itc_interpolator);
  15.240 +#endif
  15.241 +	}
  15.242 +
  15.243 +	/* Setup the CPU local timer tick */
  15.244 +	ia64_cpu_local_tick();
  15.245 +}
  15.246 +
  15.247 +#ifndef XEN
  15.248 +static struct irqaction timer_irqaction = {
  15.249 +	.handler =	timer_interrupt,
  15.250 +	.flags =	SA_INTERRUPT,
  15.251 +	.name =		"timer"
  15.252 +};
  15.253 +
  15.254 +void __init
  15.255 +time_init (void)
  15.256 +{
  15.257 +	register_percpu_irq(IA64_TIMER_VECTOR, &timer_irqaction);
  15.258 +	efi_gettimeofday(&xtime);
  15.259 +	ia64_init_itm();
  15.260 +
  15.261 +	/*
  15.262 +	 * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
  15.263 +	 * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
  15.264 +	 */
  15.265 +	set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
  15.266 +}
  15.267 +#endif
    16.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    16.2 +++ b/xen/arch/ia64/linux-xen/tlb.c	Fri Aug 26 09:05:43 2005 +0000
    16.3 @@ -0,0 +1,199 @@
    16.4 +/*
    16.5 + * TLB support routines.
    16.6 + *
    16.7 + * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
    16.8 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    16.9 + *
   16.10 + * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
   16.11 + *		Modified RID allocation for SMP
   16.12 + *          Goutham Rao <goutham.rao@intel.com>
   16.13 + *              IPI based ptc implementation and A-step IPI implementation.
   16.14 + */
   16.15 +#include <linux/config.h>
   16.16 +#include <linux/module.h>
   16.17 +#include <linux/init.h>
   16.18 +#include <linux/kernel.h>
   16.19 +#include <linux/sched.h>
   16.20 +#include <linux/smp.h>
   16.21 +#include <linux/mm.h>
   16.22 +
   16.23 +#include <asm/delay.h>
   16.24 +#include <asm/mmu_context.h>
   16.25 +#include <asm/pgalloc.h>
   16.26 +#include <asm/pal.h>
   16.27 +#include <asm/tlbflush.h>
   16.28 +
   16.29 +static struct {
   16.30 +	unsigned long mask;	/* mask of supported purge page-sizes */
   16.31 +	unsigned long max_bits;	/* log2() of largest supported purge page-size */
   16.32 +} purge;
   16.33 +
   16.34 +struct ia64_ctx ia64_ctx = {
   16.35 +	.lock =		SPIN_LOCK_UNLOCKED,
   16.36 +	.next =		1,
   16.37 +	.limit =	(1 << 15) - 1,		/* start out with the safe (architected) limit */
   16.38 +	.max_ctx =	~0U
   16.39 +};
   16.40 +
   16.41 +DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
   16.42 +
   16.43 +/*
   16.44 + * Acquire the ia64_ctx.lock before calling this function!
   16.45 + */
   16.46 +void
   16.47 +wrap_mmu_context (struct mm_struct *mm)
   16.48 +{
   16.49 +#ifdef XEN
   16.50 +printf("wrap_mmu_context: called, not implemented\n");
   16.51 +#else
   16.52 +	unsigned long tsk_context, max_ctx = ia64_ctx.max_ctx;
   16.53 +	struct task_struct *tsk;
   16.54 +	int i;
   16.55 +
   16.56 +	if (ia64_ctx.next > max_ctx)
   16.57 +		ia64_ctx.next = 300;	/* skip daemons */
   16.58 +	ia64_ctx.limit = max_ctx + 1;
   16.59 +
   16.60 +	/*
   16.61 +	 * Scan all the task's mm->context and set proper safe range
   16.62 +	 */
   16.63 +
   16.64 +	read_lock(&tasklist_lock);
   16.65 +  repeat:
   16.66 +	for_each_process(tsk) {
   16.67 +		if (!tsk->mm)
   16.68 +			continue;
   16.69 +		tsk_context = tsk->mm->context;
   16.70 +		if (tsk_context == ia64_ctx.next) {
   16.71 +			if (++ia64_ctx.next >= ia64_ctx.limit) {
   16.72 +				/* empty range: reset the range limit and start over */
   16.73 +				if (ia64_ctx.next > max_ctx)
   16.74 +					ia64_ctx.next = 300;
   16.75 +				ia64_ctx.limit = max_ctx + 1;
   16.76 +				goto repeat;
   16.77 +			}
   16.78 +		}
   16.79 +		if ((tsk_context > ia64_ctx.next) && (tsk_context < ia64_ctx.limit))
   16.80 +			ia64_ctx.limit = tsk_context;
   16.81 +	}
   16.82 +	read_unlock(&tasklist_lock);
   16.83 +	/* can't call flush_tlb_all() here because of race condition with O(1) scheduler [EF] */
   16.84 +	{
   16.85 +		int cpu = get_cpu(); /* prevent preemption/migration */
   16.86 +		for (i = 0; i < NR_CPUS; ++i)
   16.87 +			if (cpu_online(i) && (i != cpu))
   16.88 +				per_cpu(ia64_need_tlb_flush, i) = 1;
   16.89 +		put_cpu();
   16.90 +	}
   16.91 +	local_flush_tlb_all();
   16.92 +#endif
   16.93 +}
   16.94 +
   16.95 +void
   16.96 +ia64_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits)
   16.97 +{
   16.98 +	static DEFINE_SPINLOCK(ptcg_lock);
   16.99 +
  16.100 +	/* HW requires global serialization of ptc.ga.  */
  16.101 +	spin_lock(&ptcg_lock);
  16.102 +	{
  16.103 +		do {
  16.104 +			/*
  16.105 +			 * Flush ALAT entries also.
  16.106 +			 */
  16.107 +			ia64_ptcga(start, (nbits<<2));
  16.108 +			ia64_srlz_i();
  16.109 +			start += (1UL << nbits);
  16.110 +		} while (start < end);
  16.111 +	}
  16.112 +	spin_unlock(&ptcg_lock);
  16.113 +}
  16.114 +
  16.115 +void
  16.116 +local_flush_tlb_all (void)
  16.117 +{
  16.118 +	unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
  16.119 +
  16.120 +	addr    = local_cpu_data->ptce_base;
  16.121 +	count0  = local_cpu_data->ptce_count[0];
  16.122 +	count1  = local_cpu_data->ptce_count[1];
  16.123 +	stride0 = local_cpu_data->ptce_stride[0];
  16.124 +	stride1 = local_cpu_data->ptce_stride[1];
  16.125 +
  16.126 +	local_irq_save(flags);
  16.127 +	for (i = 0; i < count0; ++i) {
  16.128 +		for (j = 0; j < count1; ++j) {
  16.129 +			ia64_ptce(addr);
  16.130 +			addr += stride1;
  16.131 +		}
  16.132 +		addr += stride0;
  16.133 +	}
  16.134 +	local_irq_restore(flags);
  16.135 +	ia64_srlz_i();			/* srlz.i implies srlz.d */
  16.136 +}
  16.137 +EXPORT_SYMBOL(local_flush_tlb_all);
  16.138 +
  16.139 +void
  16.140 +flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end)
  16.141 +{
  16.142 +#ifdef XEN
  16.143 +printf("flush_tlb_range: called, not implemented\n");
  16.144 +#else
  16.145 +	struct mm_struct *mm = vma->vm_mm;
  16.146 +	unsigned long size = end - start;
  16.147 +	unsigned long nbits;
  16.148 +
  16.149 +	if (mm != current->active_mm) {
  16.150 +		/* this does happen, but perhaps it's not worth optimizing for? */
  16.151 +#ifdef CONFIG_SMP
  16.152 +		flush_tlb_all();
  16.153 +#else
  16.154 +		mm->context = 0;
  16.155 +#endif
  16.156 +		return;
  16.157 +	}
  16.158 +
  16.159 +	nbits = ia64_fls(size + 0xfff);
  16.160 +	while (unlikely (((1UL << nbits) & purge.mask) == 0) && (nbits < purge.max_bits))
  16.161 +		++nbits;
  16.162 +	if (nbits > purge.max_bits)
  16.163 +		nbits = purge.max_bits;
  16.164 +	start &= ~((1UL << nbits) - 1);
  16.165 +
  16.166 +# ifdef CONFIG_SMP
  16.167 +	platform_global_tlb_purge(start, end, nbits);
  16.168 +# else
  16.169 +	do {
  16.170 +		ia64_ptcl(start, (nbits<<2));
  16.171 +		start += (1UL << nbits);
  16.172 +	} while (start < end);
  16.173 +# endif
  16.174 +
  16.175 +	ia64_srlz_i();			/* srlz.i implies srlz.d */
  16.176 +#endif
  16.177 +}
  16.178 +EXPORT_SYMBOL(flush_tlb_range);
  16.179 +
  16.180 +void __devinit
  16.181 +ia64_tlb_init (void)
  16.182 +{
  16.183 +	ia64_ptce_info_t ptce_info;
  16.184 +	unsigned long tr_pgbits;
  16.185 +	long status;
  16.186 +
  16.187 +	if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
  16.188 +		printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld;"
  16.189 +		       "defaulting to architected purge page-sizes.\n", status);
  16.190 +		purge.mask = 0x115557000UL;
  16.191 +	}
  16.192 +	purge.max_bits = ia64_fls(purge.mask);
  16.193 +
  16.194 +	ia64_get_ptce(&ptce_info);
  16.195 +	local_cpu_data->ptce_base = ptce_info.base;
  16.196 +	local_cpu_data->ptce_count[0] = ptce_info.count[0];
  16.197 +	local_cpu_data->ptce_count[1] = ptce_info.count[1];
  16.198 +	local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
  16.199 +	local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
  16.200 +
  16.201 +	local_flush_tlb_all();		/* nuke left overs from bootstrapping... */
  16.202 +}
    17.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.2 +++ b/xen/arch/ia64/linux-xen/unaligned.c	Fri Aug 26 09:05:43 2005 +0000
    17.3 @@ -0,0 +1,1653 @@
    17.4 +/*
    17.5 + * Architecture-specific unaligned trap handling.
    17.6 + *
    17.7 + * Copyright (C) 1999-2002, 2004 Hewlett-Packard Co
    17.8 + *	Stephane Eranian <eranian@hpl.hp.com>
    17.9 + *	David Mosberger-Tang <davidm@hpl.hp.com>
   17.10 + *
   17.11 + * 2002/12/09   Fix rotating register handling (off-by-1 error, missing fr-rotation).  Fix
   17.12 + *		get_rse_reg() to not leak kernel bits to user-level (reading an out-of-frame
   17.13 + *		stacked register returns an undefined value; it does NOT trigger a
   17.14 + *		"rsvd register fault").
   17.15 + * 2001/10/11	Fix unaligned access to rotating registers in s/w pipelined loops.
   17.16 + * 2001/08/13	Correct size of extended floats (float_fsz) from 16 to 10 bytes.
   17.17 + * 2001/01/17	Add support emulation of unaligned kernel accesses.
   17.18 + */
   17.19 +#include <linux/kernel.h>
   17.20 +#include <linux/sched.h>
   17.21 +#include <linux/smp_lock.h>
   17.22 +#include <linux/tty.h>
   17.23 +
   17.24 +#include <asm/intrinsics.h>
   17.25 +#include <asm/processor.h>
   17.26 +#include <asm/rse.h>
   17.27 +#include <asm/uaccess.h>
   17.28 +#include <asm/unaligned.h>
   17.29 +
   17.30 +extern void die_if_kernel(char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
   17.31 +
   17.32 +#undef DEBUG_UNALIGNED_TRAP
   17.33 +
   17.34 +#ifdef DEBUG_UNALIGNED_TRAP
   17.35 +# define DPRINT(a...)	do { printk("%s %u: ", __FUNCTION__, __LINE__); printk (a); } while (0)
   17.36 +# define DDUMP(str,vp,len)	dump(str, vp, len)
   17.37 +
   17.38 +static void
   17.39 +dump (const char *str, void *vp, size_t len)
   17.40 +{
   17.41 +	unsigned char *cp = vp;
   17.42 +	int i;
   17.43 +
   17.44 +	printk("%s", str);
   17.45 +	for (i = 0; i < len; ++i)
   17.46 +		printk (" %02x", *cp++);
   17.47 +	printk("\n");
   17.48 +}
   17.49 +#else
   17.50 +# define DPRINT(a...)
   17.51 +# define DDUMP(str,vp,len)
   17.52 +#endif
   17.53 +
   17.54 +#define IA64_FIRST_STACKED_GR	32
   17.55 +#define IA64_FIRST_ROTATING_FR	32
   17.56 +#define SIGN_EXT9		0xffffffffffffff00ul
   17.57 +
   17.58 +/*
   17.59 + * For M-unit:
   17.60 + *
   17.61 + *  opcode |   m  |   x6    |
   17.62 + * --------|------|---------|
   17.63 + * [40-37] | [36] | [35:30] |
   17.64 + * --------|------|---------|
   17.65 + *     4   |   1  |    6    | = 11 bits
   17.66 + * --------------------------
   17.67 + * However bits [31:30] are not directly useful to distinguish between
   17.68 + * load/store so we can use [35:32] instead, which gives the following
   17.69 + * mask ([40:32]) using 9 bits. The 'e' comes from the fact that we defer
   17.70 + * checking the m-bit until later in the load/store emulation.
   17.71 + */
   17.72 +#define IA64_OPCODE_MASK	0x1ef
   17.73 +#define IA64_OPCODE_SHIFT	32
   17.74 +
   17.75 +/*
   17.76 + * Table C-28 Integer Load/Store
   17.77 + *
   17.78 + * We ignore [35:32]= 0x6, 0x7, 0xE, 0xF
   17.79 + *
   17.80 + * ld8.fill, st8.fill  MUST be aligned because the RNATs are based on
   17.81 + * the address (bits [8:3]), so we must failed.
   17.82 + */
   17.83 +#define LD_OP            0x080
   17.84 +#define LDS_OP           0x081
   17.85 +#define LDA_OP           0x082
   17.86 +#define LDSA_OP          0x083
   17.87 +#define LDBIAS_OP        0x084
   17.88 +#define LDACQ_OP         0x085
   17.89 +/* 0x086, 0x087 are not relevant */
   17.90 +#define LDCCLR_OP        0x088
   17.91 +#define LDCNC_OP         0x089
   17.92 +#define LDCCLRACQ_OP     0x08a
   17.93 +#define ST_OP            0x08c
   17.94 +#define STREL_OP         0x08d
   17.95 +/* 0x08e,0x8f are not relevant */
   17.96 +
   17.97 +/*
   17.98 + * Table C-29 Integer Load +Reg
   17.99 + *
  17.100 + * we use the ld->m (bit [36:36]) field to determine whether or not we have
  17.101 + * a load/store of this form.
  17.102 + */
  17.103 +
  17.104 +/*
  17.105 + * Table C-30 Integer Load/Store +Imm
  17.106 + *
  17.107 + * We ignore [35:32]= 0x6, 0x7, 0xE, 0xF
  17.108 + *
  17.109 + * ld8.fill, st8.fill  must be aligned because the Nat register are based on
  17.110 + * the address, so we must fail and the program must be fixed.
  17.111 + */
  17.112 +#define LD_IMM_OP            0x0a0
  17.113 +#define LDS_IMM_OP           0x0a1
  17.114 +#define LDA_IMM_OP           0x0a2
  17.115 +#define LDSA_IMM_OP          0x0a3
  17.116 +#define LDBIAS_IMM_OP        0x0a4
  17.117 +#define LDACQ_IMM_OP         0x0a5
  17.118 +/* 0x0a6, 0xa7 are not relevant */
  17.119 +#define LDCCLR_IMM_OP        0x0a8
  17.120 +#define LDCNC_IMM_OP         0x0a9
  17.121 +#define LDCCLRACQ_IMM_OP     0x0aa
  17.122 +#define ST_IMM_OP            0x0ac
  17.123 +#define STREL_IMM_OP         0x0ad
  17.124 +/* 0x0ae,0xaf are not relevant */
  17.125 +
  17.126 +/*
  17.127 + * Table C-32 Floating-point Load/Store
  17.128 + */
  17.129 +#define LDF_OP           0x0c0
  17.130 +#define LDFS_OP          0x0c1
  17.131 +#define LDFA_OP          0x0c2
  17.132 +#define LDFSA_OP         0x0c3
  17.133 +/* 0x0c6 is irrelevant */
  17.134 +#define LDFCCLR_OP       0x0c8
  17.135 +#define LDFCNC_OP        0x0c9
  17.136 +/* 0x0cb is irrelevant  */
  17.137 +#define STF_OP           0x0cc
  17.138 +
  17.139 +/*
  17.140 + * Table C-33 Floating-point Load +Reg
  17.141 + *
  17.142 + * we use the ld->m (bit [36:36]) field to determine whether or not we have
  17.143 + * a load/store of this form.
  17.144 + */
  17.145 +
  17.146 +/*
  17.147 + * Table C-34 Floating-point Load/Store +Imm
  17.148 + */
  17.149 +#define LDF_IMM_OP       0x0e0
  17.150 +#define LDFS_IMM_OP      0x0e1
  17.151 +#define LDFA_IMM_OP      0x0e2
  17.152 +#define LDFSA_IMM_OP     0x0e3
  17.153 +/* 0x0e6 is irrelevant */
  17.154 +#define LDFCCLR_IMM_OP   0x0e8
  17.155 +#define LDFCNC_IMM_OP    0x0e9
  17.156 +#define STF_IMM_OP       0x0ec
  17.157 +
  17.158 +typedef struct {
  17.159 +	unsigned long	 qp:6;	/* [0:5]   */
  17.160 +	unsigned long    r1:7;	/* [6:12]  */
  17.161 +	unsigned long   imm:7;	/* [13:19] */
  17.162 +	unsigned long    r3:7;	/* [20:26] */
  17.163 +	unsigned long     x:1;  /* [27:27] */
  17.164 +	unsigned long  hint:2;	/* [28:29] */
  17.165 +	unsigned long x6_sz:2;	/* [30:31] */
  17.166 +	unsigned long x6_op:4;	/* [32:35], x6 = x6_sz|x6_op */
  17.167 +	unsigned long     m:1;	/* [36:36] */
  17.168 +	unsigned long    op:4;	/* [37:40] */
  17.169 +	unsigned long   pad:23; /* [41:63] */
  17.170 +} load_store_t;
  17.171 +
  17.172 +
  17.173 +typedef enum {
  17.174 +	UPD_IMMEDIATE,	/* ldXZ r1=[r3],imm(9) */
  17.175 +	UPD_REG		/* ldXZ r1=[r3],r2     */
  17.176 +} update_t;
  17.177 +
  17.178 +/*
  17.179 + * We use tables to keep track of the offsets of registers in the saved state.
  17.180 + * This way we save having big switch/case statements.
  17.181 + *
  17.182 + * We use bit 0 to indicate switch_stack or pt_regs.
  17.183 + * The offset is simply shifted by 1 bit.
  17.184 + * A 2-byte value should be enough to hold any kind of offset
  17.185 + *
  17.186 + * In case the calling convention changes (and thus pt_regs/switch_stack)
  17.187 + * simply use RSW instead of RPT or vice-versa.
  17.188 + */
  17.189 +
  17.190 +#define RPO(x)	((size_t) &((struct pt_regs *)0)->x)
  17.191 +#define RSO(x)	((size_t) &((struct switch_stack *)0)->x)
  17.192 +
  17.193 +#define RPT(x)		(RPO(x) << 1)
  17.194 +#define RSW(x)		(1| RSO(x)<<1)
  17.195 +
  17.196 +#define GR_OFFS(x)	(gr_info[x]>>1)
  17.197 +#define GR_IN_SW(x)	(gr_info[x] & 0x1)
  17.198 +
  17.199 +#define FR_OFFS(x)	(fr_info[x]>>1)
  17.200 +#define FR_IN_SW(x)	(fr_info[x] & 0x1)
  17.201 +
  17.202 +static u16 gr_info[32]={
  17.203 +	0,			/* r0 is read-only : WE SHOULD NEVER GET THIS */
  17.204 +
  17.205 +	RPT(r1), RPT(r2), RPT(r3),
  17.206 +
  17.207 +#ifdef  CONFIG_VTI
  17.208 +	RPT(r4), RPT(r5), RPT(r6), RPT(r7),
  17.209 +#else   //CONFIG_VTI
  17.210 +	RSW(r4), RSW(r5), RSW(r6), RSW(r7),
  17.211 +#endif  //CONFIG_VTI
  17.212 +
  17.213 +	RPT(r8), RPT(r9), RPT(r10), RPT(r11),
  17.214 +	RPT(r12), RPT(r13), RPT(r14), RPT(r15),
  17.215 +
  17.216 +	RPT(r16), RPT(r17), RPT(r18), RPT(r19),
  17.217 +	RPT(r20), RPT(r21), RPT(r22), RPT(r23),
  17.218 +	RPT(r24), RPT(r25), RPT(r26), RPT(r27),
  17.219 +	RPT(r28), RPT(r29), RPT(r30), RPT(r31)
  17.220 +};
  17.221 +
  17.222 +static u16 fr_info[32]={
  17.223 +	0,			/* constant : WE SHOULD NEVER GET THIS */
  17.224 +	0,			/* constant : WE SHOULD NEVER GET THIS */
  17.225 +
  17.226 +	RSW(f2), RSW(f3), RSW(f4), RSW(f5),
  17.227 +
  17.228 +	RPT(f6), RPT(f7), RPT(f8), RPT(f9),
  17.229 +	RPT(f10), RPT(f11),
  17.230 +
  17.231 +	RSW(f12), RSW(f13), RSW(f14),
  17.232 +	RSW(f15), RSW(f16), RSW(f17), RSW(f18), RSW(f19),
  17.233 +	RSW(f20), RSW(f21), RSW(f22), RSW(f23), RSW(f24),
  17.234 +	RSW(f25), RSW(f26), RSW(f27), RSW(f28), RSW(f29),
  17.235 +	RSW(f30), RSW(f31)
  17.236 +};
  17.237 +
  17.238 +/* Invalidate ALAT entry for integer register REGNO.  */
  17.239 +static void
  17.240 +invala_gr (int regno)
  17.241 +{
  17.242 +#	define F(reg)	case reg: ia64_invala_gr(reg); break
  17.243 +
  17.244 +	switch (regno) {
  17.245 +		F(  0); F(  1); F(  2); F(  3); F(  4); F(  5); F(  6); F(  7);
  17.246 +		F(  8); F(  9); F( 10); F( 11); F( 12); F( 13); F( 14); F( 15);
  17.247 +		F( 16); F( 17); F( 18); F( 19); F( 20); F( 21); F( 22); F( 23);
  17.248 +		F( 24); F( 25); F( 26); F( 27); F( 28); F( 29); F( 30); F( 31);
  17.249 +		F( 32); F( 33); F( 34); F( 35); F( 36); F( 37); F( 38); F( 39);
  17.250 +		F( 40); F( 41); F( 42); F( 43); F( 44); F( 45); F( 46); F( 47);
  17.251 +		F( 48); F( 49); F( 50); F( 51); F( 52); F( 53); F( 54); F( 55);
  17.252 +		F( 56); F( 57); F( 58); F( 59); F( 60); F( 61); F( 62); F( 63);
  17.253 +		F( 64); F( 65); F( 66); F( 67); F( 68); F( 69); F( 70); F( 71);
  17.254 +		F( 72); F( 73); F( 74); F( 75); F( 76); F( 77); F( 78); F( 79);
  17.255 +		F( 80); F( 81); F( 82); F( 83); F( 84); F( 85); F( 86); F( 87);
  17.256 +		F( 88); F( 89); F( 90); F( 91); F( 92); F( 93); F( 94); F( 95);
  17.257 +		F( 96); F( 97); F( 98); F( 99); F(100); F(101); F(102); F(103);
  17.258 +		F(104); F(105); F(106); F(107); F(108); F(109); F(110); F(111);
  17.259 +		F(112); F(113); F(114); F(115); F(116); F(117); F(118); F(119);
  17.260 +		F(120); F(121); F(122); F(123); F(124); F(125); F(126); F(127);
  17.261 +	}
  17.262 +#	undef F
  17.263 +}
  17.264 +
  17.265 +/* Invalidate ALAT entry for floating-point register REGNO.  */
  17.266 +static void
  17.267 +invala_fr (int regno)
  17.268 +{
  17.269 +#	define F(reg)	case reg: ia64_invala_fr(reg); break
  17.270 +
  17.271 +	switch (regno) {
  17.272 +		F(  0); F(  1); F(  2); F(  3); F(  4); F(  5); F(  6); F(  7);
  17.273 +		F(  8); F(  9); F( 10); F( 11); F( 12); F( 13); F( 14); F( 15);
  17.274 +		F( 16); F( 17); F( 18); F( 19); F( 20); F( 21); F( 22); F( 23);
  17.275 +		F( 24); F( 25); F( 26); F( 27); F( 28); F( 29); F( 30); F( 31);
  17.276 +		F( 32); F( 33); F( 34); F( 35); F( 36); F( 37); F( 38); F( 39);
  17.277 +		F( 40); F( 41); F( 42); F( 43); F( 44); F( 45); F( 46); F( 47);
  17.278 +		F( 48); F( 49); F( 50); F( 51); F( 52); F( 53); F( 54); F( 55);
  17.279 +		F( 56); F( 57); F( 58); F( 59); F( 60); F( 61); F( 62); F( 63);
  17.280 +		F( 64); F( 65); F( 66); F( 67); F( 68); F( 69); F( 70); F( 71);
  17.281 +		F( 72); F( 73); F( 74); F( 75); F( 76); F( 77); F( 78); F( 79);
  17.282 +		F( 80); F( 81); F( 82); F( 83); F( 84); F( 85); F( 86); F( 87);
  17.283 +		F( 88); F( 89); F( 90); F( 91); F( 92); F( 93); F( 94); F( 95);
  17.284 +		F( 96); F( 97); F( 98); F( 99); F(100); F(101); F(102); F(103);
  17.285 +		F(104); F(105); F(106); F(107); F(108); F(109); F(110); F(111);
  17.286 +		F(112); F(113); F(114); F(115); F(116); F(117); F(118); F(119);
  17.287 +		F(120); F(121); F(122); F(123); F(124); F(125); F(126); F(127);
  17.288 +	}
  17.289 +#	undef F
  17.290 +}
  17.291 +
  17.292 +static inline unsigned long
  17.293 +rotate_reg (unsigned long sor, unsigned long rrb, unsigned long reg)
  17.294 +{
  17.295 +	reg += rrb;
  17.296 +	if (reg >= sor)
  17.297 +		reg -= sor;
  17.298 +	return reg;
  17.299 +}
  17.300 +
  17.301 +#ifdef CONFIG_VTI
  17.302 +static void
  17.303 +set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, unsigned long nat)
  17.304 +{
  17.305 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  17.306 +	unsigned long *bsp, *bspstore, *addr, *rnat_addr, *ubs_end;
  17.307 +	unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
  17.308 +	unsigned long rnats, nat_mask;
  17.309 +    unsigned long old_rsc,new_rsc;
  17.310 +	unsigned long on_kbs,rnat;
  17.311 +	long sof = (regs->cr_ifs) & 0x7f;
  17.312 +	long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
  17.313 +	long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
  17.314 +	long ridx = r1 - 32;
  17.315 +
  17.316 +	if (ridx >= sof) {
  17.317 +		/* this should never happen, as the "rsvd register fault" has higher priority */
  17.318 +		DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof);
  17.319 +		return;
  17.320 +	}
  17.321 +
  17.322 +	if (ridx < sor)
  17.323 +		ridx = rotate_reg(sor, rrb_gr, ridx);
  17.324 +
  17.325 +    old_rsc=ia64_get_rsc();
  17.326 +    new_rsc=old_rsc&(~0x3);
  17.327 +    ia64_set_rsc(new_rsc);
  17.328 +
  17.329 +    bspstore = ia64_get_bspstore();
  17.330 +    bsp =kbs + (regs->loadrs >> 19);//16+3
  17.331 +
  17.332 +	addr = ia64_rse_skip_regs(bsp, -sof + ridx);
  17.333 +    nat_mask = 1UL << ia64_rse_slot_num(addr);
  17.334 +	rnat_addr = ia64_rse_rnat_addr(addr);
  17.335 +
  17.336 +    if(addr >= bspstore){
  17.337 +
  17.338 +        ia64_flushrs ();
  17.339 +        ia64_mf ();
  17.340 +		*addr = val;
  17.341 +        bspstore = ia64_get_bspstore();
  17.342 +    	rnat = ia64_get_rnat ();
  17.343 +        if(bspstore < rnat_addr){
  17.344 +            rnat=rnat&(~nat_mask);
  17.345 +        }else{
  17.346 +            *rnat_addr = (*rnat_addr)&(~nat_mask);
  17.347 +        }
  17.348 +        ia64_mf();
  17.349 +        ia64_loadrs();
  17.350 +        ia64_set_rnat(rnat);
  17.351 +    }else{
  17.352 +
  17.353 +    	rnat = ia64_get_rnat ();
  17.354 +		*addr = val;
  17.355 +        if(bspstore < rnat_addr){
  17.356 +            rnat=rnat&(~nat_mask);
  17.357 +        }else{
  17.358 +            *rnat_addr = (*rnat_addr)&(~nat_mask);
  17.359 +        }
  17.360 +        ia64_set_bspstore (bspstore);
  17.361 +        ia64_set_rnat(rnat);
  17.362 +    }
  17.363 +    ia64_set_rsc(old_rsc);
  17.364 +}
  17.365 +
  17.366 +
  17.367 +static void
  17.368 +get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, unsigned long *nat)
  17.369 +{
  17.370 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  17.371 +	unsigned long *bsp, *addr, *rnat_addr, *ubs_end, *bspstore;
  17.372 +	unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
  17.373 +	unsigned long rnats, nat_mask;
  17.374 +	unsigned long on_kbs;
  17.375 +    unsigned long old_rsc, new_rsc;
  17.376 +	long sof = (regs->cr_ifs) & 0x7f;
  17.377 +	long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
  17.378 +	long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
  17.379 +	long ridx = r1 - 32;
  17.380 +
  17.381 +	if (ridx >= sof) {
  17.382 +		/* read of out-of-frame register returns an undefined value; 0 in our case.  */
  17.383 +		DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof);
  17.384 +		panic("wrong stack register number");
  17.385 +	}
  17.386 +
  17.387 +	if (ridx < sor)
  17.388 +		ridx = rotate_reg(sor, rrb_gr, ridx);
  17.389 +
  17.390 +    old_rsc=ia64_get_rsc();
  17.391 +    new_rsc=old_rsc&(~(0x3));
  17.392 +    ia64_set_rsc(new_rsc);
  17.393 +
  17.394 +    bspstore = ia64_get_bspstore();
  17.395 +    bsp =kbs + (regs->loadrs >> 19); //16+3;
  17.396 +
  17.397 +	addr = ia64_rse_skip_regs(bsp, -sof + ridx);
  17.398 +    nat_mask = 1UL << ia64_rse_slot_num(addr);
  17.399 +	rnat_addr = ia64_rse_rnat_addr(addr);
  17.400 +
  17.401 +    if(addr >= bspstore){
  17.402 +
  17.403 +        ia64_flushrs ();
  17.404 +        ia64_mf ();
  17.405 +        bspstore = ia64_get_bspstore();
  17.406 +    }
  17.407 +	*val=*addr;
  17.408 +    if(bspstore < rnat_addr){
  17.409 +        *nat=!!(ia64_get_rnat()&nat_mask);
  17.410 +    }else{
  17.411 +        *nat = !!((*rnat_addr)&nat_mask);
  17.412 +    }
  17.413 +    ia64_set_rsc(old_rsc);
  17.414 +}
  17.415 +#else // CONFIG_VTI
  17.416 +static void
  17.417 +set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, int nat)
  17.418 +{
  17.419 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  17.420 +	unsigned long *bsp, *bspstore, *addr, *rnat_addr, *ubs_end;
  17.421 +	unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
  17.422 +	unsigned long rnats, nat_mask;
  17.423 +	unsigned long on_kbs;
  17.424 +	long sof = (regs->cr_ifs) & 0x7f;
  17.425 +	long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
  17.426 +	long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
  17.427 +	long ridx = r1 - 32;
  17.428 +
  17.429 +	if (ridx >= sof) {
  17.430 +		/* this should never happen, as the "rsvd register fault" has higher priority */
  17.431 +		DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof);
  17.432 +		return;
  17.433 +	}
  17.434 +
  17.435 +	if (ridx < sor)
  17.436 +		ridx = rotate_reg(sor, rrb_gr, ridx);
  17.437 +
  17.438 +	DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n",
  17.439 +	       r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx);
  17.440 +
  17.441 +	on_kbs = ia64_rse_num_regs(kbs, (unsigned long *) sw->ar_bspstore);
  17.442 +	addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, -sof + ridx);
  17.443 +	if (addr >= kbs) {
  17.444 +		/* the register is on the kernel backing store: easy... */
  17.445 +		rnat_addr = ia64_rse_rnat_addr(addr);
  17.446 +		if ((unsigned long) rnat_addr >= sw->ar_bspstore)
  17.447 +			rnat_addr = &sw->ar_rnat;
  17.448 +		nat_mask = 1UL << ia64_rse_slot_num(addr);
  17.449 +
  17.450 +		*addr = val;
  17.451 +		if (nat)
  17.452 +			*rnat_addr |=  nat_mask;
  17.453 +		else
  17.454 +			*rnat_addr &= ~nat_mask;
  17.455 +		return;
  17.456 +	}
  17.457 +
  17.458 +	if (!user_stack(current, regs)) {
  17.459 +		DPRINT("ignoring kernel write to r%lu; register isn't on the kernel RBS!", r1);
  17.460 +		return;
  17.461 +	}
  17.462 +
  17.463 +	bspstore = (unsigned long *)regs->ar_bspstore;
  17.464 +	ubs_end = ia64_rse_skip_regs(bspstore, on_kbs);
  17.465 +	bsp     = ia64_rse_skip_regs(ubs_end, -sof);
  17.466 +	addr    = ia64_rse_skip_regs(bsp, ridx);
  17.467 +
  17.468 +	DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr);
  17.469 +
  17.470 +	ia64_poke(current, sw, (unsigned long) ubs_end, (unsigned long) addr, val);
  17.471 +
  17.472 +	rnat_addr = ia64_rse_rnat_addr(addr);
  17.473 +
  17.474 +	ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, &rnats);
  17.475 +	DPRINT("rnat @%p = 0x%lx nat=%d old nat=%ld\n",
  17.476 +	       (void *) rnat_addr, rnats, nat, (rnats >> ia64_rse_slot_num(addr)) & 1);
  17.477 +
  17.478 +	nat_mask = 1UL << ia64_rse_slot_num(addr);
  17.479 +	if (nat)
  17.480 +		rnats |=  nat_mask;
  17.481 +	else
  17.482 +		rnats &= ~nat_mask;
  17.483 +	ia64_poke(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, rnats);
  17.484 +
  17.485 +	DPRINT("rnat changed to @%p = 0x%lx\n", (void *) rnat_addr, rnats);
  17.486 +}
  17.487 +
  17.488 +
  17.489 +static void
  17.490 +get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, int *nat)
  17.491 +{
  17.492 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  17.493 +	unsigned long *bsp, *addr, *rnat_addr, *ubs_end, *bspstore;
  17.494 +	unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
  17.495 +	unsigned long rnats, nat_mask;
  17.496 +	unsigned long on_kbs;
  17.497 +	long sof = (regs->cr_ifs) & 0x7f;
  17.498 +	long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
  17.499 +	long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
  17.500 +	long ridx = r1 - 32;
  17.501 +
  17.502 +	if (ridx >= sof) {
  17.503 +		/* read of out-of-frame register returns an undefined value; 0 in our case.  */
  17.504 +		DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof);
  17.505 +		goto fail;
  17.506 +	}
  17.507 +
  17.508 +	if (ridx < sor)
  17.509 +		ridx = rotate_reg(sor, rrb_gr, ridx);
  17.510 +
  17.511 +	DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n",
  17.512 +	       r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx);
  17.513 +
  17.514 +	on_kbs = ia64_rse_num_regs(kbs, (unsigned long *) sw->ar_bspstore);
  17.515 +	addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, -sof + ridx);
  17.516 +	if (addr >= kbs) {
  17.517 +		/* the register is on the kernel backing store: easy... */
  17.518 +		*val = *addr;
  17.519 +		if (nat) {
  17.520 +			rnat_addr = ia64_rse_rnat_addr(addr);
  17.521 +			if ((unsigned long) rnat_addr >= sw->ar_bspstore)
  17.522 +				rnat_addr = &sw->ar_rnat;
  17.523 +			nat_mask = 1UL << ia64_rse_slot_num(addr);
  17.524 +			*nat = (*rnat_addr & nat_mask) != 0;
  17.525 +		}
  17.526 +		return;
  17.527 +	}
  17.528 +
  17.529 +	if (!user_stack(current, regs)) {
  17.530 +		DPRINT("ignoring kernel read of r%lu; register isn't on the RBS!", r1);
  17.531 +		goto fail;
  17.532 +	}
  17.533 +
  17.534 +	bspstore = (unsigned long *)regs->ar_bspstore;
  17.535 +	ubs_end = ia64_rse_skip_regs(bspstore, on_kbs);
  17.536 +	bsp     = ia64_rse_skip_regs(ubs_end, -sof);
  17.537 +	addr    = ia64_rse_skip_regs(bsp, ridx);
  17.538 +
  17.539 +	DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr);
  17.540 +
  17.541 +	ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) addr, val);
  17.542 +
  17.543 +	if (nat) {
  17.544 +		rnat_addr = ia64_rse_rnat_addr(addr);
  17.545 +		nat_mask = 1UL << ia64_rse_slot_num(addr);
  17.546 +
  17.547 +		DPRINT("rnat @%p = 0x%lx\n", (void *) rnat_addr, rnats);
  17.548 +
  17.549 +		ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, &rnats);
  17.550 +		*nat = (rnats & nat_mask) != 0;
  17.551 +	}
  17.552 +	return;
  17.553 +
  17.554 +  fail:
  17.555 +	*val = 0;
  17.556 +	if (nat)
  17.557 +		*nat = 0;
  17.558 +	return;
  17.559 +}
  17.560 +#endif // CONFIG_VTI
  17.561 +
  17.562 +
  17.563 +#ifdef XEN
  17.564 +void
  17.565 +#else
  17.566 +static void
  17.567 +#endif
  17.568 +setreg (unsigned long regnum, unsigned long val, int nat, struct pt_regs *regs)
  17.569 +{
  17.570 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  17.571 +	unsigned long addr;
  17.572 +	unsigned long bitmask;
  17.573 +	unsigned long *unat;
  17.574 +
  17.575 +	/*
  17.576 +	 * First takes care of stacked registers
  17.577 +	 */
  17.578 +	if (regnum >= IA64_FIRST_STACKED_GR) {
  17.579 +		set_rse_reg(regs, regnum, val, nat);
  17.580 +		return;
  17.581 +	}
  17.582 +
  17.583 +	/*
  17.584 +	 * Using r0 as a target raises a General Exception fault which has higher priority
  17.585 +	 * than the Unaligned Reference fault.
  17.586 +	 */
  17.587 +
  17.588 +	/*
  17.589 +	 * Now look at registers in [0-31] range and init correct UNAT
  17.590 +	 */
  17.591 +	if (GR_IN_SW(regnum)) {
  17.592 +		addr = (unsigned long)sw;
  17.593 +		unat = &sw->ar_unat;
  17.594 +	} else {
  17.595 +		addr = (unsigned long)regs;
  17.596 +#ifdef CONFIG_VTI
  17.597 +		unat = &regs->eml_unat;
  17.598 +#else //CONFIG_VTI
  17.599 +		unat = &sw->caller_unat;
  17.600 +#endif  //CONFIG_VTI
  17.601 +	}
  17.602 +	DPRINT("tmp_base=%lx switch_stack=%s offset=%d\n",
  17.603 +	       addr, unat==&sw->ar_unat ? "yes":"no", GR_OFFS(regnum));
  17.604 +	/*
  17.605 +	 * add offset from base of struct
  17.606 +	 * and do it !
  17.607 +	 */
  17.608 +	addr += GR_OFFS(regnum);
  17.609 +
  17.610 +	*(unsigned long *)addr = val;
  17.611 +
  17.612 +	/*
  17.613 +	 * We need to clear the corresponding UNAT bit to fully emulate the load
  17.614 +	 * UNAT bit_pos = GR[r3]{8:3} form EAS-2.4
  17.615 +	 */
  17.616 +	bitmask   = 1UL << (addr >> 3 & 0x3f);
  17.617 +	DPRINT("*0x%lx=0x%lx NaT=%d prev_unat @%p=%lx\n", addr, val, nat, (void *) unat, *unat);
  17.618 +	if (nat) {
  17.619 +		*unat |= bitmask;
  17.620 +	} else {
  17.621 +		*unat &= ~bitmask;
  17.622 +	}
  17.623 +	DPRINT("*0x%lx=0x%lx NaT=%d new unat: %p=%lx\n", addr, val, nat, (void *) unat,*unat);
  17.624 +}
  17.625 +
  17.626 +/*
  17.627 + * Return the (rotated) index for floating point register REGNUM (REGNUM must be in the
  17.628 + * range from 32-127, result is in the range from 0-95.
  17.629 + */
  17.630 +static inline unsigned long
  17.631 +fph_index (struct pt_regs *regs, long regnum)
  17.632 +{
  17.633 +	unsigned long rrb_fr = (regs->cr_ifs >> 25) & 0x7f;
  17.634 +	return rotate_reg(96, rrb_fr, (regnum - IA64_FIRST_ROTATING_FR));
  17.635 +}
  17.636 +
  17.637 +static void
  17.638 +setfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
  17.639 +{
  17.640 +	struct switch_stack *sw = (struct switch_stack *)regs - 1;
  17.641 +	unsigned long addr;
  17.642 +
  17.643 +	/*
  17.644 +	 * From EAS-2.5: FPDisableFault has higher priority than Unaligned
  17.645 +	 * Fault. Thus, when we get here, we know the partition is enabled.
  17.646 +	 * To update f32-f127, there are three choices:
  17.647 +	 *
  17.648 +	 *	(1) save f32-f127 to thread.fph and update the values there
  17.649 +	 *	(2) use a gigantic switch statement to directly access the registers
  17.650 +	 *	(3) generate code on the fly to update the desired register
  17.651 +	 *
  17.652 +	 * For now, we are using approach (1).
  17.653 +	 */
  17.654 +	if (regnum >= IA64_FIRST_ROTATING_FR) {
  17.655 +		ia64_sync_fph(current);
  17.656 +#ifdef XEN
  17.657 +		current->arch._thread.fph[fph_index(regs, regnum)] = *fpval;
  17.658 +#else
  17.659 +		current->thread.fph[fph_index(regs, regnum)] = *fpval;
  17.660 +#endif
  17.661 +	} else {
  17.662 +		/*
  17.663 +		 * pt_regs or switch_stack ?
  17.664 +		 */
  17.665 +		if (FR_IN_SW(regnum)) {
  17.666 +			addr = (unsigned long)sw;
  17.667 +		} else {
  17.668 +			addr = (unsigned long)regs;
  17.669 +		}
  17.670 +
  17.671 +		DPRINT("tmp_base=%lx offset=%d\n", addr, FR_OFFS(regnum));
  17.672 +
  17.673 +		addr += FR_OFFS(regnum);
  17.674 +		*(struct ia64_fpreg *)addr = *fpval;
  17.675 +
  17.676 +		/*
  17.677 +		 * mark the low partition as being used now
  17.678 +		 *
  17.679 +		 * It is highly unlikely that this bit is not already set, but
  17.680 +		 * let's do it for safety.
  17.681 +		 */
  17.682 +		regs->cr_ipsr |= IA64_PSR_MFL;
  17.683 +	}
  17.684 +}
  17.685 +
  17.686 +/*
  17.687 + * Those 2 inline functions generate the spilled versions of the constant floating point
  17.688 + * registers which can be used with stfX
  17.689 + */
  17.690 +static inline void
  17.691 +float_spill_f0 (struct ia64_fpreg *final)
  17.692 +{
  17.693 +	ia64_stf_spill(final, 0);
  17.694 +}
  17.695 +
  17.696 +static inline void
  17.697 +float_spill_f1 (struct ia64_fpreg *final)
  17.698 +{
  17.699 +	ia64_stf_spill(final, 1);
  17.700 +}
  17.701 +
  17.702 +static void
  17.703 +getfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
  17.704 +{
  17.705 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  17.706 +	unsigned long addr;
  17.707 +
  17.708 +	/*
  17.709 +	 * From EAS-2.5: FPDisableFault has higher priority than
  17.710 +	 * Unaligned Fault. Thus, when we get here, we know the partition is
  17.711 +	 * enabled.
  17.712 +	 *
  17.713 +	 * When regnum > 31, the register is still live and we need to force a save
  17.714 +	 * to current->thread.fph to get access to it.  See discussion in setfpreg()
  17.715 +	 * for reasons and other ways of doing this.
  17.716 +	 */
  17.717 +	if (regnum >= IA64_FIRST_ROTATING_FR) {
  17.718 +		ia64_flush_fph(current);
  17.719 +#ifdef XEN
  17.720 +		*fpval = current->arch._thread.fph[fph_index(regs, regnum)];
  17.721 +#else
  17.722 +		*fpval = current->thread.fph[fph_index(regs, regnum)];
  17.723 +#endif
  17.724 +	} else {
  17.725 +		/*
  17.726 +		 * f0 = 0.0, f1= 1.0. Those registers are constant and are thus
  17.727 +		 * not saved, we must generate their spilled form on the fly
  17.728 +		 */
  17.729 +		switch(regnum) {
  17.730 +		case 0:
  17.731 +			float_spill_f0(fpval);
  17.732 +			break;
  17.733 +		case 1:
  17.734 +			float_spill_f1(fpval);
  17.735 +			break;
  17.736 +		default:
  17.737 +			/*
  17.738 +			 * pt_regs or switch_stack ?
  17.739 +			 */
  17.740 +			addr =  FR_IN_SW(regnum) ? (unsigned long)sw
  17.741 +						 : (unsigned long)regs;
  17.742 +
  17.743 +			DPRINT("is_sw=%d tmp_base=%lx offset=0x%x\n",
  17.744 +			       FR_IN_SW(regnum), addr, FR_OFFS(regnum));
  17.745 +
  17.746 +			addr  += FR_OFFS(regnum);
  17.747 +			*fpval = *(struct ia64_fpreg *)addr;
  17.748 +		}
  17.749 +	}
  17.750 +}
  17.751 +
  17.752 +
  17.753 +#ifdef XEN
  17.754 +void
  17.755 +#else
  17.756 +static void
  17.757 +#endif
  17.758 +getreg (unsigned long regnum, unsigned long *val, int *nat, struct pt_regs *regs)
  17.759 +{
  17.760 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  17.761 +	unsigned long addr, *unat;
  17.762 +
  17.763 +	if (regnum >= IA64_FIRST_STACKED_GR) {
  17.764 +		get_rse_reg(regs, regnum, val, nat);
  17.765 +		return;
  17.766 +	}
  17.767 +
  17.768 +	/*
  17.769 +	 * take care of r0 (read-only always evaluate to 0)
  17.770 +	 */
  17.771 +	if (regnum == 0) {
  17.772 +		*val = 0;
  17.773 +		if (nat)
  17.774 +			*nat = 0;
  17.775 +		return;
  17.776 +	}
  17.777 +
  17.778 +	/*
  17.779 +	 * Now look at registers in [0-31] range and init correct UNAT
  17.780 +	 */
  17.781 +	if (GR_IN_SW(regnum)) {
  17.782 +		addr = (unsigned long)sw;
  17.783 +		unat = &sw->ar_unat;
  17.784 +	} else {
  17.785 +		addr = (unsigned long)regs;
  17.786 +#ifdef  CONFIG_VTI
  17.787 +		unat = &regs->eml_unat;;
  17.788 +#else   //CONFIG_VTI
  17.789 +		unat = &sw->caller_unat;
  17.790 +#endif  //CONFIG_VTI
  17.791 +	}
  17.792 +
  17.793 +	DPRINT("addr_base=%lx offset=0x%x\n", addr,  GR_OFFS(regnum));
  17.794 +
  17.795 +	addr += GR_OFFS(regnum);
  17.796 +
  17.797 +	*val  = *(unsigned long *)addr;
  17.798 +
  17.799 +	/*
  17.800 +	 * do it only when requested
  17.801 +	 */
  17.802 +	if (nat)
  17.803 +		*nat  = (*unat >> (addr >> 3 & 0x3f)) & 0x1UL;
  17.804 +}
  17.805 +
  17.806 +static void
  17.807 +emulate_load_updates (update_t type, load_store_t ld, struct pt_regs *regs, unsigned long ifa)
  17.808 +{
  17.809 +	/*
  17.810 +	 * IMPORTANT:
  17.811 +	 * Given the way we handle unaligned speculative loads, we should
  17.812 +	 * not get to this point in the code but we keep this sanity check,
  17.813 +	 * just in case.
  17.814 +	 */
  17.815 +	if (ld.x6_op == 1 || ld.x6_op == 3) {
  17.816 +		printk(KERN_ERR "%s: register update on speculative load, error\n", __FUNCTION__);
  17.817 +		die_if_kernel("unaligned reference on speculative load with register update\n",
  17.818 +			      regs, 30);
  17.819 +	}
  17.820 +
  17.821 +
  17.822 +	/*
  17.823 +	 * at this point, we know that the base register to update is valid i.e.,
  17.824 +	 * it's not r0
  17.825 +	 */
  17.826 +	if (type == UPD_IMMEDIATE) {
  17.827 +		unsigned long imm;
  17.828 +
  17.829 +		/*
  17.830 +		 * Load +Imm: ldXZ r1=[r3],imm(9)
  17.831 +		 *
  17.832 +		 *
  17.833 +		 * form imm9: [13:19] contain the first 7 bits
  17.834 +		 */
  17.835 +		imm = ld.x << 7 | ld.imm;
  17.836 +
  17.837 +		/*
  17.838 +		 * sign extend (1+8bits) if m set
  17.839 +		 */
  17.840 +		if (ld.m) imm |= SIGN_EXT9;
  17.841 +
  17.842 +		/*
  17.843 +		 * ifa == r3 and we know that the NaT bit on r3 was clear so
  17.844 +		 * we can directly use ifa.
  17.845 +		 */
  17.846 +		ifa += imm;
  17.847 +
  17.848 +		setreg(ld.r3, ifa, 0, regs);
  17.849 +
  17.850 +		DPRINT("ld.x=%d ld.m=%d imm=%ld r3=0x%lx\n", ld.x, ld.m, imm, ifa);
  17.851 +
  17.852 +	} else if (ld.m) {
  17.853 +		unsigned long r2;
  17.854 +		int nat_r2;
  17.855 +
  17.856 +		/*
  17.857 +		 * Load +Reg Opcode: ldXZ r1=[r3],r2
  17.858 +		 *
  17.859 +		 * Note: that we update r3 even in the case of ldfX.a
  17.860 +		 * (where the load does not happen)
  17.861 +		 *
  17.862 +		 * The way the load algorithm works, we know that r3 does not
  17.863 +		 * have its NaT bit set (would have gotten NaT consumption
  17.864 +		 * before getting the unaligned fault). So we can use ifa
  17.865 +		 * which equals r3 at this point.
  17.866 +		 *
  17.867 +		 * IMPORTANT:
  17.868 +		 * The above statement holds ONLY because we know that we
  17.869 +		 * never reach this code when trying to do a ldX.s.
  17.870 +		 * If we ever make it to here on an ldfX.s then
  17.871 +		 */
  17.872 +		getreg(ld.imm, &r2, &nat_r2, regs);
  17.873 +
  17.874 +		ifa += r2;
  17.875 +
  17.876 +		/*
  17.877 +		 * propagate Nat r2 -> r3
  17.878 +		 */
  17.879 +		setreg(ld.r3, ifa, nat_r2, regs);
  17.880 +
  17.881 +		DPRINT("imm=%d r2=%ld r3=0x%lx nat_r2=%d\n",ld.imm, r2, ifa, nat_r2);
  17.882 +	}
  17.883 +}
  17.884 +
  17.885 +
  17.886 +static int
  17.887 +emulate_load_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
  17.888 +{
  17.889 +	unsigned int len = 1 << ld.x6_sz;
  17.890 +	unsigned long val = 0;
  17.891 +
  17.892 +	/*
  17.893 +	 * r0, as target, doesn't need to be checked because Illegal Instruction
  17.894 +	 * faults have higher priority than unaligned faults.
  17.895 +	 *
  17.896 +	 * r0 cannot be found as the base as it would never generate an
  17.897 +	 * unaligned reference.
  17.898 +	 */
  17.899 +
  17.900 +	/*
  17.901 +	 * ldX.a we will emulate load and also invalidate the ALAT entry.
  17.902 +	 * See comment below for explanation on how we handle ldX.a
  17.903 +	 */
  17.904 +
  17.905 +	if (len != 2 && len != 4 && len != 8) {
  17.906 +		DPRINT("unknown size: x6=%d\n", ld.x6_sz);
  17.907 +		return -1;
  17.908 +	}
  17.909 +	/* this assumes little-endian byte-order: */
  17.910 +	if (copy_from_user(&val, (void __user *) ifa, len))
  17.911 +		return -1;
  17.912 +	setreg(ld.r1, val, 0, regs);
  17.913 +
  17.914 +	/*
  17.915 +	 * check for updates on any kind of loads
  17.916 +	 */
  17.917 +	if (ld.op == 0x5 || ld.m)
  17.918 +		emulate_load_updates(ld.op == 0x5 ? UPD_IMMEDIATE: UPD_REG, ld, regs, ifa);
  17.919 +
  17.920 +	/*
  17.921 +	 * handling of various loads (based on EAS2.4):
  17.922 +	 *
  17.923 +	 * ldX.acq (ordered load):
  17.924 +	 *	- acquire semantics would have been used, so force fence instead.
  17.925 +	 *
  17.926 +	 * ldX.c.clr (check load and clear):
  17.927 +	 *	- if we get to this handler, it's because the entry was not in the ALAT.
  17.928 +	 *	  Therefore the operation reverts to a normal load
  17.929 +	 *
  17.930 +	 * ldX.c.nc (check load no clear):
  17.931 +	 *	- same as previous one
  17.932 +	 *
  17.933 +	 * ldX.c.clr.acq (ordered check load and clear):
  17.934 +	 *	- same as above for c.clr part. The load needs to have acquire semantics. So
  17.935 +	 *	  we use the fence semantics which is stronger and thus ensures correctness.
  17.936 +	 *
  17.937 +	 * ldX.a (advanced load):
  17.938 +	 *	- suppose ldX.a r1=[r3]. If we get to the unaligned trap it's because the
  17.939 +	 *	  address doesn't match requested size alignment. This means that we would
  17.940 +	 *	  possibly need more than one load to get the result.
  17.941 +	 *
  17.942 +	 *	  The load part can be handled just like a normal load, however the difficult
  17.943 +	 *	  part is to get the right thing into the ALAT. The critical piece of information
  17.944 +	 *	  in the base address of the load & size. To do that, a ld.a must be executed,
  17.945 +	 *	  clearly any address can be pushed into the table by using ld1.a r1=[r3]. Now
  17.946 +	 *	  if we use the same target register, we will be okay for the check.a instruction.
  17.947 +	 *	  If we look at the store, basically a stX [r3]=r1 checks the ALAT  for any entry
  17.948 +	 *	  which would overlap within [r3,r3+X] (the size of the load was store in the
  17.949 +	 *	  ALAT). If such an entry is found the entry is invalidated. But this is not good
  17.950 +	 *	  enough, take the following example:
  17.951 +	 *		r3=3
  17.952 +	 *		ld4.a r1=[r3]
  17.953 +	 *
  17.954 +	 *	  Could be emulated by doing:
  17.955 +	 *		ld1.a r1=[r3],1
  17.956 +	 *		store to temporary;
  17.957 +	 *		ld1.a r1=[r3],1
  17.958 +	 *		store & shift to temporary;
  17.959 +	 *		ld1.a r1=[r3],1
  17.960 +	 *		store & shift to temporary;
  17.961 +	 *		ld1.a r1=[r3]
  17.962 +	 *		store & shift to temporary;
  17.963 +	 *		r1=temporary
  17.964 +	 *
  17.965 +	 *	  So in this case, you would get the right value is r1 but the wrong info in
  17.966 +	 *	  the ALAT.  Notice that you could do it in reverse to finish with address 3
  17.967 +	 *	  but you would still get the size wrong.  To get the size right, one needs to
  17.968 +	 *	  execute exactly the same kind of load. You could do it from a aligned
  17.969 +	 *	  temporary location, but you would get the address wrong.
  17.970 +	 *
  17.971 +	 *	  So no matter what, it is not possible to emulate an advanced load
  17.972 +	 *	  correctly. But is that really critical ?
  17.973 +	 *
  17.974 +	 *	  We will always convert ld.a into a normal load with ALAT invalidated.  This
  17.975 +	 *	  will enable compiler to do optimization where certain code path after ld.a
  17.976 +	 *	  is not required to have ld.c/chk.a, e.g., code path with no intervening stores.
  17.977 +	 *
  17.978 +	 *	  If there is a store after the advanced load, one must either do a ld.c.* or
  17.979 +	 *	  chk.a.* to reuse the value stored in the ALAT. Both can "fail" (meaning no
  17.980 +	 *	  entry found in ALAT), and that's perfectly ok because:
  17.981 +	 *
  17.982 +	 *		- ld.c.*, if the entry is not present a  normal load is executed
  17.983 +	 *		- chk.a.*, if the entry is not present, execution jumps to recovery code
  17.984 +	 *
  17.985 +	 *	  In either case, the load can be potentially retried in another form.
  17.986 +	 *
  17.987 +	 *	  ALAT must be invalidated for the register (so that chk.a or ld.c don't pick
  17.988 +	 *	  up a stale entry later). The register base update MUST also be performed.
  17.989 +	 */
  17.990 +
  17.991 +	/*
  17.992 +	 * when the load has the .acq completer then
  17.993 +	 * use ordering fence.
  17.994 +	 */
  17.995 +	if (ld.x6_op == 0x5 || ld.x6_op == 0xa)
  17.996 +		mb();
  17.997 +
  17.998 +	/*
  17.999 +	 * invalidate ALAT entry in case of advanced load
 17.1000 +	 */
 17.1001 +	if (ld.x6_op == 0x2)
 17.1002 +		invala_gr(ld.r1);
 17.1003 +
 17.1004 +	return 0;
 17.1005 +}
 17.1006 +
 17.1007 +static int
 17.1008 +emulate_store_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
 17.1009 +{
 17.1010 +	unsigned long r2;
 17.1011 +	unsigned int len = 1 << ld.x6_sz;
 17.1012 +
 17.1013 +	/*
 17.1014 +	 * if we get to this handler, Nat bits on both r3 and r2 have already
 17.1015 +	 * been checked. so we don't need to do it
 17.1016 +	 *
 17.1017 +	 * extract the value to be stored
 17.1018 +	 */
 17.1019 +	getreg(ld.imm, &r2, NULL, regs);
 17.1020 +
 17.1021 +	/*
 17.1022 +	 * we rely on the macros in unaligned.h for now i.e.,
 17.1023 +	 * we let the compiler figure out how to read memory gracefully.
 17.1024 +	 *
 17.1025 +	 * We need this switch/case because the way the inline function
 17.1026 +	 * works. The code is optimized by the compiler and looks like
 17.1027 +	 * a single switch/case.
 17.1028 +	 */
 17.1029 +	DPRINT("st%d [%lx]=%lx\n", len, ifa, r2);
 17.1030 +
 17.1031 +	if (len != 2 && len != 4 && len != 8) {
 17.1032 +		DPRINT("unknown size: x6=%d\n", ld.x6_sz);
 17.1033 +		return -1;
 17.1034 +	}
 17.1035 +
 17.1036 +	/* this assumes little-endian byte-order: */
 17.1037 +	if (copy_to_user((void __user *) ifa, &r2, len))
 17.1038 +		return -1;
 17.1039 +
 17.1040 +	/*
 17.1041 +	 * stX [r3]=r2,imm(9)
 17.1042 +	 *
 17.1043 +	 * NOTE:
 17.1044 +	 * ld.r3 can never be r0, because r0 would not generate an
 17.1045 +	 * unaligned access.
 17.1046 +	 */
 17.1047 +	if (ld.op == 0x5) {
 17.1048 +		unsigned long imm;
 17.1049 +
 17.1050 +		/*
 17.1051 +		 * form imm9: [12:6] contain first 7bits
 17.1052 +		 */
 17.1053 +		imm = ld.x << 7 | ld.r1;
 17.1054 +		/*
 17.1055 +		 * sign extend (8bits) if m set
 17.1056 +		 */
 17.1057 +		if (ld.m) imm |= SIGN_EXT9;
 17.1058 +		/*
 17.1059 +		 * ifa == r3 (NaT is necessarily cleared)
 17.1060 +		 */
 17.1061 +		ifa += imm;
 17.1062 +
 17.1063 +		DPRINT("imm=%lx r3=%lx\n", imm, ifa);
 17.1064 +
 17.1065 +		setreg(ld.r3, ifa, 0, regs);
 17.1066 +	}
 17.1067 +	/*
 17.1068 +	 * we don't have alat_invalidate_multiple() so we need
 17.1069 +	 * to do the complete flush :-<<
 17.1070 +	 */
 17.1071 +	ia64_invala();
 17.1072 +
 17.1073 +	/*
 17.1074 +	 * stX.rel: use fence instead of release
 17.1075 +	 */
 17.1076 +	if (ld.x6_op == 0xd)
 17.1077 +		mb();
 17.1078 +
 17.1079 +	return 0;
 17.1080 +}
 17.1081 +
 17.1082 +/*
 17.1083 + * floating point operations sizes in bytes
 17.1084 + */
 17.1085 +static const unsigned char float_fsz[4]={
 17.1086 +	10, /* extended precision (e) */
 17.1087 +	8,  /* integer (8)            */
 17.1088 +	4,  /* single precision (s)   */
 17.1089 +	8   /* double precision (d)   */
 17.1090 +};
 17.1091 +
 17.1092 +static inline void
 17.1093 +mem2float_extended (struct ia64_fpreg *init, struct ia64_fpreg *final)
 17.1094 +{
 17.1095 +	ia64_ldfe(6, init);
 17.1096 +	ia64_stop();
 17.1097 +	ia64_stf_spill(final, 6);
 17.1098 +}
 17.1099 +
 17.1100 +static inline void
 17.1101 +mem2float_integer (struct ia64_fpreg *init, struct ia64_fpreg *final)
 17.1102 +{
 17.1103 +	ia64_ldf8(6, init);
 17.1104 +	ia64_stop();
 17.1105 +	ia64_stf_spill(final, 6);
 17.1106 +}
 17.1107 +
 17.1108 +static inline void
 17.1109 +mem2float_single (struct ia64_fpreg *init, struct ia64_fpreg *final)
 17.1110 +{
 17.1111 +	ia64_ldfs(6, init);
 17.1112 +	ia64_stop();
 17.1113 +	ia64_stf_spill(final, 6);
 17.1114 +}
 17.1115 +
 17.1116 +static inline void
 17.1117 +mem2float_double (struct ia64_fpreg *init, struct ia64_fpreg *final)
 17.1118 +{
 17.1119 +	ia64_ldfd(6, init);
 17.1120 +	ia64_stop();
 17.1121 +	ia64_stf_spill(final, 6);
 17.1122 +}
 17.1123 +
 17.1124 +static inline void
 17.1125 +float2mem_extended (struct ia64_fpreg *init, struct ia64_fpreg *final)
 17.1126 +{
 17.1127 +	ia64_ldf_fill(6, init);
 17.1128 +	ia64_stop();
 17.1129 +	ia64_stfe(final, 6);
 17.1130 +}
 17.1131 +
 17.1132 +static inline void
 17.1133 +float2mem_integer (struct ia64_fpreg *init, struct ia64_fpreg *final)
 17.1134 +{
 17.1135 +	ia64_ldf_fill(6, init);
 17.1136 +	ia64_stop();
 17.1137 +	ia64_stf8(final, 6);
 17.1138 +}
 17.1139 +
 17.1140 +static inline void
 17.1141 +float2mem_single (struct ia64_fpreg *init, struct ia64_fpreg *final)
 17.1142 +{
 17.1143 +	ia64_ldf_fill(6, init);
 17.1144 +	ia64_stop();
 17.1145 +	ia64_stfs(final, 6);
 17.1146 +}
 17.1147 +
 17.1148 +static inline void
 17.1149 +float2mem_double (struct ia64_fpreg *init, struct ia64_fpreg *final)
 17.1150 +{
 17.1151 +	ia64_ldf_fill(6, init);
 17.1152 +	ia64_stop();
 17.1153 +	ia64_stfd(final, 6);
 17.1154 +}
 17.1155 +
 17.1156 +static int
 17.1157 +emulate_load_floatpair (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
 17.1158 +{
 17.1159 +	struct ia64_fpreg fpr_init[2];
 17.1160 +	struct ia64_fpreg fpr_final[2];
 17.1161 +	unsigned long len = float_fsz[ld.x6_sz];
 17.1162 +
 17.1163 +	/*
 17.1164 +	 * fr0 & fr1 don't need to be checked because Illegal Instruction faults have
 17.1165 +	 * higher priority than unaligned faults.
 17.1166 +	 *
 17.1167 +	 * r0 cannot be found as the base as it would never generate an unaligned
 17.1168 +	 * reference.
 17.1169 +	 */
 17.1170 +
 17.1171 +	/*
 17.1172 +	 * make sure we get clean buffers
 17.1173 +	 */
 17.1174 +	memset(&fpr_init, 0, sizeof(fpr_init));
 17.1175 +	memset(&fpr_final, 0, sizeof(fpr_final));
 17.1176 +
 17.1177 +	/*
 17.1178 +	 * ldfpX.a: we don't try to emulate anything but we must
 17.1179 +	 * invalidate the ALAT entry and execute updates, if any.
 17.1180 +	 */
 17.1181 +	if (ld.x6_op != 0x2) {
 17.1182 +		/*
 17.1183 +		 * This assumes little-endian byte-order.  Note that there is no "ldfpe"
 17.1184 +		 * instruction:
 17.1185 +		 */
 17.1186 +		if (copy_from_user(&fpr_init[0], (void __user *) ifa, len)
 17.1187 +		    || copy_from_user(&fpr_init[1], (void __user *) (ifa + len), len))
 17.1188 +			return -1;
 17.1189 +
 17.1190 +		DPRINT("ld.r1=%d ld.imm=%d x6_sz=%d\n", ld.r1, ld.imm, ld.x6_sz);
 17.1191 +		DDUMP("frp_init =", &fpr_init, 2*len);
 17.1192 +		/*
 17.1193 +		 * XXX fixme
 17.1194 +		 * Could optimize inlines by using ldfpX & 2 spills
 17.1195 +		 */
 17.1196 +		switch( ld.x6_sz ) {
 17.1197 +			case 0:
 17.1198 +				mem2float_extended(&fpr_init[0], &fpr_final[0]);
 17.1199 +				mem2float_extended(&fpr_init[1], &fpr_final[1]);
 17.1200 +				break;
 17.1201 +			case 1:
 17.1202 +				mem2float_integer(&fpr_init[0], &fpr_final[0]);
 17.1203 +				mem2float_integer(&fpr_init[1], &fpr_final[1]);
 17.1204 +				break;
 17.1205 +			case 2:
 17.1206 +				mem2float_single(&fpr_init[0], &fpr_final[0]);
 17.1207 +				mem2float_single(&fpr_init[1], &fpr_final[1]);
 17.1208 +				break;
 17.1209 +			case 3:
 17.1210 +				mem2float_double(&fpr_init[0], &fpr_final[0]);
 17.1211 +				mem2float_double(&fpr_init[1], &fpr_final[1]);
 17.1212 +				break;
 17.1213 +		}
 17.1214 +		DDUMP("fpr_final =", &fpr_final, 2*len);
 17.1215 +		/*
 17.1216 +		 * XXX fixme
 17.1217 +		 *
 17.1218 +		 * A possible optimization would be to drop fpr_final and directly
 17.1219 +		 * use the storage from the saved context i.e., the actual final
 17.1220 +		 * destination (pt_regs, switch_stack or thread structure).
 17.1221 +		 */
 17.1222 +		setfpreg(ld.r1, &fpr_final[0], regs);
 17.1223 +		setfpreg(ld.imm, &fpr_final[1], regs);
 17.1224 +	}
 17.1225 +
 17.1226 +	/*
 17.1227 +	 * Check for updates: only immediate updates are available for this
 17.1228 +	 * instruction.
 17.1229 +	 */
 17.1230 +	if (ld.m) {
 17.1231 +		/*
 17.1232 +		 * the immediate is implicit given the ldsz of the operation:
 17.1233 +		 * single: 8 (2x4) and for  all others it's 16 (2x8)
 17.1234 +		 */
 17.1235 +		ifa += len<<1;
 17.1236 +
 17.1237 +		/*
 17.1238 +		 * IMPORTANT:
 17.1239 +		 * the fact that we force the NaT of r3 to zero is ONLY valid
 17.1240 +		 * as long as we don't come here with a ldfpX.s.
 17.1241 +		 * For this reason we keep this sanity check
 17.1242 +		 */
 17.1243 +		if (ld.x6_op == 1 || ld.x6_op == 3)
 17.1244 +			printk(KERN_ERR "%s: register update on speculative load pair, error\n",
 17.1245 +			       __FUNCTION__);
 17.1246 +
 17.1247 +		setreg(ld.r3, ifa, 0, regs);
 17.1248 +	}
 17.1249 +
 17.1250 +	/*
 17.1251 +	 * Invalidate ALAT entries, if any, for both registers.
 17.1252 +	 */
 17.1253 +	if (ld.x6_op == 0x2) {
 17.1254 +		invala_fr(ld.r1);
 17.1255 +		invala_fr(ld.imm);
 17.1256 +	}
 17.1257 +	return 0;
 17.1258 +}
 17.1259 +
 17.1260 +
 17.1261 +static int
 17.1262 +emulate_load_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
 17.1263 +{
 17.1264 +	struct ia64_fpreg fpr_init;
 17.1265 +	struct ia64_fpreg fpr_final;
 17.1266 +	unsigned long len = float_fsz[ld.x6_sz];
 17.1267 +
 17.1268 +	/*
 17.1269 +	 * fr0 & fr1 don't need to be checked because Illegal Instruction
 17.1270 +	 * faults have higher priority than unaligned faults.
 17.1271 +	 *
 17.1272 +	 * r0 cannot be found as the base as it would never generate an
 17.1273 +	 * unaligned reference.
 17.1274 +	 */
 17.1275 +
 17.1276 +	/*
 17.1277 +	 * make sure we get clean buffers
 17.1278 +	 */
 17.1279 +	memset(&fpr_init,0, sizeof(fpr_init));
 17.1280 +	memset(&fpr_final,0, sizeof(fpr_final));
 17.1281 +
 17.1282 +	/*
 17.1283 +	 * ldfX.a we don't try to emulate anything but we must
 17.1284 +	 * invalidate the ALAT entry.
 17.1285 +	 * See comments in ldX for descriptions on how the various loads are handled.
 17.1286 +	 */
 17.1287 +	if (ld.x6_op != 0x2) {
 17.1288 +		if (copy_from_user(&fpr_init, (void __user *) ifa, len))
 17.1289 +			return -1;
 17.1290 +
 17.1291 +		DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz);
 17.1292 +		DDUMP("fpr_init =", &fpr_init, len);
 17.1293 +		/*
 17.1294 +		 * we only do something for x6_op={0,8,9}
 17.1295 +		 */
 17.1296 +		switch( ld.x6_sz ) {
 17.1297 +			case 0:
 17.1298 +				mem2float_extended(&fpr_init, &fpr_final);
 17.1299 +				break;
 17.1300 +			case 1:
 17.1301 +				mem2float_integer(&fpr_init, &fpr_final);
 17.1302 +				break;
 17.1303 +			case 2:
 17.1304 +				mem2float_single(&fpr_init, &fpr_final);
 17.1305 +				break;
 17.1306 +			case 3:
 17.1307 +				mem2float_double(&fpr_init, &fpr_final);
 17.1308 +				break;
 17.1309 +		}
 17.1310 +		DDUMP("fpr_final =", &fpr_final, len);
 17.1311 +		/*
 17.1312 +		 * XXX fixme
 17.1313 +		 *
 17.1314 +		 * A possible optimization would be to drop fpr_final and directly
 17.1315 +		 * use the storage from the saved context i.e., the actual final
 17.1316 +		 * destination (pt_regs, switch_stack or thread structure).
 17.1317 +		 */
 17.1318 +		setfpreg(ld.r1, &fpr_final, regs);
 17.1319 +	}
 17.1320 +
 17.1321 +	/*
 17.1322 +	 * check for updates on any loads
 17.1323 +	 */
 17.1324 +	if (ld.op == 0x7 || ld.m)
 17.1325 +		emulate_load_updates(ld.op == 0x7 ? UPD_IMMEDIATE: UPD_REG, ld, regs, ifa);
 17.1326 +
 17.1327 +	/*
 17.1328 +	 * invalidate ALAT entry in case of advanced floating point loads
 17.1329 +	 */
 17.1330 +	if (ld.x6_op == 0x2)
 17.1331 +		invala_fr(ld.r1);
 17.1332 +
 17.1333 +	return 0;
 17.1334 +}
 17.1335 +
 17.1336 +
 17.1337 +static int
 17.1338 +emulate_store_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
 17.1339 +{
 17.1340 +	struct ia64_fpreg fpr_init;
 17.1341 +	struct ia64_fpreg fpr_final;
 17.1342 +	unsigned long len = float_fsz[ld.x6_sz];
 17.1343 +
 17.1344 +	/*
 17.1345 +	 * make sure we get clean buffers
 17.1346 +	 */
 17.1347 +	memset(&fpr_init,0, sizeof(fpr_init));
 17.1348 +	memset(&fpr_final,0, sizeof(fpr_final));
 17.1349 +
 17.1350 +	/*
 17.1351 +	 * if we get to this handler, Nat bits on both r3 and r2 have already
 17.1352 +	 * been checked. so we don't need to do it
 17.1353 +	 *
 17.1354 +	 * extract the value to be stored
 17.1355 +	 */
 17.1356 +	getfpreg(ld.imm, &fpr_init, regs);
 17.1357 +	/*
 17.1358 +	 * during this step, we extract the spilled registers from the saved
 17.1359 +	 * context i.e., we refill. Then we store (no spill) to temporary
 17.1360 +	 * aligned location
 17.1361 +	 */
 17.1362 +	switch( ld.x6_sz ) {
 17.1363 +		case 0:
 17.1364 +			float2mem_extended(&fpr_init, &fpr_final);
 17.1365 +			break;
 17.1366 +		case 1:
 17.1367 +			float2mem_integer(&fpr_init, &fpr_final);
 17.1368 +			break;
 17.1369 +		case 2:
 17.1370 +			float2mem_single(&fpr_init, &fpr_final);
 17.1371 +			break;
 17.1372 +		case 3:
 17.1373 +			float2mem_double(&fpr_init, &fpr_final);
 17.1374 +			break;
 17.1375 +	}
 17.1376 +	DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz);
 17.1377 +	DDUMP("fpr_init =", &fpr_init, len);
 17.1378 +	DDUMP("fpr_final =", &fpr_final, len);
 17.1379 +
 17.1380 +	if (copy_to_user((void __user *) ifa, &fpr_final, len))
 17.1381 +		return -1;
 17.1382 +
 17.1383 +	/*
 17.1384 +	 * stfX [r3]=r2,imm(9)
 17.1385 +	 *
 17.1386 +	 * NOTE:
 17.1387 +	 * ld.r3 can never be r0, because r0 would not generate an
 17.1388 +	 * unaligned access.
 17.1389 +	 */
 17.1390 +	if (ld.op == 0x7) {
 17.1391 +		unsigned long imm;
 17.1392 +
 17.1393 +		/*
 17.1394 +		 * form imm9: [12:6] contain first 7bits
 17.1395 +		 */
 17.1396 +		imm = ld.x << 7 | ld.r1;
 17.1397 +		/*
 17.1398 +		 * sign extend (8bits) if m set
 17.1399 +		 */
 17.1400 +		if (ld.m)
 17.1401 +			imm |= SIGN_EXT9;
 17.1402 +		/*
 17.1403 +		 * ifa == r3 (NaT is necessarily cleared)
 17.1404 +		 */
 17.1405 +		ifa += imm;
 17.1406 +
 17.1407 +		DPRINT("imm=%lx r3=%lx\n", imm, ifa);
 17.1408 +
 17.1409 +		setreg(ld.r3, ifa, 0, regs);
 17.1410 +	}
 17.1411 +	/*
 17.1412 +	 * we don't have alat_invalidate_multiple() so we need
 17.1413 +	 * to do the complete flush :-<<
 17.1414 +	 */
 17.1415 +	ia64_invala();
 17.1416 +
 17.1417 +	return 0;
 17.1418 +}
 17.1419 +
 17.1420 +/*
 17.1421 + * Make sure we log the unaligned access, so that user/sysadmin can notice it and
 17.1422 + * eventually fix the program.  However, we don't want to do that for every access so we
 17.1423 + * pace it with jiffies.  This isn't really MP-safe, but it doesn't really have to be
 17.1424 + * either...
 17.1425 + */
 17.1426 +static int
 17.1427 +within_logging_rate_limit (void)
 17.1428 +{
 17.1429 +	static unsigned long count, last_time;
 17.1430 +
 17.1431 +	if (jiffies - last_time > 5*HZ)
 17.1432 +		count = 0;
 17.1433 +	if (++count < 5) {
 17.1434 +		last_time = jiffies;
 17.1435 +		return 1;
 17.1436 +	}
 17.1437 +	return 0;
 17.1438 +
 17.1439 +}
 17.1440 +
 17.1441 +void
 17.1442 +ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs)
 17.1443 +{
 17.1444 +#ifdef XEN
 17.1445 +printk("ia64_handle_unaligned: called, not working yet\n");
 17.1446 +#else
 17.1447 +	struct ia64_psr *ipsr = ia64_psr(regs);
 17.1448 +	mm_segment_t old_fs = get_fs();
 17.1449 +	unsigned long bundle[2];
 17.1450 +	unsigned long opcode;
 17.1451 +	struct siginfo si;
 17.1452 +	const struct exception_table_entry *eh = NULL;
 17.1453 +	union {
 17.1454 +		unsigned long l;
 17.1455 +		load_store_t insn;
 17.1456 +	} u;
 17.1457 +	int ret = -1;
 17.1458 +
 17.1459 +	if (ia64_psr(regs)->be) {
 17.1460 +		/* we don't support big-endian accesses */
 17.1461 +		die_if_kernel("big-endian unaligned accesses are not supported", regs, 0);
 17.1462 +		goto force_sigbus;
 17.1463 +	}
 17.1464 +
 17.1465 +	/*
 17.1466 +	 * Treat kernel accesses for which there is an exception handler entry the same as
 17.1467 +	 * user-level unaligned accesses.  Otherwise, a clever program could trick this
 17.1468 +	 * handler into reading an arbitrary kernel addresses...
 17.1469 +	 */
 17.1470 +	if (!user_mode(regs))
 17.1471 +		eh = search_exception_tables(regs->cr_iip + ia64_psr(regs)->ri);
 17.1472 +	if (user_mode(regs) || eh) {
 17.1473 +		if ((current->thread.flags & IA64_THREAD_UAC_SIGBUS) != 0)
 17.1474 +			goto force_sigbus;
 17.1475 +
 17.1476 +		if (!(current->thread.flags & IA64_THREAD_UAC_NOPRINT)
 17.1477 +		    && within_logging_rate_limit())
 17.1478 +		{
 17.1479 +			char buf[200];	/* comm[] is at most 16 bytes... */
 17.1480 +			size_t len;
 17.1481 +
 17.1482 +			len = sprintf(buf, "%s(%d): unaligned access to 0x%016lx, "
 17.1483 +				      "ip=0x%016lx\n\r", current->comm, current->pid,
 17.1484 +				      ifa, regs->cr_iip + ipsr->ri);
 17.1485 +			/*
 17.1486 +			 * Don't call tty_write_message() if we're in the kernel; we might
 17.1487 +			 * be holding locks...
 17.1488 +			 */
 17.1489 +			if (user_mode(regs))
 17.1490 +				tty_write_message(current->signal->tty, buf);
 17.1491 +			buf[len-1] = '\0';	/* drop '\r' */
 17.1492 +			printk(KERN_WARNING "%s", buf);	/* watch for command names containing %s */
 17.1493 +		}
 17.1494 +	} else {
 17.1495 +		if (within_logging_rate_limit())
 17.1496 +			printk(KERN_WARNING "kernel unaligned access to 0x%016lx, ip=0x%016lx\n",
 17.1497 +			       ifa, regs->cr_iip + ipsr->ri);
 17.1498 +		set_fs(KERNEL_DS);
 17.1499 +	}
 17.1500 +
 17.1501 +	DPRINT("iip=%lx ifa=%lx isr=%lx (ei=%d, sp=%d)\n",
 17.1502 +	       regs->cr_iip, ifa, regs->cr_ipsr, ipsr->ri, ipsr->it);
 17.1503 +
 17.1504 +	if (__copy_from_user(bundle, (void __user *) regs->cr_iip, 16))
 17.1505 +		goto failure;
 17.1506 +
 17.1507 +	/*
 17.1508 +	 * extract the instruction from the bundle given the slot number
 17.1509 +	 */
 17.1510 +	switch (ipsr->ri) {
 17.1511 +	      case 0: u.l = (bundle[0] >>  5); break;
 17.1512 +	      case 1: u.l = (bundle[0] >> 46) | (bundle[1] << 18); break;
 17.1513 +	      case 2: u.l = (bundle[1] >> 23); break;
 17.1514 +	}
 17.1515 +	opcode = (u.l >> IA64_OPCODE_SHIFT) & IA64_OPCODE_MASK;
 17.1516 +
 17.1517 +	DPRINT("opcode=%lx ld.qp=%d ld.r1=%d ld.imm=%d ld.r3=%d ld.x=%d ld.hint=%d "
 17.1518 +	       "ld.x6=0x%x ld.m=%d ld.op=%d\n", opcode, u.insn.qp, u.insn.r1, u.insn.imm,
 17.1519 +	       u.insn.r3, u.insn.x, u.insn.hint, u.insn.x6_sz, u.insn.m, u.insn.op);
 17.1520 +
 17.1521 +	/*
 17.1522 +	 * IMPORTANT:
 17.1523 +	 * Notice that the switch statement DOES not cover all possible instructions
 17.1524 +	 * that DO generate unaligned references. This is made on purpose because for some
 17.1525 +	 * instructions it DOES NOT make sense to try and emulate the access. Sometimes it
 17.1526 +	 * is WRONG to try and emulate. Here is a list of instruction we don't emulate i.e.,
 17.1527 +	 * the program will get a signal and die:
 17.1528 +	 *
 17.1529 +	 *	load/store:
 17.1530 +	 *		- ldX.spill
 17.1531 +	 *		- stX.spill
 17.1532 +	 *	Reason: RNATs are based on addresses
 17.1533 +	 *
 17.1534 +	 *	synchronization:
 17.1535 +	 *		- cmpxchg
 17.1536 +	 *		- fetchadd
 17.1537 +	 *		- xchg
 17.1538 +	 *	Reason: ATOMIC operations cannot be emulated properly using multiple
 17.1539 +	 *	        instructions.
 17.1540 +	 *
 17.1541 +	 *	speculative loads:
 17.1542 +	 *		- ldX.sZ
 17.1543 +	 *	Reason: side effects, code must be ready to deal with failure so simpler
 17.1544 +	 *		to let the load fail.
 17.1545 +	 * ---------------------------------------------------------------------------------
 17.1546 +	 * XXX fixme
 17.1547 +	 *
 17.1548 +	 * I would like to get rid of this switch case and do something
 17.1549 +	 * more elegant.
 17.1550 +	 */
 17.1551 +	switch (opcode) {
 17.1552 +	      case LDS_OP:
 17.1553 +	      case LDSA_OP:
 17.1554 +	      case LDS_IMM_OP:
 17.1555 +	      case LDSA_IMM_OP:
 17.1556 +	      case LDFS_OP:
 17.1557 +	      case LDFSA_OP:
 17.1558 +	      case LDFS_IMM_OP:
 17.1559 +		/*
 17.1560 +		 * The instruction will be retried with deferred exceptions turned on, and
 17.1561 +		 * we should get Nat bit installed
 17.1562 +		 *
 17.1563 +		 * IMPORTANT: When PSR_ED is set, the register & immediate update forms
 17.1564 +		 * are actually executed even though the operation failed. So we don't
 17.1565 +		 * need to take care of this.
 17.1566 +		 */
 17.1567 +		DPRINT("forcing PSR_ED\n");
 17.1568 +		regs->cr_ipsr |= IA64_PSR_ED;
 17.1569 +		goto done;
 17.1570 +
 17.1571 +	      case LD_OP:
 17.1572 +	      case LDA_OP:
 17.1573 +	      case LDBIAS_OP:
 17.1574 +	      case LDACQ_OP:
 17.1575 +	      case LDCCLR_OP:
 17.1576 +	      case LDCNC_OP:
 17.1577 +	      case LDCCLRACQ_OP:
 17.1578 +	      case LD_IMM_OP:
 17.1579 +	      case LDA_IMM_OP:
 17.1580 +	      case LDBIAS_IMM_OP:
 17.1581 +	      case LDACQ_IMM_OP:
 17.1582 +	      case LDCCLR_IMM_OP:
 17.1583 +	      case LDCNC_IMM_OP:
 17.1584 +	      case LDCCLRACQ_IMM_OP:
 17.1585 +		ret = emulate_load_int(ifa, u.insn, regs);
 17.1586 +		break;
 17.1587 +
 17.1588 +	      case ST_OP:
 17.1589 +	      case STREL_OP:
 17.1590 +	      case ST_IMM_OP:
 17.1591 +	      case STREL_IMM_OP:
 17.1592 +		ret = emulate_store_int(ifa, u.insn, regs);
 17.1593 +		break;
 17.1594 +
 17.1595 +	      case LDF_OP:
 17.1596 +	      case LDFA_OP:
 17.1597 +	      case LDFCCLR_OP:
 17.1598 +	      case LDFCNC_OP:
 17.1599 +	      case LDF_IMM_OP:
 17.1600 +	      case LDFA_IMM_OP:
 17.1601 +	      case LDFCCLR_IMM_OP:
 17.1602 +	      case LDFCNC_IMM_OP:
 17.1603 +		if (u.insn.x)
 17.1604 +			ret = emulate_load_floatpair(ifa, u.insn, regs);
 17.1605 +		else
 17.1606 +			ret = emulate_load_float(ifa, u.insn, regs);
 17.1607 +		break;
 17.1608 +
 17.1609 +	      case STF_OP:
 17.1610 +	      case STF_IMM_OP:
 17.1611 +		ret = emulate_store_float(ifa, u.insn, regs);
 17.1612 +		break;
 17.1613 +
 17.1614 +	      default:
 17.1615 +		goto failure;
 17.1616 +	}
 17.1617 +	DPRINT("ret=%d\n", ret);
 17.1618 +	if (ret)
 17.1619 +		goto failure;
 17.1620 +
 17.1621 +	if (ipsr->ri == 2)
 17.1622 +		/*
 17.1623 +		 * given today's architecture this case is not likely to happen because a
 17.1624 +		 * memory access instruction (M) can never be in the last slot of a
 17.1625 +		 * bundle. But let's keep it for now.
 17.1626 +		 */
 17.1627 +		regs->cr_iip += 16;
 17.1628 +	ipsr->ri = (ipsr->ri + 1) & 0x3;
 17.1629 +
 17.1630 +	DPRINT("ipsr->ri=%d iip=%lx\n", ipsr->ri, regs->cr_iip);
 17.1631 +  done:
 17.1632 +	set_fs(old_fs);		/* restore original address limit */
 17.1633 +	return;
 17.1634 +
 17.1635 +  failure:
 17.1636 +	/* something went wrong... */
 17.1637 +	if (!user_mode(regs)) {
 17.1638 +		if (eh) {
 17.1639 +			ia64_handle_exception(regs, eh);
 17.1640 +			goto done;
 17.1641 +		}
 17.1642 +		die_if_kernel("error during unaligned kernel access\n", regs, ret);
 17.1643 +		/* NOT_REACHED */
 17.1644 +	}
 17.1645 +  force_sigbus:
 17.1646 +	si.si_signo = SIGBUS;
 17.1647 +	si.si_errno = 0;
 17.1648 +	si.si_code = BUS_ADRALN;
 17.1649 +	si.si_addr = (void __user *) ifa;
 17.1650 +	si.si_flags = 0;
 17.1651 +	si.si_isr = 0;
 17.1652 +	si.si_imm = 0;
 17.1653 +	force_sig_info(SIGBUS, &si, current);
 17.1654 +	goto done;
 17.1655 +#endif
 17.1656 +}
    18.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    18.2 +++ b/xen/arch/ia64/linux/cmdline.c	Fri Aug 26 09:05:43 2005 +0000
    18.3 @@ -0,0 +1,120 @@
    18.4 +/*
    18.5 + * linux/lib/cmdline.c
    18.6 + * Helper functions generally used for parsing kernel command line
    18.7 + * and module options.
    18.8 + *
    18.9 + * Code and copyrights come from init/main.c and arch/i386/kernel/setup.c.
   18.10 + *
   18.11 + * This source code is licensed under the GNU General Public License,
   18.12 + * Version 2.  See the file COPYING for more details.
   18.13 + *
   18.14 + * GNU Indent formatting options for this file: -kr -i8 -npsl -pcs
   18.15 + *
   18.16 + */
   18.17 +
   18.18 +#include <linux/module.h>
   18.19 +#include <linux/kernel.h>
   18.20 +#include <linux/string.h>
   18.21 +
   18.22 +
   18.23 +/**
   18.24 + *	get_option - Parse integer from an option string
   18.25 + *	@str: option string
   18.26 + *	@pint: (output) integer value parsed from @str
   18.27 + *
   18.28 + *	Read an int from an option string; if available accept a subsequent
   18.29 + *	comma as well.
   18.30 + *
   18.31 + *	Return values:
   18.32 + *	0 : no int in string
   18.33 + *	1 : int found, no subsequent comma
   18.34 + *	2 : int found including a subsequent comma
   18.35 + */
   18.36 +
   18.37 +int get_option (char **str, int *pint)
   18.38 +{
   18.39 +	char *cur = *str;
   18.40 +
   18.41 +	if (!cur || !(*cur))
   18.42 +		return 0;
   18.43 +	*pint = simple_strtol (cur, str, 0);
   18.44 +	if (cur == *str)
   18.45 +		return 0;
   18.46 +	if (**str == ',') {
   18.47 +		(*str)++;
   18.48 +		return 2;
   18.49 +	}
   18.50 +
   18.51 +	return 1;
   18.52 +}
   18.53 +
   18.54 +/**
   18.55 + *	get_options - Parse a string into a list of integers
   18.56 + *	@str: String to be parsed
   18.57 + *	@nints: size of integer array
   18.58 + *	@ints: integer array
   18.59 + *
   18.60 + *	This function parses a string containing a comma-separated
   18.61 + *	list of integers.  The parse halts when the array is
   18.62 + *	full, or when no more numbers can be retrieved from the
   18.63 + *	string.
   18.64 + *
   18.65 + *	Return value is the character in the string which caused
   18.66 + *	the parse to end (typically a null terminator, if @str is
   18.67 + *	completely parseable).
   18.68 + */
   18.69 + 
   18.70 +char *get_options(const char *str, int nints, int *ints)
   18.71 +{
   18.72 +	int res, i = 1;
   18.73 +
   18.74 +	while (i < nints) {
   18.75 +		res = get_option ((char **)&str, ints + i);
   18.76 +		if (res == 0)
   18.77 +			break;
   18.78 +		i++;
   18.79 +		if (res == 1)
   18.80 +			break;
   18.81 +	}
   18.82 +	ints[0] = i - 1;
   18.83 +	return (char *)str;
   18.84 +}
   18.85 +
   18.86 +/**
   18.87 + *	memparse - parse a string with mem suffixes into a number
   18.88 + *	@ptr: Where parse begins
   18.89 + *	@retptr: (output) Pointer to next char after parse completes
   18.90 + *
   18.91 + *	Parses a string into a number.  The number stored at @ptr is
   18.92 + *	potentially suffixed with %K (for kilobytes, or 1024 bytes),
   18.93 + *	%M (for megabytes, or 1048576 bytes), or %G (for gigabytes, or
   18.94 + *	1073741824).  If the number is suffixed with K, M, or G, then
   18.95 + *	the return value is the number multiplied by one kilobyte, one
   18.96 + *	megabyte, or one gigabyte, respectively.
   18.97 + */
   18.98 +
   18.99 +unsigned long long memparse (char *ptr, char **retptr)
  18.100 +{
  18.101 +	unsigned long long ret = simple_strtoull (ptr, retptr, 0);
  18.102 +
  18.103 +	switch (**retptr) {
  18.104 +	case 'G':
  18.105 +	case 'g':
  18.106 +		ret <<= 10;
  18.107 +	case 'M':
  18.108 +	case 'm':
  18.109 +		ret <<= 10;
  18.110 +	case 'K':
  18.111 +	case 'k':
  18.112 +		ret <<= 10;
  18.113 +		(*retptr)++;
  18.114 +	default:
  18.115 +		break;
  18.116 +	}
  18.117 +	return ret;
  18.118 +}
  18.119 +
  18.120 +
  18.121 +EXPORT_SYMBOL(memparse);
  18.122 +EXPORT_SYMBOL(get_option);
  18.123 +EXPORT_SYMBOL(get_options);
    19.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    19.2 +++ b/xen/arch/ia64/linux/efi_stub.S	Fri Aug 26 09:05:43 2005 +0000
    19.3 @@ -0,0 +1,86 @@
    19.4 +/*
    19.5 + * EFI call stub.
    19.6 + *
    19.7 + * Copyright (C) 1999-2001 Hewlett-Packard Co
    19.8 + *	David Mosberger <davidm@hpl.hp.com>
    19.9 + *
   19.10 + * This stub allows us to make EFI calls in physical mode with interrupts
   19.11 + * turned off.  We need this because we can't call SetVirtualMap() until
   19.12 + * the kernel has booted far enough to allow allocation of struct vma_struct
   19.13 + * entries (which we would need to map stuff with memory attributes other
   19.14 + * than uncached or writeback...).  Since the GetTime() service gets called
   19.15 + * earlier than that, we need to be able to make physical mode EFI calls from
   19.16 + * the kernel.
   19.17 + */
   19.18 +
   19.19 +/*
   19.20 + * PSR settings as per SAL spec (Chapter 8 in the "IA-64 System
   19.21 + * Abstraction Layer Specification", revision 2.6e).  Note that
   19.22 + * psr.dfl and psr.dfh MUST be cleared, despite what this manual says.
   19.23 + * Otherwise, SAL dies whenever it's trying to do an IA-32 BIOS call
   19.24 + * (the br.ia instruction fails unless psr.dfl and psr.dfh are
   19.25 + * cleared).  Fortunately, SAL promises not to touch the floating
   19.26 + * point regs, so at least we don't have to save f2-f127.
   19.27 + */
   19.28 +#define PSR_BITS_TO_CLEAR						\
   19.29 +	(IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_RT |		\
   19.30 +	 IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED |	\
   19.31 +	 IA64_PSR_DFL | IA64_PSR_DFH)
   19.32 +
   19.33 +#define PSR_BITS_TO_SET							\
   19.34 +	(IA64_PSR_BN)
   19.35 +
   19.36 +#include <asm/processor.h>
   19.37 +#include <asm/asmmacro.h>
   19.38 +
   19.39 +/*
   19.40 + * Inputs:
   19.41 + *	in0 = address of function descriptor of EFI routine to call
   19.42 + *	in1..in7 = arguments to routine
   19.43 + *
   19.44 + * Outputs:
   19.45 + *	r8 = EFI_STATUS returned by called function
   19.46 + */
   19.47 +
   19.48 +GLOBAL_ENTRY(efi_call_phys)
   19.49 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
   19.50 +	alloc loc1=ar.pfs,8,7,7,0
   19.51 +	ld8 r2=[in0],8			// load EFI function's entry point
   19.52 +	mov loc0=rp
   19.53 +	.body
   19.54 +	;;
   19.55 +	mov loc2=gp			// save global pointer
   19.56 +	mov loc4=ar.rsc			// save RSE configuration
   19.57 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   19.58 +	;;
   19.59 +	ld8 gp=[in0]			// load EFI function's global pointer
   19.60 +	movl r16=PSR_BITS_TO_CLEAR
   19.61 +	mov loc3=psr			// save processor status word
   19.62 +	movl r17=PSR_BITS_TO_SET
   19.63 +	;;
   19.64 +	or loc3=loc3,r17
   19.65 +	mov b6=r2
   19.66 +	;;
   19.67 +	andcm r16=loc3,r16		// get psr with IT, DT, and RT bits cleared
   19.68 +	br.call.sptk.many rp=ia64_switch_mode_phys
   19.69 +.ret0:	mov out4=in5
   19.70 +	mov out0=in1
   19.71 +	mov out1=in2
   19.72 +	mov out2=in3
   19.73 +	mov out3=in4
   19.74 +	mov out5=in6
   19.75 +	mov out6=in7
   19.76 +	mov loc5=r19
   19.77 +	mov loc6=r20
   19.78 +	br.call.sptk.many rp=b6		// call the EFI function
   19.79 +.ret1:	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   19.80 +	mov r16=loc3
   19.81 +	mov r19=loc5
   19.82 +	mov r20=loc6
   19.83 +	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
   19.84 +.ret2:	mov ar.rsc=loc4			// restore RSE configuration
   19.85 +	mov ar.pfs=loc1
   19.86 +	mov rp=loc0
   19.87 +	mov gp=loc2
   19.88 +	br.ret.sptk.many rp
   19.89 +END(efi_call_phys)
    20.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    20.2 +++ b/xen/arch/ia64/linux/extable.c	Fri Aug 26 09:05:43 2005 +0000
    20.3 @@ -0,0 +1,93 @@
    20.4 +/*
    20.5 + * Kernel exception handling table support.  Derived from arch/alpha/mm/extable.c.
    20.6 + *
    20.7 + * Copyright (C) 1998, 1999, 2001-2002, 2004 Hewlett-Packard Co
    20.8 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    20.9 + */
   20.10 +
   20.11 +#include <linux/config.h>
   20.12 +
   20.13 +#include <asm/uaccess.h>
   20.14 +#include <asm/module.h>
   20.15 +
   20.16 +static inline int
   20.17 +compare_entries (struct exception_table_entry *l, struct exception_table_entry *r)
   20.18 +{
   20.19 +	u64 lip = (u64) &l->addr + l->addr;
   20.20 +	u64 rip = (u64) &r->addr + r->addr;
   20.21 +
   20.22 +	if (lip < rip)
   20.23 +		return -1;
   20.24 +	if (lip == rip)
   20.25 +		return 0;
   20.26 +	else
   20.27 +		return 1;
   20.28 +}
   20.29 +
   20.30 +static inline void
   20.31 +swap_entries (struct exception_table_entry *l, struct exception_table_entry *r)
   20.32 +{
   20.33 +	u64 delta = (u64) r - (u64) l;
   20.34 +	struct exception_table_entry tmp;
   20.35 +
   20.36 +	tmp = *l;
   20.37 +	l->addr = r->addr + delta;
   20.38 +	l->cont = r->cont + delta;
   20.39 +	r->addr = tmp.addr - delta;
   20.40 +	r->cont = tmp.cont - delta;
   20.41 +}
   20.42 +
   20.43 +/*
   20.44 + * Sort the exception table.  It's usually already sorted, but there may be unordered
   20.45 + * entries due to multiple text sections (such as the .init text section).  Note that the
   20.46 + * exception-table-entries contain location-relative addresses, which requires a bit of
   20.47 + * care during sorting to avoid overflows in the offset members (e.g., it would not be
   20.48 + * safe to make a temporary copy of an exception-table entry on the stack, because the
   20.49 + * stack may be more than 2GB away from the exception-table).
   20.50 + */
   20.51 +void
   20.52 +sort_extable (struct exception_table_entry *start, struct exception_table_entry *finish)
   20.53 +{
   20.54 +	struct exception_table_entry *p, *q;
   20.55 +
   20.56 + 	/* insertion sort */
   20.57 +	for (p = start + 1; p < finish; ++p)
   20.58 +		/* start .. p-1 is sorted; push p down to it's proper place */
   20.59 +		for (q = p; q > start && compare_entries(&q[0], &q[-1]) < 0; --q)
   20.60 +			swap_entries(&q[0], &q[-1]);
   20.61 +}
   20.62 +
   20.63 +const struct exception_table_entry *
   20.64 +search_extable (const struct exception_table_entry *first,
   20.65 +		const struct exception_table_entry *last,
   20.66 +		unsigned long ip)
   20.67 +{
   20.68 +	const struct exception_table_entry *mid;
   20.69 +	unsigned long mid_ip;
   20.70 +	long diff;
   20.71 +
   20.72 +        while (first <= last) {
   20.73 +		mid = &first[(last - first)/2];
   20.74 +		mid_ip = (u64) &mid->addr + mid->addr;
   20.75 +		diff = mid_ip - ip;
   20.76 +                if (diff == 0)
   20.77 +                        return mid;
   20.78 +                else if (diff < 0)
   20.79 +                        first = mid + 1;
   20.80 +                else
   20.81 +                        last = mid - 1;
   20.82 +        }
   20.83 +        return NULL;
   20.84 +}
   20.85 +
   20.86 +void
   20.87 +ia64_handle_exception (struct pt_regs *regs, const struct exception_table_entry *e)
   20.88 +{
   20.89 +	long fix = (u64) &e->cont + e->cont;
   20.90 +
   20.91 +	regs->r8 = -EFAULT;
   20.92 +	if (fix & 4)
   20.93 +		regs->r9 = 0;
   20.94 +	regs->cr_iip = fix & ~0xf;
   20.95 +	ia64_psr(regs)->ri = fix & 0x3;		/* set continuation slot number */
   20.96 +}
    21.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    21.2 +++ b/xen/arch/ia64/linux/hpsim.S	Fri Aug 26 09:05:43 2005 +0000
    21.3 @@ -0,0 +1,10 @@
    21.4 +#include <asm/asmmacro.h>
    21.5 +
    21.6 +/*
    21.7 + * Simulator system call.
    21.8 + */
    21.9 +GLOBAL_ENTRY(ia64_ssc)
   21.10 +	mov r15=r36
   21.11 +	break 0x80001
   21.12 +	br.ret.sptk.many rp
   21.13 +END(ia64_ssc)
    22.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    22.2 +++ b/xen/arch/ia64/linux/ia64_ksyms.c	Fri Aug 26 09:05:43 2005 +0000
    22.3 @@ -0,0 +1,127 @@
    22.4 +/*
    22.5 + * Architecture-specific kernel symbols
    22.6 + *
    22.7 + * Don't put any exports here unless it's defined in an assembler file.
    22.8 + * All other exports should be put directly after the definition.
    22.9 + */
   22.10 +
   22.11 +#include <linux/config.h>
   22.12 +#include <linux/module.h>
   22.13 +
   22.14 +#include <linux/string.h>
   22.15 +EXPORT_SYMBOL(memset);
   22.16 +EXPORT_SYMBOL(memchr);
   22.17 +EXPORT_SYMBOL(memcmp);
   22.18 +EXPORT_SYMBOL(memcpy);
   22.19 +EXPORT_SYMBOL(memmove);
   22.20 +EXPORT_SYMBOL(memscan);
   22.21 +EXPORT_SYMBOL(strcat);
   22.22 +EXPORT_SYMBOL(strchr);
   22.23 +EXPORT_SYMBOL(strcmp);
   22.24 +EXPORT_SYMBOL(strcpy);
   22.25 +EXPORT_SYMBOL(strlen);
   22.26 +EXPORT_SYMBOL(strncat);
   22.27 +EXPORT_SYMBOL(strncmp);
   22.28 +EXPORT_SYMBOL(strncpy);
   22.29 +EXPORT_SYMBOL(strnlen);
   22.30 +EXPORT_SYMBOL(strrchr);
   22.31 +EXPORT_SYMBOL(strstr);
   22.32 +EXPORT_SYMBOL(strpbrk);
   22.33 +
   22.34 +#include <asm/checksum.h>
   22.35 +EXPORT_SYMBOL(ip_fast_csum);		/* hand-coded assembly */
   22.36 +
   22.37 +#include <asm/semaphore.h>
   22.38 +EXPORT_SYMBOL(__down);
   22.39 +EXPORT_SYMBOL(__down_interruptible);
   22.40 +EXPORT_SYMBOL(__down_trylock);
   22.41 +EXPORT_SYMBOL(__up);
   22.42 +
   22.43 +#include <asm/page.h>
   22.44 +EXPORT_SYMBOL(clear_page);
   22.45 +
   22.46 +#ifdef CONFIG_VIRTUAL_MEM_MAP
   22.47 +#include <linux/bootmem.h>
   22.48 +EXPORT_SYMBOL(max_low_pfn);	/* defined by bootmem.c, but not exported by generic code */
   22.49 +#endif
   22.50 +
   22.51 +#include <asm/processor.h>
   22.52 +EXPORT_SYMBOL(per_cpu__cpu_info);
   22.53 +#ifdef CONFIG_SMP
   22.54 +EXPORT_SYMBOL(per_cpu__local_per_cpu_offset);
   22.55 +#endif
   22.56 +
   22.57 +#include <asm/uaccess.h>
   22.58 +EXPORT_SYMBOL(__copy_user);
   22.59 +EXPORT_SYMBOL(__do_clear_user);
   22.60 +EXPORT_SYMBOL(__strlen_user);
   22.61 +EXPORT_SYMBOL(__strncpy_from_user);
   22.62 +EXPORT_SYMBOL(__strnlen_user);
   22.63 +
   22.64 +#include <asm/unistd.h>
   22.65 +EXPORT_SYMBOL(__ia64_syscall);
   22.66 +
   22.67 +/* from arch/ia64/lib */
   22.68 +extern void __divsi3(void);
   22.69 +extern void __udivsi3(void);
   22.70 +extern void __modsi3(void);
   22.71 +ext