ia64/xen-unstable

changeset 15864:924c153e0cf9

svm: Greatly reduce total number of CR8 intercepts

This patch reduces the number of CR8 intercept to a fraction of the
number of CR8 intercepts without. First, CR8 read intercepts are
completely disabled since the SVM vTPR is kept kept in sync with the
HVM vLAPIC TPR. Second, CR8 write intercepts are enabled and disabled
based upon certain conditions. Most of the time, CR8 write intercepts
are disabled. They are enabled only when there is a pending interrupt
that can't be delivered because of either the current ISR or TPR (aka
PPR) because this is the only time the TPR matters.

With this patch, the number of CR8 intercepts dropped from around
10,000,000 to around 6,000 during boot of Windows 2003 Server 64-bit
(this is a rough estimate).

Signed-off-by: Travis Betak <travis.betak@amd.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Mon Sep 10 16:13:13 2007 +0100 (2007-09-10)
parents 4633e9604da9
children e3984b0b81f5
files xen/arch/x86/hvm/svm/intr.c xen/arch/x86/hvm/svm/svm.c xen/arch/x86/hvm/svm/vmcb.c
line diff
     1.1 --- a/xen/arch/x86/hvm/svm/intr.c	Mon Sep 10 14:42:30 2007 +0100
     1.2 +++ b/xen/arch/x86/hvm/svm/intr.c	Mon Sep 10 16:13:13 2007 +0100
     1.3 @@ -30,6 +30,7 @@
     1.4  #include <asm/hvm/hvm.h>
     1.5  #include <asm/hvm/io.h>
     1.6  #include <asm/hvm/support.h>
     1.7 +#include <asm/hvm/vlapic.h>
     1.8  #include <asm/hvm/svm/svm.h>
     1.9  #include <asm/hvm/svm/intr.h>
    1.10  #include <xen/event.h>
    1.11 @@ -99,6 +100,33 @@ static void enable_intr_window(struct vc
    1.12      svm_inject_dummy_vintr(v);
    1.13  }
    1.14  
    1.15 +static void update_cr8_intercept(
    1.16 +    struct vcpu *v, enum hvm_intack masked_intr_source)
    1.17 +{
    1.18 +    struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
    1.19 +    struct vlapic *vlapic = vcpu_vlapic(v);
    1.20 +    int max_irr;
    1.21 +
    1.22 +    vmcb->cr_intercepts &= ~CR_INTERCEPT_CR8_WRITE;
    1.23 +
    1.24 +    /*
    1.25 +     * If ExtInts are masked then that dominates the TPR --- the 'interrupt
    1.26 +     * window' has already been enabled in this case.
    1.27 +     */
    1.28 +    if ( (masked_intr_source == hvm_intack_lapic) ||
    1.29 +         (masked_intr_source == hvm_intack_pic) )
    1.30 +        return;
    1.31 +
    1.32 +    /* Is there an interrupt pending at the LAPIC? Nothing to do if not. */
    1.33 +    if ( !vlapic_enabled(vlapic) || 
    1.34 +         ((max_irr = vlapic_find_highest_irr(vlapic)) == -1) )
    1.35 +        return;
    1.36 +
    1.37 +    /* Highest-priority pending interrupt is masked by the TPR? */
    1.38 +    if ( (vmcb->vintr.fields.tpr & 0xf) >= (max_irr >> 4) )
    1.39 +        vmcb->cr_intercepts |= CR_INTERCEPT_CR8_WRITE;
    1.40 +}
    1.41 +
    1.42  asmlinkage void svm_intr_assist(void) 
    1.43  {
    1.44      struct vcpu *v = current;
    1.45 @@ -113,7 +141,7 @@ asmlinkage void svm_intr_assist(void)
    1.46      do {
    1.47          intr_source = hvm_vcpu_has_pending_irq(v);
    1.48          if ( likely(intr_source == hvm_intack_none) )
    1.49 -            return;
    1.50 +            goto out;
    1.51  
    1.52          /*
    1.53           * Pending IRQs must be delayed if:
    1.54 @@ -133,7 +161,7 @@ asmlinkage void svm_intr_assist(void)
    1.55               !hvm_interrupts_enabled(v, intr_source) )
    1.56          {
    1.57              enable_intr_window(v, intr_source);
    1.58 -            return;
    1.59 +            goto out;
    1.60          }
    1.61      } while ( !hvm_vcpu_ack_pending_irq(v, intr_source, &intr_vector) );
    1.62  
    1.63 @@ -152,6 +180,9 @@ asmlinkage void svm_intr_assist(void)
    1.64      intr_source = hvm_vcpu_has_pending_irq(v);
    1.65      if ( unlikely(intr_source != hvm_intack_none) )
    1.66          enable_intr_window(v, intr_source);
    1.67 +
    1.68 + out:
    1.69 +    update_cr8_intercept(v, intr_source);
    1.70  }
    1.71  
    1.72  /*
     2.1 --- a/xen/arch/x86/hvm/svm/svm.c	Mon Sep 10 14:42:30 2007 +0100
     2.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Mon Sep 10 16:13:13 2007 +0100
     2.3 @@ -2153,6 +2153,16 @@ asmlinkage void svm_vmexit_handler(struc
     2.4      eventinj_t eventinj;
     2.5      int inst_len, rc;
     2.6  
     2.7 +    /*
     2.8 +     * Before doing anything else, we need to sync up the VLAPIC's TPR with
     2.9 +     * SVM's vTPR if CR8 writes are currently disabled.  It's OK if the 
    2.10 +     * guest doesn't touch the CR8 (e.g. 32-bit Windows) because we update
    2.11 +     * the vTPR on MMIO writes to the TPR
    2.12 +     */
    2.13 +    if ( !(vmcb->cr_intercepts & CR_INTERCEPT_CR8_WRITE) )
    2.14 +        vlapic_set_reg(vcpu_vlapic(v), APIC_TASKPRI,
    2.15 +                       (vmcb->vintr.fields.tpr & 0x0F) << 4);
    2.16 +
    2.17      exit_reason = vmcb->exitcode;
    2.18  
    2.19      HVMTRACE_2D(VMEXIT, v, vmcb->rip, exit_reason);
     3.1 --- a/xen/arch/x86/hvm/svm/vmcb.c	Mon Sep 10 14:42:30 2007 +0100
     3.2 +++ b/xen/arch/x86/hvm/svm/vmcb.c	Mon Sep 10 16:13:13 2007 +0100
     3.3 @@ -114,23 +114,29 @@ static int construct_vmcb(struct vcpu *v
     3.4      svm_asid_init_vcpu(v);
     3.5  
     3.6      vmcb->general1_intercepts = 
     3.7 -        GENERAL1_INTERCEPT_INTR         | GENERAL1_INTERCEPT_NMI         |
     3.8 -        GENERAL1_INTERCEPT_SMI          | GENERAL1_INTERCEPT_INIT        |
     3.9 -        GENERAL1_INTERCEPT_CPUID        | GENERAL1_INTERCEPT_INVD        |
    3.10 -        GENERAL1_INTERCEPT_HLT          | GENERAL1_INTERCEPT_INVLPG      | 
    3.11 -        GENERAL1_INTERCEPT_INVLPGA      | GENERAL1_INTERCEPT_IOIO_PROT   |
    3.12 -        GENERAL1_INTERCEPT_MSR_PROT     | GENERAL1_INTERCEPT_SHUTDOWN_EVT;
    3.13 +        GENERAL1_INTERCEPT_INTR        | GENERAL1_INTERCEPT_NMI         |
    3.14 +        GENERAL1_INTERCEPT_SMI         | GENERAL1_INTERCEPT_INIT        |
    3.15 +        GENERAL1_INTERCEPT_CPUID       | GENERAL1_INTERCEPT_INVD        |
    3.16 +        GENERAL1_INTERCEPT_HLT         | GENERAL1_INTERCEPT_INVLPG      | 
    3.17 +        GENERAL1_INTERCEPT_INVLPGA     | GENERAL1_INTERCEPT_IOIO_PROT   |
    3.18 +        GENERAL1_INTERCEPT_MSR_PROT    | GENERAL1_INTERCEPT_SHUTDOWN_EVT;
    3.19      vmcb->general2_intercepts = 
    3.20 -        GENERAL2_INTERCEPT_VMRUN  | GENERAL2_INTERCEPT_VMMCALL | 
    3.21 -        GENERAL2_INTERCEPT_VMLOAD | GENERAL2_INTERCEPT_VMSAVE  |
    3.22 -        GENERAL2_INTERCEPT_STGI   | GENERAL2_INTERCEPT_CLGI    |
    3.23 -        GENERAL2_INTERCEPT_SKINIT | GENERAL2_INTERCEPT_RDTSCP;
    3.24 +        GENERAL2_INTERCEPT_VMRUN       | GENERAL2_INTERCEPT_VMMCALL     |
    3.25 +        GENERAL2_INTERCEPT_VMLOAD      | GENERAL2_INTERCEPT_VMSAVE      |
    3.26 +        GENERAL2_INTERCEPT_STGI        | GENERAL2_INTERCEPT_CLGI        |
    3.27 +        GENERAL2_INTERCEPT_SKINIT      | GENERAL2_INTERCEPT_RDTSCP;
    3.28  
    3.29      /* Intercept all debug-register writes. */
    3.30      vmcb->dr_intercepts = DR_INTERCEPT_ALL_WRITES;
    3.31  
    3.32 -    /* Intercept all control-register accesses, except to CR2. */
    3.33 -    vmcb->cr_intercepts = ~(CR_INTERCEPT_CR2_READ | CR_INTERCEPT_CR2_WRITE);
    3.34 +    /*
    3.35 +     * Intercept all control-register accesses except for CR2 reads/writes
    3.36 +     * and CR8 reads (and actually CR8 writes, but that's a special case
    3.37 +     * that's handled in svm/intr.c). 
    3.38 +     */
    3.39 +    vmcb->cr_intercepts = ~(CR_INTERCEPT_CR2_READ |
    3.40 +                            CR_INTERCEPT_CR2_WRITE |
    3.41 +                            CR_INTERCEPT_CR8_READ);
    3.42  
    3.43      /* I/O and MSR permission bitmaps. */
    3.44      arch_svm->msrpm = alloc_xenheap_pages(get_order_from_bytes(MSRPM_SIZE));