ia64/xen-unstable

changeset 18361:9112c53b70cd

[IA64] move back pal.S into xen/arch/ia64/linux.

Now xen/arch/ia64/linux-xen/pal.S is the same as
arch/ia64/kernel/pal.S from linux 2.6.21.
So move it back into xen/arch/ia64/linux.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Aug 25 19:04:37 2008 +0900 (2008-08-25)
parents 8f00ddcd1c47
children 6607624285b2
files xen/arch/ia64/linux-xen/Makefile xen/arch/ia64/linux-xen/README.origin xen/arch/ia64/linux-xen/pal.S xen/arch/ia64/linux/Makefile xen/arch/ia64/linux/README.origin xen/arch/ia64/linux/pal.S
line diff
     1.1 --- a/xen/arch/ia64/linux-xen/Makefile	Mon Aug 25 19:04:37 2008 +0900
     1.2 +++ b/xen/arch/ia64/linux-xen/Makefile	Mon Aug 25 19:04:37 2008 +0900
     1.3 @@ -7,7 +7,6 @@ obj-y += irq_ia64.o
     1.4  obj-y += mca.o
     1.5  obj-y += mca_asm.o
     1.6  obj-y += mm_contig.o
     1.7 -obj-y += pal.o
     1.8  obj-y += process-linux-xen.o
     1.9  obj-y += sal.o
    1.10  obj-y += setup.o
     2.1 --- a/xen/arch/ia64/linux-xen/README.origin	Mon Aug 25 19:04:37 2008 +0900
     2.2 +++ b/xen/arch/ia64/linux-xen/README.origin	Mon Aug 25 19:04:37 2008 +0900
     2.3 @@ -42,7 +42,6 @@ perfmon_montecito.h	-> linux/arch/kernel
     2.4  
     2.5  # The files below are from Linux-2.6.21
     2.6  efi.c			-> linux/arch/ia64/kernel/efi.c
     2.7 -pal.S			-> linux/arch/ia64/kernel/pal.S
     2.8  
     2.9  # The files below are from Linux-2.6.26-rc5
    2.10  acpi.c			-> linux/arch/ia64/kernel/acpi.c
     3.1 --- a/xen/arch/ia64/linux-xen/pal.S	Mon Aug 25 19:04:37 2008 +0900
     3.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.3 @@ -1,298 +0,0 @@
     3.4 -/*
     3.5 - * PAL Firmware support
     3.6 - * IA-64 Processor Programmers Reference Vol 2
     3.7 - *
     3.8 - * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
     3.9 - * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
    3.10 - * Copyright (C) 1999-2001, 2003 Hewlett-Packard Co
    3.11 - *	David Mosberger <davidm@hpl.hp.com>
    3.12 - *	Stephane Eranian <eranian@hpl.hp.com>
    3.13 - *
    3.14 - * 05/22/2000 eranian Added support for stacked register calls
    3.15 - * 05/24/2000 eranian Added support for physical mode static calls
    3.16 - */
    3.17 -
    3.18 -#include <asm/asmmacro.h>
    3.19 -#include <asm/processor.h>
    3.20 -
    3.21 -	.data
    3.22 -pal_entry_point:
    3.23 -	data8 ia64_pal_default_handler
    3.24 -	.text
    3.25 -
    3.26 -/*
    3.27 - * Set the PAL entry point address.  This could be written in C code, but we
    3.28 - * do it here to keep it all in one module (besides, it's so trivial that it's
    3.29 - * not a big deal).
    3.30 - *
    3.31 - * in0		Address of the PAL entry point (text address, NOT a function
    3.32 - *		descriptor).
    3.33 - */
    3.34 -GLOBAL_ENTRY(ia64_pal_handler_init)
    3.35 -	alloc r3=ar.pfs,1,0,0,0
    3.36 -	movl r2=pal_entry_point
    3.37 -	;;
    3.38 -	st8 [r2]=in0
    3.39 -	br.ret.sptk.many rp
    3.40 -END(ia64_pal_handler_init)
    3.41 -
    3.42 -/*
    3.43 - * Default PAL call handler.  This needs to be coded in assembly because it
    3.44 - * uses the static calling convention, i.e., the RSE may not be used and
    3.45 - * calls are done via "br.cond" (not "br.call").
    3.46 - */
    3.47 -GLOBAL_ENTRY(ia64_pal_default_handler)
    3.48 -	mov r8=-1
    3.49 -	br.cond.sptk.many rp
    3.50 -END(ia64_pal_default_handler)
    3.51 -
    3.52 -/*
    3.53 - * Make a PAL call using the static calling convention.
    3.54 - *
    3.55 - * in0         Index of PAL service
    3.56 - * in1 - in3   Remaining PAL arguments
    3.57 - */
    3.58 -GLOBAL_ENTRY(ia64_pal_call_static)
    3.59 -	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
    3.60 -	alloc loc1 = ar.pfs,4,5,0,0
    3.61 -	movl loc2 = pal_entry_point
    3.62 -1:	{
    3.63 -	  mov r28 = in0
    3.64 -	  mov r29 = in1
    3.65 -	  mov r8 = ip
    3.66 -	}
    3.67 -	;;
    3.68 -	ld8 loc2 = [loc2]		// loc2 <- entry point
    3.69 -	adds r8 = 1f-1b,r8
    3.70 -	mov loc4=ar.rsc			// save RSE configuration
    3.71 -	;;
    3.72 -	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
    3.73 -	mov loc3 = psr
    3.74 -	mov loc0 = rp
    3.75 -	.body
    3.76 -	mov r30 = in2
    3.77 -
    3.78 -	mov r31 = in3
    3.79 -	mov b7 = loc2
    3.80 -
    3.81 -	rsm psr.i
    3.82 -	;;
    3.83 -	mov rp = r8
    3.84 -	br.cond.sptk.many b7
    3.85 -1:	mov psr.l = loc3
    3.86 -	mov ar.rsc = loc4		// restore RSE configuration
    3.87 -	mov ar.pfs = loc1
    3.88 -	mov rp = loc0
    3.89 -	;;
    3.90 -	srlz.d				// seralize restoration of psr.l
    3.91 -	br.ret.sptk.many b0
    3.92 -END(ia64_pal_call_static)
    3.93 -
    3.94 -/*
    3.95 - * Make a PAL call using the stacked registers calling convention.
    3.96 - *
    3.97 - * Inputs:
    3.98 - *	in0         Index of PAL service
    3.99 - *	in2 - in3   Remaining PAL arguments
   3.100 - */
   3.101 -GLOBAL_ENTRY(ia64_pal_call_stacked)
   3.102 -	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
   3.103 -	alloc loc1 = ar.pfs,4,4,4,0
   3.104 -	movl loc2 = pal_entry_point
   3.105 -
   3.106 -	mov r28  = in0			// Index MUST be copied to r28
   3.107 -	mov out0 = in0			// AND in0 of PAL function
   3.108 -	mov loc0 = rp
   3.109 -	.body
   3.110 -	;;
   3.111 -	ld8 loc2 = [loc2]		// loc2 <- entry point
   3.112 -	mov out1 = in1
   3.113 -	mov out2 = in2
   3.114 -	mov out3 = in3
   3.115 -	mov loc3 = psr
   3.116 -	;;
   3.117 -	rsm psr.i
   3.118 -	mov b7 = loc2
   3.119 -	;;
   3.120 -	br.call.sptk.many rp=b7		// now make the call
   3.121 -.ret0:	mov psr.l  = loc3
   3.122 -	mov ar.pfs = loc1
   3.123 -	mov rp = loc0
   3.124 -	;;
   3.125 -	srlz.d				// serialize restoration of psr.l
   3.126 -	br.ret.sptk.many b0
   3.127 -END(ia64_pal_call_stacked)
   3.128 -
   3.129 -/*
   3.130 - * Make a physical mode PAL call using the static registers calling convention.
   3.131 - *
   3.132 - * Inputs:
   3.133 - *	in0         Index of PAL service
   3.134 - *	in2 - in3   Remaining PAL arguments
   3.135 - *
   3.136 - * PSR_LP, PSR_TB, PSR_ID, PSR_DA are never set by the kernel.
   3.137 - * So we don't need to clear them.
   3.138 - */
   3.139 -#define PAL_PSR_BITS_TO_CLEAR						      \
   3.140 -	(IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT  | IA64_PSR_DB | IA64_PSR_RT |\
   3.141 -	 IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED |	      \
   3.142 -	 IA64_PSR_DFL | IA64_PSR_DFH)
   3.143 -
   3.144 -#define PAL_PSR_BITS_TO_SET						      \
   3.145 -	(IA64_PSR_BN)
   3.146 -
   3.147 -
   3.148 -GLOBAL_ENTRY(ia64_pal_call_phys_static)
   3.149 -	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
   3.150 -	alloc loc1 = ar.pfs,4,7,0,0
   3.151 -	movl loc2 = pal_entry_point
   3.152 -1:	{
   3.153 -	  mov r28  = in0		// copy procedure index
   3.154 -	  mov r8   = ip			// save ip to compute branch
   3.155 -	  mov loc0 = rp			// save rp
   3.156 -	}
   3.157 -	.body
   3.158 -	;;
   3.159 -	ld8 loc2 = [loc2]		// loc2 <- entry point
   3.160 -	mov r29  = in1			// first argument
   3.161 -	mov r30  = in2			// copy arg2
   3.162 -	mov r31  = in3			// copy arg3
   3.163 -	;;
   3.164 -	mov loc3 = psr			// save psr
   3.165 -	adds r8  = 1f-1b,r8		// calculate return address for call
   3.166 -	;;
   3.167 -	mov loc4=ar.rsc			// save RSE configuration
   3.168 -	dep.z loc2=loc2,0,61		// convert pal entry point to physical
   3.169 -	tpa r8=r8			// convert rp to physical
   3.170 -	;;
   3.171 -	mov b7 = loc2			// install target to branch reg
   3.172 -	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   3.173 -	movl r16=PAL_PSR_BITS_TO_CLEAR
   3.174 -	movl r17=PAL_PSR_BITS_TO_SET
   3.175 -	;;
   3.176 -	or loc3=loc3,r17		// add in psr the bits to set
   3.177 -	;;
   3.178 -	andcm r16=loc3,r16		// removes bits to clear from psr
   3.179 -	br.call.sptk.many rp=ia64_switch_mode_phys
   3.180 -	mov rp = r8			// install return address (physical)
   3.181 -	mov loc5 = r19
   3.182 -	mov loc6 = r20
   3.183 -	br.cond.sptk.many b7
   3.184 -1:
   3.185 -	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   3.186 -	mov r16=loc3			// r16= original psr
   3.187 -	mov r19=loc5
   3.188 -	mov r20=loc6
   3.189 -	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
   3.190 -	mov psr.l = loc3		// restore init PSR
   3.191 -
   3.192 -	mov ar.pfs = loc1
   3.193 -	mov rp = loc0
   3.194 -	;;
   3.195 -	mov ar.rsc=loc4			// restore RSE configuration
   3.196 -	srlz.d				// seralize restoration of psr.l
   3.197 -	br.ret.sptk.many b0
   3.198 -END(ia64_pal_call_phys_static)
   3.199 -
   3.200 -/*
   3.201 - * Make a PAL call using the stacked registers in physical mode.
   3.202 - *
   3.203 - * Inputs:
   3.204 - *	in0         Index of PAL service
   3.205 - *	in2 - in3   Remaining PAL arguments
   3.206 - */
   3.207 -GLOBAL_ENTRY(ia64_pal_call_phys_stacked)
   3.208 -	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
   3.209 -	alloc	loc1 = ar.pfs,5,7,4,0
   3.210 -	movl	loc2 = pal_entry_point
   3.211 -1:	{
   3.212 -	  mov r28  = in0		// copy procedure index
   3.213 -	  mov loc0 = rp			// save rp
   3.214 -	}
   3.215 -	.body
   3.216 -	;;
   3.217 -	ld8 loc2 = [loc2]		// loc2 <- entry point
   3.218 -	mov loc3 = psr			// save psr
   3.219 -	;;
   3.220 -	mov loc4=ar.rsc			// save RSE configuration
   3.221 -	dep.z loc2=loc2,0,61		// convert pal entry point to physical
   3.222 -	;;
   3.223 -	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   3.224 -	movl r16=PAL_PSR_BITS_TO_CLEAR
   3.225 -	movl r17=PAL_PSR_BITS_TO_SET
   3.226 -	;;
   3.227 -	or loc3=loc3,r17		// add in psr the bits to set
   3.228 -	mov b7 = loc2			// install target to branch reg
   3.229 -	;;
   3.230 -	andcm r16=loc3,r16		// removes bits to clear from psr
   3.231 -	br.call.sptk.many rp=ia64_switch_mode_phys
   3.232 -
   3.233 -	mov out0 = in0			// first argument
   3.234 -	mov out1 = in1			// copy arg2
   3.235 -	mov out2 = in2			// copy arg3
   3.236 -	mov out3 = in3			// copy arg3
   3.237 -	mov loc5 = r19
   3.238 -	mov loc6 = r20
   3.239 -
   3.240 -	br.call.sptk.many rp=b7		// now make the call
   3.241 -
   3.242 -	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   3.243 -	mov r16=loc3			// r16= original psr
   3.244 -	mov r19=loc5
   3.245 -	mov r20=loc6
   3.246 -	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
   3.247 -
   3.248 -	mov psr.l  = loc3		// restore init PSR
   3.249 -	mov ar.pfs = loc1
   3.250 -	mov rp = loc0
   3.251 -	;;
   3.252 -	mov ar.rsc=loc4			// restore RSE configuration
   3.253 -	srlz.d				// seralize restoration of psr.l
   3.254 -	br.ret.sptk.many b0
   3.255 -END(ia64_pal_call_phys_stacked)
   3.256 -
   3.257 -/*
   3.258 - * Save scratch fp scratch regs which aren't saved in pt_regs already
   3.259 - * (fp10-fp15).
   3.260 - *
   3.261 - * NOTE: We need to do this since firmware (SAL and PAL) may use any of the
   3.262 - * scratch regs fp-low partition.
   3.263 - *
   3.264 - * Inputs:
   3.265 - *      in0	Address of stack storage for fp regs
   3.266 - */
   3.267 -GLOBAL_ENTRY(ia64_save_scratch_fpregs)
   3.268 -	alloc r3=ar.pfs,1,0,0,0
   3.269 -	add r2=16,in0
   3.270 -	;;
   3.271 -	stf.spill [in0] = f10,32
   3.272 -	stf.spill [r2]  = f11,32
   3.273 -	;;
   3.274 -	stf.spill [in0] = f12,32
   3.275 -	stf.spill [r2]  = f13,32
   3.276 -	;;
   3.277 -	stf.spill [in0] = f14,32
   3.278 -	stf.spill [r2]  = f15,32
   3.279 -	br.ret.sptk.many rp
   3.280 -END(ia64_save_scratch_fpregs)
   3.281 -
   3.282 -/*
   3.283 - * Load scratch fp scratch regs (fp10-fp15)
   3.284 - *
   3.285 - * Inputs:
   3.286 - *      in0	Address of stack storage for fp regs
   3.287 - */
   3.288 -GLOBAL_ENTRY(ia64_load_scratch_fpregs)
   3.289 -	alloc r3=ar.pfs,1,0,0,0
   3.290 -	add r2=16,in0
   3.291 -	;;
   3.292 -	ldf.fill  f10 = [in0],32
   3.293 -	ldf.fill  f11 = [r2],32
   3.294 -	;;
   3.295 -	ldf.fill  f12 = [in0],32
   3.296 -	ldf.fill  f13 = [r2],32
   3.297 -	;;
   3.298 -	ldf.fill  f14 = [in0],32
   3.299 -	ldf.fill  f15 = [r2],32
   3.300 -	br.ret.sptk.many rp
   3.301 -END(ia64_load_scratch_fpregs)
     4.1 --- a/xen/arch/ia64/linux/Makefile	Mon Aug 25 19:04:37 2008 +0900
     4.2 +++ b/xen/arch/ia64/linux/Makefile	Mon Aug 25 19:04:37 2008 +0900
     4.3 @@ -15,6 +15,7 @@ obj-y += machvec.o
     4.4  obj-y += memcpy_mck.o
     4.5  obj-y += memset.o
     4.6  obj-y += numa.o
     4.7 +obj-y += pal.o
     4.8  obj-y += strlen.o
     4.9  
    4.10  obj-y += __divsi3.o
     5.1 --- a/xen/arch/ia64/linux/README.origin	Mon Aug 25 19:04:37 2008 +0900
     5.2 +++ b/xen/arch/ia64/linux/README.origin	Mon Aug 25 19:04:37 2008 +0900
     5.3 @@ -29,3 +29,6 @@ carta_random.S		-> linux/arch/ia64/lib/c
     5.4  
     5.5  # The files below are from Linux-2.6.19
     5.6  io.c			-> linux/arch/ia64/lib/io.c
     5.7 +
     5.8 +# The files below are from Linux-2.6.21
     5.9 +pal.S			-> linux/arch/ia64/kernel/pal.S
     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/xen/arch/ia64/linux/pal.S	Mon Aug 25 19:04:37 2008 +0900
     6.3 @@ -0,0 +1,298 @@
     6.4 +/*
     6.5 + * PAL Firmware support
     6.6 + * IA-64 Processor Programmers Reference Vol 2
     6.7 + *
     6.8 + * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
     6.9 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
    6.10 + * Copyright (C) 1999-2001, 2003 Hewlett-Packard Co
    6.11 + *	David Mosberger <davidm@hpl.hp.com>
    6.12 + *	Stephane Eranian <eranian@hpl.hp.com>
    6.13 + *
    6.14 + * 05/22/2000 eranian Added support for stacked register calls
    6.15 + * 05/24/2000 eranian Added support for physical mode static calls
    6.16 + */
    6.17 +
    6.18 +#include <asm/asmmacro.h>
    6.19 +#include <asm/processor.h>
    6.20 +
    6.21 +	.data
    6.22 +pal_entry_point:
    6.23 +	data8 ia64_pal_default_handler
    6.24 +	.text
    6.25 +
    6.26 +/*
    6.27 + * Set the PAL entry point address.  This could be written in C code, but we
    6.28 + * do it here to keep it all in one module (besides, it's so trivial that it's
    6.29 + * not a big deal).
    6.30 + *
    6.31 + * in0		Address of the PAL entry point (text address, NOT a function
    6.32 + *		descriptor).
    6.33 + */
    6.34 +GLOBAL_ENTRY(ia64_pal_handler_init)
    6.35 +	alloc r3=ar.pfs,1,0,0,0
    6.36 +	movl r2=pal_entry_point
    6.37 +	;;
    6.38 +	st8 [r2]=in0
    6.39 +	br.ret.sptk.many rp
    6.40 +END(ia64_pal_handler_init)
    6.41 +
    6.42 +/*
    6.43 + * Default PAL call handler.  This needs to be coded in assembly because it
    6.44 + * uses the static calling convention, i.e., the RSE may not be used and
    6.45 + * calls are done via "br.cond" (not "br.call").
    6.46 + */
    6.47 +GLOBAL_ENTRY(ia64_pal_default_handler)
    6.48 +	mov r8=-1
    6.49 +	br.cond.sptk.many rp
    6.50 +END(ia64_pal_default_handler)
    6.51 +
    6.52 +/*
    6.53 + * Make a PAL call using the static calling convention.
    6.54 + *
    6.55 + * in0         Index of PAL service
    6.56 + * in1 - in3   Remaining PAL arguments
    6.57 + */
    6.58 +GLOBAL_ENTRY(ia64_pal_call_static)
    6.59 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
    6.60 +	alloc loc1 = ar.pfs,4,5,0,0
    6.61 +	movl loc2 = pal_entry_point
    6.62 +1:	{
    6.63 +	  mov r28 = in0
    6.64 +	  mov r29 = in1
    6.65 +	  mov r8 = ip
    6.66 +	}
    6.67 +	;;
    6.68 +	ld8 loc2 = [loc2]		// loc2 <- entry point
    6.69 +	adds r8 = 1f-1b,r8
    6.70 +	mov loc4=ar.rsc			// save RSE configuration
    6.71 +	;;
    6.72 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
    6.73 +	mov loc3 = psr
    6.74 +	mov loc0 = rp
    6.75 +	.body
    6.76 +	mov r30 = in2
    6.77 +
    6.78 +	mov r31 = in3
    6.79 +	mov b7 = loc2
    6.80 +
    6.81 +	rsm psr.i
    6.82 +	;;
    6.83 +	mov rp = r8
    6.84 +	br.cond.sptk.many b7
    6.85 +1:	mov psr.l = loc3
    6.86 +	mov ar.rsc = loc4		// restore RSE configuration
    6.87 +	mov ar.pfs = loc1
    6.88 +	mov rp = loc0
    6.89 +	;;
    6.90 +	srlz.d				// seralize restoration of psr.l
    6.91 +	br.ret.sptk.many b0
    6.92 +END(ia64_pal_call_static)
    6.93 +
    6.94 +/*
    6.95 + * Make a PAL call using the stacked registers calling convention.
    6.96 + *
    6.97 + * Inputs:
    6.98 + *	in0         Index of PAL service
    6.99 + *	in2 - in3   Remaining PAL arguments
   6.100 + */
   6.101 +GLOBAL_ENTRY(ia64_pal_call_stacked)
   6.102 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
   6.103 +	alloc loc1 = ar.pfs,4,4,4,0
   6.104 +	movl loc2 = pal_entry_point
   6.105 +
   6.106 +	mov r28  = in0			// Index MUST be copied to r28
   6.107 +	mov out0 = in0			// AND in0 of PAL function
   6.108 +	mov loc0 = rp
   6.109 +	.body
   6.110 +	;;
   6.111 +	ld8 loc2 = [loc2]		// loc2 <- entry point
   6.112 +	mov out1 = in1
   6.113 +	mov out2 = in2
   6.114 +	mov out3 = in3
   6.115 +	mov loc3 = psr
   6.116 +	;;
   6.117 +	rsm psr.i
   6.118 +	mov b7 = loc2
   6.119 +	;;
   6.120 +	br.call.sptk.many rp=b7		// now make the call
   6.121 +.ret0:	mov psr.l  = loc3
   6.122 +	mov ar.pfs = loc1
   6.123 +	mov rp = loc0
   6.124 +	;;
   6.125 +	srlz.d				// serialize restoration of psr.l
   6.126 +	br.ret.sptk.many b0
   6.127 +END(ia64_pal_call_stacked)
   6.128 +
   6.129 +/*
   6.130 + * Make a physical mode PAL call using the static registers calling convention.
   6.131 + *
   6.132 + * Inputs:
   6.133 + *	in0         Index of PAL service
   6.134 + *	in2 - in3   Remaining PAL arguments
   6.135 + *
   6.136 + * PSR_LP, PSR_TB, PSR_ID, PSR_DA are never set by the kernel.
   6.137 + * So we don't need to clear them.
   6.138 + */
   6.139 +#define PAL_PSR_BITS_TO_CLEAR						      \
   6.140 +	(IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT  | IA64_PSR_DB | IA64_PSR_RT |\
   6.141 +	 IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED |	      \
   6.142 +	 IA64_PSR_DFL | IA64_PSR_DFH)
   6.143 +
   6.144 +#define PAL_PSR_BITS_TO_SET						      \
   6.145 +	(IA64_PSR_BN)
   6.146 +
   6.147 +
   6.148 +GLOBAL_ENTRY(ia64_pal_call_phys_static)
   6.149 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
   6.150 +	alloc loc1 = ar.pfs,4,7,0,0
   6.151 +	movl loc2 = pal_entry_point
   6.152 +1:	{
   6.153 +	  mov r28  = in0		// copy procedure index
   6.154 +	  mov r8   = ip			// save ip to compute branch
   6.155 +	  mov loc0 = rp			// save rp
   6.156 +	}
   6.157 +	.body
   6.158 +	;;
   6.159 +	ld8 loc2 = [loc2]		// loc2 <- entry point
   6.160 +	mov r29  = in1			// first argument
   6.161 +	mov r30  = in2			// copy arg2
   6.162 +	mov r31  = in3			// copy arg3
   6.163 +	;;
   6.164 +	mov loc3 = psr			// save psr
   6.165 +	adds r8  = 1f-1b,r8		// calculate return address for call
   6.166 +	;;
   6.167 +	mov loc4=ar.rsc			// save RSE configuration
   6.168 +	dep.z loc2=loc2,0,61		// convert pal entry point to physical
   6.169 +	tpa r8=r8			// convert rp to physical
   6.170 +	;;
   6.171 +	mov b7 = loc2			// install target to branch reg
   6.172 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   6.173 +	movl r16=PAL_PSR_BITS_TO_CLEAR
   6.174 +	movl r17=PAL_PSR_BITS_TO_SET
   6.175 +	;;
   6.176 +	or loc3=loc3,r17		// add in psr the bits to set
   6.177 +	;;
   6.178 +	andcm r16=loc3,r16		// removes bits to clear from psr
   6.179 +	br.call.sptk.many rp=ia64_switch_mode_phys
   6.180 +	mov rp = r8			// install return address (physical)
   6.181 +	mov loc5 = r19
   6.182 +	mov loc6 = r20
   6.183 +	br.cond.sptk.many b7
   6.184 +1:
   6.185 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   6.186 +	mov r16=loc3			// r16= original psr
   6.187 +	mov r19=loc5
   6.188 +	mov r20=loc6
   6.189 +	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
   6.190 +	mov psr.l = loc3		// restore init PSR
   6.191 +
   6.192 +	mov ar.pfs = loc1
   6.193 +	mov rp = loc0
   6.194 +	;;
   6.195 +	mov ar.rsc=loc4			// restore RSE configuration
   6.196 +	srlz.d				// seralize restoration of psr.l
   6.197 +	br.ret.sptk.many b0
   6.198 +END(ia64_pal_call_phys_static)
   6.199 +
   6.200 +/*
   6.201 + * Make a PAL call using the stacked registers in physical mode.
   6.202 + *
   6.203 + * Inputs:
   6.204 + *	in0         Index of PAL service
   6.205 + *	in2 - in3   Remaining PAL arguments
   6.206 + */
   6.207 +GLOBAL_ENTRY(ia64_pal_call_phys_stacked)
   6.208 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
   6.209 +	alloc	loc1 = ar.pfs,5,7,4,0
   6.210 +	movl	loc2 = pal_entry_point
   6.211 +1:	{
   6.212 +	  mov r28  = in0		// copy procedure index
   6.213 +	  mov loc0 = rp			// save rp
   6.214 +	}
   6.215 +	.body
   6.216 +	;;
   6.217 +	ld8 loc2 = [loc2]		// loc2 <- entry point
   6.218 +	mov loc3 = psr			// save psr
   6.219 +	;;
   6.220 +	mov loc4=ar.rsc			// save RSE configuration
   6.221 +	dep.z loc2=loc2,0,61		// convert pal entry point to physical
   6.222 +	;;
   6.223 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   6.224 +	movl r16=PAL_PSR_BITS_TO_CLEAR
   6.225 +	movl r17=PAL_PSR_BITS_TO_SET
   6.226 +	;;
   6.227 +	or loc3=loc3,r17		// add in psr the bits to set
   6.228 +	mov b7 = loc2			// install target to branch reg
   6.229 +	;;
   6.230 +	andcm r16=loc3,r16		// removes bits to clear from psr
   6.231 +	br.call.sptk.many rp=ia64_switch_mode_phys
   6.232 +
   6.233 +	mov out0 = in0			// first argument
   6.234 +	mov out1 = in1			// copy arg2
   6.235 +	mov out2 = in2			// copy arg3
   6.236 +	mov out3 = in3			// copy arg3
   6.237 +	mov loc5 = r19
   6.238 +	mov loc6 = r20
   6.239 +
   6.240 +	br.call.sptk.many rp=b7		// now make the call
   6.241 +
   6.242 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   6.243 +	mov r16=loc3			// r16= original psr
   6.244 +	mov r19=loc5
   6.245 +	mov r20=loc6
   6.246 +	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
   6.247 +
   6.248 +	mov psr.l  = loc3		// restore init PSR
   6.249 +	mov ar.pfs = loc1
   6.250 +	mov rp = loc0
   6.251 +	;;
   6.252 +	mov ar.rsc=loc4			// restore RSE configuration
   6.253 +	srlz.d				// seralize restoration of psr.l
   6.254 +	br.ret.sptk.many b0
   6.255 +END(ia64_pal_call_phys_stacked)
   6.256 +
   6.257 +/*
   6.258 + * Save scratch fp scratch regs which aren't saved in pt_regs already
   6.259 + * (fp10-fp15).
   6.260 + *
   6.261 + * NOTE: We need to do this since firmware (SAL and PAL) may use any of the
   6.262 + * scratch regs fp-low partition.
   6.263 + *
   6.264 + * Inputs:
   6.265 + *      in0	Address of stack storage for fp regs
   6.266 + */
   6.267 +GLOBAL_ENTRY(ia64_save_scratch_fpregs)
   6.268 +	alloc r3=ar.pfs,1,0,0,0
   6.269 +	add r2=16,in0
   6.270 +	;;
   6.271 +	stf.spill [in0] = f10,32
   6.272 +	stf.spill [r2]  = f11,32
   6.273 +	;;
   6.274 +	stf.spill [in0] = f12,32
   6.275 +	stf.spill [r2]  = f13,32
   6.276 +	;;
   6.277 +	stf.spill [in0] = f14,32
   6.278 +	stf.spill [r2]  = f15,32
   6.279 +	br.ret.sptk.many rp
   6.280 +END(ia64_save_scratch_fpregs)
   6.281 +
   6.282 +/*
   6.283 + * Load scratch fp scratch regs (fp10-fp15)
   6.284 + *
   6.285 + * Inputs:
   6.286 + *      in0	Address of stack storage for fp regs
   6.287 + */
   6.288 +GLOBAL_ENTRY(ia64_load_scratch_fpregs)
   6.289 +	alloc r3=ar.pfs,1,0,0,0
   6.290 +	add r2=16,in0
   6.291 +	;;
   6.292 +	ldf.fill  f10 = [in0],32
   6.293 +	ldf.fill  f11 = [r2],32
   6.294 +	;;
   6.295 +	ldf.fill  f12 = [in0],32
   6.296 +	ldf.fill  f13 = [r2],32
   6.297 +	;;
   6.298 +	ldf.fill  f14 = [in0],32
   6.299 +	ldf.fill  f15 = [r2],32
   6.300 +	br.ret.sptk.many rp
   6.301 +END(ia64_load_scratch_fpregs)