ia64/xen-unstable

changeset 17540:8bced3d8a907

MSI 1/6: Move PCI functions and headers to a common location.

Signed-off-by: Shan Haitao <haitao.shan@intel.com>
Signed-off-by: Jiang Yunhong <yunhong.jiang@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu May 01 10:26:58 2008 +0100 (2008-05-01)
parents 5e5bc5b2bb6d
children 6ecbb00e58cd
files xen/arch/x86/domctl.c xen/arch/x86/pci.c xen/drivers/passthrough/amd/iommu_detect.c xen/drivers/passthrough/amd/iommu_init.c xen/drivers/passthrough/amd/pci_amd_iommu.c xen/drivers/passthrough/pci_regs.h xen/drivers/passthrough/vtd/dmar.c xen/drivers/passthrough/vtd/intremap.c xen/drivers/passthrough/vtd/iommu.c xen/drivers/passthrough/vtd/qinval.c xen/drivers/passthrough/vtd/utils.c xen/include/xen/iommu.h xen/include/xen/pci.h xen/include/xen/pci_regs.h
line diff
     1.1 --- a/xen/arch/x86/domctl.c	Thu May 01 10:00:00 2008 +0100
     1.2 +++ b/xen/arch/x86/domctl.c	Thu May 01 10:26:58 2008 +0100
     1.3 @@ -10,6 +10,7 @@
     1.4  #include <xen/mm.h>
     1.5  #include <xen/guest_access.h>
     1.6  #include <xen/compat.h>
     1.7 +#include <xen/pci.h>
     1.8  #include <public/domctl.h>
     1.9  #include <xen/sched.h>
    1.10  #include <xen/domain.h>
     2.1 --- a/xen/arch/x86/pci.c	Thu May 01 10:00:00 2008 +0100
     2.2 +++ b/xen/arch/x86/pci.c	Thu May 01 10:26:58 2008 +0100
     2.3 @@ -6,6 +6,7 @@
     2.4  
     2.5  #include <xen/config.h>
     2.6  #include <xen/pci.h>
     2.7 +#include <xen/pci_regs.h>
     2.8  #include <xen/spinlock.h>
     2.9  #include <asm/io.h>
    2.10  
    2.11 @@ -116,3 +117,60 @@ void pci_conf_write32(
    2.12      BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255));
    2.13      pci_conf_write(PCI_CONF_ADDRESS(bus, dev, func, reg), 0, 4, data);
    2.14  }
    2.15 +
    2.16 +int pci_find_cap_offset(u8 bus, u8 dev, u8 func, u8 cap)
    2.17 +{
    2.18 +    u8 id;
    2.19 +    int max_cap = 48;
    2.20 +    u8 pos = PCI_CAPABILITY_LIST;
    2.21 +    u16 status;
    2.22 +
    2.23 +    status = pci_conf_read16(bus, dev, func, PCI_STATUS);
    2.24 +    if ( (status & PCI_STATUS_CAP_LIST) == 0 )
    2.25 +        return 0;
    2.26 +
    2.27 +    while ( max_cap-- )
    2.28 +    {
    2.29 +        pos = pci_conf_read8(bus, dev, func, pos);
    2.30 +        if ( pos < 0x40 )
    2.31 +            break;
    2.32 +
    2.33 +        pos &= ~3;
    2.34 +        id = pci_conf_read8(bus, dev, func, pos + PCI_CAP_LIST_ID);
    2.35 +
    2.36 +        if ( id == 0xff )
    2.37 +            break;
    2.38 +        else if ( id == cap )
    2.39 +            return pos;
    2.40 +
    2.41 +        pos += PCI_CAP_LIST_NEXT;
    2.42 +    }
    2.43 +
    2.44 +    return 0;
    2.45 +}
    2.46 +
    2.47 +int pci_find_next_cap(u8 bus, unsigned int devfn, u8 pos, int cap)
    2.48 +{
    2.49 +    u8 id;
    2.50 +    int ttl = 48;
    2.51 +
    2.52 +    while ( ttl-- )
    2.53 +    {
    2.54 +        pos = pci_conf_read8(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos);
    2.55 +        if ( pos < 0x40 )
    2.56 +            break;
    2.57 +
    2.58 +        pos &= ~3;
    2.59 +        id = pci_conf_read8(bus, PCI_SLOT(devfn), PCI_FUNC(devfn),
    2.60 +                            pos + PCI_CAP_LIST_ID);
    2.61 +
    2.62 +        if ( id == 0xff )
    2.63 +            break;
    2.64 +        if ( id == cap )
    2.65 +            return pos;
    2.66 +
    2.67 +        pos += PCI_CAP_LIST_NEXT;
    2.68 +    }
    2.69 +    return 0;
    2.70 +}
    2.71 +
     3.1 --- a/xen/drivers/passthrough/amd/iommu_detect.c	Thu May 01 10:00:00 2008 +0100
     3.2 +++ b/xen/drivers/passthrough/amd/iommu_detect.c	Thu May 01 10:26:58 2008 +0100
     3.3 @@ -22,9 +22,9 @@
     3.4  #include <xen/errno.h>
     3.5  #include <xen/iommu.h>
     3.6  #include <xen/pci.h>
     3.7 +#include <xen/pci_regs.h>
     3.8  #include <asm/amd-iommu.h>
     3.9  #include <asm/hvm/svm/amd-iommu-proto.h>
    3.10 -#include "../pci_regs.h"
    3.11  
    3.12  static int __init valid_bridge_bus_config(
    3.13      int bus, int dev, int func, int *sec_bus, int *sub_bus)
     4.1 --- a/xen/drivers/passthrough/amd/iommu_init.c	Thu May 01 10:00:00 2008 +0100
     4.2 +++ b/xen/drivers/passthrough/amd/iommu_init.c	Thu May 01 10:26:58 2008 +0100
     4.3 @@ -21,10 +21,10 @@
     4.4  #include <xen/config.h>
     4.5  #include <xen/errno.h>
     4.6  #include <xen/pci.h>
     4.7 +#include <xen/pci_regs.h>
     4.8  #include <asm/amd-iommu.h>
     4.9  #include <asm/hvm/svm/amd-iommu-proto.h>
    4.10  #include <asm-x86/fixmap.h>
    4.11 -#include "../pci_regs.h"
    4.12  
    4.13  extern int nr_amd_iommus;
    4.14  static struct amd_iommu *vector_to_iommu[NR_VECTORS];
     5.1 --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c	Thu May 01 10:00:00 2008 +0100
     5.2 +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c	Thu May 01 10:26:58 2008 +0100
     5.3 @@ -20,11 +20,11 @@
     5.4  
     5.5  #include <xen/sched.h>
     5.6  #include <xen/pci.h>
     5.7 +#include <xen/pci_regs.h>
     5.8  #include <asm/amd-iommu.h>
     5.9  #include <asm/hvm/svm/amd-iommu-proto.h>
    5.10  #include <asm/hvm/svm/amd-iommu-acpi.h>
    5.11  #include <asm/mm.h>
    5.12 -#include "../pci_regs.h"
    5.13  
    5.14  struct list_head amd_iommu_head;
    5.15  long amd_iommu_poll_comp_wait = COMPLETION_WAIT_DEFAULT_POLLING_COUNT;
     6.1 --- a/xen/drivers/passthrough/pci_regs.h	Thu May 01 10:00:00 2008 +0100
     6.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.3 @@ -1,530 +0,0 @@
     6.4 -/*
     6.5 - *	pci_regs.h
     6.6 - *
     6.7 - *	PCI standard defines
     6.8 - *	Copyright 1994, Drew Eckhardt
     6.9 - *	Copyright 1997--1999 Martin Mares <mj@ucw.cz>
    6.10 - *
    6.11 - *	For more information, please consult the following manuals (look at
    6.12 - *	http://www.pcisig.com/ for how to get them):
    6.13 - *
    6.14 - *	PCI BIOS Specification
    6.15 - *	PCI Local Bus Specification
    6.16 - *	PCI to PCI Bridge Specification
    6.17 - *	PCI System Design Guide
    6.18 - *
    6.19 - * 	For hypertransport information, please consult the following manuals
    6.20 - * 	from http://www.hypertransport.org
    6.21 - *
    6.22 - *	The Hypertransport I/O Link Specification
    6.23 - */
    6.24 -
    6.25 -#ifndef LINUX_PCI_REGS_H
    6.26 -#define LINUX_PCI_REGS_H
    6.27 -
    6.28 -/*
    6.29 - * Under PCI, each device has 256 bytes of configuration address space,
    6.30 - * of which the first 64 bytes are standardized as follows:
    6.31 - */
    6.32 -#define PCI_VENDOR_ID		0x00	/* 16 bits */
    6.33 -#define PCI_DEVICE_ID		0x02	/* 16 bits */
    6.34 -#define PCI_COMMAND		0x04	/* 16 bits */
    6.35 -#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
    6.36 -#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
    6.37 -#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
    6.38 -#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
    6.39 -#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
    6.40 -#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
    6.41 -#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
    6.42 -#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
    6.43 -#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
    6.44 -#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
    6.45 -#define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
    6.46 -
    6.47 -#define PCI_STATUS		0x06	/* 16 bits */
    6.48 -#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
    6.49 -#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
    6.50 -#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
    6.51 -#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
    6.52 -#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
    6.53 -#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
    6.54 -#define  PCI_STATUS_DEVSEL_FAST		0x000
    6.55 -#define  PCI_STATUS_DEVSEL_MEDIUM	0x200
    6.56 -#define  PCI_STATUS_DEVSEL_SLOW		0x400
    6.57 -#define  PCI_STATUS_SIG_TARGET_ABORT	0x800 /* Set on target abort */
    6.58 -#define  PCI_STATUS_REC_TARGET_ABORT	0x1000 /* Master ack of " */
    6.59 -#define  PCI_STATUS_REC_MASTER_ABORT	0x2000 /* Set on master abort */
    6.60 -#define  PCI_STATUS_SIG_SYSTEM_ERROR	0x4000 /* Set when we drive SERR */
    6.61 -#define  PCI_STATUS_DETECTED_PARITY	0x8000 /* Set on parity error */
    6.62 -
    6.63 -#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8 revision */
    6.64 -#define PCI_REVISION_ID		0x08	/* Revision ID */
    6.65 -#define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
    6.66 -#define PCI_CLASS_DEVICE	0x0a	/* Device class */
    6.67 -
    6.68 -#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
    6.69 -#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
    6.70 -#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
    6.71 -#define  PCI_HEADER_TYPE_NORMAL		0
    6.72 -#define  PCI_HEADER_TYPE_BRIDGE		1
    6.73 -#define  PCI_HEADER_TYPE_CARDBUS	2
    6.74 -
    6.75 -#define PCI_BIST		0x0f	/* 8 bits */
    6.76 -#define  PCI_BIST_CODE_MASK	0x0f	/* Return result */
    6.77 -#define  PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
    6.78 -#define  PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
    6.79 -
    6.80 -/*
    6.81 - * Base addresses specify locations in memory or I/O space.
    6.82 - * Decoded size can be determined by writing a value of
    6.83 - * 0xffffffff to the register, and reading it back.  Only
    6.84 - * 1 bits are decoded.
    6.85 - */
    6.86 -#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
    6.87 -#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
    6.88 -#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
    6.89 -#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
    6.90 -#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
    6.91 -#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
    6.92 -#define  PCI_BASE_ADDRESS_SPACE		0x01	/* 0 = memory, 1 = I/O */
    6.93 -#define  PCI_BASE_ADDRESS_SPACE_IO	0x01
    6.94 -#define  PCI_BASE_ADDRESS_SPACE_MEMORY	0x00
    6.95 -#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK	0x06
    6.96 -#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
    6.97 -#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
    6.98 -#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
    6.99 -#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
   6.100 -#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
   6.101 -#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
   6.102 -/* bit 1 is reserved if address_space = 1 */
   6.103 -
   6.104 -/* Header type 0 (normal devices) */
   6.105 -#define PCI_CARDBUS_CIS		0x28
   6.106 -#define PCI_SUBSYSTEM_VENDOR_ID	0x2c
   6.107 -#define PCI_SUBSYSTEM_ID	0x2e
   6.108 -#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
   6.109 -#define  PCI_ROM_ADDRESS_ENABLE	0x01
   6.110 -#define PCI_ROM_ADDRESS_MASK	(~0x7ffUL)
   6.111 -
   6.112 -#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
   6.113 -
   6.114 -/* 0x35-0x3b are reserved */
   6.115 -#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
   6.116 -#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
   6.117 -#define PCI_MIN_GNT		0x3e	/* 8 bits */
   6.118 -#define PCI_MAX_LAT		0x3f	/* 8 bits */
   6.119 -
   6.120 -/* Header type 1 (PCI-to-PCI bridges) */
   6.121 -#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
   6.122 -#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
   6.123 -#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
   6.124 -#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
   6.125 -#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
   6.126 -#define PCI_IO_LIMIT		0x1d
   6.127 -#define  PCI_IO_RANGE_TYPE_MASK	0x0fUL	/* I/O bridging type */
   6.128 -#define  PCI_IO_RANGE_TYPE_16	0x00
   6.129 -#define  PCI_IO_RANGE_TYPE_32	0x01
   6.130 -#define  PCI_IO_RANGE_MASK	(~0x0fUL)
   6.131 -#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
   6.132 -#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
   6.133 -#define PCI_MEMORY_LIMIT	0x22
   6.134 -#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
   6.135 -#define  PCI_MEMORY_RANGE_MASK	(~0x0fUL)
   6.136 -#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
   6.137 -#define PCI_PREF_MEMORY_LIMIT	0x26
   6.138 -#define  PCI_PREF_RANGE_TYPE_MASK 0x0fUL
   6.139 -#define  PCI_PREF_RANGE_TYPE_32	0x00
   6.140 -#define  PCI_PREF_RANGE_TYPE_64	0x01
   6.141 -#define  PCI_PREF_RANGE_MASK	(~0x0fUL)
   6.142 -#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
   6.143 -#define PCI_PREF_LIMIT_UPPER32	0x2c
   6.144 -#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
   6.145 -#define PCI_IO_LIMIT_UPPER16	0x32
   6.146 -/* 0x34 same as for htype 0 */
   6.147 -/* 0x35-0x3b is reserved */
   6.148 -#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
   6.149 -/* 0x3c-0x3d are same as for htype 0 */
   6.150 -#define PCI_BRIDGE_CONTROL	0x3e
   6.151 -#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
   6.152 -#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
   6.153 -#define  PCI_BRIDGE_CTL_ISA	0x04	/* Enable ISA mode */
   6.154 -#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
   6.155 -#define  PCI_BRIDGE_CTL_MASTER_ABORT	0x20  /* Report master aborts */
   6.156 -#define  PCI_BRIDGE_CTL_BUS_RESET	0x40	/* Secondary bus reset */
   6.157 -#define  PCI_BRIDGE_CTL_FAST_BACK	0x80	/* Fast Back2Back enabled on secondary interface */
   6.158 -
   6.159 -/* Header type 2 (CardBus bridges) */
   6.160 -#define PCI_CB_CAPABILITY_LIST	0x14
   6.161 -/* 0x15 reserved */
   6.162 -#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
   6.163 -#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
   6.164 -#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
   6.165 -#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
   6.166 -#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
   6.167 -#define PCI_CB_MEMORY_BASE_0	0x1c
   6.168 -#define PCI_CB_MEMORY_LIMIT_0	0x20
   6.169 -#define PCI_CB_MEMORY_BASE_1	0x24
   6.170 -#define PCI_CB_MEMORY_LIMIT_1	0x28
   6.171 -#define PCI_CB_IO_BASE_0	0x2c
   6.172 -#define PCI_CB_IO_BASE_0_HI	0x2e
   6.173 -#define PCI_CB_IO_LIMIT_0	0x30
   6.174 -#define PCI_CB_IO_LIMIT_0_HI	0x32
   6.175 -#define PCI_CB_IO_BASE_1	0x34
   6.176 -#define PCI_CB_IO_BASE_1_HI	0x36
   6.177 -#define PCI_CB_IO_LIMIT_1	0x38
   6.178 -#define PCI_CB_IO_LIMIT_1_HI	0x3a
   6.179 -#define  PCI_CB_IO_RANGE_MASK	(~0x03UL)
   6.180 -/* 0x3c-0x3d are same as for htype 0 */
   6.181 -#define PCI_CB_BRIDGE_CONTROL	0x3e
   6.182 -#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
   6.183 -#define  PCI_CB_BRIDGE_CTL_SERR		0x02
   6.184 -#define  PCI_CB_BRIDGE_CTL_ISA		0x04
   6.185 -#define  PCI_CB_BRIDGE_CTL_VGA		0x08
   6.186 -#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT	0x20
   6.187 -#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
   6.188 -#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
   6.189 -#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
   6.190 -#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
   6.191 -#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
   6.192 -#define PCI_CB_SUBSYSTEM_VENDOR_ID	0x40
   6.193 -#define PCI_CB_SUBSYSTEM_ID		0x42
   6.194 -#define PCI_CB_LEGACY_MODE_BASE		0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
   6.195 -/* 0x48-0x7f reserved */
   6.196 -
   6.197 -/* Capability lists */
   6.198 -
   6.199 -#define PCI_CAP_LIST_ID		0	/* Capability ID */
   6.200 -#define  PCI_CAP_ID_PM		0x01	/* Power Management */
   6.201 -#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
   6.202 -#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
   6.203 -#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
   6.204 -#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
   6.205 -#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
   6.206 -#define  PCI_CAP_ID_PCIX	0x07	/* PCI-X */
   6.207 -#define  PCI_CAP_ID_HT		0x08	/* HyperTransport */
   6.208 -#define  PCI_CAP_ID_VNDR	0x09	/* Vendor specific */
   6.209 -#define  PCI_CAP_ID_DBG		0x0A	/* Debug port */
   6.210 -#define  PCI_CAP_ID_CCRC	0x0B	/* CompactPCI Central Resource Control */
   6.211 -#define  PCI_CAP_ID_SHPC 	0x0C	/* PCI Standard Hot-Plug Controller */
   6.212 -#define  PCI_CAP_ID_SSVID	0x0D	/* Bridge subsystem vendor/device ID */
   6.213 -#define  PCI_CAP_ID_AGP3	0x0E	/* AGP Target PCI-PCI bridge */
   6.214 -#define  PCI_CAP_ID_EXP 	0x10	/* PCI Express */
   6.215 -#define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
   6.216 -#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
   6.217 -#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
   6.218 -#define PCI_CAP_SIZEOF		4
   6.219 -
   6.220 -/* Power Management Registers */
   6.221 -
   6.222 -#define PCI_PM_PMC		2	/* PM Capabilities Register */
   6.223 -#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
   6.224 -#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
   6.225 -#define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
   6.226 -#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
   6.227 -#define  PCI_PM_CAP_AUX_POWER	0x01C0	/* Auxilliary power support mask */
   6.228 -#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
   6.229 -#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
   6.230 -#define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
   6.231 -#define  PCI_PM_CAP_PME_MASK	0xF800	/* PME Mask of all supported states */
   6.232 -#define  PCI_PM_CAP_PME_D0	0x0800	/* PME# from D0 */
   6.233 -#define  PCI_PM_CAP_PME_D1	0x1000	/* PME# from D1 */
   6.234 -#define  PCI_PM_CAP_PME_D2	0x2000	/* PME# from D2 */
   6.235 -#define  PCI_PM_CAP_PME_D3	0x4000	/* PME# from D3 (hot) */
   6.236 -#define  PCI_PM_CAP_PME_D3cold	0x8000	/* PME# from D3 (cold) */
   6.237 -#define PCI_PM_CTRL		4	/* PM control and status register */
   6.238 -#define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
   6.239 -#define  PCI_PM_CTRL_NO_SOFT_RESET	0x0004	/* No reset for D3hot->D0 */
   6.240 -#define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
   6.241 -#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
   6.242 -#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
   6.243 -#define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
   6.244 -#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
   6.245 -#define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
   6.246 -#define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
   6.247 -#define PCI_PM_DATA_REGISTER	7	/* (??) */
   6.248 -#define PCI_PM_SIZEOF		8
   6.249 -
   6.250 -/* AGP registers */
   6.251 -
   6.252 -#define PCI_AGP_VERSION		2	/* BCD version number */
   6.253 -#define PCI_AGP_RFU		3	/* Rest of capability flags */
   6.254 -#define PCI_AGP_STATUS		4	/* Status register */
   6.255 -#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
   6.256 -#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
   6.257 -#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
   6.258 -#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
   6.259 -#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
   6.260 -#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
   6.261 -#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
   6.262 -#define PCI_AGP_COMMAND		8	/* Control register */
   6.263 -#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
   6.264 -#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
   6.265 -#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
   6.266 -#define  PCI_AGP_COMMAND_64BIT	0x0020 	/* Allow processing of 64-bit addresses */
   6.267 -#define  PCI_AGP_COMMAND_FW	0x0010 	/* Force FW transfers */
   6.268 -#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
   6.269 -#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 2x rate */
   6.270 -#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 1x rate */
   6.271 -#define PCI_AGP_SIZEOF		12
   6.272 -
   6.273 -/* Vital Product Data */
   6.274 -
   6.275 -#define PCI_VPD_ADDR		2	/* Address to access (15 bits!) */
   6.276 -#define  PCI_VPD_ADDR_MASK	0x7fff	/* Address mask */
   6.277 -#define  PCI_VPD_ADDR_F		0x8000	/* Write 0, 1 indicates completion */
   6.278 -#define PCI_VPD_DATA		4	/* 32-bits of data returned here */
   6.279 -
   6.280 -/* Slot Identification */
   6.281 -
   6.282 -#define PCI_SID_ESR		2	/* Expansion Slot Register */
   6.283 -#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
   6.284 -#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
   6.285 -#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
   6.286 -
   6.287 -/* Message Signalled Interrupts registers */
   6.288 -
   6.289 -#define PCI_MSI_FLAGS		2	/* Various flags */
   6.290 -#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
   6.291 -#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
   6.292 -#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
   6.293 -#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
   6.294 -#define  PCI_MSI_FLAGS_MASKBIT	0x100	/* 64-bit mask bits allowed */
   6.295 -#define PCI_MSI_RFU		3	/* Rest of capability flags */
   6.296 -#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
   6.297 -#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
   6.298 -#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
   6.299 -#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
   6.300 -#define PCI_MSI_MASK_BIT	16	/* Mask bits register */
   6.301 -
   6.302 -/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */
   6.303 -#define PCI_MSIX_FLAGS		2
   6.304 -#define  PCI_MSIX_FLAGS_QSIZE	0x7FF
   6.305 -#define  PCI_MSIX_FLAGS_ENABLE	(1 << 15)
   6.306 -#define  PCI_MSIX_FLAGS_MASKALL	(1 << 14)
   6.307 -#define PCI_MSIX_FLAGS_BIRMASK	(7 << 0)
   6.308 -#define PCI_MSIX_FLAGS_BITMASK	(1 << 0)
   6.309 -
   6.310 -/* CompactPCI Hotswap Register */
   6.311 -
   6.312 -#define PCI_CHSWP_CSR		2	/* Control and Status Register */
   6.313 -#define  PCI_CHSWP_DHA		0x01	/* Device Hiding Arm */
   6.314 -#define  PCI_CHSWP_EIM		0x02	/* ENUM# Signal Mask */
   6.315 -#define  PCI_CHSWP_PIE		0x04	/* Pending Insert or Extract */
   6.316 -#define  PCI_CHSWP_LOO		0x08	/* LED On / Off */
   6.317 -#define  PCI_CHSWP_PI		0x30	/* Programming Interface */
   6.318 -#define  PCI_CHSWP_EXT		0x40	/* ENUM# status - extraction */
   6.319 -#define  PCI_CHSWP_INS		0x80	/* ENUM# status - insertion */
   6.320 -
   6.321 -/* PCI-X registers */
   6.322 -
   6.323 -#define PCI_X_CMD		2	/* Modes & Features */
   6.324 -#define  PCI_X_CMD_DPERR_E	0x0001	/* Data Parity Error Recovery Enable */
   6.325 -#define  PCI_X_CMD_ERO		0x0002	/* Enable Relaxed Ordering */
   6.326 -#define  PCI_X_CMD_READ_512	0x0000	/* 512 byte maximum read byte count */
   6.327 -#define  PCI_X_CMD_READ_1K	0x0004	/* 1Kbyte maximum read byte count */
   6.328 -#define  PCI_X_CMD_READ_2K	0x0008	/* 2Kbyte maximum read byte count */
   6.329 -#define  PCI_X_CMD_READ_4K	0x000c	/* 4Kbyte maximum read byte count */
   6.330 -#define  PCI_X_CMD_MAX_READ	0x000c	/* Max Memory Read Byte Count */
   6.331 -				/* Max # of outstanding split transactions */
   6.332 -#define  PCI_X_CMD_SPLIT_1	0x0000	/* Max 1 */
   6.333 -#define  PCI_X_CMD_SPLIT_2	0x0010	/* Max 2 */
   6.334 -#define  PCI_X_CMD_SPLIT_3	0x0020	/* Max 3 */
   6.335 -#define  PCI_X_CMD_SPLIT_4	0x0030	/* Max 4 */
   6.336 -#define  PCI_X_CMD_SPLIT_8	0x0040	/* Max 8 */
   6.337 -#define  PCI_X_CMD_SPLIT_12	0x0050	/* Max 12 */
   6.338 -#define  PCI_X_CMD_SPLIT_16	0x0060	/* Max 16 */
   6.339 -#define  PCI_X_CMD_SPLIT_32	0x0070	/* Max 32 */
   6.340 -#define  PCI_X_CMD_MAX_SPLIT	0x0070	/* Max Outstanding Split Transactions */
   6.341 -#define  PCI_X_CMD_VERSION(x) 	(((x) >> 12) & 3) /* Version */
   6.342 -#define PCI_X_STATUS		4	/* PCI-X capabilities */
   6.343 -#define  PCI_X_STATUS_DEVFN	0x000000ff	/* A copy of devfn */
   6.344 -#define  PCI_X_STATUS_BUS	0x0000ff00	/* A copy of bus nr */
   6.345 -#define  PCI_X_STATUS_64BIT	0x00010000	/* 64-bit device */
   6.346 -#define  PCI_X_STATUS_133MHZ	0x00020000	/* 133 MHz capable */
   6.347 -#define  PCI_X_STATUS_SPL_DISC	0x00040000	/* Split Completion Discarded */
   6.348 -#define  PCI_X_STATUS_UNX_SPL	0x00080000	/* Unexpected Split Completion */
   6.349 -#define  PCI_X_STATUS_COMPLEX	0x00100000	/* Device Complexity */
   6.350 -#define  PCI_X_STATUS_MAX_READ	0x00600000	/* Designed Max Memory Read Count */
   6.351 -#define  PCI_X_STATUS_MAX_SPLIT	0x03800000	/* Designed Max Outstanding Split Transactions */
   6.352 -#define  PCI_X_STATUS_MAX_CUM	0x1c000000	/* Designed Max Cumulative Read Size */
   6.353 -#define  PCI_X_STATUS_SPL_ERR	0x20000000	/* Rcvd Split Completion Error Msg */
   6.354 -#define  PCI_X_STATUS_266MHZ	0x40000000	/* 266 MHz capable */
   6.355 -#define  PCI_X_STATUS_533MHZ	0x80000000	/* 533 MHz capable */
   6.356 -
   6.357 -/* PCI Express capability registers */
   6.358 -
   6.359 -#define PCI_EXP_FLAGS		2	/* Capabilities register */
   6.360 -#define PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
   6.361 -#define PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
   6.362 -#define  PCI_EXP_TYPE_ENDPOINT	0x0	/* Express Endpoint */
   6.363 -#define  PCI_EXP_TYPE_LEG_END	0x1	/* Legacy Endpoint */
   6.364 -#define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
   6.365 -#define  PCI_EXP_TYPE_UPSTREAM	0x5	/* Upstream Port */
   6.366 -#define  PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
   6.367 -#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCI/PCI-X Bridge */
   6.368 -#define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
   6.369 -#define PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
   6.370 -#define PCI_EXP_DEVCAP		4	/* Device capabilities */
   6.371 -#define  PCI_EXP_DEVCAP_PAYLOAD	0x07	/* Max_Payload_Size */
   6.372 -#define  PCI_EXP_DEVCAP_PHANTOM	0x18	/* Phantom functions */
   6.373 -#define  PCI_EXP_DEVCAP_EXT_TAG	0x20	/* Extended tags */
   6.374 -#define  PCI_EXP_DEVCAP_L0S	0x1c0	/* L0s Acceptable Latency */
   6.375 -#define  PCI_EXP_DEVCAP_L1	0xe00	/* L1 Acceptable Latency */
   6.376 -#define  PCI_EXP_DEVCAP_ATN_BUT	0x1000	/* Attention Button Present */
   6.377 -#define  PCI_EXP_DEVCAP_ATN_IND	0x2000	/* Attention Indicator Present */
   6.378 -#define  PCI_EXP_DEVCAP_PWR_IND	0x4000	/* Power Indicator Present */
   6.379 -#define  PCI_EXP_DEVCAP_PWR_VAL	0x3fc0000 /* Slot Power Limit Value */
   6.380 -#define  PCI_EXP_DEVCAP_PWR_SCL	0xc000000 /* Slot Power Limit Scale */
   6.381 -#define PCI_EXP_DEVCTL		8	/* Device Control */
   6.382 -#define  PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Error Reporting En. */
   6.383 -#define  PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Error Reporting Enable */
   6.384 -#define  PCI_EXP_DEVCTL_FERE	0x0004	/* Fatal Error Reporting Enable */
   6.385 -#define  PCI_EXP_DEVCTL_URRE	0x0008	/* Unsupported Request Reporting En. */
   6.386 -#define  PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
   6.387 -#define  PCI_EXP_DEVCTL_PAYLOAD	0x00e0	/* Max_Payload_Size */
   6.388 -#define  PCI_EXP_DEVCTL_EXT_TAG	0x0100	/* Extended Tag Field Enable */
   6.389 -#define  PCI_EXP_DEVCTL_PHANTOM	0x0200	/* Phantom Functions Enable */
   6.390 -#define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
   6.391 -#define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
   6.392 -#define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
   6.393 -#define PCI_EXP_DEVSTA		10	/* Device Status */
   6.394 -#define  PCI_EXP_DEVSTA_CED	0x01	/* Correctable Error Detected */
   6.395 -#define  PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
   6.396 -#define  PCI_EXP_DEVSTA_FED	0x04	/* Fatal Error Detected */
   6.397 -#define  PCI_EXP_DEVSTA_URD	0x08	/* Unsupported Request Detected */
   6.398 -#define  PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
   6.399 -#define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
   6.400 -#define PCI_EXP_LNKCAP		12	/* Link Capabilities */
   6.401 -#define PCI_EXP_LNKCTL		16	/* Link Control */
   6.402 -#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x100	/* Enable clkreq */
   6.403 -#define PCI_EXP_LNKSTA		18	/* Link Status */
   6.404 -#define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
   6.405 -#define PCI_EXP_SLTCTL		24	/* Slot Control */
   6.406 -#define PCI_EXP_SLTSTA		26	/* Slot Status */
   6.407 -#define PCI_EXP_RTCTL		28	/* Root Control */
   6.408 -#define  PCI_EXP_RTCTL_SECEE	0x01	/* System Error on Correctable Error */
   6.409 -#define  PCI_EXP_RTCTL_SENFEE	0x02	/* System Error on Non-Fatal Error */
   6.410 -#define  PCI_EXP_RTCTL_SEFEE	0x04	/* System Error on Fatal Error */
   6.411 -#define  PCI_EXP_RTCTL_PMEIE	0x08	/* PME Interrupt Enable */
   6.412 -#define  PCI_EXP_RTCTL_CRSSVE	0x10	/* CRS Software Visibility Enable */
   6.413 -#define PCI_EXP_RTCAP		30	/* Root Capabilities */
   6.414 -#define PCI_EXP_RTSTA		32	/* Root Status */
   6.415 -
   6.416 -/* Extended Capabilities (PCI-X 2.0 and Express) */
   6.417 -#define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)
   6.418 -#define PCI_EXT_CAP_VER(header)		((header >> 16) & 0xf)
   6.419 -#define PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
   6.420 -
   6.421 -#define PCI_EXT_CAP_ID_ERR	1
   6.422 -#define PCI_EXT_CAP_ID_VC	2
   6.423 -#define PCI_EXT_CAP_ID_DSN	3
   6.424 -#define PCI_EXT_CAP_ID_PWR	4
   6.425 -
   6.426 -/* Advanced Error Reporting */
   6.427 -#define PCI_ERR_UNCOR_STATUS	4	/* Uncorrectable Error Status */
   6.428 -#define  PCI_ERR_UNC_TRAIN	0x00000001	/* Training */
   6.429 -#define  PCI_ERR_UNC_DLP	0x00000010	/* Data Link Protocol */
   6.430 -#define  PCI_ERR_UNC_POISON_TLP	0x00001000	/* Poisoned TLP */
   6.431 -#define  PCI_ERR_UNC_FCP	0x00002000	/* Flow Control Protocol */
   6.432 -#define  PCI_ERR_UNC_COMP_TIME	0x00004000	/* Completion Timeout */
   6.433 -#define  PCI_ERR_UNC_COMP_ABORT	0x00008000	/* Completer Abort */
   6.434 -#define  PCI_ERR_UNC_UNX_COMP	0x00010000	/* Unexpected Completion */
   6.435 -#define  PCI_ERR_UNC_RX_OVER	0x00020000	/* Receiver Overflow */
   6.436 -#define  PCI_ERR_UNC_MALF_TLP	0x00040000	/* Malformed TLP */
   6.437 -#define  PCI_ERR_UNC_ECRC	0x00080000	/* ECRC Error Status */
   6.438 -#define  PCI_ERR_UNC_UNSUP	0x00100000	/* Unsupported Request */
   6.439 -#define PCI_ERR_UNCOR_MASK	8	/* Uncorrectable Error Mask */
   6.440 -	/* Same bits as above */
   6.441 -#define PCI_ERR_UNCOR_SEVER	12	/* Uncorrectable Error Severity */
   6.442 -	/* Same bits as above */
   6.443 -#define PCI_ERR_COR_STATUS	16	/* Correctable Error Status */
   6.444 -#define  PCI_ERR_COR_RCVR	0x00000001	/* Receiver Error Status */
   6.445 -#define  PCI_ERR_COR_BAD_TLP	0x00000040	/* Bad TLP Status */
   6.446 -#define  PCI_ERR_COR_BAD_DLLP	0x00000080	/* Bad DLLP Status */
   6.447 -#define  PCI_ERR_COR_REP_ROLL	0x00000100	/* REPLAY_NUM Rollover */
   6.448 -#define  PCI_ERR_COR_REP_TIMER	0x00001000	/* Replay Timer Timeout */
   6.449 -#define PCI_ERR_COR_MASK	20	/* Correctable Error Mask */
   6.450 -	/* Same bits as above */
   6.451 -#define PCI_ERR_CAP		24	/* Advanced Error Capabilities */
   6.452 -#define  PCI_ERR_CAP_FEP(x)	((x) & 31)	/* First Error Pointer */
   6.453 -#define  PCI_ERR_CAP_ECRC_GENC	0x00000020	/* ECRC Generation Capable */
   6.454 -#define  PCI_ERR_CAP_ECRC_GENE	0x00000040	/* ECRC Generation Enable */
   6.455 -#define  PCI_ERR_CAP_ECRC_CHKC	0x00000080	/* ECRC Check Capable */
   6.456 -#define  PCI_ERR_CAP_ECRC_CHKE	0x00000100	/* ECRC Check Enable */
   6.457 -#define PCI_ERR_HEADER_LOG	28	/* Header Log Register (16 bytes) */
   6.458 -#define PCI_ERR_ROOT_COMMAND	44	/* Root Error Command */
   6.459 -/* Correctable Err Reporting Enable */
   6.460 -#define PCI_ERR_ROOT_CMD_COR_EN		0x00000001
   6.461 -/* Non-fatal Err Reporting Enable */
   6.462 -#define PCI_ERR_ROOT_CMD_NONFATAL_EN	0x00000002
   6.463 -/* Fatal Err Reporting Enable */
   6.464 -#define PCI_ERR_ROOT_CMD_FATAL_EN	0x00000004
   6.465 -#define PCI_ERR_ROOT_STATUS	48
   6.466 -#define PCI_ERR_ROOT_COR_RCV		0x00000001	/* ERR_COR Received */
   6.467 -/* Multi ERR_COR Received */
   6.468 -#define PCI_ERR_ROOT_MULTI_COR_RCV	0x00000002
   6.469 -/* ERR_FATAL/NONFATAL Recevied */
   6.470 -#define PCI_ERR_ROOT_UNCOR_RCV		0x00000004
   6.471 -/* Multi ERR_FATAL/NONFATAL Recevied */
   6.472 -#define PCI_ERR_ROOT_MULTI_UNCOR_RCV	0x00000008
   6.473 -#define PCI_ERR_ROOT_FIRST_FATAL	0x00000010	/* First Fatal */
   6.474 -#define PCI_ERR_ROOT_NONFATAL_RCV	0x00000020	/* Non-Fatal Received */
   6.475 -#define PCI_ERR_ROOT_FATAL_RCV		0x00000040	/* Fatal Received */
   6.476 -#define PCI_ERR_ROOT_COR_SRC	52
   6.477 -#define PCI_ERR_ROOT_SRC	54
   6.478 -
   6.479 -/* Virtual Channel */
   6.480 -#define PCI_VC_PORT_REG1	4
   6.481 -#define PCI_VC_PORT_REG2	8
   6.482 -#define PCI_VC_PORT_CTRL	12
   6.483 -#define PCI_VC_PORT_STATUS	14
   6.484 -#define PCI_VC_RES_CAP		16
   6.485 -#define PCI_VC_RES_CTRL		20
   6.486 -#define PCI_VC_RES_STATUS	26
   6.487 -
   6.488 -/* Power Budgeting */
   6.489 -#define PCI_PWR_DSR		4	/* Data Select Register */
   6.490 -#define PCI_PWR_DATA		8	/* Data Register */
   6.491 -#define  PCI_PWR_DATA_BASE(x)	((x) & 0xff)	    /* Base Power */
   6.492 -#define  PCI_PWR_DATA_SCALE(x)	(((x) >> 8) & 3)    /* Data Scale */
   6.493 -#define  PCI_PWR_DATA_PM_SUB(x)	(((x) >> 10) & 7)   /* PM Sub State */
   6.494 -#define  PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
   6.495 -#define  PCI_PWR_DATA_TYPE(x)	(((x) >> 15) & 7)   /* Type */
   6.496 -#define  PCI_PWR_DATA_RAIL(x)	(((x) >> 18) & 7)   /* Power Rail */
   6.497 -#define PCI_PWR_CAP		12	/* Capability */
   6.498 -#define  PCI_PWR_CAP_BUDGET(x)	((x) & 1)	/* Included in system budget */
   6.499 -
   6.500 -/*
   6.501 - * Hypertransport sub capability types
   6.502 - *
   6.503 - * Unfortunately there are both 3 bit and 5 bit capability types defined
   6.504 - * in the HT spec, catering for that is a little messy. You probably don't
   6.505 - * want to use these directly, just use pci_find_ht_capability() and it
   6.506 - * will do the right thing for you.
   6.507 - */
   6.508 -#define HT_3BIT_CAP_MASK	0xE0
   6.509 -#define HT_CAPTYPE_SLAVE	0x00	/* Slave/Primary link configuration */
   6.510 -#define HT_CAPTYPE_HOST		0x20	/* Host/Secondary link configuration */
   6.511 -
   6.512 -#define HT_5BIT_CAP_MASK	0xF8
   6.513 -#define HT_CAPTYPE_IRQ		0x80	/* IRQ Configuration */
   6.514 -#define HT_CAPTYPE_REMAPPING_40	0xA0	/* 40 bit address remapping */
   6.515 -#define HT_CAPTYPE_REMAPPING_64 0xA2	/* 64 bit address remapping */
   6.516 -#define HT_CAPTYPE_UNITID_CLUMP	0x90	/* Unit ID clumping */
   6.517 -#define HT_CAPTYPE_EXTCONF	0x98	/* Extended Configuration Space Access */
   6.518 -#define HT_CAPTYPE_MSI_MAPPING	0xA8	/* MSI Mapping Capability */
   6.519 -#define  HT_MSI_FLAGS		0x02		/* Offset to flags */
   6.520 -#define  HT_MSI_FLAGS_ENABLE	0x1		/* Mapping enable */
   6.521 -#define  HT_MSI_FLAGS_FIXED	0x2		/* Fixed mapping only */
   6.522 -#define  HT_MSI_FIXED_ADDR	0x00000000FEE00000ULL	/* Fixed addr */
   6.523 -#define  HT_MSI_ADDR_LO		0x04		/* Offset to low addr bits */
   6.524 -#define  HT_MSI_ADDR_LO_MASK	0xFFF00000	/* Low address bit mask */
   6.525 -#define  HT_MSI_ADDR_HI		0x08		/* Offset to high addr bits */
   6.526 -#define HT_CAPTYPE_DIRECT_ROUTE	0xB0	/* Direct routing configuration */
   6.527 -#define HT_CAPTYPE_VCSET	0xB8	/* Virtual Channel configuration */
   6.528 -#define HT_CAPTYPE_ERROR_RETRY	0xC0	/* Retry on error configuration */
   6.529 -#define HT_CAPTYPE_GEN3		0xD0	/* Generation 3 hypertransport configuration */
   6.530 -#define HT_CAPTYPE_PM		0xE0	/* Hypertransport powermanagement configuration */
   6.531 -
   6.532 -
   6.533 -#endif /* LINUX_PCI_REGS_H */
     7.1 --- a/xen/drivers/passthrough/vtd/dmar.c	Thu May 01 10:00:00 2008 +0100
     7.2 +++ b/xen/drivers/passthrough/vtd/dmar.c	Thu May 01 10:26:58 2008 +0100
     7.3 @@ -26,9 +26,9 @@
     7.4  #include <xen/mm.h>
     7.5  #include <xen/xmalloc.h>
     7.6  #include <xen/pci.h>
     7.7 +#include <xen/pci_regs.h>
     7.8  #include <asm/string.h>
     7.9  #include "dmar.h"
    7.10 -#include "../pci_regs.h"
    7.11  
    7.12  int vtd_enabled = 1;
    7.13  
     8.1 --- a/xen/drivers/passthrough/vtd/intremap.c	Thu May 01 10:00:00 2008 +0100
     8.2 +++ b/xen/drivers/passthrough/vtd/intremap.c	Thu May 01 10:26:58 2008 +0100
     8.3 @@ -23,10 +23,10 @@
     8.4  #include <xen/iommu.h>
     8.5  #include <xen/time.h>
     8.6  #include <xen/pci.h>
     8.7 +#include <xen/pci_regs.h>
     8.8  #include "iommu.h"
     8.9  #include "dmar.h"
    8.10  #include "vtd.h"
    8.11 -#include "../pci_regs.h"
    8.12  #include "msi.h"
    8.13  #include "extern.h"
    8.14  
     9.1 --- a/xen/drivers/passthrough/vtd/iommu.c	Thu May 01 10:00:00 2008 +0100
     9.2 +++ b/xen/drivers/passthrough/vtd/iommu.c	Thu May 01 10:26:58 2008 +0100
     9.3 @@ -27,10 +27,10 @@
     9.4  #include <xen/numa.h>
     9.5  #include <xen/time.h>
     9.6  #include <xen/pci.h>
     9.7 +#include <xen/pci_regs.h>
     9.8  #include <asm/paging.h>
     9.9  #include "iommu.h"
    9.10  #include "dmar.h"
    9.11 -#include "../pci_regs.h"
    9.12  #include "msi.h"
    9.13  #include "extern.h"
    9.14  #include "vtd.h"
    9.15 @@ -1182,31 +1182,6 @@ static int domain_context_mapping_one(
    9.16      return 0;
    9.17  }
    9.18  
    9.19 -static int __pci_find_next_cap(u8 bus, unsigned int devfn, u8 pos, int cap)
    9.20 -{
    9.21 -    u8 id;
    9.22 -    int ttl = 48;
    9.23 -
    9.24 -    while ( ttl-- )
    9.25 -    {
    9.26 -        pos = pci_conf_read8(bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos);
    9.27 -        if ( pos < 0x40 )
    9.28 -            break;
    9.29 -
    9.30 -        pos &= ~3;
    9.31 -        id = pci_conf_read8(bus, PCI_SLOT(devfn), PCI_FUNC(devfn),
    9.32 -                            pos + PCI_CAP_LIST_ID);
    9.33 -
    9.34 -        if ( id == 0xff )
    9.35 -            break;
    9.36 -        if ( id == cap )
    9.37 -            return pos;
    9.38 -
    9.39 -        pos += PCI_CAP_LIST_NEXT;
    9.40 -    }
    9.41 -    return 0;
    9.42 -}
    9.43 -
    9.44  #define PCI_BASE_CLASS_BRIDGE    0x06
    9.45  #define PCI_CLASS_BRIDGE_PCI     0x0604
    9.46  
    9.47 @@ -1230,7 +1205,7 @@ int pdev_type(struct pci_dev *dev)
    9.48      if ( !(status & PCI_STATUS_CAP_LIST) )
    9.49          return DEV_TYPE_PCI;
    9.50  
    9.51 -    if ( __pci_find_next_cap(dev->bus, dev->devfn,
    9.52 +    if ( pci_find_next_cap(dev->bus, dev->devfn,
    9.53                              PCI_CAPABILITY_LIST, PCI_CAP_ID_EXP) )
    9.54          return DEV_TYPE_PCIe_ENDPOINT;
    9.55  
    10.1 --- a/xen/drivers/passthrough/vtd/qinval.c	Thu May 01 10:00:00 2008 +0100
    10.2 +++ b/xen/drivers/passthrough/vtd/qinval.c	Thu May 01 10:26:58 2008 +0100
    10.3 @@ -23,10 +23,10 @@
    10.4  #include <xen/iommu.h>
    10.5  #include <xen/time.h>
    10.6  #include <xen/pci.h>
    10.7 +#include <xen/pci_regs.h>
    10.8  #include "iommu.h"
    10.9  #include "dmar.h"
   10.10  #include "vtd.h"
   10.11 -#include "../pci_regs.h"
   10.12  #include "msi.h"
   10.13  #include "extern.h"
   10.14  
    11.1 --- a/xen/drivers/passthrough/vtd/utils.c	Thu May 01 10:00:00 2008 +0100
    11.2 +++ b/xen/drivers/passthrough/vtd/utils.c	Thu May 01 10:26:58 2008 +0100
    11.3 @@ -22,9 +22,9 @@
    11.4  #include <xen/iommu.h>
    11.5  #include <xen/time.h>
    11.6  #include <xen/pci.h>
    11.7 +#include <xen/pci_regs.h>
    11.8  #include "iommu.h"
    11.9  #include "dmar.h"
   11.10 -#include "../pci_regs.h"
   11.11  #include "msi.h"
   11.12  #include "vtd.h"
   11.13  
   11.14 @@ -96,37 +96,6 @@ void disable_pmr(struct iommu *iommu)
   11.15              "Disabled protected memory registers\n");
   11.16  }
   11.17  
   11.18 -static u8 find_cap_offset(u8 bus, u8 dev, u8 func, u8 cap)
   11.19 -{
   11.20 -    u8 id;
   11.21 -    int max_cap = 48;
   11.22 -    u8 pos = PCI_CAPABILITY_LIST;
   11.23 -    u16 status;
   11.24 -
   11.25 -    status = pci_conf_read16(bus, dev, func, PCI_STATUS);
   11.26 -    if ( (status & PCI_STATUS_CAP_LIST) == 0 )
   11.27 -        return 0;
   11.28 -
   11.29 -    while ( max_cap-- )
   11.30 -    {
   11.31 -        pos = pci_conf_read8(bus, dev, func, pos);
   11.32 -        if ( pos < 0x40 )
   11.33 -            break;
   11.34 -
   11.35 -        pos &= ~3;
   11.36 -        id = pci_conf_read8(bus, dev, func, pos + PCI_CAP_LIST_ID);
   11.37 -
   11.38 -        if ( id == 0xff )
   11.39 -            break;
   11.40 -        else if ( id == cap )
   11.41 -            return pos;
   11.42 -
   11.43 -        pos += PCI_CAP_LIST_NEXT;
   11.44 -    }
   11.45 -
   11.46 -    return 0;
   11.47 -}
   11.48 -
   11.49  #define PCI_D3hot   (3)
   11.50  #define PCI_CONFIG_DWORD_SIZE   (64)
   11.51  #define PCI_EXP_DEVCAP_FLR      (1 << 28)
   11.52 @@ -140,7 +109,7 @@ void pdev_flr(u8 bus, u8 devfn)
   11.53      u8 dev = PCI_SLOT(devfn);
   11.54      u8 func = PCI_FUNC(devfn);
   11.55  
   11.56 -    pos = find_cap_offset(bus, dev, func, PCI_CAP_ID_EXP);
   11.57 +    pos = pci_find_cap_offset(bus, dev, func, PCI_CAP_ID_EXP);
   11.58      if ( pos != 0 )
   11.59      {
   11.60          dev_cap = pci_conf_read32(bus, dev, func, pos + PCI_EXP_DEVCAP);
   11.61 @@ -163,7 +132,7 @@ void pdev_flr(u8 bus, u8 devfn)
   11.62       */
   11.63      if ( flr == 0 )
   11.64      {
   11.65 -        pos = find_cap_offset(bus, dev, func, PCI_CAP_ID_PM);
   11.66 +        pos = pci_find_cap_offset(bus, dev, func, PCI_CAP_ID_PM);
   11.67          if ( pos != 0 )
   11.68          {
   11.69              int i;
    12.1 --- a/xen/include/xen/iommu.h	Thu May 01 10:00:00 2008 +0100
    12.2 +++ b/xen/include/xen/iommu.h	Thu May 01 10:26:58 2008 +0100
    12.3 @@ -21,7 +21,7 @@
    12.4  #define _IOMMU_H_
    12.5  
    12.6  #include <xen/init.h>
    12.7 -#include <xen/list.h>
    12.8 +#include <xen/pci.h>
    12.9  #include <xen/spinlock.h>
   12.10  #include <public/hvm/ioreq.h>
   12.11  #include <public/domctl.h>
   12.12 @@ -39,25 +39,6 @@ extern int iommu_enabled;
   12.13  #define PAGE_MASK_4K        (((u64)-1) << PAGE_SHIFT_4K)
   12.14  #define PAGE_ALIGN_4K(addr) (((addr) + PAGE_SIZE_4K - 1) & PAGE_MASK_4K)
   12.15  
   12.16 -/*
   12.17 - * The PCI interface treats multi-function devices as independent
   12.18 - * devices.  The slot/function address of each device is encoded
   12.19 - * in a single byte as follows:
   12.20 - *
   12.21 - * 15:8 = bus
   12.22 - *  7:3 = slot
   12.23 - *  2:0 = function
   12.24 - */
   12.25 -#define PCI_DEVFN(slot,func)  (((slot & 0x1f) << 3) | (func & 0x07))
   12.26 -#define PCI_SLOT(devfn)       (((devfn) >> 3) & 0x1f)
   12.27 -#define PCI_FUNC(devfn)       ((devfn) & 0x07)
   12.28 -
   12.29 -struct pci_dev {
   12.30 -    struct list_head list;
   12.31 -    u8 bus;
   12.32 -    u8 devfn;
   12.33 -};
   12.34 -
   12.35  struct iommu {
   12.36      struct list_head list;
   12.37      void __iomem *reg; /* Pointer to hardware regs, virtual addr */
    13.1 --- a/xen/include/xen/pci.h	Thu May 01 10:00:00 2008 +0100
    13.2 +++ b/xen/include/xen/pci.h	Thu May 01 10:26:58 2008 +0100
    13.3 @@ -9,6 +9,26 @@
    13.4  
    13.5  #include <xen/config.h>
    13.6  #include <xen/types.h>
    13.7 +#include <xen/list.h>
    13.8 +
    13.9 +/*
   13.10 + * The PCI interface treats multi-function devices as independent
   13.11 + * devices.  The slot/function address of each device is encoded
   13.12 + * in a single byte as follows:
   13.13 + *
   13.14 + * 15:8 = bus
   13.15 + *  7:3 = slot
   13.16 + *  2:0 = function
   13.17 + */
   13.18 +#define PCI_DEVFN(slot,func)  (((slot & 0x1f) << 3) | (func & 0x07))
   13.19 +#define PCI_SLOT(devfn)       (((devfn) >> 3) & 0x1f)
   13.20 +#define PCI_FUNC(devfn)       ((devfn) & 0x07)
   13.21 +
   13.22 +struct pci_dev {
   13.23 +    struct list_head list;
   13.24 +    u8 bus;
   13.25 +    u8 devfn;
   13.26 +};
   13.27  
   13.28  uint8_t pci_conf_read8(
   13.29      unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg);
   13.30 @@ -25,5 +45,7 @@ void pci_conf_write16(
   13.31  void pci_conf_write32(
   13.32      unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg,
   13.33      uint32_t data);
   13.34 +int pci_find_cap_offset(u8 bus, u8 dev, u8 func, u8 cap);
   13.35 +int pci_find_next_cap(u8 bus, unsigned int devfn, u8 pos, int cap);
   13.36  
   13.37  #endif /* __XEN_PCI_H__ */
    14.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.2 +++ b/xen/include/xen/pci_regs.h	Thu May 01 10:26:58 2008 +0100
    14.3 @@ -0,0 +1,530 @@
    14.4 +/*
    14.5 + *	pci_regs.h
    14.6 + *
    14.7 + *	PCI standard defines
    14.8 + *	Copyright 1994, Drew Eckhardt
    14.9 + *	Copyright 1997--1999 Martin Mares <mj@ucw.cz>
   14.10 + *
   14.11 + *	For more information, please consult the following manuals (look at
   14.12 + *	http://www.pcisig.com/ for how to get them):
   14.13 + *
   14.14 + *	PCI BIOS Specification
   14.15 + *	PCI Local Bus Specification
   14.16 + *	PCI to PCI Bridge Specification
   14.17 + *	PCI System Design Guide
   14.18 + *
   14.19 + * 	For hypertransport information, please consult the following manuals
   14.20 + * 	from http://www.hypertransport.org
   14.21 + *
   14.22 + *	The Hypertransport I/O Link Specification
   14.23 + */
   14.24 +
   14.25 +#ifndef LINUX_PCI_REGS_H
   14.26 +#define LINUX_PCI_REGS_H
   14.27 +
   14.28 +/*
   14.29 + * Under PCI, each device has 256 bytes of configuration address space,
   14.30 + * of which the first 64 bytes are standardized as follows:
   14.31 + */
   14.32 +#define PCI_VENDOR_ID		0x00	/* 16 bits */
   14.33 +#define PCI_DEVICE_ID		0x02	/* 16 bits */
   14.34 +#define PCI_COMMAND		0x04	/* 16 bits */
   14.35 +#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
   14.36 +#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
   14.37 +#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
   14.38 +#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
   14.39 +#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
   14.40 +#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
   14.41 +#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
   14.42 +#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
   14.43 +#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
   14.44 +#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
   14.45 +#define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
   14.46 +
   14.47 +#define PCI_STATUS		0x06	/* 16 bits */
   14.48 +#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
   14.49 +#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
   14.50 +#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
   14.51 +#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
   14.52 +#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
   14.53 +#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
   14.54 +#define  PCI_STATUS_DEVSEL_FAST		0x000
   14.55 +#define  PCI_STATUS_DEVSEL_MEDIUM	0x200
   14.56 +#define  PCI_STATUS_DEVSEL_SLOW		0x400
   14.57 +#define  PCI_STATUS_SIG_TARGET_ABORT	0x800 /* Set on target abort */
   14.58 +#define  PCI_STATUS_REC_TARGET_ABORT	0x1000 /* Master ack of " */
   14.59 +#define  PCI_STATUS_REC_MASTER_ABORT	0x2000 /* Set on master abort */
   14.60 +#define  PCI_STATUS_SIG_SYSTEM_ERROR	0x4000 /* Set when we drive SERR */
   14.61 +#define  PCI_STATUS_DETECTED_PARITY	0x8000 /* Set on parity error */
   14.62 +
   14.63 +#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8 revision */
   14.64 +#define PCI_REVISION_ID		0x08	/* Revision ID */
   14.65 +#define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
   14.66 +#define PCI_CLASS_DEVICE	0x0a	/* Device class */
   14.67 +
   14.68 +#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
   14.69 +#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
   14.70 +#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
   14.71 +#define  PCI_HEADER_TYPE_NORMAL		0
   14.72 +#define  PCI_HEADER_TYPE_BRIDGE		1
   14.73 +#define  PCI_HEADER_TYPE_CARDBUS	2
   14.74 +
   14.75 +#define PCI_BIST		0x0f	/* 8 bits */
   14.76 +#define  PCI_BIST_CODE_MASK	0x0f	/* Return result */
   14.77 +#define  PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
   14.78 +#define  PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
   14.79 +
   14.80 +/*
   14.81 + * Base addresses specify locations in memory or I/O space.
   14.82 + * Decoded size can be determined by writing a value of
   14.83 + * 0xffffffff to the register, and reading it back.  Only
   14.84 + * 1 bits are decoded.
   14.85 + */
   14.86 +#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
   14.87 +#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
   14.88 +#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
   14.89 +#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
   14.90 +#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
   14.91 +#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
   14.92 +#define  PCI_BASE_ADDRESS_SPACE		0x01	/* 0 = memory, 1 = I/O */
   14.93 +#define  PCI_BASE_ADDRESS_SPACE_IO	0x01
   14.94 +#define  PCI_BASE_ADDRESS_SPACE_MEMORY	0x00
   14.95 +#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK	0x06
   14.96 +#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
   14.97 +#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
   14.98 +#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
   14.99 +#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
  14.100 +#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
  14.101 +#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
  14.102 +/* bit 1 is reserved if address_space = 1 */
  14.103 +
  14.104 +/* Header type 0 (normal devices) */
  14.105 +#define PCI_CARDBUS_CIS		0x28
  14.106 +#define PCI_SUBSYSTEM_VENDOR_ID	0x2c
  14.107 +#define PCI_SUBSYSTEM_ID	0x2e
  14.108 +#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
  14.109 +#define  PCI_ROM_ADDRESS_ENABLE	0x01
  14.110 +#define PCI_ROM_ADDRESS_MASK	(~0x7ffUL)
  14.111 +
  14.112 +#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
  14.113 +
  14.114 +/* 0x35-0x3b are reserved */
  14.115 +#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
  14.116 +#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
  14.117 +#define PCI_MIN_GNT		0x3e	/* 8 bits */
  14.118 +#define PCI_MAX_LAT		0x3f	/* 8 bits */
  14.119 +
  14.120 +/* Header type 1 (PCI-to-PCI bridges) */
  14.121 +#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
  14.122 +#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
  14.123 +#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
  14.124 +#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
  14.125 +#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
  14.126 +#define PCI_IO_LIMIT		0x1d
  14.127 +#define  PCI_IO_RANGE_TYPE_MASK	0x0fUL	/* I/O bridging type */
  14.128 +#define  PCI_IO_RANGE_TYPE_16	0x00
  14.129 +#define  PCI_IO_RANGE_TYPE_32	0x01
  14.130 +#define  PCI_IO_RANGE_MASK	(~0x0fUL)
  14.131 +#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
  14.132 +#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
  14.133 +#define PCI_MEMORY_LIMIT	0x22
  14.134 +#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
  14.135 +#define  PCI_MEMORY_RANGE_MASK	(~0x0fUL)
  14.136 +#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
  14.137 +#define PCI_PREF_MEMORY_LIMIT	0x26
  14.138 +#define  PCI_PREF_RANGE_TYPE_MASK 0x0fUL
  14.139 +#define  PCI_PREF_RANGE_TYPE_32	0x00
  14.140 +#define  PCI_PREF_RANGE_TYPE_64	0x01
  14.141 +#define  PCI_PREF_RANGE_MASK	(~0x0fUL)
  14.142 +#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
  14.143 +#define PCI_PREF_LIMIT_UPPER32	0x2c
  14.144 +#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
  14.145 +#define PCI_IO_LIMIT_UPPER16	0x32
  14.146 +/* 0x34 same as for htype 0 */
  14.147 +/* 0x35-0x3b is reserved */
  14.148 +#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
  14.149 +/* 0x3c-0x3d are same as for htype 0 */
  14.150 +#define PCI_BRIDGE_CONTROL	0x3e
  14.151 +#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
  14.152 +#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
  14.153 +#define  PCI_BRIDGE_CTL_ISA	0x04	/* Enable ISA mode */
  14.154 +#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
  14.155 +#define  PCI_BRIDGE_CTL_MASTER_ABORT	0x20  /* Report master aborts */
  14.156 +#define  PCI_BRIDGE_CTL_BUS_RESET	0x40	/* Secondary bus reset */
  14.157 +#define  PCI_BRIDGE_CTL_FAST_BACK	0x80	/* Fast Back2Back enabled on secondary interface */
  14.158 +
  14.159 +/* Header type 2 (CardBus bridges) */
  14.160 +#define PCI_CB_CAPABILITY_LIST	0x14
  14.161 +/* 0x15 reserved */
  14.162 +#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
  14.163 +#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
  14.164 +#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
  14.165 +#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
  14.166 +#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
  14.167 +#define PCI_CB_MEMORY_BASE_0	0x1c
  14.168 +#define PCI_CB_MEMORY_LIMIT_0	0x20
  14.169 +#define PCI_CB_MEMORY_BASE_1	0x24
  14.170 +#define PCI_CB_MEMORY_LIMIT_1	0x28
  14.171 +#define PCI_CB_IO_BASE_0	0x2c
  14.172 +#define PCI_CB_IO_BASE_0_HI	0x2e
  14.173 +#define PCI_CB_IO_LIMIT_0	0x30
  14.174 +#define PCI_CB_IO_LIMIT_0_HI	0x32
  14.175 +#define PCI_CB_IO_BASE_1	0x34
  14.176 +#define PCI_CB_IO_BASE_1_HI	0x36
  14.177 +#define PCI_CB_IO_LIMIT_1	0x38
  14.178 +#define PCI_CB_IO_LIMIT_1_HI	0x3a
  14.179 +#define  PCI_CB_IO_RANGE_MASK	(~0x03UL)
  14.180 +/* 0x3c-0x3d are same as for htype 0 */
  14.181 +#define PCI_CB_BRIDGE_CONTROL	0x3e
  14.182 +#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
  14.183 +#define  PCI_CB_BRIDGE_CTL_SERR		0x02
  14.184 +#define  PCI_CB_BRIDGE_CTL_ISA		0x04
  14.185 +#define  PCI_CB_BRIDGE_CTL_VGA		0x08
  14.186 +#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT	0x20
  14.187 +#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
  14.188 +#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
  14.189 +#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
  14.190 +#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
  14.191 +#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
  14.192 +#define PCI_CB_SUBSYSTEM_VENDOR_ID	0x40
  14.193 +#define PCI_CB_SUBSYSTEM_ID		0x42
  14.194 +#define PCI_CB_LEGACY_MODE_BASE		0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
  14.195 +/* 0x48-0x7f reserved */
  14.196 +
  14.197 +/* Capability lists */
  14.198 +
  14.199 +#define PCI_CAP_LIST_ID		0	/* Capability ID */
  14.200 +#define  PCI_CAP_ID_PM		0x01	/* Power Management */
  14.201 +#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
  14.202 +#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
  14.203 +#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
  14.204 +#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
  14.205 +#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
  14.206 +#define  PCI_CAP_ID_PCIX	0x07	/* PCI-X */
  14.207 +#define  PCI_CAP_ID_HT		0x08	/* HyperTransport */
  14.208 +#define  PCI_CAP_ID_VNDR	0x09	/* Vendor specific */
  14.209 +#define  PCI_CAP_ID_DBG		0x0A	/* Debug port */
  14.210 +#define  PCI_CAP_ID_CCRC	0x0B	/* CompactPCI Central Resource Control */
  14.211 +#define  PCI_CAP_ID_SHPC 	0x0C	/* PCI Standard Hot-Plug Controller */
  14.212 +#define  PCI_CAP_ID_SSVID	0x0D	/* Bridge subsystem vendor/device ID */
  14.213 +#define  PCI_CAP_ID_AGP3	0x0E	/* AGP Target PCI-PCI bridge */
  14.214 +#define  PCI_CAP_ID_EXP 	0x10	/* PCI Express */
  14.215 +#define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
  14.216 +#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
  14.217 +#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
  14.218 +#define PCI_CAP_SIZEOF		4
  14.219 +
  14.220 +/* Power Management Registers */
  14.221 +
  14.222 +#define PCI_PM_PMC		2	/* PM Capabilities Register */
  14.223 +#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
  14.224 +#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
  14.225 +#define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
  14.226 +#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
  14.227 +#define  PCI_PM_CAP_AUX_POWER	0x01C0	/* Auxilliary power support mask */
  14.228 +#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
  14.229 +#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
  14.230 +#define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
  14.231 +#define  PCI_PM_CAP_PME_MASK	0xF800	/* PME Mask of all supported states */
  14.232 +#define  PCI_PM_CAP_PME_D0	0x0800	/* PME# from D0 */
  14.233 +#define  PCI_PM_CAP_PME_D1	0x1000	/* PME# from D1 */
  14.234 +#define  PCI_PM_CAP_PME_D2	0x2000	/* PME# from D2 */
  14.235 +#define  PCI_PM_CAP_PME_D3	0x4000	/* PME# from D3 (hot) */
  14.236 +#define  PCI_PM_CAP_PME_D3cold	0x8000	/* PME# from D3 (cold) */
  14.237 +#define PCI_PM_CTRL		4	/* PM control and status register */
  14.238 +#define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
  14.239 +#define  PCI_PM_CTRL_NO_SOFT_RESET	0x0004	/* No reset for D3hot->D0 */
  14.240 +#define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
  14.241 +#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
  14.242 +#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
  14.243 +#define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
  14.244 +#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
  14.245 +#define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
  14.246 +#define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
  14.247 +#define PCI_PM_DATA_REGISTER	7	/* (??) */
  14.248 +#define PCI_PM_SIZEOF		8
  14.249 +
  14.250 +/* AGP registers */
  14.251 +
  14.252 +#define PCI_AGP_VERSION		2	/* BCD version number */
  14.253 +#define PCI_AGP_RFU		3	/* Rest of capability flags */
  14.254 +#define PCI_AGP_STATUS		4	/* Status register */
  14.255 +#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
  14.256 +#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
  14.257 +#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
  14.258 +#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
  14.259 +#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
  14.260 +#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
  14.261 +#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
  14.262 +#define PCI_AGP_COMMAND		8	/* Control register */
  14.263 +#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
  14.264 +#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
  14.265 +#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
  14.266 +#define  PCI_AGP_COMMAND_64BIT	0x0020 	/* Allow processing of 64-bit addresses */
  14.267 +#define  PCI_AGP_COMMAND_FW	0x0010 	/* Force FW transfers */
  14.268 +#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
  14.269 +#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 2x rate */
  14.270 +#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 1x rate */
  14.271 +#define PCI_AGP_SIZEOF		12
  14.272 +
  14.273 +/* Vital Product Data */
  14.274 +
  14.275 +#define PCI_VPD_ADDR		2	/* Address to access (15 bits!) */
  14.276 +#define  PCI_VPD_ADDR_MASK	0x7fff	/* Address mask */
  14.277 +#define  PCI_VPD_ADDR_F		0x8000	/* Write 0, 1 indicates completion */
  14.278 +#define PCI_VPD_DATA		4	/* 32-bits of data returned here */
  14.279 +
  14.280 +/* Slot Identification */
  14.281 +
  14.282 +#define PCI_SID_ESR		2	/* Expansion Slot Register */
  14.283 +#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
  14.284 +#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
  14.285 +#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
  14.286 +
  14.287 +/* Message Signalled Interrupts registers */
  14.288 +
  14.289 +#define PCI_MSI_FLAGS		2	/* Various flags */
  14.290 +#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
  14.291 +#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
  14.292 +#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
  14.293 +#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
  14.294 +#define  PCI_MSI_FLAGS_MASKBIT	0x100	/* 64-bit mask bits allowed */
  14.295 +#define PCI_MSI_RFU		3	/* Rest of capability flags */
  14.296 +#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
  14.297 +#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
  14.298 +#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
  14.299 +#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
  14.300 +#define PCI_MSI_MASK_BIT	16	/* Mask bits register */
  14.301 +
  14.302 +/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */
  14.303 +#define PCI_MSIX_FLAGS		2
  14.304 +#define  PCI_MSIX_FLAGS_QSIZE	0x7FF
  14.305 +#define  PCI_MSIX_FLAGS_ENABLE	(1 << 15)
  14.306 +#define  PCI_MSIX_FLAGS_MASKALL	(1 << 14)
  14.307 +#define PCI_MSIX_FLAGS_BIRMASK	(7 << 0)
  14.308 +#define PCI_MSIX_FLAGS_BITMASK	(1 << 0)
  14.309 +
  14.310 +/* CompactPCI Hotswap Register */
  14.311 +
  14.312 +#define PCI_CHSWP_CSR		2	/* Control and Status Register */
  14.313 +#define  PCI_CHSWP_DHA		0x01	/* Device Hiding Arm */
  14.314 +#define  PCI_CHSWP_EIM		0x02	/* ENUM# Signal Mask */
  14.315 +#define  PCI_CHSWP_PIE		0x04	/* Pending Insert or Extract */
  14.316 +#define  PCI_CHSWP_LOO		0x08	/* LED On / Off */
  14.317 +#define  PCI_CHSWP_PI		0x30	/* Programming Interface */
  14.318 +#define  PCI_CHSWP_EXT		0x40	/* ENUM# status - extraction */
  14.319 +#define  PCI_CHSWP_INS		0x80	/* ENUM# status - insertion */
  14.320 +
  14.321 +/* PCI-X registers */
  14.322 +
  14.323 +#define PCI_X_CMD		2	/* Modes & Features */
  14.324 +#define  PCI_X_CMD_DPERR_E	0x0001	/* Data Parity Error Recovery Enable */
  14.325 +#define  PCI_X_CMD_ERO		0x0002	/* Enable Relaxed Ordering */
  14.326 +#define  PCI_X_CMD_READ_512	0x0000	/* 512 byte maximum read byte count */
  14.327 +#define  PCI_X_CMD_READ_1K	0x0004	/* 1Kbyte maximum read byte count */
  14.328 +#define  PCI_X_CMD_READ_2K	0x0008	/* 2Kbyte maximum read byte count */
  14.329 +#define  PCI_X_CMD_READ_4K	0x000c	/* 4Kbyte maximum read byte count */
  14.330 +#define  PCI_X_CMD_MAX_READ	0x000c	/* Max Memory Read Byte Count */
  14.331 +				/* Max # of outstanding split transactions */
  14.332 +#define  PCI_X_CMD_SPLIT_1	0x0000	/* Max 1 */
  14.333 +#define  PCI_X_CMD_SPLIT_2	0x0010	/* Max 2 */
  14.334 +#define  PCI_X_CMD_SPLIT_3	0x0020	/* Max 3 */
  14.335 +#define  PCI_X_CMD_SPLIT_4	0x0030	/* Max 4 */
  14.336 +#define  PCI_X_CMD_SPLIT_8	0x0040	/* Max 8 */
  14.337 +#define  PCI_X_CMD_SPLIT_12	0x0050	/* Max 12 */
  14.338 +#define  PCI_X_CMD_SPLIT_16	0x0060	/* Max 16 */
  14.339 +#define  PCI_X_CMD_SPLIT_32	0x0070	/* Max 32 */
  14.340 +#define  PCI_X_CMD_MAX_SPLIT	0x0070	/* Max Outstanding Split Transactions */
  14.341 +#define  PCI_X_CMD_VERSION(x) 	(((x) >> 12) & 3) /* Version */
  14.342 +#define PCI_X_STATUS		4	/* PCI-X capabilities */
  14.343 +#define  PCI_X_STATUS_DEVFN	0x000000ff	/* A copy of devfn */
  14.344 +#define  PCI_X_STATUS_BUS	0x0000ff00	/* A copy of bus nr */
  14.345 +#define  PCI_X_STATUS_64BIT	0x00010000	/* 64-bit device */
  14.346 +#define  PCI_X_STATUS_133MHZ	0x00020000	/* 133 MHz capable */
  14.347 +#define  PCI_X_STATUS_SPL_DISC	0x00040000	/* Split Completion Discarded */
  14.348 +#define  PCI_X_STATUS_UNX_SPL	0x00080000	/* Unexpected Split Completion */
  14.349 +#define  PCI_X_STATUS_COMPLEX	0x00100000	/* Device Complexity */
  14.350 +#define  PCI_X_STATUS_MAX_READ	0x00600000	/* Designed Max Memory Read Count */
  14.351 +#define  PCI_X_STATUS_MAX_SPLIT	0x03800000	/* Designed Max Outstanding Split Transactions */
  14.352 +#define  PCI_X_STATUS_MAX_CUM	0x1c000000	/* Designed Max Cumulative Read Size */
  14.353 +#define  PCI_X_STATUS_SPL_ERR	0x20000000	/* Rcvd Split Completion Error Msg */
  14.354 +#define  PCI_X_STATUS_266MHZ	0x40000000	/* 266 MHz capable */
  14.355 +#define  PCI_X_STATUS_533MHZ	0x80000000	/* 533 MHz capable */
  14.356 +
  14.357 +/* PCI Express capability registers */
  14.358 +
  14.359 +#define PCI_EXP_FLAGS		2	/* Capabilities register */
  14.360 +#define PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
  14.361 +#define PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
  14.362 +#define  PCI_EXP_TYPE_ENDPOINT	0x0	/* Express Endpoint */
  14.363 +#define  PCI_EXP_TYPE_LEG_END	0x1	/* Legacy Endpoint */
  14.364 +#define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
  14.365 +#define  PCI_EXP_TYPE_UPSTREAM	0x5	/* Upstream Port */
  14.366 +#define  PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
  14.367 +#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCI/PCI-X Bridge */
  14.368 +#define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
  14.369 +#define PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
  14.370 +#define PCI_EXP_DEVCAP		4	/* Device capabilities */
  14.371 +#define  PCI_EXP_DEVCAP_PAYLOAD	0x07	/* Max_Payload_Size */
  14.372 +#define  PCI_EXP_DEVCAP_PHANTOM	0x18	/* Phantom functions */
  14.373 +#define  PCI_EXP_DEVCAP_EXT_TAG	0x20	/* Extended tags */
  14.374 +#define  PCI_EXP_DEVCAP_L0S	0x1c0	/* L0s Acceptable Latency */
  14.375 +#define  PCI_EXP_DEVCAP_L1	0xe00	/* L1 Acceptable Latency */
  14.376 +#define  PCI_EXP_DEVCAP_ATN_BUT	0x1000	/* Attention Button Present */
  14.377 +#define  PCI_EXP_DEVCAP_ATN_IND	0x2000	/* Attention Indicator Present */
  14.378 +#define  PCI_EXP_DEVCAP_PWR_IND	0x4000	/* Power Indicator Present */
  14.379 +#define  PCI_EXP_DEVCAP_PWR_VAL	0x3fc0000 /* Slot Power Limit Value */
  14.380 +#define  PCI_EXP_DEVCAP_PWR_SCL	0xc000000 /* Slot Power Limit Scale */
  14.381 +#define PCI_EXP_DEVCTL		8	/* Device Control */
  14.382 +#define  PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Error Reporting En. */
  14.383 +#define  PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Error Reporting Enable */
  14.384 +#define  PCI_EXP_DEVCTL_FERE	0x0004	/* Fatal Error Reporting Enable */
  14.385 +#define  PCI_EXP_DEVCTL_URRE	0x0008	/* Unsupported Request Reporting En. */
  14.386 +#define  PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
  14.387 +#define  PCI_EXP_DEVCTL_PAYLOAD	0x00e0	/* Max_Payload_Size */
  14.388 +#define  PCI_EXP_DEVCTL_EXT_TAG	0x0100	/* Extended Tag Field Enable */
  14.389 +#define  PCI_EXP_DEVCTL_PHANTOM	0x0200	/* Phantom Functions Enable */
  14.390 +#define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
  14.391 +#define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
  14.392 +#define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
  14.393 +#define PCI_EXP_DEVSTA		10	/* Device Status */
  14.394 +#define  PCI_EXP_DEVSTA_CED	0x01	/* Correctable Error Detected */
  14.395 +#define  PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
  14.396 +#define  PCI_EXP_DEVSTA_FED	0x04	/* Fatal Error Detected */
  14.397 +#define  PCI_EXP_DEVSTA_URD	0x08	/* Unsupported Request Detected */
  14.398 +#define  PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
  14.399 +#define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
  14.400 +#define PCI_EXP_LNKCAP		12	/* Link Capabilities */
  14.401 +#define PCI_EXP_LNKCTL		16	/* Link Control */
  14.402 +#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x100	/* Enable clkreq */
  14.403 +#define PCI_EXP_LNKSTA		18	/* Link Status */
  14.404 +#define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
  14.405 +#define PCI_EXP_SLTCTL		24	/* Slot Control */
  14.406 +#define PCI_EXP_SLTSTA		26	/* Slot Status */
  14.407 +#define PCI_EXP_RTCTL		28	/* Root Control */
  14.408 +#define  PCI_EXP_RTCTL_SECEE	0x01	/* System Error on Correctable Error */
  14.409 +#define  PCI_EXP_RTCTL_SENFEE	0x02	/* System Error on Non-Fatal Error */
  14.410 +#define  PCI_EXP_RTCTL_SEFEE	0x04	/* System Error on Fatal Error */
  14.411 +#define  PCI_EXP_RTCTL_PMEIE	0x08	/* PME Interrupt Enable */
  14.412 +#define  PCI_EXP_RTCTL_CRSSVE	0x10	/* CRS Software Visibility Enable */
  14.413 +#define PCI_EXP_RTCAP		30	/* Root Capabilities */
  14.414 +#define PCI_EXP_RTSTA		32	/* Root Status */
  14.415 +
  14.416 +/* Extended Capabilities (PCI-X 2.0 and Express) */
  14.417 +#define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)
  14.418 +#define PCI_EXT_CAP_VER(header)		((header >> 16) & 0xf)
  14.419 +#define PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
  14.420 +
  14.421 +#define PCI_EXT_CAP_ID_ERR	1
  14.422 +#define PCI_EXT_CAP_ID_VC	2
  14.423 +#define PCI_EXT_CAP_ID_DSN	3
  14.424 +#define PCI_EXT_CAP_ID_PWR	4
  14.425 +
  14.426 +/* Advanced Error Reporting */
  14.427 +#define PCI_ERR_UNCOR_STATUS	4	/* Uncorrectable Error Status */
  14.428 +#define  PCI_ERR_UNC_TRAIN	0x00000001	/* Training */
  14.429 +#define  PCI_ERR_UNC_DLP	0x00000010	/* Data Link Protocol */
  14.430 +#define  PCI_ERR_UNC_POISON_TLP	0x00001000	/* Poisoned TLP */
  14.431 +#define  PCI_ERR_UNC_FCP	0x00002000	/* Flow Control Protocol */
  14.432 +#define  PCI_ERR_UNC_COMP_TIME	0x00004000	/* Completion Timeout */
  14.433 +#define  PCI_ERR_UNC_COMP_ABORT	0x00008000	/* Completer Abort */
  14.434 +#define  PCI_ERR_UNC_UNX_COMP	0x00010000	/* Unexpected Completion */
  14.435 +#define  PCI_ERR_UNC_RX_OVER	0x00020000	/* Receiver Overflow */
  14.436 +#define  PCI_ERR_UNC_MALF_TLP	0x00040000	/* Malformed TLP */
  14.437 +#define  PCI_ERR_UNC_ECRC	0x00080000	/* ECRC Error Status */
  14.438 +#define  PCI_ERR_UNC_UNSUP	0x00100000	/* Unsupported Request */
  14.439 +#define PCI_ERR_UNCOR_MASK	8	/* Uncorrectable Error Mask */
  14.440 +	/* Same bits as above */
  14.441 +#define PCI_ERR_UNCOR_SEVER	12	/* Uncorrectable Error Severity */
  14.442 +	/* Same bits as above */
  14.443 +#define PCI_ERR_COR_STATUS	16	/* Correctable Error Status */
  14.444 +#define  PCI_ERR_COR_RCVR	0x00000001	/* Receiver Error Status */
  14.445 +#define  PCI_ERR_COR_BAD_TLP	0x00000040	/* Bad TLP Status */
  14.446 +#define  PCI_ERR_COR_BAD_DLLP	0x00000080	/* Bad DLLP Status */
  14.447 +#define  PCI_ERR_COR_REP_ROLL	0x00000100	/* REPLAY_NUM Rollover */
  14.448 +#define  PCI_ERR_COR_REP_TIMER	0x00001000	/* Replay Timer Timeout */
  14.449 +#define PCI_ERR_COR_MASK	20	/* Correctable Error Mask */
  14.450 +	/* Same bits as above */
  14.451 +#define PCI_ERR_CAP		24	/* Advanced Error Capabilities */
  14.452 +#define  PCI_ERR_CAP_FEP(x)	((x) & 31)	/* First Error Pointer */
  14.453 +#define  PCI_ERR_CAP_ECRC_GENC	0x00000020	/* ECRC Generation Capable */
  14.454 +#define  PCI_ERR_CAP_ECRC_GENE	0x00000040	/* ECRC Generation Enable */
  14.455 +#define  PCI_ERR_CAP_ECRC_CHKC	0x00000080	/* ECRC Check Capable */
  14.456 +#define  PCI_ERR_CAP_ECRC_CHKE	0x00000100	/* ECRC Check Enable */
  14.457 +#define PCI_ERR_HEADER_LOG	28	/* Header Log Register (16 bytes) */
  14.458 +#define PCI_ERR_ROOT_COMMAND	44	/* Root Error Command */
  14.459 +/* Correctable Err Reporting Enable */
  14.460 +#define PCI_ERR_ROOT_CMD_COR_EN		0x00000001
  14.461 +/* Non-fatal Err Reporting Enable */
  14.462 +#define PCI_ERR_ROOT_CMD_NONFATAL_EN	0x00000002
  14.463 +/* Fatal Err Reporting Enable */
  14.464 +#define PCI_ERR_ROOT_CMD_FATAL_EN	0x00000004
  14.465 +#define PCI_ERR_ROOT_STATUS	48
  14.466 +#define PCI_ERR_ROOT_COR_RCV		0x00000001	/* ERR_COR Received */
  14.467 +/* Multi ERR_COR Received */
  14.468 +#define PCI_ERR_ROOT_MULTI_COR_RCV	0x00000002
  14.469 +/* ERR_FATAL/NONFATAL Recevied */
  14.470 +#define PCI_ERR_ROOT_UNCOR_RCV		0x00000004
  14.471 +/* Multi ERR_FATAL/NONFATAL Recevied */
  14.472 +#define PCI_ERR_ROOT_MULTI_UNCOR_RCV	0x00000008
  14.473 +#define PCI_ERR_ROOT_FIRST_FATAL	0x00000010	/* First Fatal */
  14.474 +#define PCI_ERR_ROOT_NONFATAL_RCV	0x00000020	/* Non-Fatal Received */
  14.475 +#define PCI_ERR_ROOT_FATAL_RCV		0x00000040	/* Fatal Received */
  14.476 +#define PCI_ERR_ROOT_COR_SRC	52
  14.477 +#define PCI_ERR_ROOT_SRC	54
  14.478 +
  14.479 +/* Virtual Channel */
  14.480 +#define PCI_VC_PORT_REG1	4
  14.481 +#define PCI_VC_PORT_REG2	8
  14.482 +#define PCI_VC_PORT_CTRL	12
  14.483 +#define PCI_VC_PORT_STATUS	14
  14.484 +#define PCI_VC_RES_CAP		16
  14.485 +#define PCI_VC_RES_CTRL		20
  14.486 +#define PCI_VC_RES_STATUS	26
  14.487 +
  14.488 +/* Power Budgeting */
  14.489 +#define PCI_PWR_DSR		4	/* Data Select Register */
  14.490 +#define PCI_PWR_DATA		8	/* Data Register */
  14.491 +#define  PCI_PWR_DATA_BASE(x)	((x) & 0xff)	    /* Base Power */
  14.492 +#define  PCI_PWR_DATA_SCALE(x)	(((x) >> 8) & 3)    /* Data Scale */
  14.493 +#define  PCI_PWR_DATA_PM_SUB(x)	(((x) >> 10) & 7)   /* PM Sub State */
  14.494 +#define  PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
  14.495 +#define  PCI_PWR_DATA_TYPE(x)	(((x) >> 15) & 7)   /* Type */
  14.496 +#define  PCI_PWR_DATA_RAIL(x)	(((x) >> 18) & 7)   /* Power Rail */
  14.497 +#define PCI_PWR_CAP		12	/* Capability */
  14.498 +#define  PCI_PWR_CAP_BUDGET(x)	((x) & 1)	/* Included in system budget */
  14.499 +
  14.500 +/*
  14.501 + * Hypertransport sub capability types
  14.502 + *
  14.503 + * Unfortunately there are both 3 bit and 5 bit capability types defined
  14.504 + * in the HT spec, catering for that is a little messy. You probably don't
  14.505 + * want to use these directly, just use pci_find_ht_capability() and it
  14.506 + * will do the right thing for you.
  14.507 + */
  14.508 +#define HT_3BIT_CAP_MASK	0xE0
  14.509 +#define HT_CAPTYPE_SLAVE	0x00	/* Slave/Primary link configuration */
  14.510 +#define HT_CAPTYPE_HOST		0x20	/* Host/Secondary link configuration */
  14.511 +
  14.512 +#define HT_5BIT_CAP_MASK	0xF8
  14.513 +#define HT_CAPTYPE_IRQ		0x80	/* IRQ Configuration */
  14.514 +#define HT_CAPTYPE_REMAPPING_40	0xA0	/* 40 bit address remapping */
  14.515 +#define HT_CAPTYPE_REMAPPING_64 0xA2	/* 64 bit address remapping */
  14.516 +#define HT_CAPTYPE_UNITID_CLUMP	0x90	/* Unit ID clumping */
  14.517 +#define HT_CAPTYPE_EXTCONF	0x98	/* Extended Configuration Space Access */
  14.518 +#define HT_CAPTYPE_MSI_MAPPING	0xA8	/* MSI Mapping Capability */
  14.519 +#define  HT_MSI_FLAGS		0x02		/* Offset to flags */
  14.520 +#define  HT_MSI_FLAGS_ENABLE	0x1		/* Mapping enable */
  14.521 +#define  HT_MSI_FLAGS_FIXED	0x2		/* Fixed mapping only */
  14.522 +#define  HT_MSI_FIXED_ADDR	0x00000000FEE00000ULL	/* Fixed addr */
  14.523 +#define  HT_MSI_ADDR_LO		0x04		/* Offset to low addr bits */
  14.524 +#define  HT_MSI_ADDR_LO_MASK	0xFFF00000	/* Low address bit mask */
  14.525 +#define  HT_MSI_ADDR_HI		0x08		/* Offset to high addr bits */
  14.526 +#define HT_CAPTYPE_DIRECT_ROUTE	0xB0	/* Direct routing configuration */
  14.527 +#define HT_CAPTYPE_VCSET	0xB8	/* Virtual Channel configuration */
  14.528 +#define HT_CAPTYPE_ERROR_RETRY	0xC0	/* Retry on error configuration */
  14.529 +#define HT_CAPTYPE_GEN3		0xD0	/* Generation 3 hypertransport configuration */
  14.530 +#define HT_CAPTYPE_PM		0xE0	/* Hypertransport powermanagement configuration */
  14.531 +
  14.532 +
  14.533 +#endif /* LINUX_PCI_REGS_H */