ia64/xen-unstable

changeset 148:8b22726a81da

bitkeeper revision 1.22.2.17 (3e4a8d40dV6GGD3Pv0mYGrE1vSVPAw)

final bit of checkin
author smh22@boulderdash.cl.cam.ac.uk
date Wed Feb 12 18:06:56 2003 +0000 (2003-02-12)
parents 2868f9ebcc69
children 9641fabdd4fd
files .rootkeys xen-2.4.16/drivers/ide/ide-xeno.c xen-2.4.16/drivers/ide/piix.c
line diff
     1.1 --- a/.rootkeys	Wed Feb 12 18:06:34 2003 +0000
     1.2 +++ b/.rootkeys	Wed Feb 12 18:06:56 2003 +0000
     1.3 @@ -70,8 +70,10 @@ 3ddb79bdh1ohsWYRH_KdaXr7cqs12w xen-2.4.1
     1.4  3ddb79bdYcxXT-2UEaDcG0Ic4MIK1g xen-2.4.16/drivers/ide/ide-pci.c
     1.5  3ddb79bdOXTbcImJo8DwmlNX88k78Q xen-2.4.16/drivers/ide/ide-probe.c
     1.6  3ddb79bdDWFwINnKn29RlFDwGJhjYg xen-2.4.16/drivers/ide/ide-taskfile.c
     1.7 +3e4a8d40XMqvT05EwZwJg1HMsFDUBA xen-2.4.16/drivers/ide/ide-xeno.c
     1.8  3ddb79bdkDY1bSOYkToP1Cc49VdBxg xen-2.4.16/drivers/ide/ide.c
     1.9  3ddb79bdPyAvT_WZTAFhaX0jp-yXSw xen-2.4.16/drivers/ide/ide_modes.h
    1.10 +3e4a8d401aSwOzCScQXR3lsmNlAwUQ xen-2.4.16/drivers/ide/piix.c
    1.11  3ddb79bfogeJNHTIepPjd8fy1TyoTw xen-2.4.16/drivers/net/3c509.c
    1.12  3ddb79bfMlOcWUwjtg6oMYhGySHDDw xen-2.4.16/drivers/net/3c59x.c
    1.13  3ddb79bfl_DWxZQFKiJ2BXrSedV4lg xen-2.4.16/drivers/net/8139cp.c
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/xen-2.4.16/drivers/ide/ide-xeno.c	Wed Feb 12 18:06:56 2003 +0000
     2.3 @@ -0,0 +1,46 @@
     2.4 +#include <xeno/config.h>
     2.5 +#include <xeno/types.h>
     2.6 +#include <xeno/lib.h>
     2.7 +#include <xeno/ide.h>
     2.8 +#include <hypervisor-ifs/block.h>
     2.9 +
    2.10 +
    2.11 +void
    2.12 +ide_probe_devices (xen_disk_info_t* xdi)
    2.13 +{
    2.14 +  int loop;
    2.15 +
    2.16 +  for (loop = 0; loop < MAX_HWIFS; ++loop)
    2.17 +  {
    2.18 +    ide_hwif_t *hwif = &ide_hwifs[loop];
    2.19 +    if (hwif->present)
    2.20 +    {
    2.21 +      struct gendisk *gd = hwif->gd;
    2.22 +      unsigned int unit;
    2.23 +
    2.24 +      for (unit = 0; unit < MAX_DRIVES; ++unit)
    2.25 +      {
    2.26 +	unsigned long capacity;
    2.27 +
    2.28 +	ide_drive_t *drive = &hwif->drives[unit];
    2.29 +
    2.30 +	if (drive->present)
    2.31 +	{
    2.32 +	  capacity = current_capacity (drive);
    2.33 +
    2.34 +	  xdi->disks[xdi->count].type = XEN_DISK_IDE;
    2.35 +	  xdi->disks[xdi->count].capacity = capacity;
    2.36 +	  xdi->count++;
    2.37 +
    2.38 +	  printk (KERN_ALERT "IDE-XENO %d\n", xdi->count);
    2.39 +	  printk (KERN_ALERT "  capacity  0x%x\n", capacity);
    2.40 +	  printk (KERN_ALERT "  head      0x%x\n", drive->bios_head);
    2.41 +	  printk (KERN_ALERT "  sector    0x%x\n", drive->bios_sect);
    2.42 +	  printk (KERN_ALERT "  cylinder  0x%x\n", drive->bios_cyl);
    2.43 +	}
    2.44 +      }
    2.45 +    }
    2.46 +  }
    2.47 +
    2.48 +  return;
    2.49 +}
     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/xen-2.4.16/drivers/ide/piix.c	Wed Feb 12 18:06:56 2003 +0000
     3.3 @@ -0,0 +1,536 @@
     3.4 +/*
     3.5 + *  linux/drivers/ide/piix.c		Version 0.32	June 9, 2000
     3.6 + *
     3.7 + *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
     3.8 + *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
     3.9 + *  May be copied or modified under the terms of the GNU General Public License
    3.10 + *
    3.11 + *  PIO mode setting function for Intel chipsets.  
    3.12 + *  For use instead of BIOS settings.
    3.13 + *
    3.14 + * 40-41
    3.15 + * 42-43
    3.16 + * 
    3.17 + *                 41
    3.18 + *                 43
    3.19 + *
    3.20 + * | PIO 0       | c0 | 80 | 0 | 	piix_tune_drive(drive, 0);
    3.21 + * | PIO 2 | SW2 | d0 | 90 | 4 | 	piix_tune_drive(drive, 2);
    3.22 + * | PIO 3 | MW1 | e1 | a1 | 9 | 	piix_tune_drive(drive, 3);
    3.23 + * | PIO 4 | MW2 | e3 | a3 | b | 	piix_tune_drive(drive, 4);
    3.24 + * 
    3.25 + * sitre = word40 & 0x4000; primary
    3.26 + * sitre = word42 & 0x4000; secondary
    3.27 + *
    3.28 + * 44 8421|8421    hdd|hdb
    3.29 + * 
    3.30 + * 48 8421         hdd|hdc|hdb|hda udma enabled
    3.31 + *
    3.32 + *    0001         hda
    3.33 + *    0010         hdb
    3.34 + *    0100         hdc
    3.35 + *    1000         hdd
    3.36 + *
    3.37 + * 4a 84|21        hdb|hda
    3.38 + * 4b 84|21        hdd|hdc
    3.39 + *
    3.40 + *    ata-33/82371AB
    3.41 + *    ata-33/82371EB
    3.42 + *    ata-33/82801AB            ata-66/82801AA
    3.43 + *    00|00 udma 0              00|00 reserved
    3.44 + *    01|01 udma 1              01|01 udma 3
    3.45 + *    10|10 udma 2              10|10 udma 4
    3.46 + *    11|11 reserved            11|11 reserved
    3.47 + *
    3.48 + * 54 8421|8421    ata66 drive|ata66 enable
    3.49 + *
    3.50 + * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
    3.51 + * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
    3.52 + * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
    3.53 + * pci_read_config_word(HWIF(drive)->pci_dev, 0x48, &reg48);
    3.54 + * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
    3.55 + * pci_read_config_word(HWIF(drive)->pci_dev, 0x54, &reg54);
    3.56 + *
    3.57 + */
    3.58 +
    3.59 +#include <linux/config.h>
    3.60 +#include <linux/types.h>
    3.61 +#include <linux/kernel.h>
    3.62 +#include <linux/ioport.h>
    3.63 +#include <linux/pci.h>
    3.64 +#include <linux/hdreg.h>
    3.65 +#include <linux/ide.h>
    3.66 +#include <linux/delay.h>
    3.67 +#include <linux/init.h>
    3.68 +
    3.69 +#include <asm/io.h>
    3.70 +
    3.71 +#include "ide_modes.h"
    3.72 +
    3.73 +#define PIIX_DEBUG_DRIVE_INFO		0
    3.74 +
    3.75 +#define DISPLAY_PIIX_TIMINGS
    3.76 +
    3.77 +#if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
    3.78 +#include <linux/stat.h>
    3.79 +#include <linux/proc_fs.h>
    3.80 +
    3.81 +static int piix_get_info(char *, char **, off_t, int);
    3.82 +extern int (*piix_display_info)(char *, char **, off_t, int); /* ide-proc.c */
    3.83 +extern char *ide_media_verbose(ide_drive_t *);
    3.84 +static struct pci_dev *bmide_dev;
    3.85 +
    3.86 +static int piix_get_info (char *buffer, char **addr, off_t offset, int count)
    3.87 +{
    3.88 +	char *p = buffer;
    3.89 +	u32 bibma = pci_resource_start(bmide_dev, 4);
    3.90 +        u16 reg40 = 0, psitre = 0, reg42 = 0, ssitre = 0;
    3.91 +	u8  c0 = 0, c1 = 0;
    3.92 +	u8  reg44 = 0, reg48 = 0, reg4a = 0, reg4b = 0, reg54 = 0, reg55 = 0;
    3.93 +
    3.94 +	switch(bmide_dev->device) {
    3.95 +		case PCI_DEVICE_ID_INTEL_82801BA_8:
    3.96 +		case PCI_DEVICE_ID_INTEL_82801BA_9:
    3.97 +	        case PCI_DEVICE_ID_INTEL_82801CA_10:
    3.98 +			p += sprintf(p, "\n                                Intel PIIX4 Ultra 100 Chipset.\n");
    3.99 +			break;
   3.100 +		case PCI_DEVICE_ID_INTEL_82372FB_1:
   3.101 +		case PCI_DEVICE_ID_INTEL_82801AA_1:
   3.102 +			p += sprintf(p, "\n                                Intel PIIX4 Ultra 66 Chipset.\n");
   3.103 +			break;
   3.104 +		case PCI_DEVICE_ID_INTEL_82451NX:
   3.105 +		case PCI_DEVICE_ID_INTEL_82801AB_1:
   3.106 +		case PCI_DEVICE_ID_INTEL_82443MX_1:
   3.107 +		case PCI_DEVICE_ID_INTEL_82371AB:
   3.108 +			p += sprintf(p, "\n                                Intel PIIX4 Ultra 33 Chipset.\n");
   3.109 +			break;
   3.110 +		case PCI_DEVICE_ID_INTEL_82371SB_1:
   3.111 +			p += sprintf(p, "\n                                Intel PIIX3 Chipset.\n");
   3.112 +			break;
   3.113 +		case PCI_DEVICE_ID_INTEL_82371MX:
   3.114 +			p += sprintf(p, "\n                                Intel MPIIX Chipset.\n");
   3.115 +			return p-buffer;	/* => must be less than 4k! */
   3.116 +		case PCI_DEVICE_ID_INTEL_82371FB_1:
   3.117 +		case PCI_DEVICE_ID_INTEL_82371FB_0:
   3.118 +		default:
   3.119 +			p += sprintf(p, "\n                                Intel PIIX Chipset.\n");
   3.120 +			break;
   3.121 +	}
   3.122 +
   3.123 +	pci_read_config_word(bmide_dev, 0x40, &reg40);
   3.124 +	pci_read_config_word(bmide_dev, 0x42, &reg42);
   3.125 +	pci_read_config_byte(bmide_dev, 0x44, &reg44);
   3.126 +	pci_read_config_byte(bmide_dev, 0x48, &reg48);
   3.127 +	pci_read_config_byte(bmide_dev, 0x4a, &reg4a);
   3.128 +	pci_read_config_byte(bmide_dev, 0x4b, &reg4b);
   3.129 +	pci_read_config_byte(bmide_dev, 0x54, &reg54);
   3.130 +	pci_read_config_byte(bmide_dev, 0x55, &reg55);
   3.131 +
   3.132 +	psitre = (reg40 & 0x4000) ? 1 : 0;
   3.133 +	ssitre = (reg42 & 0x4000) ? 1 : 0;
   3.134 +
   3.135 +	/*
   3.136 +	 * at that point bibma+0x2 et bibma+0xa are byte registers
   3.137 +	 * to investigate:
   3.138 +	 */
   3.139 +	c0 = inb_p((unsigned short)bibma + 0x02);
   3.140 +	c1 = inb_p((unsigned short)bibma + 0x0a);
   3.141 +
   3.142 +	p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
   3.143 +	p += sprintf(p, "                %sabled                         %sabled\n",
   3.144 +			(c0&0x80) ? "dis" : " en",
   3.145 +			(c1&0x80) ? "dis" : " en");
   3.146 +	p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
   3.147 +	p += sprintf(p, "DMA enabled:    %s              %s             %s               %s\n",
   3.148 +			(c0&0x20) ? "yes" : "no ",
   3.149 +			(c0&0x40) ? "yes" : "no ",
   3.150 +			(c1&0x20) ? "yes" : "no ",
   3.151 +			(c1&0x40) ? "yes" : "no " );
   3.152 +	p += sprintf(p, "UDMA enabled:   %s              %s             %s               %s\n",
   3.153 +			(reg48&0x01) ? "yes" : "no ",
   3.154 +			(reg48&0x02) ? "yes" : "no ",
   3.155 +			(reg48&0x04) ? "yes" : "no ",
   3.156 +			(reg48&0x08) ? "yes" : "no " );
   3.157 +	p += sprintf(p, "UDMA enabled:   %s                %s               %s                 %s\n",
   3.158 +			((reg54&0x11) && (reg55&0x10) && (reg4a&0x01)) ? "5" :
   3.159 +			((reg54&0x11) && (reg4a&0x02)) ? "4" :
   3.160 +			((reg54&0x11) && (reg4a&0x01)) ? "3" :
   3.161 +			(reg4a&0x02) ? "2" :
   3.162 +			(reg4a&0x01) ? "1" :
   3.163 +			(reg4a&0x00) ? "0" : "X",
   3.164 +			((reg54&0x22) && (reg55&0x20) && (reg4a&0x10)) ? "5" :
   3.165 +			((reg54&0x22) && (reg4a&0x20)) ? "4" :
   3.166 +			((reg54&0x22) && (reg4a&0x10)) ? "3" :
   3.167 +			(reg4a&0x20) ? "2" :
   3.168 +			(reg4a&0x10) ? "1" :
   3.169 +			(reg4a&0x00) ? "0" : "X",
   3.170 +			((reg54&0x44) && (reg55&0x40) && (reg4b&0x03)) ? "5" :
   3.171 +			((reg54&0x44) && (reg4b&0x02)) ? "4" :
   3.172 +			((reg54&0x44) && (reg4b&0x01)) ? "3" :
   3.173 +			(reg4b&0x02) ? "2" :
   3.174 +			(reg4b&0x01) ? "1" :
   3.175 +			(reg4b&0x00) ? "0" : "X",
   3.176 +			((reg54&0x88) && (reg55&0x80) && (reg4b&0x30)) ? "5" :
   3.177 +			((reg54&0x88) && (reg4b&0x20)) ? "4" :
   3.178 +			((reg54&0x88) && (reg4b&0x10)) ? "3" :
   3.179 +			(reg4b&0x20) ? "2" :
   3.180 +			(reg4b&0x10) ? "1" :
   3.181 +			(reg4b&0x00) ? "0" : "X");
   3.182 +
   3.183 +	p += sprintf(p, "UDMA\n");
   3.184 +	p += sprintf(p, "DMA\n");
   3.185 +	p += sprintf(p, "PIO\n");
   3.186 +
   3.187 +/*
   3.188 + *	FIXME.... Add configuration junk data....blah blah......
   3.189 + */
   3.190 +
   3.191 +	return p-buffer;	 /* => must be less than 4k! */
   3.192 +}
   3.193 +#endif  /* defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS) */
   3.194 +
   3.195 +/*
   3.196 + *  Used to set Fifo configuration via kernel command line:
   3.197 + */
   3.198 +
   3.199 +byte piix_proc = 0;
   3.200 +
   3.201 +extern char *ide_xfer_verbose (byte xfer_rate);
   3.202 +
   3.203 +#if defined(CONFIG_BLK_DEV_IDEDMA) && defined(CONFIG_PIIX_TUNING)
   3.204 +/*
   3.205 + *
   3.206 + */
   3.207 +static byte piix_dma_2_pio (byte xfer_rate) {
   3.208 +	switch(xfer_rate) {
   3.209 +		case XFER_UDMA_5:
   3.210 +		case XFER_UDMA_4:
   3.211 +		case XFER_UDMA_3:
   3.212 +		case XFER_UDMA_2:
   3.213 +		case XFER_UDMA_1:
   3.214 +		case XFER_UDMA_0:
   3.215 +		case XFER_MW_DMA_2:
   3.216 +		case XFER_PIO_4:
   3.217 +			return 4;
   3.218 +		case XFER_MW_DMA_1:
   3.219 +		case XFER_PIO_3:
   3.220 +			return 3;
   3.221 +		case XFER_SW_DMA_2:
   3.222 +		case XFER_PIO_2:
   3.223 +			return 2;
   3.224 +		case XFER_MW_DMA_0:
   3.225 +		case XFER_SW_DMA_1:
   3.226 +		case XFER_SW_DMA_0:
   3.227 +		case XFER_PIO_1:
   3.228 +		case XFER_PIO_0:
   3.229 +		case XFER_PIO_SLOW:
   3.230 +		default:
   3.231 +			return 0;
   3.232 +	}
   3.233 +}
   3.234 +#endif /* defined(CONFIG_BLK_DEV_IDEDMA) && (CONFIG_PIIX_TUNING) */
   3.235 +
   3.236 +/*
   3.237 + *  Based on settings done by AMI BIOS
   3.238 + *  (might be useful if drive is not registered in CMOS for any reason).
   3.239 + */
   3.240 +static void piix_tune_drive (ide_drive_t *drive, byte pio)
   3.241 +{
   3.242 +	unsigned long flags;
   3.243 +	u16 master_data;
   3.244 +	byte slave_data;
   3.245 +	int is_slave		= (&HWIF(drive)->drives[1] == drive);
   3.246 +	int master_port		= HWIF(drive)->index ? 0x42 : 0x40;
   3.247 +	int slave_port		= 0x44;
   3.248 +				 /* ISP  RTC */
   3.249 +	byte timings[][2]	= { { 0, 0 },
   3.250 +				    { 0, 0 },
   3.251 +				    { 1, 0 },
   3.252 +				    { 2, 1 },
   3.253 +				    { 2, 3 }, };
   3.254 +
   3.255 +	pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
   3.256 +	pci_read_config_word(HWIF(drive)->pci_dev, master_port, &master_data);
   3.257 +	if (is_slave) {
   3.258 +		master_data = master_data | 0x4000;
   3.259 +		if (pio > 1)
   3.260 +			/* enable PPE, IE and TIME */
   3.261 +			master_data = master_data | 0x0070;
   3.262 +		pci_read_config_byte(HWIF(drive)->pci_dev, slave_port, &slave_data);
   3.263 +		slave_data = slave_data & (HWIF(drive)->index ? 0x0f : 0xf0);
   3.264 +		slave_data = slave_data | ((timings[pio][0] << 2) | (timings[pio][1]
   3.265 +					   << (HWIF(drive)->index ? 4 : 0)));
   3.266 +	} else {
   3.267 +		master_data = master_data & 0xccf8;
   3.268 +		if (pio > 1)
   3.269 +			/* enable PPE, IE and TIME */
   3.270 +			master_data = master_data | 0x0007;
   3.271 +		master_data = master_data | (timings[pio][0] << 12) |
   3.272 +			      (timings[pio][1] << 8);
   3.273 +	}
   3.274 +	save_flags(flags);
   3.275 +	cli();
   3.276 +	pci_write_config_word(HWIF(drive)->pci_dev, master_port, master_data);
   3.277 +	if (is_slave)
   3.278 +		pci_write_config_byte(HWIF(drive)->pci_dev, slave_port, slave_data);
   3.279 +	restore_flags(flags);
   3.280 +}
   3.281 +
   3.282 +#if defined(CONFIG_BLK_DEV_IDEDMA) && defined(CONFIG_PIIX_TUNING)
   3.283 +static int piix_tune_chipset (ide_drive_t *drive, byte speed)
   3.284 +{
   3.285 +	ide_hwif_t *hwif	= HWIF(drive);
   3.286 +	struct pci_dev *dev	= hwif->pci_dev;
   3.287 +	byte maslave		= hwif->channel ? 0x42 : 0x40;
   3.288 +	int a_speed		= 3 << (drive->dn * 4);
   3.289 +	int u_flag		= 1 << drive->dn;
   3.290 +	int v_flag		= 0x01 << drive->dn;
   3.291 +	int w_flag		= 0x10 << drive->dn;
   3.292 +	int u_speed		= 0;
   3.293 +	int err			= 0;
   3.294 +	int			sitre;
   3.295 +	short			reg4042, reg44, reg48, reg4a, reg54;
   3.296 +	byte			reg55;
   3.297 +
   3.298 +	pci_read_config_word(dev, maslave, &reg4042);
   3.299 +	sitre = (reg4042 & 0x4000) ? 1 : 0;
   3.300 +	pci_read_config_word(dev, 0x44, &reg44);
   3.301 +	pci_read_config_word(dev, 0x48, &reg48);
   3.302 +	pci_read_config_word(dev, 0x4a, &reg4a);
   3.303 +	pci_read_config_word(dev, 0x54, &reg54);
   3.304 +	pci_read_config_byte(dev, 0x55, &reg55);
   3.305 +
   3.306 +	switch(speed) {
   3.307 +		case XFER_UDMA_4:
   3.308 +		case XFER_UDMA_2:	u_speed = 2 << (drive->dn * 4); break;
   3.309 +		case XFER_UDMA_5:
   3.310 +		case XFER_UDMA_3:
   3.311 +		case XFER_UDMA_1:	u_speed = 1 << (drive->dn * 4); break;
   3.312 +		case XFER_UDMA_0:	u_speed = 0 << (drive->dn * 4); break;
   3.313 +		case XFER_MW_DMA_2:
   3.314 +		case XFER_MW_DMA_1:
   3.315 +		case XFER_SW_DMA_2:	break;
   3.316 +		default:		return -1;
   3.317 +	}
   3.318 +
   3.319 +	if (speed >= XFER_UDMA_0) {
   3.320 +		if (!(reg48 & u_flag))
   3.321 +			pci_write_config_word(dev, 0x48, reg48|u_flag);
   3.322 +		if (speed == XFER_UDMA_5) {
   3.323 +			pci_write_config_byte(dev, 0x55, (byte) reg55|w_flag);
   3.324 +		} else {
   3.325 +			pci_write_config_byte(dev, 0x55, (byte) reg55 & ~w_flag);
   3.326 +		}
   3.327 +		if (!(reg4a & u_speed)) {
   3.328 +			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
   3.329 +			pci_write_config_word(dev, 0x4a, reg4a|u_speed);
   3.330 +		}
   3.331 +		if (speed > XFER_UDMA_2) {
   3.332 +			if (!(reg54 & v_flag)) {
   3.333 +				pci_write_config_word(dev, 0x54, reg54|v_flag);
   3.334 +			}
   3.335 +		} else {
   3.336 +			pci_write_config_word(dev, 0x54, reg54 & ~v_flag);
   3.337 +		}
   3.338 +	}
   3.339 +	if (speed < XFER_UDMA_0) {
   3.340 +		if (reg48 & u_flag)
   3.341 +			pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
   3.342 +		if (reg4a & a_speed)
   3.343 +			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
   3.344 +		if (reg54 & v_flag)
   3.345 +			pci_write_config_word(dev, 0x54, reg54 & ~v_flag);
   3.346 +		if (reg55 & w_flag)
   3.347 +			pci_write_config_byte(dev, 0x55, (byte) reg55 & ~w_flag);
   3.348 +	}
   3.349 +
   3.350 +	piix_tune_drive(drive, piix_dma_2_pio(speed));
   3.351 +
   3.352 +#if PIIX_DEBUG_DRIVE_INFO
   3.353 +	printk("%s: %s drive%d\n", drive->name, ide_xfer_verbose(speed), drive->dn);
   3.354 +#endif /* PIIX_DEBUG_DRIVE_INFO */
   3.355 +	if (!drive->init_speed)
   3.356 +		drive->init_speed = speed;
   3.357 +	err = ide_config_drive_speed(drive, speed);
   3.358 +	drive->current_speed = speed;
   3.359 +	return err;
   3.360 +}
   3.361 +
   3.362 +static int piix_config_drive_for_dma (ide_drive_t *drive)
   3.363 +{
   3.364 +	struct hd_driveid *id	= drive->id;
   3.365 +	ide_hwif_t *hwif	= HWIF(drive);
   3.366 +	struct pci_dev *dev	= hwif->pci_dev;
   3.367 +	byte			speed;
   3.368 +
   3.369 +	byte udma_66		= eighty_ninty_three(drive);
   3.370 +	int ultra100		= ((dev->device == PCI_DEVICE_ID_INTEL_82801BA_8) ||
   3.371 +				   (dev->device == PCI_DEVICE_ID_INTEL_82801BA_9) ||
   3.372 +				   (dev->device == PCI_DEVICE_ID_INTEL_82801CA_10)) ? 1 : 0;
   3.373 +	int ultra66		= ((ultra100) ||
   3.374 +				   (dev->device == PCI_DEVICE_ID_INTEL_82801AA_1) ||
   3.375 +				   (dev->device == PCI_DEVICE_ID_INTEL_82372FB_1)) ? 1 : 0;
   3.376 +	int ultra		= ((ultra66) ||
   3.377 +				   (dev->device == PCI_DEVICE_ID_INTEL_82371AB) ||
   3.378 +				   (dev->device == PCI_DEVICE_ID_INTEL_82443MX_1) ||
   3.379 +				   (dev->device == PCI_DEVICE_ID_INTEL_82451NX) ||
   3.380 +				   (dev->device == PCI_DEVICE_ID_INTEL_82801AB_1)) ? 1 : 0;
   3.381 +
   3.382 +	if ((id->dma_ultra & 0x0020) && (udma_66) && (ultra100)) {
   3.383 +		speed = XFER_UDMA_5;
   3.384 +	} else if ((id->dma_ultra & 0x0010) && (ultra)) {
   3.385 +		speed = ((udma_66) && (ultra66)) ? XFER_UDMA_4 : XFER_UDMA_2;
   3.386 +	} else if ((id->dma_ultra & 0x0008) && (ultra)) {
   3.387 +		speed = ((udma_66) && (ultra66)) ? XFER_UDMA_3 : XFER_UDMA_1;
   3.388 +	} else if ((id->dma_ultra & 0x0004) && (ultra)) {
   3.389 +		speed = XFER_UDMA_2;
   3.390 +	} else if ((id->dma_ultra & 0x0002) && (ultra)) {
   3.391 +		speed = XFER_UDMA_1;
   3.392 +	} else if ((id->dma_ultra & 0x0001) && (ultra)) {
   3.393 +		speed = XFER_UDMA_0;
   3.394 +	} else if (id->dma_mword & 0x0004) {
   3.395 +		speed = XFER_MW_DMA_2;
   3.396 +	} else if (id->dma_mword & 0x0002) {
   3.397 +		speed = XFER_MW_DMA_1;
   3.398 +	} else if (id->dma_1word & 0x0004) {
   3.399 +		speed = XFER_SW_DMA_2;
   3.400 +        } else {
   3.401 +		speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
   3.402 +	}
   3.403 +
   3.404 +	(void) piix_tune_chipset(drive, speed);
   3.405 +
   3.406 +	return ((int)	((id->dma_ultra >> 11) & 7) ? ide_dma_on :
   3.407 +			((id->dma_ultra >> 8) & 7) ? ide_dma_on :
   3.408 +			((id->dma_mword >> 8) & 7) ? ide_dma_on :
   3.409 +			((id->dma_1word >> 8) & 7) ? ide_dma_on :
   3.410 +						     ide_dma_off_quietly);
   3.411 +}
   3.412 +
   3.413 +static void config_chipset_for_pio (ide_drive_t *drive)
   3.414 +{
   3.415 +	piix_tune_drive(drive, ide_get_best_pio_mode(drive, 255, 5, NULL));
   3.416 +}
   3.417 +
   3.418 +static int config_drive_xfer_rate (ide_drive_t *drive)
   3.419 +{
   3.420 +	struct hd_driveid *id = drive->id;
   3.421 +	ide_dma_action_t dma_func = ide_dma_on;
   3.422 +
   3.423 +	if (id && (id->capability & 1) && HWIF(drive)->autodma) {
   3.424 +		/* Consult the list of known "bad" drives */
   3.425 +		if (ide_dmaproc(ide_dma_bad_drive, drive)) {
   3.426 +			dma_func = ide_dma_off;
   3.427 +			goto fast_ata_pio;
   3.428 +		}
   3.429 +		dma_func = ide_dma_off_quietly;
   3.430 +		if (id->field_valid & 4) {
   3.431 +			if (id->dma_ultra & 0x002F) {
   3.432 +				/* Force if Capable UltraDMA */
   3.433 +				dma_func = piix_config_drive_for_dma(drive);
   3.434 +				if ((id->field_valid & 2) &&
   3.435 +				    (dma_func != ide_dma_on))
   3.436 +					goto try_dma_modes;
   3.437 +			}
   3.438 +		} else if (id->field_valid & 2) {
   3.439 +try_dma_modes:
   3.440 +			if ((id->dma_mword & 0x0007) ||
   3.441 +			    (id->dma_1word & 0x007)) {
   3.442 +				/* Force if Capable regular DMA modes */
   3.443 +				dma_func = piix_config_drive_for_dma(drive);
   3.444 +				if (dma_func != ide_dma_on)
   3.445 +					goto no_dma_set;
   3.446 +			}
   3.447 +		} else if (ide_dmaproc(ide_dma_good_drive, drive)) {
   3.448 +			if (id->eide_dma_time > 150) {
   3.449 +				goto no_dma_set;
   3.450 +			}
   3.451 +			/* Consult the list of known "good" drives */
   3.452 +			dma_func = piix_config_drive_for_dma(drive);
   3.453 +			if (dma_func != ide_dma_on)
   3.454 +				goto no_dma_set;
   3.455 +		} else {
   3.456 +			goto fast_ata_pio;
   3.457 +		}
   3.458 +	} else if ((id->capability & 8) || (id->field_valid & 2)) {
   3.459 +fast_ata_pio:
   3.460 +		dma_func = ide_dma_off_quietly;
   3.461 +no_dma_set:
   3.462 +		config_chipset_for_pio(drive);
   3.463 +	}
   3.464 +	return HWIF(drive)->dmaproc(dma_func, drive);
   3.465 +}
   3.466 +
   3.467 +static int piix_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
   3.468 +{
   3.469 +	switch (func) {
   3.470 +		case ide_dma_check:
   3.471 +			return config_drive_xfer_rate(drive);
   3.472 +		default :
   3.473 +			break;
   3.474 +	}
   3.475 +	/* Other cases are done by generic IDE-DMA code. */
   3.476 +	return ide_dmaproc(func, drive);
   3.477 +}
   3.478 +#endif /* defined(CONFIG_BLK_DEV_IDEDMA) && (CONFIG_PIIX_TUNING) */
   3.479 +
   3.480 +unsigned int __init pci_init_piix (struct pci_dev *dev, const char *name)
   3.481 +{
   3.482 +#if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
   3.483 +	if (!piix_proc) {
   3.484 +		piix_proc = 1;
   3.485 +		bmide_dev = dev;
   3.486 +		piix_display_info = &piix_get_info;
   3.487 +	}
   3.488 +#endif /* DISPLAY_PIIX_TIMINGS && CONFIG_PROC_FS */
   3.489 +	return 0;
   3.490 +}
   3.491 +
   3.492 +/*
   3.493 + * Sheesh, someone at Intel needs to go read the ATA-4/5 T13 standards.
   3.494 + * It does not specify device detection, but channel!!!
   3.495 + * You determine later if bit 13 of word93 is set...
   3.496 + */
   3.497 +unsigned int __init ata66_piix (ide_hwif_t *hwif)
   3.498 +{
   3.499 +	byte reg54h = 0, reg55h = 0, ata66 = 0;
   3.500 +	byte mask = hwif->channel ? 0xc0 : 0x30;
   3.501 +
   3.502 +	pci_read_config_byte(hwif->pci_dev, 0x54, &reg54h);
   3.503 +	pci_read_config_byte(hwif->pci_dev, 0x55, &reg55h);
   3.504 +
   3.505 +	ata66 = (reg54h & mask) ? 1 : 0;
   3.506 +
   3.507 +	return ata66;
   3.508 +}
   3.509 +
   3.510 +void __init ide_init_piix (ide_hwif_t *hwif)
   3.511 +{
   3.512 +#ifndef CONFIG_IA64
   3.513 +	if (!hwif->irq)
   3.514 +		hwif->irq = hwif->channel ? 15 : 14;
   3.515 +#endif /* CONFIG_IA64 */
   3.516 +
   3.517 +	if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
   3.518 +		/* This is a painful system best to let it self tune for now */
   3.519 +		return;
   3.520 +	}
   3.521 +
   3.522 +	hwif->tuneproc = &piix_tune_drive;
   3.523 +	hwif->drives[0].autotune = 1;
   3.524 +	hwif->drives[1].autotune = 1;
   3.525 +
   3.526 +	if (!hwif->dma_base)
   3.527 +		return;
   3.528 +
   3.529 +#ifndef CONFIG_BLK_DEV_IDEDMA
   3.530 +	hwif->autodma = 0;
   3.531 +#else /* CONFIG_BLK_DEV_IDEDMA */
   3.532 +#ifdef CONFIG_PIIX_TUNING
   3.533 +	if (!noautodma)
   3.534 +		hwif->autodma = 1;
   3.535 +	hwif->dmaproc = &piix_dmaproc;
   3.536 +	hwif->speedproc = &piix_tune_chipset;
   3.537 +#endif /* CONFIG_PIIX_TUNING */
   3.538 +#endif /* !CONFIG_BLK_DEV_IDEDMA */
   3.539 +}