ia64/xen-unstable

changeset 4771:86c325c8937a

bitkeeper revision 1.1389.5.15 (427a1f89783q7rsxC220wc9YSyIgxg)

Merge firebug.cl.cam.ac.uk:/auto/groups/xeno-xenod/BK/xen-unstable.bk
into firebug.cl.cam.ac.uk:/local/scratch/smh22/xen-unstable.bk
author smh22@firebug.cl.cam.ac.uk
date Thu May 05 13:28:41 2005 +0000 (2005-05-05)
parents aee6d65586c1 90278aede77e
children e2c5e62c7c0d
files linux-2.6.11-xen-sparse/arch/xen/i386/Kconfig linux-2.6.11-xen-sparse/arch/xen/i386/kernel/acpi/boot.c linux-2.6.11-xen-sparse/arch/xen/i386/kernel/io_apic.c linux-2.6.11-xen-sparse/drivers/acpi/tables.c linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/fixmap.h linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/io_apic.h tools/libxc/xc_domain.c
line diff
     1.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/Kconfig	Wed May 04 17:40:45 2005 +0000
     1.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/Kconfig	Thu May 05 13:28:41 2005 +0000
     1.3 @@ -788,7 +788,7 @@ config PCI_MMCONFIG
     1.4  	bool
     1.5  	depends on PCI && (PCI_GOMMCONFIG || (PCI_GOANY && ACPI))
     1.6  	select ACPI_BOOT
     1.7 -	default y
     1.8 +	default n
     1.9  
    1.10  source "drivers/pci/pcie/Kconfig"
    1.11  
     2.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/acpi/boot.c	Wed May 04 17:40:45 2005 +0000
     2.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/acpi/boot.c	Thu May 05 13:28:41 2005 +0000
     2.3 @@ -109,17 +109,18 @@ enum acpi_irq_model_id		acpi_irq_model =
     2.4  
     2.5  char *__acpi_map_table(unsigned long phys_addr, unsigned long size)
     2.6  {
     2.7 -        unsigned int i,j;
     2.8 +	unsigned int i,j;
     2.9  
    2.10 -        j = PAGE_ALIGN(size) >> PAGE_SHIFT;
    2.11 -        for (i = 0; (i < FIX_ACPI_PAGES) && j ; i++, j--) {
    2.12 -                __set_fixmap_ma(FIX_ACPI_END - i,
    2.13 -                                (phys_addr & PAGE_MASK) + (i << PAGE_SHIFT),
    2.14 -                                PAGE_KERNEL);
    2.15 -        }
    2.16 +	j = PAGE_ALIGN(size) >> PAGE_SHIFT;
    2.17 +	for (i = 0; (i < FIX_ACPI_PAGES) && j ; i++, j--) {
    2.18 +		__set_fixmap_ma(FIX_ACPI_END - i,
    2.19 +				(phys_addr & PAGE_MASK) + (i << PAGE_SHIFT),
    2.20 +				PAGE_KERNEL);
    2.21 +	}
    2.22  
    2.23 -        return (char *) __fix_to_virt(FIX_ACPI_END) + (phys_addr & ~PAGE_MASK);
    2.24 +	return (char *) __fix_to_virt(FIX_ACPI_END) + (phys_addr & ~PAGE_MASK);
    2.25  }
    2.26 +
    2.27  #else
    2.28  #ifdef	CONFIG_X86_64
    2.29  
    2.30 @@ -523,7 +524,7 @@ acpi_scan_rsdp (
    2.31  {
    2.32  	unsigned long		offset = 0;
    2.33  	unsigned long		sig_len = sizeof("RSD PTR ") - 1;
    2.34 -        unsigned long           vstart = isa_bus_to_virt(start);
    2.35 +	unsigned long		vstart = (unsigned long)isa_bus_to_virt(start);
    2.36  
    2.37  	/*
    2.38  	 * Scan all 16-byte boundaries of the physical memory region for the
    2.39 @@ -649,7 +650,6 @@ acpi_find_rsdp (void)
    2.40  		else if (efi.acpi)
    2.41  			return __pa(efi.acpi);
    2.42  	}
    2.43 -
    2.44  	/*
    2.45  	 * Scan memory looking for the RSDP signature. First search EBDA (low
    2.46  	 * memory) paragraphs and then search upper memory (E0000-FFFFF).
    2.47 @@ -658,7 +658,7 @@ acpi_find_rsdp (void)
    2.48  	if (!rsdp_phys)
    2.49  		rsdp_phys = acpi_scan_rsdp (0xE0000, 0x20000);
    2.50  
    2.51 -        __set_fixmap_ma(FIX_ACPI_RSDP_PAGE, rsdp_phys, PAGE_KERNEL);
    2.52 +	__set_fixmap_ma(FIX_ACPI_RSDP_PAGE, rsdp_phys, PAGE_KERNEL);
    2.53  
    2.54  	return rsdp_phys;
    2.55  }
    2.56 @@ -674,7 +674,7 @@ acpi_parse_madt_lapic_entries(void)
    2.57  	int count;
    2.58  
    2.59  #ifdef CONFIG_XEN
    2.60 -        return 0;
    2.61 +	return 0;
    2.62  #endif
    2.63  
    2.64  	/* 
    2.65 @@ -872,7 +872,9 @@ acpi_boot_table_init(void)
    2.66  	}
    2.67  
    2.68  #ifdef __i386__
    2.69 -	//check_acpi_pci();
    2.70 +#ifndef CONFIG_XEN
    2.71 +	check_acpi_pci();
    2.72 +#endif
    2.73  #endif
    2.74  
    2.75  	acpi_table_parse(ACPI_BOOT, acpi_parse_sbf);
     3.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/io_apic.c	Wed May 04 17:40:45 2005 +0000
     3.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/io_apic.c	Thu May 05 13:28:41 2005 +0000
     3.3 @@ -48,7 +48,6 @@ int (*ioapic_renumber_irq)(int ioapic, i
     3.4  atomic_t irq_mis_count;
     3.5  
     3.6  unsigned long io_apic_irqs;
     3.7 -int skip_ioapic_setup;
     3.8  
     3.9  static DEFINE_SPINLOCK(ioapic_lock);
    3.10  
    3.11 @@ -89,24 +88,6 @@ int vector_irq[NR_VECTORS] = { [0 ... NR
    3.12  #define vector_to_irq(vector)	(vector)
    3.13  #endif
    3.14  
    3.15 -
    3.16 -#ifndef CONFIG_SMP
    3.17 -void fastcall send_IPI_self(int vector)
    3.18 -{
    3.19 -     return; 
    3.20 -}
    3.21 -#endif
    3.22 -
    3.23 -int irqbalance_disable(char *str)
    3.24 -{
    3.25 -     return 0; 
    3.26 -}
    3.27 -
    3.28 -void print_IO_APIC(void)
    3.29 -{
    3.30 -     return; 
    3.31 -}
    3.32 -
    3.33  /*
    3.34   * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
    3.35   * shared ISA-space IRQs, so we have to support them. We are super
    3.36 @@ -131,6 +112,582 @@ static void add_pin_to_irq(unsigned int 
    3.37  }
    3.38  
    3.39  /*
    3.40 + * Reroute an IRQ to a different pin.
    3.41 + */
    3.42 +static void __init replace_pin_at_irq(unsigned int irq,
    3.43 +				      int oldapic, int oldpin,
    3.44 +				      int newapic, int newpin)
    3.45 +{
    3.46 +	struct irq_pin_list *entry = irq_2_pin + irq;
    3.47 +
    3.48 +	while (1) {
    3.49 +		if (entry->apic == oldapic && entry->pin == oldpin) {
    3.50 +			entry->apic = newapic;
    3.51 +			entry->pin = newpin;
    3.52 +		}
    3.53 +		if (!entry->next)
    3.54 +			break;
    3.55 +		entry = irq_2_pin + entry->next;
    3.56 +	}
    3.57 +}
    3.58 +
    3.59 +static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
    3.60 +{
    3.61 +	struct irq_pin_list *entry = irq_2_pin + irq;
    3.62 +	unsigned int pin, reg;
    3.63 +
    3.64 +	for (;;) {
    3.65 +		pin = entry->pin;
    3.66 +		if (pin == -1)
    3.67 +			break;
    3.68 +		reg = io_apic_read(entry->apic, 0x10 + pin*2);
    3.69 +		reg &= ~disable;
    3.70 +		reg |= enable;
    3.71 +		io_apic_modify(entry->apic, 0x10 + pin*2, reg);
    3.72 +		if (!entry->next)
    3.73 +			break;
    3.74 +		entry = irq_2_pin + entry->next;
    3.75 +	}
    3.76 +}
    3.77 +
    3.78 +/* mask = 1 */
    3.79 +static void __mask_IO_APIC_irq (unsigned int irq)
    3.80 +{
    3.81 +	__modify_IO_APIC_irq(irq, 0x00010000, 0);
    3.82 +}
    3.83 +
    3.84 +/* mask = 0 */
    3.85 +static void __unmask_IO_APIC_irq (unsigned int irq)
    3.86 +{
    3.87 +	__modify_IO_APIC_irq(irq, 0, 0x00010000);
    3.88 +}
    3.89 +
    3.90 +/* mask = 1, trigger = 0 */
    3.91 +static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
    3.92 +{
    3.93 +	__modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
    3.94 +}
    3.95 +
    3.96 +/* mask = 0, trigger = 1 */
    3.97 +static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
    3.98 +{
    3.99 +	__modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
   3.100 +}
   3.101 +
   3.102 +static void mask_IO_APIC_irq (unsigned int irq)
   3.103 +{
   3.104 +	unsigned long flags;
   3.105 +
   3.106 +	spin_lock_irqsave(&ioapic_lock, flags);
   3.107 +	__mask_IO_APIC_irq(irq);
   3.108 +	spin_unlock_irqrestore(&ioapic_lock, flags);
   3.109 +}
   3.110 +
   3.111 +static void unmask_IO_APIC_irq (unsigned int irq)
   3.112 +{
   3.113 +	unsigned long flags;
   3.114 +
   3.115 +	spin_lock_irqsave(&ioapic_lock, flags);
   3.116 +	__unmask_IO_APIC_irq(irq);
   3.117 +	spin_unlock_irqrestore(&ioapic_lock, flags);
   3.118 +}
   3.119 +
   3.120 +void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
   3.121 +{
   3.122 +	struct IO_APIC_route_entry entry;
   3.123 +	unsigned long flags;
   3.124 +	
   3.125 +	/* Check delivery_mode to be sure we're not clearing an SMI pin */
   3.126 +	spin_lock_irqsave(&ioapic_lock, flags);
   3.127 +	*(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
   3.128 +	*(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
   3.129 +	spin_unlock_irqrestore(&ioapic_lock, flags);
   3.130 +	if (entry.delivery_mode == dest_SMI)
   3.131 +		return;
   3.132 +
   3.133 +	/*
   3.134 +	 * Disable it in the IO-APIC irq-routing table:
   3.135 +	 */
   3.136 +	memset(&entry, 0, sizeof(entry));
   3.137 +	entry.mask = 1;
   3.138 +	spin_lock_irqsave(&ioapic_lock, flags);
   3.139 +	io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
   3.140 +	io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
   3.141 +	spin_unlock_irqrestore(&ioapic_lock, flags);
   3.142 +}
   3.143 +
   3.144 +static void clear_IO_APIC (void)
   3.145 +{
   3.146 +	int apic, pin;
   3.147 +
   3.148 +	for (apic = 0; apic < nr_ioapics; apic++)
   3.149 +		for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
   3.150 +			clear_IO_APIC_pin(apic, pin);
   3.151 +}
   3.152 +
   3.153 +static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
   3.154 +{
   3.155 +	unsigned long flags;
   3.156 +	int pin;
   3.157 +	struct irq_pin_list *entry = irq_2_pin + irq;
   3.158 +	unsigned int apicid_value;
   3.159 +	
   3.160 +	apicid_value = cpu_mask_to_apicid(cpumask);
   3.161 +	/* Prepare to do the io_apic_write */
   3.162 +	apicid_value = apicid_value << 24;
   3.163 +	spin_lock_irqsave(&ioapic_lock, flags);
   3.164 +	for (;;) {
   3.165 +		pin = entry->pin;
   3.166 +		if (pin == -1)
   3.167 +			break;
   3.168 +		io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
   3.169 +		if (!entry->next)
   3.170 +			break;
   3.171 +		entry = irq_2_pin + entry->next;
   3.172 +	}
   3.173 +	spin_unlock_irqrestore(&ioapic_lock, flags);
   3.174 +}
   3.175 +
   3.176 +#if defined(CONFIG_IRQBALANCE)
   3.177 +# include <asm/processor.h>	/* kernel_thread() */
   3.178 +# include <linux/kernel_stat.h>	/* kstat */
   3.179 +# include <linux/slab.h>		/* kmalloc() */
   3.180 +# include <linux/timer.h>	/* time_after() */
   3.181 + 
   3.182 +# ifdef CONFIG_BALANCED_IRQ_DEBUG
   3.183 +#  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
   3.184 +#  define Dprintk(x...) do { TDprintk(x); } while (0)
   3.185 +# else
   3.186 +#  define TDprintk(x...) 
   3.187 +#  define Dprintk(x...) 
   3.188 +# endif
   3.189 +
   3.190 +cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
   3.191 +
   3.192 +#define IRQBALANCE_CHECK_ARCH -999
   3.193 +static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
   3.194 +static int physical_balance = 0;
   3.195 +
   3.196 +struct irq_cpu_info {
   3.197 +	unsigned long * last_irq;
   3.198 +	unsigned long * irq_delta;
   3.199 +	unsigned long irq;
   3.200 +} irq_cpu_data[NR_CPUS];
   3.201 +
   3.202 +#define CPU_IRQ(cpu)		(irq_cpu_data[cpu].irq)
   3.203 +#define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
   3.204 +#define IRQ_DELTA(cpu,irq) 	(irq_cpu_data[cpu].irq_delta[irq])
   3.205 +
   3.206 +#define IDLE_ENOUGH(cpu,now) \
   3.207 +		(idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
   3.208 +
   3.209 +#define IRQ_ALLOWED(cpu, allowed_mask)	cpu_isset(cpu, allowed_mask)
   3.210 +
   3.211 +#define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
   3.212 +
   3.213 +#define MAX_BALANCED_IRQ_INTERVAL	(5*HZ)
   3.214 +#define MIN_BALANCED_IRQ_INTERVAL	(HZ/2)
   3.215 +#define BALANCED_IRQ_MORE_DELTA		(HZ/10)
   3.216 +#define BALANCED_IRQ_LESS_DELTA		(HZ)
   3.217 +
   3.218 +long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
   3.219 +
   3.220 +static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
   3.221 +			unsigned long now, int direction)
   3.222 +{
   3.223 +	int search_idle = 1;
   3.224 +	int cpu = curr_cpu;
   3.225 +
   3.226 +	goto inside;
   3.227 +
   3.228 +	do {
   3.229 +		if (unlikely(cpu == curr_cpu))
   3.230 +			search_idle = 0;
   3.231 +inside:
   3.232 +		if (direction == 1) {
   3.233 +			cpu++;
   3.234 +			if (cpu >= NR_CPUS)
   3.235 +				cpu = 0;
   3.236 +		} else {
   3.237 +			cpu--;
   3.238 +			if (cpu == -1)
   3.239 +				cpu = NR_CPUS-1;
   3.240 +		}
   3.241 +	} while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
   3.242 +			(search_idle && !IDLE_ENOUGH(cpu,now)));
   3.243 +
   3.244 +	return cpu;
   3.245 +}
   3.246 +
   3.247 +static inline void balance_irq(int cpu, int irq)
   3.248 +{
   3.249 +	unsigned long now = jiffies;
   3.250 +	cpumask_t allowed_mask;
   3.251 +	unsigned int new_cpu;
   3.252 +		
   3.253 +	if (irqbalance_disabled)
   3.254 +		return; 
   3.255 +
   3.256 +	cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
   3.257 +	new_cpu = move(cpu, allowed_mask, now, 1);
   3.258 +	if (cpu != new_cpu) {
   3.259 +		irq_desc_t *desc = irq_desc + irq;
   3.260 +		unsigned long flags;
   3.261 +
   3.262 +		spin_lock_irqsave(&desc->lock, flags);
   3.263 +		pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
   3.264 +		spin_unlock_irqrestore(&desc->lock, flags);
   3.265 +	}
   3.266 +}
   3.267 +
   3.268 +static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
   3.269 +{
   3.270 +	int i, j;
   3.271 +	Dprintk("Rotating IRQs among CPUs.\n");
   3.272 +	for (i = 0; i < NR_CPUS; i++) {
   3.273 +		for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
   3.274 +			if (!irq_desc[j].action)
   3.275 +				continue;
   3.276 +			/* Is it a significant load ?  */
   3.277 +			if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
   3.278 +						useful_load_threshold)
   3.279 +				continue;
   3.280 +			balance_irq(i, j);
   3.281 +		}
   3.282 +	}
   3.283 +	balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
   3.284 +		balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);	
   3.285 +	return;
   3.286 +}
   3.287 +
   3.288 +static void do_irq_balance(void)
   3.289 +{
   3.290 +	int i, j;
   3.291 +	unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
   3.292 +	unsigned long move_this_load = 0;
   3.293 +	int max_loaded = 0, min_loaded = 0;
   3.294 +	int load;
   3.295 +	unsigned long useful_load_threshold = balanced_irq_interval + 10;
   3.296 +	int selected_irq;
   3.297 +	int tmp_loaded, first_attempt = 1;
   3.298 +	unsigned long tmp_cpu_irq;
   3.299 +	unsigned long imbalance = 0;
   3.300 +	cpumask_t allowed_mask, target_cpu_mask, tmp;
   3.301 +
   3.302 +	for (i = 0; i < NR_CPUS; i++) {
   3.303 +		int package_index;
   3.304 +		CPU_IRQ(i) = 0;
   3.305 +		if (!cpu_online(i))
   3.306 +			continue;
   3.307 +		package_index = CPU_TO_PACKAGEINDEX(i);
   3.308 +		for (j = 0; j < NR_IRQS; j++) {
   3.309 +			unsigned long value_now, delta;
   3.310 +			/* Is this an active IRQ? */
   3.311 +			if (!irq_desc[j].action)
   3.312 +				continue;
   3.313 +			if ( package_index == i )
   3.314 +				IRQ_DELTA(package_index,j) = 0;
   3.315 +			/* Determine the total count per processor per IRQ */
   3.316 +			value_now = (unsigned long) kstat_cpu(i).irqs[j];
   3.317 +
   3.318 +			/* Determine the activity per processor per IRQ */
   3.319 +			delta = value_now - LAST_CPU_IRQ(i,j);
   3.320 +
   3.321 +			/* Update last_cpu_irq[][] for the next time */
   3.322 +			LAST_CPU_IRQ(i,j) = value_now;
   3.323 +
   3.324 +			/* Ignore IRQs whose rate is less than the clock */
   3.325 +			if (delta < useful_load_threshold)
   3.326 +				continue;
   3.327 +			/* update the load for the processor or package total */
   3.328 +			IRQ_DELTA(package_index,j) += delta;
   3.329 +
   3.330 +			/* Keep track of the higher numbered sibling as well */
   3.331 +			if (i != package_index)
   3.332 +				CPU_IRQ(i) += delta;
   3.333 +			/*
   3.334 +			 * We have sibling A and sibling B in the package
   3.335 +			 *
   3.336 +			 * cpu_irq[A] = load for cpu A + load for cpu B
   3.337 +			 * cpu_irq[B] = load for cpu B
   3.338 +			 */
   3.339 +			CPU_IRQ(package_index) += delta;
   3.340 +		}
   3.341 +	}
   3.342 +	/* Find the least loaded processor package */
   3.343 +	for (i = 0; i < NR_CPUS; i++) {
   3.344 +		if (!cpu_online(i))
   3.345 +			continue;
   3.346 +		if (i != CPU_TO_PACKAGEINDEX(i))
   3.347 +			continue;
   3.348 +		if (min_cpu_irq > CPU_IRQ(i)) {
   3.349 +			min_cpu_irq = CPU_IRQ(i);
   3.350 +			min_loaded = i;
   3.351 +		}
   3.352 +	}
   3.353 +	max_cpu_irq = ULONG_MAX;
   3.354 +
   3.355 +tryanothercpu:
   3.356 +	/* Look for heaviest loaded processor.
   3.357 +	 * We may come back to get the next heaviest loaded processor.
   3.358 +	 * Skip processors with trivial loads.
   3.359 +	 */
   3.360 +	tmp_cpu_irq = 0;
   3.361 +	tmp_loaded = -1;
   3.362 +	for (i = 0; i < NR_CPUS; i++) {
   3.363 +		if (!cpu_online(i))
   3.364 +			continue;
   3.365 +		if (i != CPU_TO_PACKAGEINDEX(i))
   3.366 +			continue;
   3.367 +		if (max_cpu_irq <= CPU_IRQ(i)) 
   3.368 +			continue;
   3.369 +		if (tmp_cpu_irq < CPU_IRQ(i)) {
   3.370 +			tmp_cpu_irq = CPU_IRQ(i);
   3.371 +			tmp_loaded = i;
   3.372 +		}
   3.373 +	}
   3.374 +
   3.375 +	if (tmp_loaded == -1) {
   3.376 + 	 /* In the case of small number of heavy interrupt sources, 
   3.377 +	  * loading some of the cpus too much. We use Ingo's original 
   3.378 +	  * approach to rotate them around.
   3.379 +	  */
   3.380 +		if (!first_attempt && imbalance >= useful_load_threshold) {
   3.381 +			rotate_irqs_among_cpus(useful_load_threshold);
   3.382 +			return;
   3.383 +		}
   3.384 +		goto not_worth_the_effort;
   3.385 +	}
   3.386 +	
   3.387 +	first_attempt = 0;		/* heaviest search */
   3.388 +	max_cpu_irq = tmp_cpu_irq;	/* load */
   3.389 +	max_loaded = tmp_loaded;	/* processor */
   3.390 +	imbalance = (max_cpu_irq - min_cpu_irq) / 2;
   3.391 +	
   3.392 +	Dprintk("max_loaded cpu = %d\n", max_loaded);
   3.393 +	Dprintk("min_loaded cpu = %d\n", min_loaded);
   3.394 +	Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
   3.395 +	Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
   3.396 +	Dprintk("load imbalance = %lu\n", imbalance);
   3.397 +
   3.398 +	/* if imbalance is less than approx 10% of max load, then
   3.399 +	 * observe diminishing returns action. - quit
   3.400 +	 */
   3.401 +	if (imbalance < (max_cpu_irq >> 3)) {
   3.402 +		Dprintk("Imbalance too trivial\n");
   3.403 +		goto not_worth_the_effort;
   3.404 +	}
   3.405 +
   3.406 +tryanotherirq:
   3.407 +	/* if we select an IRQ to move that can't go where we want, then
   3.408 +	 * see if there is another one to try.
   3.409 +	 */
   3.410 +	move_this_load = 0;
   3.411 +	selected_irq = -1;
   3.412 +	for (j = 0; j < NR_IRQS; j++) {
   3.413 +		/* Is this an active IRQ? */
   3.414 +		if (!irq_desc[j].action)
   3.415 +			continue;
   3.416 +		if (imbalance <= IRQ_DELTA(max_loaded,j))
   3.417 +			continue;
   3.418 +		/* Try to find the IRQ that is closest to the imbalance
   3.419 +		 * without going over.
   3.420 +		 */
   3.421 +		if (move_this_load < IRQ_DELTA(max_loaded,j)) {
   3.422 +			move_this_load = IRQ_DELTA(max_loaded,j);
   3.423 +			selected_irq = j;
   3.424 +		}
   3.425 +	}
   3.426 +	if (selected_irq == -1) {
   3.427 +		goto tryanothercpu;
   3.428 +	}
   3.429 +
   3.430 +	imbalance = move_this_load;
   3.431 +	
   3.432 +	/* For physical_balance case, we accumlated both load
   3.433 +	 * values in the one of the siblings cpu_irq[],
   3.434 +	 * to use the same code for physical and logical processors
   3.435 +	 * as much as possible. 
   3.436 +	 *
   3.437 +	 * NOTE: the cpu_irq[] array holds the sum of the load for
   3.438 +	 * sibling A and sibling B in the slot for the lowest numbered
   3.439 +	 * sibling (A), _AND_ the load for sibling B in the slot for
   3.440 +	 * the higher numbered sibling.
   3.441 +	 *
   3.442 +	 * We seek the least loaded sibling by making the comparison
   3.443 +	 * (A+B)/2 vs B
   3.444 +	 */
   3.445 +	load = CPU_IRQ(min_loaded) >> 1;
   3.446 +	for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
   3.447 +		if (load > CPU_IRQ(j)) {
   3.448 +			/* This won't change cpu_sibling_map[min_loaded] */
   3.449 +			load = CPU_IRQ(j);
   3.450 +			min_loaded = j;
   3.451 +		}
   3.452 +	}
   3.453 +
   3.454 +	cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
   3.455 +	target_cpu_mask = cpumask_of_cpu(min_loaded);
   3.456 +	cpus_and(tmp, target_cpu_mask, allowed_mask);
   3.457 +
   3.458 +	if (!cpus_empty(tmp)) {
   3.459 +		irq_desc_t *desc = irq_desc + selected_irq;
   3.460 +		unsigned long flags;
   3.461 +
   3.462 +		Dprintk("irq = %d moved to cpu = %d\n",
   3.463 +				selected_irq, min_loaded);
   3.464 +		/* mark for change destination */
   3.465 +		spin_lock_irqsave(&desc->lock, flags);
   3.466 +		pending_irq_balance_cpumask[selected_irq] =
   3.467 +					cpumask_of_cpu(min_loaded);
   3.468 +		spin_unlock_irqrestore(&desc->lock, flags);
   3.469 +		/* Since we made a change, come back sooner to 
   3.470 +		 * check for more variation.
   3.471 +		 */
   3.472 +		balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
   3.473 +			balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);	
   3.474 +		return;
   3.475 +	}
   3.476 +	goto tryanotherirq;
   3.477 +
   3.478 +not_worth_the_effort:
   3.479 +	/*
   3.480 +	 * if we did not find an IRQ to move, then adjust the time interval
   3.481 +	 * upward
   3.482 +	 */
   3.483 +	balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
   3.484 +		balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);	
   3.485 +	Dprintk("IRQ worth rotating not found\n");
   3.486 +	return;
   3.487 +}
   3.488 +
   3.489 +static int balanced_irq(void *unused)
   3.490 +{
   3.491 +	int i;
   3.492 +	unsigned long prev_balance_time = jiffies;
   3.493 +	long time_remaining = balanced_irq_interval;
   3.494 +
   3.495 +	daemonize("kirqd");
   3.496 +	
   3.497 +	/* push everything to CPU 0 to give us a starting point.  */
   3.498 +	for (i = 0 ; i < NR_IRQS ; i++) {
   3.499 +		pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
   3.500 +	}
   3.501 +
   3.502 +	for ( ; ; ) {
   3.503 +		set_current_state(TASK_INTERRUPTIBLE);
   3.504 +		time_remaining = schedule_timeout(time_remaining);
   3.505 +		try_to_freeze(PF_FREEZE);
   3.506 +		if (time_after(jiffies,
   3.507 +				prev_balance_time+balanced_irq_interval)) {
   3.508 +			do_irq_balance();
   3.509 +			prev_balance_time = jiffies;
   3.510 +			time_remaining = balanced_irq_interval;
   3.511 +		}
   3.512 +	}
   3.513 +	return 0;
   3.514 +}
   3.515 +
   3.516 +static int __init balanced_irq_init(void)
   3.517 +{
   3.518 +	int i;
   3.519 +	struct cpuinfo_x86 *c;
   3.520 +	cpumask_t tmp;
   3.521 +
   3.522 +	cpus_shift_right(tmp, cpu_online_map, 2);
   3.523 +        c = &boot_cpu_data;
   3.524 +	/* When not overwritten by the command line ask subarchitecture. */
   3.525 +	if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
   3.526 +		irqbalance_disabled = NO_BALANCE_IRQ;
   3.527 +	if (irqbalance_disabled)
   3.528 +		return 0;
   3.529 +	
   3.530 +	 /* disable irqbalance completely if there is only one processor online */
   3.531 +	if (num_online_cpus() < 2) {
   3.532 +		irqbalance_disabled = 1;
   3.533 +		return 0;
   3.534 +	}
   3.535 +	/*
   3.536 +	 * Enable physical balance only if more than 1 physical processor
   3.537 +	 * is present
   3.538 +	 */
   3.539 +	if (smp_num_siblings > 1 && !cpus_empty(tmp))
   3.540 +		physical_balance = 1;
   3.541 +
   3.542 +	for (i = 0; i < NR_CPUS; i++) {
   3.543 +		if (!cpu_online(i))
   3.544 +			continue;
   3.545 +		irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
   3.546 +		irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
   3.547 +		if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
   3.548 +			printk(KERN_ERR "balanced_irq_init: out of memory");
   3.549 +			goto failed;
   3.550 +		}
   3.551 +		memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
   3.552 +		memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
   3.553 +	}
   3.554 +	
   3.555 +	printk(KERN_INFO "Starting balanced_irq\n");
   3.556 +	if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0) 
   3.557 +		return 0;
   3.558 +	else 
   3.559 +		printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
   3.560 +failed:
   3.561 +	for (i = 0; i < NR_CPUS; i++) {
   3.562 +		if(irq_cpu_data[i].irq_delta)
   3.563 +			kfree(irq_cpu_data[i].irq_delta);
   3.564 +		if(irq_cpu_data[i].last_irq)
   3.565 +			kfree(irq_cpu_data[i].last_irq);
   3.566 +	}
   3.567 +	return 0;
   3.568 +}
   3.569 +
   3.570 +int __init irqbalance_disable(char *str)
   3.571 +{
   3.572 +	irqbalance_disabled = 1;
   3.573 +	return 0;
   3.574 +}
   3.575 +
   3.576 +__setup("noirqbalance", irqbalance_disable);
   3.577 +
   3.578 +static inline void move_irq(int irq)
   3.579 +{
   3.580 +	/* note - we hold the desc->lock */
   3.581 +	if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
   3.582 +		set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
   3.583 +		cpus_clear(pending_irq_balance_cpumask[irq]);
   3.584 +	}
   3.585 +}
   3.586 +
   3.587 +late_initcall(balanced_irq_init);
   3.588 +
   3.589 +#else /* !CONFIG_IRQBALANCE */
   3.590 +static inline void move_irq(int irq) { }
   3.591 +#endif /* CONFIG_IRQBALANCE */
   3.592 +
   3.593 +#ifndef CONFIG_SMP
   3.594 +void fastcall send_IPI_self(int vector)
   3.595 +{
   3.596 +#if 1
   3.597 +	return;
   3.598 +#else
   3.599 +	unsigned int cfg;
   3.600 +
   3.601 +	/*
   3.602 +	 * Wait for idle.
   3.603 +	 */
   3.604 +	apic_wait_icr_idle();
   3.605 +	cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
   3.606 +	/*
   3.607 +	 * Send the IPI. The write to APIC_ICR fires this off.
   3.608 +	 */
   3.609 +	apic_write_around(APIC_ICR, cfg);
   3.610 +#endif
   3.611 +}
   3.612 +#endif /* !CONFIG_SMP */
   3.613 +
   3.614 +
   3.615 +/*
   3.616   * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
   3.617   * specific CPU-side IRQs.
   3.618   */
   3.619 @@ -138,6 +695,86 @@ static void add_pin_to_irq(unsigned int 
   3.620  #define MAX_PIRQS 8
   3.621  int pirq_entries [MAX_PIRQS];
   3.622  int pirqs_enabled;
   3.623 +int skip_ioapic_setup;
   3.624 +
   3.625 +static int __init ioapic_setup(char *str)
   3.626 +{
   3.627 +	skip_ioapic_setup = 1;
   3.628 +	return 1;
   3.629 +}
   3.630 +
   3.631 +__setup("noapic", ioapic_setup);
   3.632 +
   3.633 +static int __init ioapic_pirq_setup(char *str)
   3.634 +{
   3.635 +	int i, max;
   3.636 +	int ints[MAX_PIRQS+1];
   3.637 +
   3.638 +	get_options(str, ARRAY_SIZE(ints), ints);
   3.639 +
   3.640 +	for (i = 0; i < MAX_PIRQS; i++)
   3.641 +		pirq_entries[i] = -1;
   3.642 +
   3.643 +	pirqs_enabled = 1;
   3.644 +	apic_printk(APIC_VERBOSE, KERN_INFO
   3.645 +			"PIRQ redirection, working around broken MP-BIOS.\n");
   3.646 +	max = MAX_PIRQS;
   3.647 +	if (ints[0] < MAX_PIRQS)
   3.648 +		max = ints[0];
   3.649 +
   3.650 +	for (i = 0; i < max; i++) {
   3.651 +		apic_printk(APIC_VERBOSE, KERN_DEBUG
   3.652 +				"... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
   3.653 +		/*
   3.654 +		 * PIRQs are mapped upside down, usually.
   3.655 +		 */
   3.656 +		pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
   3.657 +	}
   3.658 +	return 1;
   3.659 +}
   3.660 +
   3.661 +__setup("pirq=", ioapic_pirq_setup);
   3.662 +
   3.663 +/*
   3.664 + * Find the IRQ entry number of a certain pin.
   3.665 + */
   3.666 +static int find_irq_entry(int apic, int pin, int type)
   3.667 +{
   3.668 +	int i;
   3.669 +
   3.670 +	for (i = 0; i < mp_irq_entries; i++)
   3.671 +		if (mp_irqs[i].mpc_irqtype == type &&
   3.672 +		    (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
   3.673 +		     mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
   3.674 +		    mp_irqs[i].mpc_dstirq == pin)
   3.675 +			return i;
   3.676 +
   3.677 +	return -1;
   3.678 +}
   3.679 +
   3.680 +/*
   3.681 + * Find the pin to which IRQ[irq] (ISA) is connected
   3.682 + */
   3.683 +static int find_isa_irq_pin(int irq, int type)
   3.684 +{
   3.685 +	int i;
   3.686 +
   3.687 +	for (i = 0; i < mp_irq_entries; i++) {
   3.688 +		int lbus = mp_irqs[i].mpc_srcbus;
   3.689 +
   3.690 +		if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
   3.691 +		     mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
   3.692 +		     mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
   3.693 +		     mp_bus_id_to_type[lbus] == MP_BUS_NEC98
   3.694 +		    ) &&
   3.695 +		    (mp_irqs[i].mpc_irqtype == type) &&
   3.696 +		    (mp_irqs[i].mpc_srcbusirq == irq))
   3.697 +
   3.698 +			return mp_irqs[i].mpc_dstirq;
   3.699 +	}
   3.700 +	return -1;
   3.701 +}
   3.702 +
   3.703  /*
   3.704   * Find a specific PCI IRQ entry.
   3.705   * Not an __init, possibly needed by modules
   3.706 @@ -184,6 +821,234 @@ int IO_APIC_get_PCI_irq_vector(int bus, 
   3.707  	return best_guess;
   3.708  }
   3.709  
   3.710 +/*
   3.711 + * This function currently is only a helper for the i386 smp boot process where 
   3.712 + * we need to reprogram the ioredtbls to cater for the cpus which have come online
   3.713 + * so mask in all cases should simply be TARGET_CPUS
   3.714 + */
   3.715 +void __init setup_ioapic_dest(void)
   3.716 +{
   3.717 +	int pin, ioapic, irq, irq_entry;
   3.718 +
   3.719 +	if (skip_ioapic_setup == 1)
   3.720 +		return;
   3.721 +
   3.722 +	for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
   3.723 +		for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
   3.724 +			irq_entry = find_irq_entry(ioapic, pin, mp_INT);
   3.725 +			if (irq_entry == -1)
   3.726 +				continue;
   3.727 +			irq = pin_2_irq(irq_entry, ioapic, pin);
   3.728 +			set_ioapic_affinity_irq(irq, TARGET_CPUS);
   3.729 +		}
   3.730 +
   3.731 +	}
   3.732 +}
   3.733 +
   3.734 +/*
   3.735 + * EISA Edge/Level control register, ELCR
   3.736 + */
   3.737 +static int EISA_ELCR(unsigned int irq)
   3.738 +{
   3.739 +	if (irq < 16) {
   3.740 +		unsigned int port = 0x4d0 + (irq >> 3);
   3.741 +		return (inb(port) >> (irq & 7)) & 1;
   3.742 +	}
   3.743 +	apic_printk(APIC_VERBOSE, KERN_INFO
   3.744 +			"Broken MPtable reports ISA irq %d\n", irq);
   3.745 +	return 0;
   3.746 +}
   3.747 +
   3.748 +/* EISA interrupts are always polarity zero and can be edge or level
   3.749 + * trigger depending on the ELCR value.  If an interrupt is listed as
   3.750 + * EISA conforming in the MP table, that means its trigger type must
   3.751 + * be read in from the ELCR */
   3.752 +
   3.753 +#define default_EISA_trigger(idx)	(EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
   3.754 +#define default_EISA_polarity(idx)	(0)
   3.755 +
   3.756 +/* ISA interrupts are always polarity zero edge triggered,
   3.757 + * when listed as conforming in the MP table. */
   3.758 +
   3.759 +#define default_ISA_trigger(idx)	(0)
   3.760 +#define default_ISA_polarity(idx)	(0)
   3.761 +
   3.762 +/* PCI interrupts are always polarity one level triggered,
   3.763 + * when listed as conforming in the MP table. */
   3.764 +
   3.765 +#define default_PCI_trigger(idx)	(1)
   3.766 +#define default_PCI_polarity(idx)	(1)
   3.767 +
   3.768 +/* MCA interrupts are always polarity zero level triggered,
   3.769 + * when listed as conforming in the MP table. */
   3.770 +
   3.771 +#define default_MCA_trigger(idx)	(1)
   3.772 +#define default_MCA_polarity(idx)	(0)
   3.773 +
   3.774 +/* NEC98 interrupts are always polarity zero edge triggered,
   3.775 + * when listed as conforming in the MP table. */
   3.776 +
   3.777 +#define default_NEC98_trigger(idx)     (0)
   3.778 +#define default_NEC98_polarity(idx)    (0)
   3.779 +
   3.780 +static int __init MPBIOS_polarity(int idx)
   3.781 +{
   3.782 +	int bus = mp_irqs[idx].mpc_srcbus;
   3.783 +	int polarity;
   3.784 +
   3.785 +	/*
   3.786 +	 * Determine IRQ line polarity (high active or low active):
   3.787 +	 */
   3.788 +	switch (mp_irqs[idx].mpc_irqflag & 3)
   3.789 +	{
   3.790 +		case 0: /* conforms, ie. bus-type dependent polarity */
   3.791 +		{
   3.792 +			switch (mp_bus_id_to_type[bus])
   3.793 +			{
   3.794 +				case MP_BUS_ISA: /* ISA pin */
   3.795 +				{
   3.796 +					polarity = default_ISA_polarity(idx);
   3.797 +					break;
   3.798 +				}
   3.799 +				case MP_BUS_EISA: /* EISA pin */
   3.800 +				{
   3.801 +					polarity = default_EISA_polarity(idx);
   3.802 +					break;
   3.803 +				}
   3.804 +				case MP_BUS_PCI: /* PCI pin */
   3.805 +				{
   3.806 +					polarity = default_PCI_polarity(idx);
   3.807 +					break;
   3.808 +				}
   3.809 +				case MP_BUS_MCA: /* MCA pin */
   3.810 +				{
   3.811 +					polarity = default_MCA_polarity(idx);
   3.812 +					break;
   3.813 +				}
   3.814 +				case MP_BUS_NEC98: /* NEC 98 pin */
   3.815 +				{
   3.816 +					polarity = default_NEC98_polarity(idx);
   3.817 +					break;
   3.818 +				}
   3.819 +				default:
   3.820 +				{
   3.821 +					printk(KERN_WARNING "broken BIOS!!\n");
   3.822 +					polarity = 1;
   3.823 +					break;
   3.824 +				}
   3.825 +			}
   3.826 +			break;
   3.827 +		}
   3.828 +		case 1: /* high active */
   3.829 +		{
   3.830 +			polarity = 0;
   3.831 +			break;
   3.832 +		}
   3.833 +		case 2: /* reserved */
   3.834 +		{
   3.835 +			printk(KERN_WARNING "broken BIOS!!\n");
   3.836 +			polarity = 1;
   3.837 +			break;
   3.838 +		}
   3.839 +		case 3: /* low active */
   3.840 +		{
   3.841 +			polarity = 1;
   3.842 +			break;
   3.843 +		}
   3.844 +		default: /* invalid */
   3.845 +		{
   3.846 +			printk(KERN_WARNING "broken BIOS!!\n");
   3.847 +			polarity = 1;
   3.848 +			break;
   3.849 +		}
   3.850 +	}
   3.851 +	return polarity;
   3.852 +}
   3.853 +
   3.854 +static int MPBIOS_trigger(int idx)
   3.855 +{
   3.856 +	int bus = mp_irqs[idx].mpc_srcbus;
   3.857 +	int trigger;
   3.858 +
   3.859 +	/*
   3.860 +	 * Determine IRQ trigger mode (edge or level sensitive):
   3.861 +	 */
   3.862 +	switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
   3.863 +	{
   3.864 +		case 0: /* conforms, ie. bus-type dependent */
   3.865 +		{
   3.866 +			switch (mp_bus_id_to_type[bus])
   3.867 +			{
   3.868 +				case MP_BUS_ISA: /* ISA pin */
   3.869 +				{
   3.870 +					trigger = default_ISA_trigger(idx);
   3.871 +					break;
   3.872 +				}
   3.873 +				case MP_BUS_EISA: /* EISA pin */
   3.874 +				{
   3.875 +					trigger = default_EISA_trigger(idx);
   3.876 +					break;
   3.877 +				}
   3.878 +				case MP_BUS_PCI: /* PCI pin */
   3.879 +				{
   3.880 +					trigger = default_PCI_trigger(idx);
   3.881 +					break;
   3.882 +				}
   3.883 +				case MP_BUS_MCA: /* MCA pin */
   3.884 +				{
   3.885 +					trigger = default_MCA_trigger(idx);
   3.886 +					break;
   3.887 +				}
   3.888 +				case MP_BUS_NEC98: /* NEC 98 pin */
   3.889 +				{
   3.890 +					trigger = default_NEC98_trigger(idx);
   3.891 +					break;
   3.892 +				}
   3.893 +				default:
   3.894 +				{
   3.895 +					printk(KERN_WARNING "broken BIOS!!\n");
   3.896 +					trigger = 1;
   3.897 +					break;
   3.898 +				}
   3.899 +			}
   3.900 +			break;
   3.901 +		}
   3.902 +		case 1: /* edge */
   3.903 +		{
   3.904 +			trigger = 0;
   3.905 +			break;
   3.906 +		}
   3.907 +		case 2: /* reserved */
   3.908 +		{
   3.909 +			printk(KERN_WARNING "broken BIOS!!\n");
   3.910 +			trigger = 1;
   3.911 +			break;
   3.912 +		}
   3.913 +		case 3: /* level */
   3.914 +		{
   3.915 +			trigger = 1;
   3.916 +			break;
   3.917 +		}
   3.918 +		default: /* invalid */
   3.919 +		{
   3.920 +			printk(KERN_WARNING "broken BIOS!!\n");
   3.921 +			trigger = 0;
   3.922 +			break;
   3.923 +		}
   3.924 +	}
   3.925 +	return trigger;
   3.926 +}
   3.927 +
   3.928 +static inline int irq_polarity(int idx)
   3.929 +{
   3.930 +	return MPBIOS_polarity(idx);
   3.931 +}
   3.932 +
   3.933 +static inline int irq_trigger(int idx)
   3.934 +{
   3.935 +	return MPBIOS_trigger(idx);
   3.936 +}
   3.937 +
   3.938  static int pin_2_irq(int idx, int apic, int pin)
   3.939  {
   3.940  	int irq, i;
   3.941 @@ -250,26 +1115,41 @@ static int pin_2_irq(int idx, int apic, 
   3.942  	return irq;
   3.943  }
   3.944  
   3.945 +static inline int IO_APIC_irq_trigger(int irq)
   3.946 +{
   3.947 +	int apic, idx, pin;
   3.948 +
   3.949 +	for (apic = 0; apic < nr_ioapics; apic++) {
   3.950 +		for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
   3.951 +			idx = find_irq_entry(apic,pin,mp_INT);
   3.952 +			if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
   3.953 +				return irq_trigger(idx);
   3.954 +		}
   3.955 +	}
   3.956 +	/*
   3.957 +	 * nonexistent IRQs are edge default
   3.958 +	 */
   3.959 +	return 0;
   3.960 +}
   3.961 +
   3.962  /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
   3.963  u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
   3.964  
   3.965  int assign_irq_vector(int irq)
   3.966  {
   3.967  	static int current_vector = FIRST_DEVICE_VECTOR;
   3.968 -        physdev_op_t op;
   3.969 -        int ret;
   3.970 +	physdev_op_t op;
   3.971  
   3.972  	BUG_ON(irq >= NR_IRQ_VECTORS);
   3.973  	if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
   3.974  		return IO_APIC_VECTOR(irq);
   3.975  
   3.976 -        op.cmd = PHYSDEVOP_ASSIGN_VECTOR;
   3.977 -        op.u.irq_op.irq = irq;
   3.978 -        ret = HYPERVISOR_physdev_op(&op);
   3.979 -        if (ret)
   3.980 -            return -ENOSPC;
   3.981 +	op.cmd = PHYSDEVOP_ASSIGN_VECTOR;
   3.982 +	op.u.irq_op.irq = irq;
   3.983 +	if (HYPERVISOR_physdev_op(&op))
   3.984 +		return -ENOSPC;
   3.985 +	current_vector = op.u.irq_op.vector;
   3.986  
   3.987 -        current_vector = op.u.irq_op.vector;
   3.988  	vector_irq[current_vector] = irq;
   3.989  	if (irq != AUTO_ASSIGN)
   3.990  		IO_APIC_VECTOR(irq) = current_vector;
   3.991 @@ -277,12 +1157,1271 @@ int assign_irq_vector(int irq)
   3.992  	return current_vector;
   3.993  }
   3.994  
   3.995 +static struct hw_interrupt_type ioapic_level_type;
   3.996 +static struct hw_interrupt_type ioapic_edge_type;
   3.997 +
   3.998 +#define IOAPIC_AUTO	-1
   3.999 +#define IOAPIC_EDGE	0
  3.1000 +#define IOAPIC_LEVEL	1
  3.1001 +
  3.1002 +static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
  3.1003 +{
  3.1004 +	if (use_pci_vector() && !platform_legacy_irq(irq)) {
  3.1005 +		if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
  3.1006 +				trigger == IOAPIC_LEVEL)
  3.1007 +			irq_desc[vector].handler = &ioapic_level_type;
  3.1008 +		else
  3.1009 +			irq_desc[vector].handler = &ioapic_edge_type;
  3.1010 +#if 0
  3.1011 +		set_intr_gate(vector, interrupt[vector]);
  3.1012 +#endif
  3.1013 +	} else	{
  3.1014 +		if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
  3.1015 +				trigger == IOAPIC_LEVEL)
  3.1016 +			irq_desc[irq].handler = &ioapic_level_type;
  3.1017 +		else
  3.1018 +			irq_desc[irq].handler = &ioapic_edge_type;
  3.1019 +#if 0
  3.1020 +		set_intr_gate(vector, interrupt[irq]);
  3.1021 +#endif
  3.1022 +	}
  3.1023 +}
  3.1024 +
  3.1025 +void __init setup_IO_APIC_irqs(void)
  3.1026 +{
  3.1027 +	struct IO_APIC_route_entry entry;
  3.1028 +	int apic, pin, idx, irq, first_notcon = 1, vector;
  3.1029 +	unsigned long flags;
  3.1030 +
  3.1031 +	apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
  3.1032 +
  3.1033 +	for (apic = 0; apic < nr_ioapics; apic++) {
  3.1034 +	for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
  3.1035 +
  3.1036 +		/*
  3.1037 +		 * add it to the IO-APIC irq-routing table:
  3.1038 +		 */
  3.1039 +		memset(&entry,0,sizeof(entry));
  3.1040 +
  3.1041 +		entry.delivery_mode = INT_DELIVERY_MODE;
  3.1042 +		entry.dest_mode = INT_DEST_MODE;
  3.1043 +		entry.mask = 0;				/* enable IRQ */
  3.1044 +		entry.dest.logical.logical_dest = 
  3.1045 +					cpu_mask_to_apicid(TARGET_CPUS);
  3.1046 +
  3.1047 +		idx = find_irq_entry(apic,pin,mp_INT);
  3.1048 +		if (idx == -1) {
  3.1049 +			if (first_notcon) {
  3.1050 +				apic_printk(APIC_VERBOSE, KERN_DEBUG
  3.1051 +						" IO-APIC (apicid-pin) %d-%d",
  3.1052 +						mp_ioapics[apic].mpc_apicid,
  3.1053 +						pin);
  3.1054 +				first_notcon = 0;
  3.1055 +			} else
  3.1056 +				apic_printk(APIC_VERBOSE, ", %d-%d",
  3.1057 +					mp_ioapics[apic].mpc_apicid, pin);
  3.1058 +			continue;
  3.1059 +		}
  3.1060 +
  3.1061 +		entry.trigger = irq_trigger(idx);
  3.1062 +		entry.polarity = irq_polarity(idx);
  3.1063 +
  3.1064 +		if (irq_trigger(idx)) {
  3.1065 +			entry.trigger = 1;
  3.1066 +			entry.mask = 1;
  3.1067 +		}
  3.1068 +
  3.1069 +		irq = pin_2_irq(idx, apic, pin);
  3.1070 +		/*
  3.1071 +		 * skip adding the timer int on secondary nodes, which causes
  3.1072 +		 * a small but painful rift in the time-space continuum
  3.1073 +		 */
  3.1074 +		if (multi_timer_check(apic, irq))
  3.1075 +			continue;
  3.1076 +		else
  3.1077 +			add_pin_to_irq(irq, apic, pin);
  3.1078 +
  3.1079 +		if (!apic && !IO_APIC_IRQ(irq))
  3.1080 +			continue;
  3.1081 +
  3.1082 +		if (IO_APIC_IRQ(irq)) {
  3.1083 +			vector = assign_irq_vector(irq);
  3.1084 +			entry.vector = vector;
  3.1085 +			ioapic_register_intr(irq, vector, IOAPIC_AUTO);
  3.1086 +		
  3.1087 +#if 0
  3.1088 +			if (!apic && (irq < 16))
  3.1089 +				disable_8259A_irq(irq);
  3.1090 +#endif
  3.1091 +		}
  3.1092 +		spin_lock_irqsave(&ioapic_lock, flags);
  3.1093 +		io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
  3.1094 +		io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
  3.1095 +		spin_unlock_irqrestore(&ioapic_lock, flags);
  3.1096 +	}
  3.1097 +	}
  3.1098 +
  3.1099 +	if (!first_notcon)
  3.1100 +		apic_printk(APIC_VERBOSE, " not connected.\n");
  3.1101 +}
  3.1102 +
  3.1103 +/*
  3.1104 + * Set up the 8259A-master output pin:
  3.1105 + */
  3.1106 +void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
  3.1107 +{
  3.1108 +	struct IO_APIC_route_entry entry;
  3.1109 +	unsigned long flags;
  3.1110 +
  3.1111 +	memset(&entry,0,sizeof(entry));
  3.1112 +
  3.1113 +#if 0
  3.1114 +	disable_8259A_irq(0);
  3.1115 +#endif
  3.1116 +
  3.1117 +	/* mask LVT0 */
  3.1118 +	apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
  3.1119 +
  3.1120 +	/*
  3.1121 +	 * We use logical delivery to get the timer IRQ
  3.1122 +	 * to the first CPU.
  3.1123 +	 */
  3.1124 +	entry.dest_mode = INT_DEST_MODE;
  3.1125 +	entry.mask = 0;					/* unmask IRQ now */
  3.1126 +	entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
  3.1127 +	entry.delivery_mode = INT_DELIVERY_MODE;
  3.1128 +	entry.polarity = 0;
  3.1129 +	entry.trigger = 0;
  3.1130 +	entry.vector = vector;
  3.1131 +
  3.1132 +	/*
  3.1133 +	 * The timer IRQ doesn't have to know that behind the
  3.1134 +	 * scene we have a 8259A-master in AEOI mode ...
  3.1135 +	 */
  3.1136 +	irq_desc[0].handler = &ioapic_edge_type;
  3.1137 +
  3.1138 +	/*
  3.1139 +	 * Add it to the IO-APIC irq-routing table:
  3.1140 +	 */
  3.1141 +	spin_lock_irqsave(&ioapic_lock, flags);
  3.1142 +	io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
  3.1143 +	io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
  3.1144 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  3.1145 +
  3.1146 +#if 0
  3.1147 +	enable_8259A_irq(0);
  3.1148 +#endif
  3.1149 +}
  3.1150 +
  3.1151 +static inline void UNEXPECTED_IO_APIC(void)
  3.1152 +{
  3.1153 +}
  3.1154 +
  3.1155 +void __init print_IO_APIC(void)
  3.1156 +{
  3.1157 +	int apic, i;
  3.1158 +	union IO_APIC_reg_00 reg_00;
  3.1159 +	union IO_APIC_reg_01 reg_01;
  3.1160 +	union IO_APIC_reg_02 reg_02;
  3.1161 +	union IO_APIC_reg_03 reg_03;
  3.1162 +	unsigned long flags;
  3.1163 +
  3.1164 +	if (apic_verbosity == APIC_QUIET)
  3.1165 +		return;
  3.1166 +
  3.1167 + 	printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
  3.1168 +	for (i = 0; i < nr_ioapics; i++)
  3.1169 +		printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
  3.1170 +		       mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
  3.1171 +
  3.1172 +	/*
  3.1173 +	 * We are a bit conservative about what we expect.  We have to
  3.1174 +	 * know about every hardware change ASAP.
  3.1175 +	 */
  3.1176 +	printk(KERN_INFO "testing the IO APIC.......................\n");
  3.1177 +
  3.1178 +	for (apic = 0; apic < nr_ioapics; apic++) {
  3.1179 +
  3.1180 +	spin_lock_irqsave(&ioapic_lock, flags);
  3.1181 +	reg_00.raw = io_apic_read(apic, 0);
  3.1182 +	reg_01.raw = io_apic_read(apic, 1);
  3.1183 +	if (reg_01.bits.version >= 0x10)
  3.1184 +		reg_02.raw = io_apic_read(apic, 2);
  3.1185 +	if (reg_01.bits.version >= 0x20)
  3.1186 +		reg_03.raw = io_apic_read(apic, 3);
  3.1187 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  3.1188 +
  3.1189 +	printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
  3.1190 +	printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
  3.1191 +	printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
  3.1192 +	printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
  3.1193 +	printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
  3.1194 +	if (reg_00.bits.ID >= get_physical_broadcast())
  3.1195 +		UNEXPECTED_IO_APIC();
  3.1196 +	if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
  3.1197 +		UNEXPECTED_IO_APIC();
  3.1198 +
  3.1199 +	printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
  3.1200 +	printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
  3.1201 +	if (	(reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
  3.1202 +		(reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
  3.1203 +		(reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
  3.1204 +		(reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
  3.1205 +		(reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
  3.1206 +		(reg_01.bits.entries != 0x2E) &&
  3.1207 +		(reg_01.bits.entries != 0x3F)
  3.1208 +	)
  3.1209 +		UNEXPECTED_IO_APIC();
  3.1210 +
  3.1211 +	printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
  3.1212 +	printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
  3.1213 +	if (	(reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
  3.1214 +		(reg_01.bits.version != 0x10) && /* oldest IO-APICs */
  3.1215 +		(reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
  3.1216 +		(reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
  3.1217 +		(reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
  3.1218 +	)
  3.1219 +		UNEXPECTED_IO_APIC();
  3.1220 +	if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
  3.1221 +		UNEXPECTED_IO_APIC();
  3.1222 +
  3.1223 +	/*
  3.1224 +	 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
  3.1225 +	 * but the value of reg_02 is read as the previous read register
  3.1226 +	 * value, so ignore it if reg_02 == reg_01.
  3.1227 +	 */
  3.1228 +	if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
  3.1229 +		printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
  3.1230 +		printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
  3.1231 +		if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
  3.1232 +			UNEXPECTED_IO_APIC();
  3.1233 +	}
  3.1234 +
  3.1235 +	/*
  3.1236 +	 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
  3.1237 +	 * or reg_03, but the value of reg_0[23] is read as the previous read
  3.1238 +	 * register value, so ignore it if reg_03 == reg_0[12].
  3.1239 +	 */
  3.1240 +	if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
  3.1241 +	    reg_03.raw != reg_01.raw) {
  3.1242 +		printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
  3.1243 +		printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
  3.1244 +		if (reg_03.bits.__reserved_1)
  3.1245 +			UNEXPECTED_IO_APIC();
  3.1246 +	}
  3.1247 +
  3.1248 +	printk(KERN_DEBUG ".... IRQ redirection table:\n");
  3.1249 +
  3.1250 +	printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
  3.1251 +			  " Stat Dest Deli Vect:   \n");
  3.1252 +
  3.1253 +	for (i = 0; i <= reg_01.bits.entries; i++) {
  3.1254 +		struct IO_APIC_route_entry entry;
  3.1255 +
  3.1256 +		spin_lock_irqsave(&ioapic_lock, flags);
  3.1257 +		*(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
  3.1258 +		*(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
  3.1259 +		spin_unlock_irqrestore(&ioapic_lock, flags);
  3.1260 +
  3.1261 +		printk(KERN_DEBUG " %02x %03X %02X  ",
  3.1262 +			i,
  3.1263 +			entry.dest.logical.logical_dest,
  3.1264 +			entry.dest.physical.physical_dest
  3.1265 +		);
  3.1266 +
  3.1267 +		printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
  3.1268 +			entry.mask,
  3.1269 +			entry.trigger,
  3.1270 +			entry.irr,
  3.1271 +			entry.polarity,
  3.1272 +			entry.delivery_status,
  3.1273 +			entry.dest_mode,
  3.1274 +			entry.delivery_mode,
  3.1275 +			entry.vector
  3.1276 +		);
  3.1277 +	}
  3.1278 +	}
  3.1279 +	if (use_pci_vector())
  3.1280 +		printk(KERN_INFO "Using vector-based indexing\n");
  3.1281 +	printk(KERN_DEBUG "IRQ to pin mappings:\n");
  3.1282 +	for (i = 0; i < NR_IRQS; i++) {
  3.1283 +		struct irq_pin_list *entry = irq_2_pin + i;
  3.1284 +		if (entry->pin < 0)
  3.1285 +			continue;
  3.1286 + 		if (use_pci_vector() && !platform_legacy_irq(i))
  3.1287 +			printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
  3.1288 +		else
  3.1289 +			printk(KERN_DEBUG "IRQ%d ", i);
  3.1290 +		for (;;) {
  3.1291 +			printk("-> %d:%d", entry->apic, entry->pin);
  3.1292 +			if (!entry->next)
  3.1293 +				break;
  3.1294 +			entry = irq_2_pin + entry->next;
  3.1295 +		}
  3.1296 +		printk("\n");
  3.1297 +	}
  3.1298 +
  3.1299 +	printk(KERN_INFO ".................................... done.\n");
  3.1300 +
  3.1301 +	return;
  3.1302 +}
  3.1303 +
  3.1304 +static void print_APIC_bitfield (int base)
  3.1305 +{
  3.1306 +	unsigned int v;
  3.1307 +	int i, j;
  3.1308 +
  3.1309 +	if (apic_verbosity == APIC_QUIET)
  3.1310 +		return;
  3.1311 +
  3.1312 +	printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
  3.1313 +	for (i = 0; i < 8; i++) {
  3.1314 +		v = apic_read(base + i*0x10);
  3.1315 +		for (j = 0; j < 32; j++) {
  3.1316 +			if (v & (1<<j))
  3.1317 +				printk("1");
  3.1318 +			else
  3.1319 +				printk("0");
  3.1320 +		}
  3.1321 +		printk("\n");
  3.1322 +	}
  3.1323 +}
  3.1324 +
  3.1325 +void /*__init*/ print_local_APIC(void * dummy)
  3.1326 +{
  3.1327 +#if 0
  3.1328 +	unsigned int v, ver, maxlvt;
  3.1329 +
  3.1330 +	if (apic_verbosity == APIC_QUIET)
  3.1331 +		return;
  3.1332 +
  3.1333 +	printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
  3.1334 +		smp_processor_id(), hard_smp_processor_id());
  3.1335 +	v = apic_read(APIC_ID);
  3.1336 +	printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
  3.1337 +	v = apic_read(APIC_LVR);
  3.1338 +	printk(KERN_INFO "... APIC VERSION: %08x\n", v);
  3.1339 +	ver = GET_APIC_VERSION(v);
  3.1340 +	maxlvt = get_maxlvt();
  3.1341 +
  3.1342 +	v = apic_read(APIC_TASKPRI);
  3.1343 +	printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
  3.1344 +
  3.1345 +	if (APIC_INTEGRATED(ver)) {			/* !82489DX */
  3.1346 +		v = apic_read(APIC_ARBPRI);
  3.1347 +		printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
  3.1348 +			v & APIC_ARBPRI_MASK);
  3.1349 +		v = apic_read(APIC_PROCPRI);
  3.1350 +		printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
  3.1351 +	}
  3.1352 +
  3.1353 +	v = apic_read(APIC_EOI);
  3.1354 +	printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
  3.1355 +	v = apic_read(APIC_RRR);
  3.1356 +	printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
  3.1357 +	v = apic_read(APIC_LDR);
  3.1358 +	printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
  3.1359 +	v = apic_read(APIC_DFR);
  3.1360 +	printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
  3.1361 +	v = apic_read(APIC_SPIV);
  3.1362 +	printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
  3.1363 +
  3.1364 +	printk(KERN_DEBUG "... APIC ISR field:\n");
  3.1365 +	print_APIC_bitfield(APIC_ISR);
  3.1366 +	printk(KERN_DEBUG "... APIC TMR field:\n");
  3.1367 +	print_APIC_bitfield(APIC_TMR);
  3.1368 +	printk(KERN_DEBUG "... APIC IRR field:\n");
  3.1369 +	print_APIC_bitfield(APIC_IRR);
  3.1370 +
  3.1371 +	if (APIC_INTEGRATED(ver)) {		/* !82489DX */
  3.1372 +		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
  3.1373 +			apic_write(APIC_ESR, 0);
  3.1374 +		v = apic_read(APIC_ESR);
  3.1375 +		printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
  3.1376 +	}
  3.1377 +
  3.1378 +	v = apic_read(APIC_ICR);
  3.1379 +	printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
  3.1380 +	v = apic_read(APIC_ICR2);
  3.1381 +	printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
  3.1382 +
  3.1383 +	v = apic_read(APIC_LVTT);
  3.1384 +	printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
  3.1385 +
  3.1386 +	if (maxlvt > 3) {                       /* PC is LVT#4. */
  3.1387 +		v = apic_read(APIC_LVTPC);
  3.1388 +		printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
  3.1389 +	}
  3.1390 +	v = apic_read(APIC_LVT0);
  3.1391 +	printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
  3.1392 +	v = apic_read(APIC_LVT1);
  3.1393 +	printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
  3.1394 +
  3.1395 +	if (maxlvt > 2) {			/* ERR is LVT#3. */
  3.1396 +		v = apic_read(APIC_LVTERR);
  3.1397 +		printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
  3.1398 +	}
  3.1399 +
  3.1400 +	v = apic_read(APIC_TMICT);
  3.1401 +	printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
  3.1402 +	v = apic_read(APIC_TMCCT);
  3.1403 +	printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
  3.1404 +	v = apic_read(APIC_TDCR);
  3.1405 +	printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
  3.1406 +	printk("\n");
  3.1407 +#endif
  3.1408 +}
  3.1409 +
  3.1410 +void print_all_local_APICs (void)
  3.1411 +{
  3.1412 +	on_each_cpu(print_local_APIC, NULL, 1, 1);
  3.1413 +}
  3.1414 +
  3.1415 +void /*__init*/ print_PIC(void)
  3.1416 +{
  3.1417 +	extern spinlock_t i8259A_lock;
  3.1418 +	unsigned int v;
  3.1419 +	unsigned long flags;
  3.1420 +
  3.1421 +	if (apic_verbosity == APIC_QUIET)
  3.1422 +		return;
  3.1423 +
  3.1424 +	printk(KERN_DEBUG "\nprinting PIC contents\n");
  3.1425 +
  3.1426 +	spin_lock_irqsave(&i8259A_lock, flags);
  3.1427 +
  3.1428 +	v = inb(0xa1) << 8 | inb(0x21);
  3.1429 +	printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
  3.1430 +
  3.1431 +	v = inb(0xa0) << 8 | inb(0x20);
  3.1432 +	printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
  3.1433 +
  3.1434 +	outb(0x0b,0xa0);
  3.1435 +	outb(0x0b,0x20);
  3.1436 +	v = inb(0xa0) << 8 | inb(0x20);
  3.1437 +	outb(0x0a,0xa0);
  3.1438 +	outb(0x0a,0x20);
  3.1439 +
  3.1440 +	spin_unlock_irqrestore(&i8259A_lock, flags);
  3.1441 +
  3.1442 +	printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
  3.1443 +
  3.1444 +	v = inb(0x4d1) << 8 | inb(0x4d0);
  3.1445 +	printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
  3.1446 +}
  3.1447 +
  3.1448 +static void __init enable_IO_APIC(void)
  3.1449 +{
  3.1450 +	union IO_APIC_reg_01 reg_01;
  3.1451 +	int i;
  3.1452 +	unsigned long flags;
  3.1453 +
  3.1454 +	for (i = 0; i < PIN_MAP_SIZE; i++) {
  3.1455 +		irq_2_pin[i].pin = -1;
  3.1456 +		irq_2_pin[i].next = 0;
  3.1457 +	}
  3.1458 +	if (!pirqs_enabled)
  3.1459 +		for (i = 0; i < MAX_PIRQS; i++)
  3.1460 +			pirq_entries[i] = -1;
  3.1461 +
  3.1462 +	/*
  3.1463 +	 * The number of IO-APIC IRQ registers (== #pins):
  3.1464 +	 */
  3.1465 +	for (i = 0; i < nr_ioapics; i++) {
  3.1466 +		spin_lock_irqsave(&ioapic_lock, flags);
  3.1467 +		reg_01.raw = io_apic_read(i, 1);
  3.1468 +		spin_unlock_irqrestore(&ioapic_lock, flags);
  3.1469 +		nr_ioapic_registers[i] = reg_01.bits.entries+1;
  3.1470 +	}
  3.1471 +
  3.1472 +	/*
  3.1473 +	 * Do not trust the IO-APIC being empty at bootup
  3.1474 +	 */
  3.1475 +	clear_IO_APIC();
  3.1476 +}
  3.1477 +
  3.1478 +/*
  3.1479 + * Not an __init, needed by the reboot code
  3.1480 + */
  3.1481 +void disable_IO_APIC(void)
  3.1482 +{
  3.1483 +	/*
  3.1484 +	 * Clear the IO-APIC before rebooting:
  3.1485 +	 */
  3.1486 +	clear_IO_APIC();
  3.1487 +
  3.1488 +#if 0
  3.1489 +	disconnect_bsp_APIC();
  3.1490 +#endif
  3.1491 +}
  3.1492 +
  3.1493 +/*
  3.1494 + * function to set the IO-APIC physical IDs based on the
  3.1495 + * values stored in the MPC table.
  3.1496 + *
  3.1497 + * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
  3.1498 + */
  3.1499 +
  3.1500 +#ifndef CONFIG_X86_NUMAQ
  3.1501 +static void __init setup_ioapic_ids_from_mpc(void)
  3.1502 +{
  3.1503 +	union IO_APIC_reg_00 reg_00;
  3.1504 +	physid_mask_t phys_id_present_map;
  3.1505 +	int apic;
  3.1506 +	int i;
  3.1507 +	unsigned char old_id;
  3.1508 +	unsigned long flags;
  3.1509 +
  3.1510 +	/*
  3.1511 +	 * This is broken; anything with a real cpu count has to
  3.1512 +	 * circumvent this idiocy regardless.
  3.1513 +	 */
  3.1514 +	phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
  3.1515 +
  3.1516 +	/*
  3.1517 +	 * Set the IOAPIC ID to the value stored in the MPC table.
  3.1518 +	 */
  3.1519 +	for (apic = 0; apic < nr_ioapics; apic++) {
  3.1520 +
  3.1521 +		/* Read the register 0 value */
  3.1522 +		spin_lock_irqsave(&ioapic_lock, flags);
  3.1523 +		reg_00.raw = io_apic_read(apic, 0);
  3.1524 +		spin_unlock_irqrestore(&ioapic_lock, flags);
  3.1525 +		
  3.1526 +		old_id = mp_ioapics[apic].mpc_apicid;
  3.1527 +
  3.1528 +		if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
  3.1529 +			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
  3.1530 +				apic, mp_ioapics[apic].mpc_apicid);
  3.1531 +			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
  3.1532 +				reg_00.bits.ID);
  3.1533 +			mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
  3.1534 +		}
  3.1535 +
  3.1536 +		/* Don't check I/O APIC IDs for some xAPIC systems.  They have
  3.1537 +		 * no meaning without the serial APIC bus. */
  3.1538 +		if (NO_IOAPIC_CHECK)
  3.1539 +			continue;
  3.1540 +		/*
  3.1541 +		 * Sanity check, is the ID really free? Every APIC in a
  3.1542 +		 * system must have a unique ID or we get lots of nice
  3.1543 +		 * 'stuck on smp_invalidate_needed IPI wait' messages.
  3.1544 +		 */
  3.1545 +		if (check_apicid_used(phys_id_present_map,
  3.1546 +					mp_ioapics[apic].mpc_apicid)) {
  3.1547 +			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
  3.1548 +				apic, mp_ioapics[apic].mpc_apicid);
  3.1549 +			for (i = 0; i < get_physical_broadcast(); i++)
  3.1550 +				if (!physid_isset(i, phys_id_present_map))
  3.1551 +					break;
  3.1552 +			if (i >= get_physical_broadcast())
  3.1553 +				panic("Max APIC ID exceeded!\n");
  3.1554 +			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
  3.1555 +				i);
  3.1556 +			physid_set(i, phys_id_present_map);
  3.1557 +			mp_ioapics[apic].mpc_apicid = i;
  3.1558 +		} else {
  3.1559 +			physid_mask_t tmp;
  3.1560 +			tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
  3.1561 +			apic_printk(APIC_VERBOSE, "Setting %d in the "
  3.1562 +					"phys_id_present_map\n",
  3.1563 +					mp_ioapics[apic].mpc_apicid);
  3.1564 +			physids_or(phys_id_present_map, phys_id_present_map, tmp);
  3.1565 +		}
  3.1566 +
  3.1567 +
  3.1568 +		/*
  3.1569 +		 * We need to adjust the IRQ routing table
  3.1570 +		 * if the ID changed.
  3.1571 +		 */
  3.1572 +		if (old_id != mp_ioapics[apic].mpc_apicid)
  3.1573 +			for (i = 0; i < mp_irq_entries; i++)
  3.1574 +				if (mp_irqs[i].mpc_dstapic == old_id)
  3.1575 +					mp_irqs[i].mpc_dstapic
  3.1576 +						= mp_ioapics[apic].mpc_apicid;
  3.1577 +
  3.1578 +		/*
  3.1579 +		 * Read the right value from the MPC table and
  3.1580 +		 * write it into the ID register.
  3.1581 +	 	 */
  3.1582 +		apic_printk(APIC_VERBOSE, KERN_INFO
  3.1583 +			"...changing IO-APIC physical APIC ID to %d ...",
  3.1584 +			mp_ioapics[apic].mpc_apicid);
  3.1585 +
  3.1586 +		reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
  3.1587 +		spin_lock_irqsave(&ioapic_lock, flags);
  3.1588 +		io_apic_write(apic, 0, reg_00.raw);
  3.1589 +		spin_unlock_irqrestore(&ioapic_lock, flags);
  3.1590 +
  3.1591 +		/*
  3.1592 +		 * Sanity check
  3.1593 +		 */
  3.1594 +		spin_lock_irqsave(&ioapic_lock, flags);
  3.1595 +		reg_00.raw = io_apic_read(apic, 0);
  3.1596 +		spin_unlock_irqrestore(&ioapic_lock, flags);
  3.1597 +		if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
  3.1598 +			printk("could not set ID!\n");
  3.1599 +		else
  3.1600 +			apic_printk(APIC_VERBOSE, " ok.\n");
  3.1601 +	}
  3.1602 +}
  3.1603 +#else
  3.1604 +static void __init setup_ioapic_ids_from_mpc(void) { }
  3.1605 +#endif
  3.1606 +
  3.1607 +/*
  3.1608 + * There is a nasty bug in some older SMP boards, their mptable lies
  3.1609 + * about the timer IRQ. We do the following to work around the situation:
  3.1610 + *
  3.1611 + *	- timer IRQ defaults to IO-APIC IRQ
  3.1612 + *	- if this function detects that timer IRQs are defunct, then we fall
  3.1613 + *	  back to ISA timer IRQs
  3.1614 + */
  3.1615 +static int __init timer_irq_works(void)
  3.1616 +{
  3.1617 +	unsigned long t1 = jiffies;
  3.1618 +
  3.1619 +	local_irq_enable();
  3.1620 +	/* Let ten ticks pass... */
  3.1621 +	mdelay((10 * 1000) / HZ);
  3.1622 +
  3.1623 +	/*
  3.1624 +	 * Expect a few ticks at least, to be sure some possible
  3.1625 +	 * glue logic does not lock up after one or two first
  3.1626 +	 * ticks in a non-ExtINT mode.  Also the local APIC
  3.1627 +	 * might have cached one ExtINT interrupt.  Finally, at
  3.1628 +	 * least one tick may be lost due to delays.
  3.1629 +	 */
  3.1630 +	if (jiffies - t1 > 4)
  3.1631 +		return 1;
  3.1632 +
  3.1633 +	return 0;
  3.1634 +}
  3.1635 +
  3.1636 +/*
  3.1637 + * In the SMP+IOAPIC case it might happen that there are an unspecified
  3.1638 + * number of pending IRQ events unhandled. These cases are very rare,
  3.1639 + * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
  3.1640 + * better to do it this way as thus we do not have to be aware of
  3.1641 + * 'pending' interrupts in the IRQ path, except at this point.
  3.1642 + */
  3.1643 +/*
  3.1644 + * Edge triggered needs to resend any interrupt
  3.1645 + * that was delayed but this is now handled in the device
  3.1646 + * independent code.
  3.1647 + */
  3.1648 +
  3.1649 +/*
  3.1650 + * Starting up a edge-triggered IO-APIC interrupt is
  3.1651 + * nasty - we need to make sure that we get the edge.
  3.1652 + * If it is already asserted for some reason, we need
  3.1653 + * return 1 to indicate that is was pending.
  3.1654 + *
  3.1655 + * This is not complete - we should be able to fake
  3.1656 + * an edge even if it isn't on the 8259A...
  3.1657 + */
  3.1658 +static unsigned int startup_edge_ioapic_irq(unsigned int irq)
  3.1659 +{
  3.1660 +	int was_pending = 0;
  3.1661 +	unsigned long flags;
  3.1662 +
  3.1663 +	spin_lock_irqsave(&ioapic_lock, flags);
  3.1664 +#if 0
  3.1665 +	if (irq < 16) {
  3.1666 +		disable_8259A_irq(irq);
  3.1667 +		if (i8259A_irq_pending(irq))
  3.1668 +			was_pending = 1;
  3.1669 +	}
  3.1670 +#endif
  3.1671 +	__unmask_IO_APIC_irq(irq);
  3.1672 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  3.1673 +
  3.1674 +	return was_pending;
  3.1675 +}
  3.1676 +
  3.1677 +/*
  3.1678 + * Once we have recorded IRQ_PENDING already, we can mask the
  3.1679 + * interrupt for real. This prevents IRQ storms from unhandled
  3.1680 + * devices.
  3.1681 + */
  3.1682 +static void ack_edge_ioapic_irq(unsigned int irq)
  3.1683 +{
  3.1684 +	move_irq(irq);
  3.1685 +	if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
  3.1686 +					== (IRQ_PENDING | IRQ_DISABLED))
  3.1687 +		mask_IO_APIC_irq(irq);
  3.1688 +	ack_APIC_irq();
  3.1689 +}
  3.1690 +
  3.1691 +/*
  3.1692 + * Level triggered interrupts can just be masked,
  3.1693 + * and shutting down and starting up the interrupt
  3.1694 + * is the same as enabling and disabling them -- except
  3.1695 + * with a startup need to return a "was pending" value.
  3.1696 + *
  3.1697 + * Level triggered interrupts are special because we
  3.1698 + * do not touch any IO-APIC register while handling
  3.1699 + * them. We ack the APIC in the end-IRQ handler, not
  3.1700 + * in the start-IRQ-handler. Protection against reentrance
  3.1701 + * from the same interrupt is still provided, both by the
  3.1702 + * generic IRQ layer and by the fact that an unacked local
  3.1703 + * APIC does not accept IRQs.
  3.1704 + */
  3.1705 +static unsigned int startup_level_ioapic_irq (unsigned int irq)
  3.1706 +{
  3.1707 +	unmask_IO_APIC_irq(irq);
  3.1708 +
  3.1709 +	return 0; /* don't check for pending */
  3.1710 +}
  3.1711 +
  3.1712 +static void end_level_ioapic_irq (unsigned int irq)
  3.1713 +{
  3.1714 +	unsigned long v;
  3.1715 +	int i;
  3.1716 +
  3.1717 +	move_irq(irq);
  3.1718 +/*
  3.1719 + * It appears there is an erratum which affects at least version 0x11
  3.1720 + * of I/O APIC (that's the 82093AA and cores integrated into various
  3.1721 + * chipsets).  Under certain conditions a level-triggered interrupt is
  3.1722 + * erroneously delivered as edge-triggered one but the respective IRR
  3.1723 + * bit gets set nevertheless.  As a result the I/O unit expects an EOI
  3.1724 + * message but it will never arrive and further interrupts are blocked
  3.1725 + * from the source.  The exact reason is so far unknown, but the
  3.1726 + * phenomenon was observed when two consecutive interrupt requests
  3.1727 + * from a given source get delivered to the same CPU and the source is
  3.1728 + * temporarily disabled in between.
  3.1729 + *
  3.1730 + * A workaround is to simulate an EOI message manually.  We achieve it
  3.1731 + * by setting the trigger mode to edge and then to level when the edge
  3.1732 + * trigger mode gets detected in the TMR of a local APIC for a
  3.1733 + * level-triggered interrupt.  We mask the source for the time of the
  3.1734 + * operation to prevent an edge-triggered interrupt escaping meanwhile.
  3.1735 + * The idea is from Manfred Spraul.  --macro
  3.1736 + */
  3.1737 +	i = IO_APIC_VECTOR(irq);
  3.1738 +
  3.1739 +	v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
  3.1740 +
  3.1741 +	ack_APIC_irq();
  3.1742 +
  3.1743 +	if (!(v & (1 << (i & 0x1f)))) {
  3.1744 +		atomic_inc(&irq_mis_count);
  3.1745 +		spin_lock(&ioapic_lock);
  3.1746 +		__mask_and_edge_IO_APIC_irq(irq);
  3.1747 +		__unmask_and_level_IO_APIC_irq(irq);
  3.1748 +		spin_unlock(&ioapic_lock);
  3.1749 +	}
  3.1750 +}
  3.1751 +
  3.1752 +#ifdef CONFIG_PCI_MSI
  3.1753 +static unsigned int startup_edge_ioapic_vector(unsigned int vector)
  3.1754 +{
  3.1755 +	int irq = vector_to_irq(vector);
  3.1756 +
  3.1757 +	return startup_edge_ioapic_irq(irq);
  3.1758 +}
  3.1759 +
  3.1760 +static void ack_edge_ioapic_vector(unsigned int vector)
  3.1761 +{
  3.1762 +	int irq = vector_to_irq(vector);
  3.1763 +
  3.1764 +	ack_edge_ioapic_irq(irq);
  3.1765 +}
  3.1766 +
  3.1767 +static unsigned int startup_level_ioapic_vector (unsigned int vector)
  3.1768 +{
  3.1769 +	int irq = vector_to_irq(vector);
  3.1770 +
  3.1771 +	return startup_level_ioapic_irq (irq);
  3.1772 +}
  3.1773 +
  3.1774 +static void end_level_ioapic_vector (unsigned int vector)
  3.1775 +{
  3.1776 +	int irq = vector_to_irq(vector);
  3.1777 +
  3.1778 +	end_level_ioapic_irq(irq);
  3.1779 +}
  3.1780 +
  3.1781 +static void mask_IO_APIC_vector (unsigned int vector)
  3.1782 +{
  3.1783 +	int irq = vector_to_irq(vector);
  3.1784 +
  3.1785 +	mask_IO_APIC_irq(irq);
  3.1786 +}
  3.1787 +
  3.1788 +static void unmask_IO_APIC_vector (unsigned int vector)
  3.1789 +{
  3.1790 +	int irq = vector_to_irq(vector);
  3.1791 +
  3.1792 +	unmask_IO_APIC_irq(irq);
  3.1793 +}
  3.1794 +
  3.1795 +static void set_ioapic_affinity_vector (unsigned int vector,
  3.1796 +					cpumask_t cpu_mask)
  3.1797 +{
  3.1798 +	int irq = vector_to_irq(vector);
  3.1799 +
  3.1800 +	set_ioapic_affinity_irq(irq, cpu_mask);
  3.1801 +}
  3.1802 +#endif
  3.1803 +
  3.1804 +/*
  3.1805 + * Level and edge triggered IO-APIC interrupts need different handling,
  3.1806 + * so we use two separate IRQ descriptors. Edge triggered IRQs can be
  3.1807 + * handled with the level-triggered descriptor, but that one has slightly
  3.1808 + * more overhead. Level-triggered interrupts cannot be handled with the
  3.1809 + * edge-triggered handler, without risking IRQ storms and other ugly
  3.1810 + * races.
  3.1811 + */
  3.1812 +static struct hw_interrupt_type ioapic_edge_type = {
  3.1813 +	.typename 	= "IO-APIC-edge",
  3.1814 +	.startup 	= startup_edge_ioapic,
  3.1815 +	.shutdown 	= shutdown_edge_ioapic,
  3.1816 +	.enable 	= enable_edge_ioapic,
  3.1817 +	.disable 	= disable_edge_ioapic,
  3.1818 +	.ack 		= ack_edge_ioapic,
  3.1819 +	.end 		= end_edge_ioapic,
  3.1820 +	.set_affinity 	= set_ioapic_affinity,
  3.1821 +};
  3.1822 +
  3.1823 +static struct hw_interrupt_type ioapic_level_type = {
  3.1824 +	.typename 	= "IO-APIC-level",
  3.1825 +	.startup 	= startup_level_ioapic,
  3.1826 +	.shutdown 	= shutdown_level_ioapic,
  3.1827 +	.enable 	= enable_level_ioapic,
  3.1828 +	.disable 	= disable_level_ioapic,
  3.1829 +	.ack 		= mask_and_ack_level_ioapic,
  3.1830 +	.end 		= end_level_ioapic,
  3.1831 +	.set_affinity 	= set_ioapic_affinity,
  3.1832 +};
  3.1833 +
  3.1834 +static inline void init_IO_APIC_traps(void)
  3.1835 +{
  3.1836 +	int irq;
  3.1837 +
  3.1838 +	/*
  3.1839 +	 * NOTE! The local APIC isn't very good at handling
  3.1840 +	 * multiple interrupts at the same interrupt level.
  3.1841 +	 * As the interrupt level is determined by taking the
  3.1842 +	 * vector number and shifting that right by 4, we
  3.1843 +	 * want to spread these out a bit so that they don't
  3.1844 +	 * all fall in the same interrupt level.
  3.1845 +	 *
  3.1846 +	 * Also, we've got to be careful not to trash gate
  3.1847 +	 * 0x80, because int 0x80 is hm, kind of importantish. ;)
  3.1848 +	 */
  3.1849 +	for (irq = 0; irq < NR_IRQS ; irq++) {
  3.1850 +		int tmp = irq;
  3.1851 +		if (use_pci_vector()) {
  3.1852 +			if (!platform_legacy_irq(tmp))
  3.1853 +				if ((tmp = vector_to_irq(tmp)) == -1)
  3.1854 +					continue;
  3.1855 +		}
  3.1856 +		if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
  3.1857 +			/*
  3.1858 +			 * Hmm.. We don't have an entry for this,
  3.1859 +			 * so default to an old-fashioned 8259
  3.1860 +			 * interrupt if we can..
  3.1861 +			 */
  3.1862 +#if 0
  3.1863 +			if (irq < 16)
  3.1864 +				make_8259A_irq(irq);
  3.1865 +			else
  3.1866 +#endif
  3.1867 +				/* Strange. Oh, well.. */
  3.1868 +				irq_desc[irq].handler = &no_irq_type;
  3.1869 +		}
  3.1870 +	}
  3.1871 +}
  3.1872 +
  3.1873 +static void enable_lapic_irq (unsigned int irq)
  3.1874 +{
  3.1875 +	unsigned long v;
  3.1876 +
  3.1877 +	v = apic_read(APIC_LVT0);
  3.1878 +	apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
  3.1879 +}
  3.1880 +
  3.1881 +static void disable_lapic_irq (unsigned int irq)
  3.1882 +{
  3.1883 +	unsigned long v;
  3.1884 +
  3.1885 +	v = apic_read(APIC_LVT0);
  3.1886 +	apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
  3.1887 +}
  3.1888 +
  3.1889 +static void ack_lapic_irq (unsigned int irq)
  3.1890 +{
  3.1891 +	ack_APIC_irq();
  3.1892 +}
  3.1893 +
  3.1894 +static void end_lapic_irq (unsigned int i) { /* nothing */ }
  3.1895 +
  3.1896 +static struct hw_interrupt_type lapic_irq_type = {
  3.1897 +	.typename 	= "local-APIC-edge",
  3.1898 +	.startup 	= NULL, /* startup_irq() not used for IRQ0 */
  3.1899 +	.shutdown 	= NULL, /* shutdown_irq() not used for IRQ0 */
  3.1900 +	.enable 	= enable_lapic_irq,
  3.1901 +	.disable 	= disable_lapic_irq,
  3.1902 +	.ack 		= ack_lapic_irq,
  3.1903 +	.end 		= end_lapic_irq
  3.1904 +};
  3.1905 +
  3.1906 +static void setup_nmi (void)
  3.1907 +{
  3.1908 +	/*
  3.1909 + 	 * Dirty trick to enable the NMI watchdog ...
  3.1910 +	 * We put the 8259A master into AEOI mode and
  3.1911 +	 * unmask on all local APICs LVT0 as NMI.
  3.1912 +	 *
  3.1913 +	 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
  3.1914 +	 * is from Maciej W. Rozycki - so we do not have to EOI from
  3.1915 +	 * the NMI handler or the timer interrupt.
  3.1916 +	 */ 
  3.1917 +	apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
  3.1918 +
  3.1919 +#if 0
  3.1920 +	on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
  3.1921 +#endif
  3.1922 +
  3.1923 +	apic_printk(APIC_VERBOSE, " done.\n");
  3.1924 +}
  3.1925 +
  3.1926 +/*
  3.1927 + * This looks a bit hackish but it's about the only one way of sending
  3.1928 + * a few INTA cycles to 8259As and any associated glue logic.  ICR does
  3.1929 + * not support the ExtINT mode, unfortunately.  We need to send these
  3.1930 + * cycles as some i82489DX-based boards have glue logic that keeps the
  3.1931 + * 8259A interrupt line asserted until INTA.  --macro
  3.1932 + */
  3.1933 +static inline void unlock_ExtINT_logic(void)
  3.1934 +{
  3.1935 +	int pin, i;
  3.1936 +	struct IO_APIC_route_entry entry0, entry1;
  3.1937 +	unsigned char save_control, save_freq_select;
  3.1938 +	unsigned long flags;
  3.1939 +
  3.1940 +	pin = find_isa_irq_pin(8, mp_INT);
  3.1941 +	if (pin == -1)
  3.1942 +		return;
  3.1943 +
  3.1944 +	spin_lock_irqsave(&ioapic_lock, flags);
  3.1945 +	*(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
  3.1946 +	*(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
  3.1947 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  3.1948 +	clear_IO_APIC_pin(0, pin);
  3.1949 +
  3.1950 +	memset(&entry1, 0, sizeof(entry1));
  3.1951 +
  3.1952 +	entry1.dest_mode = 0;			/* physical delivery */
  3.1953 +	entry1.mask = 0;			/* unmask IRQ now */
  3.1954 +	entry1.dest.physical.physical_dest = hard_smp_processor_id();
  3.1955 +	entry1.delivery_mode = dest_ExtINT;
  3.1956 +	entry1.polarity = entry0.polarity;
  3.1957 +	entry1.trigger = 0;
  3.1958 +	entry1.vector = 0;
  3.1959 +
  3.1960 +	spin_lock_irqsave(&ioapic_lock, flags);
  3.1961 +	io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
  3.1962 +	io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
  3.1963 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  3.1964 +
  3.1965 +	save_control = CMOS_READ(RTC_CONTROL);
  3.1966 +	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
  3.1967 +	CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
  3.1968 +		   RTC_FREQ_SELECT);
  3.1969 +	CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
  3.1970 +
  3.1971 +	i = 100;
  3.1972 +	while (i-- > 0) {
  3.1973 +		mdelay(10);
  3.1974 +		if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
  3.1975 +			i -= 10;
  3.1976 +	}
  3.1977 +
  3.1978 +	CMOS_WRITE(save_control, RTC_CONTROL);
  3.1979 +	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
  3.1980 +	clear_IO_APIC_pin(0, pin);
  3.1981 +
  3.1982 +	spin_lock_irqsave(&ioapic_lock, flags);
  3.1983 +	io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
  3.1984 +	io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
  3.1985 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  3.1986 +}
  3.1987 +
  3.1988 +/*
  3.1989 + * This code may look a bit paranoid, but it's supposed to cooperate with
  3.1990 + * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
  3.1991 + * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
  3.1992 + * fanatically on his truly buggy board.
  3.1993 + */
  3.1994 +static inline void check_timer(void)
  3.1995 +{
  3.1996 +#if 0
  3.1997 +	int pin1, pin2;
  3.1998 +	int vector;
  3.1999 +
  3.2000 +	/*
  3.2001 +	 * get/set the timer IRQ vector:
  3.2002 +	 */
  3.2003 +	disable_8259A_irq(0);
  3.2004 +	vector = assign_irq_vector(0);
  3.2005 +	set_intr_gate(vector, interrupt[0]);
  3.2006 +
  3.2007 +	/*
  3.2008 +	 * Subtle, code in do_timer_interrupt() expects an AEOI
  3.2009 +	 * mode for the 8259A whenever interrupts are routed
  3.2010 +	 * through I/O APICs.  Also IRQ0 has to be enabled in
  3.2011 +	 * the 8259A which implies the virtual wire has to be
  3.2012 +	 * disabled in the local APIC.
  3.2013 +	 */
  3.2014 +	apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
  3.2015 +	init_8259A(1);
  3.2016 +	timer_ack = 1;
  3.2017 +	enable_8259A_irq(0);
  3.2018 +
  3.2019 +	pin1 = find_isa_irq_pin(0, mp_INT);
  3.2020 +	pin2 = find_isa_irq_pin(0, mp_ExtINT);
  3.2021 +
  3.2022 +	printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
  3.2023 +
  3.2024 +	if (pin1 != -1) {
  3.2025 +		/*
  3.2026 +		 * Ok, does IRQ0 through the IOAPIC work?
  3.2027 +		 */
  3.2028 +		unmask_IO_APIC_irq(0);
  3.2029 +		if (timer_irq_works()) {
  3.2030 +			if (nmi_watchdog == NMI_IO_APIC) {
  3.2031 +				disable_8259A_irq(0);
  3.2032 +				setup_nmi();
  3.2033 +				enable_8259A_irq(0);
  3.2034 +				check_nmi_watchdog();
  3.2035 +			}
  3.2036 +			return;
  3.2037 +		}
  3.2038 +		clear_IO_APIC_pin(0, pin1);
  3.2039 +		printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
  3.2040 +	}
  3.2041 +
  3.2042 +	printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
  3.2043 +	if (pin2 != -1) {
  3.2044 +		printk("\n..... (found pin %d) ...", pin2);
  3.2045 +		/*
  3.2046 +		 * legacy devices should be connected to IO APIC #0
  3.2047 +		 */
  3.2048 +		setup_ExtINT_IRQ0_pin(pin2, vector);
  3.2049 +		if (timer_irq_works()) {
  3.2050 +			printk("works.\n");
  3.2051 +			if (pin1 != -1)
  3.2052 +				replace_pin_at_irq(0, 0, pin1, 0, pin2);
  3.2053 +			else
  3.2054 +				add_pin_to_irq(0, 0, pin2);
  3.2055 +			if (nmi_watchdog == NMI_IO_APIC) {
  3.2056 +				setup_nmi();
  3.2057 +				check_nmi_watchdog();
  3.2058 +			}
  3.2059 +			return;
  3.2060 +		}
  3.2061 +		/*
  3.2062 +		 * Cleanup, just in case ...
  3.2063 +		 */
  3.2064 +		clear_IO_APIC_pin(0, pin2);
  3.2065 +	}
  3.2066 +	printk(" failed.\n");
  3.2067 +
  3.2068 +	if (nmi_watchdog == NMI_IO_APIC) {
  3.2069 +		printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
  3.2070 +		nmi_watchdog = 0;
  3.2071 +	}
  3.2072 +
  3.2073 +	printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
  3.2074 +
  3.2075 +	disable_8259A_irq(0);
  3.2076 +	irq_desc[0].handler = &lapic_irq_type;
  3.2077 +	apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);	/* Fixed mode */
  3.2078 +	enable_8259A_irq(0);
  3.2079 +
  3.2080 +	if (timer_irq_works()) {
  3.2081 +		printk(" works.\n");
  3.2082 +		return;
  3.2083 +	}
  3.2084 +	apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
  3.2085 +	printk(" failed.\n");
  3.2086 +
  3.2087 +	printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
  3.2088 +
  3.2089 +	timer_ack = 0;
  3.2090 +	init_8259A(0);
  3.2091 +	make_8259A_irq(0);
  3.2092 +	apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
  3.2093 +
  3.2094 +	unlock_ExtINT_logic();
  3.2095 +
  3.2096 +	if (timer_irq_works()) {
  3.2097 +		printk(" works.\n");
  3.2098 +		return;
  3.2099 +	}
  3.2100 +	printk(" failed :(.\n");
  3.2101 +	panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
  3.2102 +		"report.  Then try booting with the 'noapic' option");
  3.2103 +#endif
  3.2104 +}
  3.2105 +
  3.2106 +/*
  3.2107 + *
  3.2108 + * IRQ's that are handled by the PIC in the MPS IOAPIC case.
  3.2109 + * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
  3.2110 + *   Linux doesn't really care, as it's not actually used
  3.2111 + *   for any interrupt handling anyway.
  3.2112 + */
  3.2113 +#define PIC_IRQS	(1 << PIC_CASCADE_IR)
  3.2114 +
  3.2115 +void __init setup_IO_APIC(void)
  3.2116 +{
  3.2117 +	enable_IO_APIC();
  3.2118 +
  3.2119 +	if (acpi_ioapic)
  3.2120 +		io_apic_irqs = ~0;	/* all IRQs go through IOAPIC */
  3.2121 +	else
  3.2122 +		io_apic_irqs = ~PIC_IRQS;
  3.2123 +
  3.2124 +	printk("ENABLING IO-APIC IRQs\n");
  3.2125 +
  3.2126 +	/*
  3.2127 +	 * Set up IO-APIC IRQ routing.
  3.2128 +	 */
  3.2129 +	if (!acpi_ioapic)
  3.2130 +		setup_ioapic_ids_from_mpc();
  3.2131 +#if 0
  3.2132 +	sync_Arb_IDs();
  3.2133 +#endif
  3.2134 +	setup_IO_APIC_irqs();
  3.2135 +	init_IO_APIC_traps();
  3.2136 +	check_timer();
  3.2137 +	if (!acpi_ioapic)
  3.2138 +		print_IO_APIC();
  3.2139 +}
  3.2140 +
  3.2141 +/*
  3.2142 + *	Called after all the initialization is done. If we didnt find any
  3.2143 + *	APIC bugs then we can allow the modify fast path
  3.2144 + */
  3.2145 + 
  3.2146 +static int __init io_apic_bug_finalize(void)
  3.2147 +{
  3.2148 +	if(sis_apic_bug == -1)
  3.2149 +		sis_apic_bug = 0;
  3.2150 +	return 0;
  3.2151 +}
  3.2152 +
  3.2153 +late_initcall(io_apic_bug_finalize);
  3.2154 +
  3.2155 +struct sysfs_ioapic_data {
  3.2156 +	struct sys_device dev;
  3.2157 +	struct IO_APIC_route_entry entry[0];
  3.2158 +};
  3.2159 +static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
  3.2160 +
  3.2161 +static int ioapic_suspend(struct sys_device *dev, u32 state)
  3.2162 +{
  3.2163 +	struct IO_APIC_route_entry *entry;
  3.2164 +	struct sysfs_ioapic_data *data;
  3.2165 +	unsigned long flags;
  3.2166 +	int i;
  3.2167 +	
  3.2168 +	data = container_of(dev, struct sysfs_ioapic_data, dev);
  3.2169 +	entry = data->entry;
  3.2170 +	spin_lock_irqsave(&ioapic_lock, flags);
  3.2171 +	for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
  3.2172 +		*(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
  3.2173 +		*(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
  3.2174 +	}
  3.2175 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  3.2176 +
  3.2177 +	return 0;
  3.2178 +}
  3.2179 +
  3.2180 +static int ioapic_resume(struct sys_device *dev)
  3.2181 +{
  3.2182 +	struct IO_APIC_route_entry *entry;
  3.2183 +	struct sysfs_ioapic_data *data;
  3.2184 +	unsigned long flags;
  3.2185 +	union IO_APIC_reg_00 reg_00;
  3.2186 +	int i;
  3.2187 +	
  3.2188 +	data = container_of(dev, struct sysfs_ioapic_data, dev);
  3.2189 +	entry = data->entry;
  3.2190 +
  3.2191 +	spin_lock_irqsave(&ioapic_lock, flags);
  3.2192 +	reg_00.raw = io_apic_read(dev->id, 0);
  3.2193 +	if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
  3.2194 +		reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
  3.2195 +		io_apic_write(dev->id, 0, reg_00.raw);
  3.2196 +	}
  3.2197 +	for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
  3.2198 +		io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
  3.2199 +		io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
  3.2200 +	}
  3.2201 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  3.2202 +
  3.2203 +	return 0;
  3.2204 +}
  3.2205 +
  3.2206 +static struct sysdev_class ioapic_sysdev_class = {
  3.2207 +	set_kset_name("ioapic"),
  3.2208 +	.suspend = ioapic_suspend,
  3.2209 +	.resume = ioapic_resume,
  3.2210 +};
  3.2211 +
  3.2212 +static int __init ioapic_init_sysfs(void)
  3.2213 +{
  3.2214 +	struct sys_device * dev;
  3.2215 +	int i, size, error = 0;
  3.2216 +
  3.2217 +	error = sysdev_class_register(&ioapic_sysdev_class);
  3.2218 +	if (error)
  3.2219 +		return error;
  3.2220 +
  3.2221 +	for (i = 0; i < nr_ioapics; i++ ) {
  3.2222 +		size = sizeof(struct sys_device) + nr_ioapic_registers[i] 
  3.2223 +			* sizeof(struct IO_APIC_route_entry);
  3.2224 +		mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
  3.2225 +		if (!mp_ioapic_data[i]) {
  3.2226 +			printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
  3.2227 +			continue;
  3.2228 +		}
  3.2229 +		memset(mp_ioapic_data[i], 0, size);
  3.2230 +		dev = &mp_ioapic_data[i]->dev;
  3.2231 +		dev->id = i; 
  3.2232 +		dev->cls = &ioapic_sysdev_class;
  3.2233 +		error = sysdev_register(dev);
  3.2234 +		if (error) {
  3.2235 +			kfree(mp_ioapic_data[i]);
  3.2236 +			mp_ioapic_data[i] = NULL;
  3.2237 +			printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
  3.2238 +			continue;
  3.2239 +		}
  3.2240 +	}
  3.2241 +
  3.2242 +	return 0;
  3.2243 +}
  3.2244 +
  3.2245 +device_initcall(ioapic_init_sysfs);
  3.2246 +
  3.2247 +/* --------------------------------------------------------------------------
  3.2248 +                          ACPI-based IOAPIC Configuration
  3.2249 +   -------------------------------------------------------------------------- */
  3.2250 +
  3.2251  #ifdef CONFIG_ACPI_BOOT
  3.2252 +
  3.2253  int __init io_apic_get_unique_id (int ioapic, int apic_id)
  3.2254  {
  3.2255  	union IO_APIC_reg_00 reg_00;
  3.2256  	static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
  3.2257 +	physid_mask_t tmp;
  3.2258  	unsigned long flags;
  3.2259 +	int i = 0;
  3.2260  
  3.2261  	/*
  3.2262  	 * The P4 platform supports up to 256 APIC IDs on two separate APIC 
  3.2263 @@ -306,6 +2445,44 @@ int __init io_apic_get_unique_id (int io
  3.2264  		apic_id = reg_00.bits.ID;
  3.2265  	}
  3.2266  
  3.2267 +#if 0
  3.2268 +	/*
  3.2269 +	 * Every APIC in a system must have a unique ID or we get lots of nice 
  3.2270 +	 * 'stuck on smp_invalidate_needed IPI wait' messages.
  3.2271 +	 */
  3.2272 +	if (check_apicid_used(apic_id_map, apic_id)) {
  3.2273 +
  3.2274 +		for (i = 0; i < get_physical_broadcast(); i++) {
  3.2275 +			if (!check_apicid_used(apic_id_map, i))
  3.2276 +				break;
  3.2277 +		}
  3.2278 +
  3.2279 +		if (i == get_physical_broadcast())
  3.2280 +			panic("Max apic_id exceeded!\n");
  3.2281 +
  3.2282 +		printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
  3.2283 +			"trying %d\n", ioapic, apic_id, i);
  3.2284 +
  3.2285 +		apic_id = i;
  3.2286 +	} 
  3.2287 +
  3.2288 +	tmp = apicid_to_cpu_present(apic_id);
  3.2289 +	physids_or(apic_id_map, apic_id_map, tmp);
  3.2290 +
  3.2291 +	if (reg_00.bits.ID != apic_id) {
  3.2292 +		reg_00.bits.ID = apic_id;
  3.2293 +
  3.2294 +		spin_lock_irqsave(&ioapic_lock, flags);
  3.2295 +		io_apic_write(ioapic, 0, reg_00.raw);
  3.2296 +		reg_00.raw = io_apic_read(ioapic, 0);
  3.2297 +		spin_unlock_irqrestore(&ioapic_lock, flags);
  3.2298 +
  3.2299 +		/* Sanity check */
  3.2300 +		if (reg_00.bits.ID != apic_id)
  3.2301 +			panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
  3.2302 +	}
  3.2303 +#endif
  3.2304 +
  3.2305  	apic_printk(APIC_VERBOSE, KERN_INFO
  3.2306  			"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
  3.2307  
  3.2308 @@ -338,6 +2515,7 @@ int __init io_apic_get_redir_entries (in
  3.2309  	return reg_01.bits.entries;
  3.2310  }
  3.2311  
  3.2312 +
  3.2313  int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
  3.2314  {
  3.2315  	struct IO_APIC_route_entry entry;
  3.2316 @@ -391,4 +2569,5 @@ int io_apic_set_pci_routing (int ioapic,
  3.2317  
  3.2318  	return 0;
  3.2319  }
  3.2320 +
  3.2321  #endif /*CONFIG_ACPI_BOOT*/
     4.1 --- a/linux-2.6.11-xen-sparse/drivers/acpi/tables.c	Wed May 04 17:40:45 2005 +0000
     4.2 +++ b/linux-2.6.11-xen-sparse/drivers/acpi/tables.c	Thu May 05 13:28:41 2005 +0000
     4.3 @@ -581,8 +581,8 @@ acpi_table_init (void)
     4.4  		return -ENODEV;
     4.5  	}
     4.6  
     4.7 -        rsdp = (struct acpi_table_rsdp *) (__fix_to_virt(FIX_ACPI_RSDP_PAGE)
     4.8 -                                           + (rsdp_phys & ~PAGE_MASK));
     4.9 +	rsdp = (struct acpi_table_rsdp *) (__fix_to_virt(FIX_ACPI_RSDP_PAGE) +
    4.10 +					   (rsdp_phys & ~PAGE_MASK));
    4.11  	if (!rsdp) {
    4.12  		printk(KERN_WARNING PREFIX "Unable to map RSDP\n");
    4.13  		return -ENODEV;
     5.1 --- a/linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/fixmap.h	Wed May 04 17:40:45 2005 +0000
     5.2 +++ b/linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/fixmap.h	Thu May 05 13:28:41 2005 +0000
     5.3 @@ -80,7 +80,7 @@ enum fixed_addresses {
     5.4  #ifdef CONFIG_ACPI_BOOT
     5.5  	FIX_ACPI_BEGIN,
     5.6  	FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1,
     5.7 -        FIX_ACPI_RSDP_PAGE,
     5.8 +	FIX_ACPI_RSDP_PAGE,
     5.9  #endif
    5.10  #ifdef CONFIG_PCI_MMCONFIG
    5.11  	FIX_PCIE_MCFG,
     6.1 --- a/linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/io_apic.h	Wed May 04 17:40:45 2005 +0000
     6.2 +++ b/linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/io_apic.h	Thu May 05 13:28:41 2005 +0000
     6.3 @@ -165,28 +165,27 @@ extern int mpc_default_type;
     6.4  
     6.5  static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
     6.6  {
     6.7 -        physdev_op_t op;
     6.8 -        int ret;
     6.9 +	physdev_op_t op;
    6.10 +	int ret;
    6.11  
    6.12 -        op.cmd = PHYSDEVOP_APIC_READ;
    6.13 -        op.u.apic_op.apic = apic;
    6.14 -        op.u.apic_op.offset = reg;
    6.15 -        ret = HYPERVISOR_physdev_op(&op);
    6.16 -        if (ret)
    6.17 -                return ret;
    6.18 -        return op.u.apic_op.value;
    6.19 +	op.cmd = PHYSDEVOP_APIC_READ;
    6.20 +	op.u.apic_op.apic = apic;
    6.21 +	op.u.apic_op.offset = reg;
    6.22 +	ret = HYPERVISOR_physdev_op(&op);
    6.23 +	if (ret)
    6.24 +		return ret;
    6.25 +	return op.u.apic_op.value;
    6.26  }
    6.27  
    6.28  static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
    6.29  {
    6.30 -        physdev_op_t op;
    6.31 -        int ret;
    6.32 +	physdev_op_t op;
    6.33  
    6.34 -        op.cmd = PHYSDEVOP_APIC_WRITE;
    6.35 -        op.u.apic_op.apic = apic;
    6.36 -        op.u.apic_op.offset = reg;
    6.37 -        op.u.apic_op.value = value;
    6.38 -        ret = HYPERVISOR_physdev_op(&op);
    6.39 +	op.cmd = PHYSDEVOP_APIC_WRITE;
    6.40 +	op.u.apic_op.apic = apic;
    6.41 +	op.u.apic_op.offset = reg;
    6.42 +	op.u.apic_op.value = value;
    6.43 +	HYPERVISOR_physdev_op(&op);
    6.44  }
    6.45  
    6.46  /*
     7.1 --- a/tools/libxc/xc_domain.c	Wed May 04 17:40:45 2005 +0000
     7.2 +++ b/tools/libxc/xc_domain.c	Thu May 05 13:28:41 2005 +0000
     7.3 @@ -43,7 +43,7 @@ int xc_domain_create(int xc_handle,
     7.4          goto fail;
     7.5      }
     7.6  
     7.7 -    return err;
     7.8 +    return 0;
     7.9  
    7.10   fail:
    7.11      errno_saved = errno;