ia64/xen-unstable

changeset 15325:855fe0bf6590

[IA64] Change virtual address of XEN UC indentity area.

This slightly simplifies the code and makes flexible map possible.

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author Alex Williamson <alex.williamson@hp.com>
date Tue Jun 12 15:20:06 2007 -0600 (2007-06-12)
parents c4256be388cc
children f5d22922444d
files xen/arch/ia64/vmx/vmx_ivt.S xen/arch/ia64/xen/ivt.S xen/include/asm-ia64/xensystem.h
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Tue Jun 12 15:17:16 2007 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Tue Jun 12 15:20:06 2007 -0600
     1.3 @@ -320,14 +320,12 @@ vmx_alt_itlb_miss_1:
     1.4      movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
     1.5      ;;
     1.6      and r19=r19,r16     // clear ed, reserved bits, and PTE control bits
     1.7 -    shr.u r18=r16,55    // move address bit 59 to bit 4
     1.8 +    extr.u r18=r16,XEN_VIRT_UC_BIT, 15    // extract UC bit
     1.9      ;;
    1.10 -    and r18=0x10,r18    // bit 4=address-bit(61)
    1.11      or r19=r17,r19      // insert PTE control bits into r19
    1.12 +    mov r20=IA64_GRANULE_SHIFT<<2
    1.13      ;;
    1.14 -    mov r20=IA64_GRANULE_SHIFT<<2
    1.15 -    or r19=r19,r18	// set bit 4 (uncached) if the access was to UC region
    1.16 -    ;;
    1.17 +    dep r19=r18,r19,4,1	// set bit 4 (uncached) if the access was to UC region
    1.18      mov cr.itir=r20
    1.19      ;;
    1.20      itc.i r19		// insert the TLB entry
    1.21 @@ -363,19 +361,17 @@ vmx_alt_dtlb_miss_1:
    1.22      ;;
    1.23      and r22=IA64_ISR_CODE_MASK,r20		// get the isr.code field
    1.24      tbit.nz p6,p7=r20,IA64_ISR_SP_BIT		// is speculation bit on?
    1.25 -    shr.u r18=r16,55				// move address bit 59 to bit 4
    1.26 +    extr.u r18=r16,XEN_VIRT_UC_BIT, 1		// extract UC bit
    1.27      and r19=r19,r16				// clear ed, reserved bits, and PTE control bits
    1.28      tbit.nz p9,p0=r20,IA64_ISR_NA_BIT		// is non-access bit on?
    1.29      ;;
    1.30 -    and r18=0x10,r18				// bit 4=address-bit(61)
    1.31  (p9)cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22	// check isr.code field
    1.32      dep r24=-1,r24,IA64_PSR_ED_BIT,1
    1.33      or r19=r19,r17				// insert PTE control bits into r19
    1.34 -    ;;
    1.35 -    or r19=r19,r18				// set bit 4 (uncached) if the access was to UC region
    1.36 -(p6)mov cr.ipsr=r24
    1.37      mov r20=IA64_GRANULE_SHIFT<<2
    1.38      ;;
    1.39 +    dep r19=r18,r19,4,1	// set bit 4 (uncached) if the access was to UC region
    1.40 +(p6)mov cr.ipsr=r24
    1.41      mov cr.itir=r20
    1.42      ;;
    1.43  (p7)itc.d r19		// insert the TLB entry
     2.1 --- a/xen/arch/ia64/xen/ivt.S	Tue Jun 12 15:17:16 2007 -0600
     2.2 +++ b/xen/arch/ia64/xen/ivt.S	Tue Jun 12 15:20:06 2007 -0600
     2.3 @@ -119,12 +119,7 @@ ENTRY(itlb_miss)
     2.4  	;;
     2.5  	/* If address belongs to VMM, go to alt tlb handler */
     2.6  	cmp.eq p6,p0=0x1e,r17
     2.7 -	;;
     2.8 -	cmp.eq.or p6,p0=0x1d,r17
     2.9  (p6)	br.cond.spnt	late_alt_itlb_miss
    2.10 -	;;
    2.11 -	mov pr = r31, 0x1ffff
    2.12 -	;;							
    2.13  	br.cond.sptk fast_tlb_miss_reflect
    2.14  	;;
    2.15  END(itlb_miss)
    2.16 @@ -141,8 +136,6 @@ ENTRY(dtlb_miss)
    2.17  	;;
    2.18  	/* If address belongs to VMM, go to alt tlb handler */
    2.19  	cmp.eq p6,p0=0x1e,r17
    2.20 -	;;
    2.21 -	cmp.eq.or p6,p0=0x1d,r17
    2.22  (p6)	br.cond.spnt	late_alt_dtlb_miss
    2.23  	br.cond.sptk fast_tlb_miss_reflect
    2.24  	;;
    2.25 @@ -162,15 +155,13 @@ late_alt_itlb_miss:
    2.26  	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
    2.27  	;;
    2.28  	extr.u r23=r21,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
    2.29 -	and r19=r19,r16		// clear ed, reserved bits, and PTE control bits
    2.30 -	shr.u r18=r16,55	// move address bit 59 to bit 4
    2.31 +	and r19=r19,r16		// clear ed, reserved bits, and PTE ctrl bits
    2.32 +	extr.u r18=r16,XEN_VIRT_UC_BIT,1	// extract UC bit
    2.33  	;;
    2.34 -	and r18=0x10,r18	// bit 4=address-bit(59)
    2.35  	cmp.ne p8,p0=r0,r23	// psr.cpl != 0?
    2.36  	or r19=r17,r19		// insert PTE control bits into r19
    2.37  	;;
    2.38 -	or r19=r19,r18		// set bit 4 (uncached) if the access was to
    2.39 -				//   region 6
    2.40 +	dep r19=r18,r19,4,1	// set bit 4 (uncached) if access to UC area.
    2.41  (p8)	br.cond.spnt page_fault
    2.42  	;;
    2.43  	itc.i r19		// insert the TLB entry
    2.44 @@ -195,12 +186,11 @@ late_alt_dtlb_miss:
    2.45  	extr.u r23=r21,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
    2.46  	and r22=IA64_ISR_CODE_MASK,r20		// get the isr.code field
    2.47  	tbit.nz p6,p7=r20,IA64_ISR_SP_BIT	// is speculation bit on?
    2.48 -	shr.u r18=r16,55			// move address bit 59 to bit 4
    2.49 +	extr.u r18=r16,XEN_VIRT_UC_BIT,1	// extract UC bit
    2.50  	and r19=r19,r16				// clear ed, reserved bits, and
    2.51  						//   PTE control bits
    2.52  	tbit.nz p9,p0=r20,IA64_ISR_NA_BIT	// is non-access bit on?
    2.53  	;;
    2.54 -	and r18=0x10,r18	// bit 4=address-bit(59)
    2.55  	cmp.ne p8,p0=r0,r23
    2.56  (p9)	cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22	// check isr.code field
    2.57  (p8)	br.cond.spnt page_fault
    2.58 @@ -212,22 +202,15 @@ late_alt_dtlb_miss:
    2.59  (p8)	br.cond.sptk frametable_miss ;;
    2.60  #endif
    2.61  	// If it is not a Xen address, handle it via page_fault.
    2.62 -	// Note that 0xf000 (cached) and 0xe800 (uncached) addresses
    2.63 -	// should be OK.
    2.64  	extr.u r22=r16,59,5
    2.65  	;;
    2.66 -	cmp.eq p8,p0=0x1e,r22
    2.67 -(p8)	br.cond.spnt 1f
    2.68 -	;;
    2.69 -	cmp.ne p8,p0=0x1d,r22
    2.70 +	cmp.ne p8,p0=0x1e,r22
    2.71  (p8)	br.cond.sptk page_fault
    2.72  	;;
    2.73 -1:
    2.74  	dep r21=-1,r21,IA64_PSR_ED_BIT,1
    2.75  	or r19=r19,r17		// insert PTE control bits into r19
    2.76  	;;
    2.77 -	or r19=r19,r18		// set bit 4 (uncached) if the access was to
    2.78 -				//   region 6
    2.79 +	dep r19=r18,r19,4,1	// set bit 4 (uncached) if access to UC area
    2.80  (p6)	mov cr.ipsr=r21
    2.81  	;;
    2.82  (p7)	itc.d r19		// insert the TLB entry
     3.1 --- a/xen/include/asm-ia64/xensystem.h	Tue Jun 12 15:17:16 2007 -0600
     3.2 +++ b/xen/include/asm-ia64/xensystem.h	Tue Jun 12 15:20:06 2007 -0600
     3.3 @@ -16,9 +16,8 @@
     3.4     VMM memory space is protected by CPL for paravirtualized domains and
     3.5     by VA for VTi domains.  VTi imposes VA bit 60 != VA bit 59 for VMM.  */
     3.6  
     3.7 -#define HYPERVISOR_VIRT_START	 0xe800000000000000
     3.8 -#define KERNEL_START		 0xf000000004000000
     3.9 -#define GATE_ADDR		KERNEL_START
    3.10 +#define HYPERVISOR_VIRT_START	 0xf000000000000000
    3.11 +#define __IA64_UNCACHED_OFFSET	 0xf200000000000000UL
    3.12  #define DEFAULT_SHAREDINFO_ADDR	 0xf500000000000000
    3.13  #define PERCPU_ADDR		 (DEFAULT_SHAREDINFO_ADDR - PERCPU_PAGE_SIZE)
    3.14  #ifdef CONFIG_VIRTUAL_FRAME_TABLE
    3.15 @@ -28,7 +27,11 @@
    3.16  #define HYPERVISOR_VIRT_END	 0xf800000000000000
    3.17  
    3.18  #define PAGE_OFFSET		 __IA64_UL_CONST(0xf000000000000000)
    3.19 -#define __IA64_UNCACHED_OFFSET	 0xe800000000000000UL
    3.20 +
    3.21 +#define XEN_VIRT_UC_BIT	 57
    3.22 +
    3.23 +#define KERNEL_START		 0xf000000004000000
    3.24 +#define GATE_ADDR		 KERNEL_START
    3.25  
    3.26  #define IS_VMM_ADDRESS(addr) ((((addr) >> 60) ^ ((addr) >> 59)) & 1)
    3.27