ia64/xen-unstable

changeset 15694:82f5fbe59e26

[IA64] Use defines instead of hard coded numbers

Some minor instruction grouping enhancements

Signed-off-by: Juergen Gross juergen.gross@fujitsu-siemens.com
author Alex Williamson <alex.williamson@hp.com>
date Sun Aug 12 12:06:43 2007 -0600 (2007-08-12)
parents 87a72ba32301
children 54c721bb6d45
files xen/arch/ia64/xen/hyperprivop.S xen/include/asm-ia64/vmmu.h xen/include/asm-ia64/xenkregs.h
line diff
     1.1 --- a/xen/arch/ia64/xen/hyperprivop.S	Wed Aug 08 20:48:11 2007 -0600
     1.2 +++ b/xen/arch/ia64/xen/hyperprivop.S	Sun Aug 12 12:06:43 2007 -0600
     1.3 @@ -14,12 +14,12 @@
     1.4  #include <asm/system.h>
     1.5  #include <asm/debugger.h>
     1.6  #include <asm/asm-xsi-offsets.h>
     1.7 +#include <asm/pgtable.h>
     1.8 +#include <asm/vmmu.h>
     1.9  #include <public/xen.h>
    1.10  
    1.11  
    1.12 -#define	_PAGE_PPN_MASK	0x0003fffffffff000 //asm/pgtable.h doesn't do assembly
    1.13 -#define PAGE_PHYS	(0x0010000000000661 | _PAGE_PL_PRIV)
    1.14 -			//__pgprot(__DIRTY_BITS|_PAGE_PL_PRIV|_PAGE_AR_RWX)
    1.15 +#define PAGE_PHYS	(__DIRTY_BITS | _PAGE_PL_PRIV | _PAGE_AR_RWX)
    1.16  
    1.17  #if 1	 // change to 0 to turn off all fast paths
    1.18  # define FAST_HYPERPRIVOPS
    1.19 @@ -221,7 +221,7 @@ ENTRY(hyper_ssm_i)
    1.20  	br.spnt.few dispatch_break_fault ;;
    1.21  #endif
    1.22  	// give up for now if: ipsr.be==1, ipsr.pp==1
    1.23 -	mov r30=cr.ipsr;;
    1.24 +	mov r30=cr.ipsr
    1.25  	mov r29=cr.iip;;
    1.26  	extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
    1.27  	cmp.ne p7,p0=r21,r0
    1.28 @@ -236,23 +236,23 @@ ENTRY(hyper_ssm_i)
    1.29  	st4 [r20]=r21;;
    1.30  #endif
    1.31  	// set shared_mem iip to instruction after HYPER_SSM_I
    1.32 -	extr.u r20=r30,41,2 ;;
    1.33 +	extr.u r20=r30,IA64_PSR_RI_BIT,2 ;;
    1.34  	cmp.eq p6,p7=2,r20 ;;
    1.35  (p6)	mov r20=0
    1.36  (p6)	adds r29=16,r29
    1.37  (p7)	adds r20=1,r20 ;;
    1.38 -	dep r30=r20,r30,41,2;;	// adjust cr.ipsr.ri but don't save yet
    1.39 +	dep r30=r20,r30,IA64_PSR_RI_BIT,2	// adjust cr.ipsr.ri but don't save yet
    1.40  	adds r21=XSI_IIP_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.41  	st8 [r21]=r29 ;;
    1.42  	// set shared_mem isr
    1.43 -	extr.u r16=r16,38,1;;	// grab cr.isr.ir bit
    1.44 -	dep r16=r16,r0,38,1 ;;	// insert into cr.isr (rest of bits zero)
    1.45 -	dep r16=r20,r16,41,2 ;; // deposit cr.isr.ri
    1.46 +	extr.u r16=r16,IA64_ISR_IR_BIT,1;;	// grab cr.isr.ir bit
    1.47 +	dep r16=r16,r0,IA64_ISR_IR_BIT,1;;	// insert into cr.isr (rest of bits zero)
    1.48 +	dep r16=r20,r16,IA64_PSR_RI_BIT,2	// deposit cr.isr.ri
    1.49  	adds r21=XSI_ISR_OFS-XSI_PSR_IC_OFS,r18 ;; 
    1.50 -	st8 [r21]=r16 ;;
    1.51 +	st8 [r21]=r16
    1.52  	// set cr.ipsr
    1.53 -	mov r29=r30 ;;
    1.54 -	movl r28=DELIVER_PSR_SET;;
    1.55 +	mov r29=r30
    1.56 +	movl r28=DELIVER_PSR_SET
    1.57  	movl r27=~DELIVER_PSR_CLR;;
    1.58  	and r29=r29,r27;;
    1.59  	or r29=r29,r28;;
    1.60 @@ -265,9 +265,8 @@ ENTRY(hyper_ssm_i)
    1.61  	extr.u r29=r30,IA64_PSR_CPL0_BIT,2;;
    1.62  	cmp.eq p7,p0=CONFIG_CPL0_EMUL,r29;;
    1.63  (p7)	dep r30=0,r30,IA64_PSR_CPL0_BIT,2
    1.64 -	;;
    1.65  	// FOR SSM_I ONLY, also turn on psr.i and psr.ic
    1.66 -	movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT|IA64_PSR_I|IA64_PSR_IC);;
    1.67 +	movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT|IA64_PSR_I|IA64_PSR_IC)
    1.68  //	movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN);;
    1.69  	movl r27=~(IA64_PSR_BE|IA64_PSR_BN);;
    1.70  	or r30=r30,r28;;
    1.71 @@ -276,7 +275,6 @@ ENTRY(hyper_ssm_i)
    1.72  	movl r22=THIS_CPU(current_psr_i_addr)
    1.73  	adds r21=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.74  	ld8 r22=[r22]
    1.75 -	;;
    1.76  	adds r27=XSI_VPSR_DFH_OFS-XSI_PSR_IC_OFS,r18;;
    1.77  	ld1 r28=[r27];;
    1.78  	st1 [r27]=r0
    1.79 @@ -290,7 +288,7 @@ ENTRY(hyper_ssm_i)
    1.80  	// cover and set shared_mem precover_ifs to cr.ifs
    1.81  	// set shared_mem ifs to 0
    1.82  	cover ;;
    1.83 -	mov r20=cr.ifs;;
    1.84 +	mov r20=cr.ifs
    1.85  	adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.86  	st8 [r21]=r0 ;;
    1.87  	adds r21=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.88 @@ -306,28 +304,28 @@ ENTRY(hyper_ssm_i)
    1.89  	mov r30=r2
    1.90  	mov r29=r3
    1.91  	;;
    1.92 -	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18;
    1.93 -	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18;;
    1.94 +	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18
    1.95 +	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18
    1.96  	// temporarily save ar.unat
    1.97  	mov r28=ar.unat   
    1.98  	bsw.1;;
    1.99  	// FIXME?: ar.unat is not really handled correctly,
   1.100  	// but may not matter if the OS is NaT-clean
   1.101 -	.mem.offset 0,0; st8.spill [r2]=r16,16;
   1.102 +	.mem.offset 0,0; st8.spill [r2]=r16,16
   1.103  	.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
   1.104 -	.mem.offset 0,0; st8.spill [r2]=r18,16;
   1.105 +	.mem.offset 0,0; st8.spill [r2]=r18,16
   1.106  	.mem.offset 8,0; st8.spill [r3]=r19,16 ;;
   1.107 -	.mem.offset 0,0; st8.spill [r2]=r20,16;
   1.108 +	.mem.offset 0,0; st8.spill [r2]=r20,16
   1.109  	.mem.offset 8,0; st8.spill [r3]=r21,16 ;;
   1.110 -	.mem.offset 0,0; st8.spill [r2]=r22,16;
   1.111 +	.mem.offset 0,0; st8.spill [r2]=r22,16
   1.112  	.mem.offset 8,0; st8.spill [r3]=r23,16 ;;
   1.113 -	.mem.offset 0,0; st8.spill [r2]=r24,16;
   1.114 +	.mem.offset 0,0; st8.spill [r2]=r24,16
   1.115  	.mem.offset 8,0; st8.spill [r3]=r25,16 ;;
   1.116 -	.mem.offset 0,0; st8.spill [r2]=r26,16;
   1.117 +	.mem.offset 0,0; st8.spill [r2]=r26,16
   1.118  	.mem.offset 8,0; st8.spill [r3]=r27,16 ;;
   1.119 -	.mem.offset 0,0; st8.spill [r2]=r28,16;
   1.120 +	.mem.offset 0,0; st8.spill [r2]=r28,16
   1.121  	.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
   1.122 -	.mem.offset 0,0; st8.spill [r2]=r30,16;
   1.123 +	.mem.offset 0,0; st8.spill [r2]=r30,16
   1.124  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
   1.125  	bsw.0 ;;
   1.126  	mov r27=ar.unat
   1.127 @@ -339,7 +337,7 @@ ENTRY(hyper_ssm_i)
   1.128  	mov r2=r30
   1.129  	mov r3=r29
   1.130  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.131 -	st4 [r20]=r0 ;;
   1.132 +	st4 [r20]=r0
   1.133  	mov pr=r31,-1 ;;
   1.134  	rfi
   1.135  	;;
   1.136 @@ -357,7 +355,7 @@ GLOBAL_ENTRY(fast_tick_reflect)
   1.137  	cmp.ne p6,p0=r28,r30
   1.138  (p6)	br.cond.spnt.few rp;;
   1.139  	movl r20=THIS_CPU(cpu_info)+IA64_CPUINFO_ITM_NEXT_OFFSET;;
   1.140 -	ld8 r26=[r20];;
   1.141 +	ld8 r26=[r20]
   1.142  	mov r27=ar.itc;;
   1.143  	adds r27=200,r27;;	// safety margin
   1.144  	cmp.ltu p6,p0=r26,r27
   1.145 @@ -371,9 +369,9 @@ GLOBAL_ENTRY(fast_tick_reflect)
   1.146  	cmp.ne p6,p0=r21,r0
   1.147  (p6)	br.cond.spnt.few rp;;
   1.148  	// definitely have a domain tick
   1.149 -	mov cr.eoi=r0;;
   1.150 -	mov rp=r29;;
   1.151 -	mov cr.itm=r26;;	// ensure next tick
   1.152 +	mov cr.eoi=r0
   1.153 +	mov rp=r29
   1.154 +	mov cr.itm=r26		// ensure next tick
   1.155  #ifdef FAST_REFLECT_CNT
   1.156  	movl r20=PERFC(fast_reflect + (0x3000>>8));;
   1.157  	ld4 r21=[r20];;
   1.158 @@ -392,29 +390,29 @@ GLOBAL_ENTRY(fast_tick_reflect)
   1.159  	tbit.nz p6,p0=r20,16;;	// check itv.m (discard) bit
   1.160  (p6)	br.cond.spnt.few fast_tick_reflect_done;;
   1.161  	extr.u r27=r20,0,6	// r27 has low 6 bits of itv.vector
   1.162 -	extr.u r26=r20,6,2;;	// r26 has irr index of itv.vector
   1.163 +	extr.u r26=r20,6,2	// r26 has irr index of itv.vector
   1.164  	movl r19=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
   1.165  	ld8 r19=[r19];;
   1.166  	adds r22=IA64_VCPU_DOMAIN_ITM_LAST_OFFSET,r19
   1.167  	adds r23=IA64_VCPU_DOMAIN_ITM_OFFSET,r19;;
   1.168 -	ld8 r24=[r22];;
   1.169 +	ld8 r24=[r22]
   1.170  	ld8 r23=[r23];;
   1.171  	cmp.eq p6,p0=r23,r24	// skip if this tick already delivered
   1.172  (p6)	br.cond.spnt.few fast_tick_reflect_done;;
   1.173  	// set irr bit
   1.174 -	adds r21=IA64_VCPU_IRR0_OFFSET,r19;
   1.175 +	adds r21=IA64_VCPU_IRR0_OFFSET,r19
   1.176  	shl r26=r26,3;;
   1.177 -	add r21=r21,r26;;
   1.178 +	add r21=r21,r26
   1.179  	mov r25=1;;
   1.180 -	shl r22=r25,r27;;
   1.181 +	shl r22=r25,r27
   1.182  	ld8 r23=[r21];;
   1.183  	or r22=r22,r23;;
   1.184 -	st8 [r21]=r22;;
   1.185 +	st8 [r21]=r22
   1.186  	// set evtchn_upcall_pending!
   1.187  	adds r20=XSI_PSR_I_ADDR_OFS-XSI_PSR_IC_OFS,r18;;
   1.188  	ld8 r20=[r20];;
   1.189  	adds r20=-1,r20;;		// evtchn_upcall_pending
   1.190 -	st1 [r20]=r25;;
   1.191 +	st1 [r20]=r25
   1.192  	// if interrupted at pl0, we're done
   1.193  	extr.u r16=r17,IA64_PSR_CPL0_BIT,2;;
   1.194  	cmp.eq p6,p0=r16,r0;;
   1.195 @@ -432,20 +430,20 @@ GLOBAL_ENTRY(fast_tick_reflect)
   1.196  	//	r18 == XSI_PSR_IC
   1.197  	//	r19 == IA64_KR(CURRENT)
   1.198  	//	r31 == pr
   1.199 -	mov r16=cr.isr;;
   1.200 -	mov r29=cr.iip;;
   1.201 +	mov r16=cr.isr
   1.202 +	mov r29=cr.iip
   1.203  	adds r21=XSI_IIP_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.204 -	st8 [r21]=r29 ;;
   1.205 +	st8 [r21]=r29
   1.206  	// set shared_mem isr
   1.207 -	extr.u r16=r16,38,1;;	// grab cr.isr.ir bit
   1.208 -	dep r16=r16,r0,38,1 ;;	// insert into cr.isr (rest of bits zero)
   1.209 -	extr.u r20=r17,41,2 ;;	// get ipsr.ri
   1.210 -	dep r16=r20,r16,41,2 ;; // deposit cr.isr.ei
   1.211 -	adds r21=XSI_ISR_OFS-XSI_PSR_IC_OFS,r18 ;; 
   1.212 -	st8 [r21]=r16 ;;
   1.213 +	extr.u r16=r16,IA64_ISR_IR_BIT,1;;	// grab cr.isr.ir bit
   1.214 +	dep r16=r16,r0,IA64_ISR_IR_BIT,1	// insert into cr.isr (rest of bits zero)
   1.215 +	extr.u r20=r17,IA64_PSR_RI_BIT,2;;	// get ipsr.ri
   1.216 +	dep r16=r20,r16,IA64_PSR_RI_BIT,2	// deposit cr.isr.ei
   1.217 +	adds r21=XSI_ISR_OFS-XSI_PSR_IC_OFS,r18;; 
   1.218 +	st8 [r21]=r16
   1.219  	// set cr.ipsr (make sure cpl==2!)
   1.220 -	mov r29=r17 ;;
   1.221 -	movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT);;
   1.222 +	mov r29=r17
   1.223 +	movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT)
   1.224  	movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0|IA64_PSR_CPL1);;
   1.225  	and r29=r29,r27;;
   1.226  	or r29=r29,r28;;
   1.227 @@ -454,94 +452,93 @@ GLOBAL_ENTRY(fast_tick_reflect)
   1.228  	extr.u r29=r17,IA64_PSR_CPL0_BIT,2;;
   1.229  	cmp.eq p7,p0=CONFIG_CPL0_EMUL,r29;;
   1.230  (p7)	dep r17=0,r17,IA64_PSR_CPL0_BIT,2
   1.231 -	;;
   1.232 -	movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT);;
   1.233 +	movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT)
   1.234  	movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN|IA64_PSR_I|IA64_PSR_IC);;
   1.235  	or r17=r17,r28;;
   1.236 -	and r17=r17,r27;;
   1.237 +	and r17=r17,r27
   1.238  	ld4 r16=[r18];;
   1.239 -	cmp.ne p6,p0=r16,r0;;
   1.240 +	cmp.ne p6,p0=r16,r0
   1.241  	movl r22=THIS_CPU(current_psr_i_addr);;
   1.242  	ld8 r22=[r22]
   1.243  (p6)	dep r17=-1,r17,IA64_PSR_IC_BIT,1 ;;
   1.244  	ld1 r16=[r22];;
   1.245  	cmp.eq p6,p0=r16,r0;;
   1.246 -(p6)	dep r17=-1,r17,IA64_PSR_I_BIT,1 ;;
   1.247 +(p6)	dep r17=-1,r17,IA64_PSR_I_BIT,1
   1.248  	mov r20=1
   1.249 -	adds r21=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.250 -	st8 [r21]=r17 ;;
   1.251 +	adds r21=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18;;
   1.252 +	st8 [r21]=r17
   1.253  	// set shared_mem interrupt_delivery_enabled to 0
   1.254  	// set shared_mem interrupt_collection_enabled to 0
   1.255 -	st1 [r22]=r20;;
   1.256 +	st1 [r22]=r20
   1.257  	st4 [r18]=r0;;
   1.258  	// cover and set shared_mem precover_ifs to cr.ifs
   1.259  	// set shared_mem ifs to 0
   1.260  	cover ;;
   1.261 -	mov r20=cr.ifs;;
   1.262 +	mov r20=cr.ifs
   1.263  	adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.264  	st8 [r21]=r0 ;;
   1.265  	adds r21=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.266 -	st8 [r21]=r20 ;;
   1.267 +	st8 [r21]=r20
   1.268  	// leave cr.ifs alone for later rfi
   1.269  	// set iip to go to domain IVA break instruction vector
   1.270  	adds r22=IA64_VCPU_IVA_OFFSET,r19;;
   1.271 -	ld8 r23=[r22];;
   1.272 +	ld8 r23=[r22]
   1.273  	movl r24=0x3000;;
   1.274  	add r24=r24,r23;;
   1.275 -	mov cr.iip=r24;;
   1.276 +	mov cr.iip=r24
   1.277  	// OK, now all set to go except for switch to virtual bank0
   1.278  	mov r30=r2
   1.279  	mov r29=r3
   1.280  #ifdef HANDLE_AR_UNAT
   1.281 -	mov r28=ar.unat;
   1.282 +	mov r28=ar.unat
   1.283  #endif
   1.284  	;;
   1.285  	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18
   1.286  	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18
   1.287  	;;
   1.288  	bsw.1;;
   1.289 -	.mem.offset 0,0; st8.spill [r2]=r16,16;
   1.290 +	.mem.offset 0,0; st8.spill [r2]=r16,16
   1.291  	.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
   1.292 -	.mem.offset 0,0; st8.spill [r2]=r18,16;
   1.293 +	.mem.offset 0,0; st8.spill [r2]=r18,16
   1.294  	.mem.offset 8,0; st8.spill [r3]=r19,16 ;;
   1.295 -	.mem.offset 0,0; st8.spill [r2]=r20,16;
   1.296 +	.mem.offset 0,0; st8.spill [r2]=r20,16
   1.297  	.mem.offset 8,0; st8.spill [r3]=r21,16 ;;
   1.298 -	.mem.offset 0,0; st8.spill [r2]=r22,16;
   1.299 +	.mem.offset 0,0; st8.spill [r2]=r22,16
   1.300  	.mem.offset 8,0; st8.spill [r3]=r23,16 ;;
   1.301 -	.mem.offset 0,0; st8.spill [r2]=r24,16;
   1.302 +	.mem.offset 0,0; st8.spill [r2]=r24,16
   1.303  	.mem.offset 8,0; st8.spill [r3]=r25,16 ;;
   1.304 -	.mem.offset 0,0; st8.spill [r2]=r26,16;
   1.305 +	.mem.offset 0,0; st8.spill [r2]=r26,16
   1.306  	.mem.offset 8,0; st8.spill [r3]=r27,16 ;;
   1.307 -	.mem.offset 0,0; st8.spill [r2]=r28,16;
   1.308 +	.mem.offset 0,0; st8.spill [r2]=r28,16
   1.309  	.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
   1.310 -	.mem.offset 0,0; st8.spill [r2]=r30,16;
   1.311 +	.mem.offset 0,0; st8.spill [r2]=r30,16
   1.312  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
   1.313  #ifdef HANDLE_AR_UNAT
   1.314   	// r16~r23 are preserved regsin bank0 regs, we need to restore them,
   1.315  	// r24~r31 are scratch regs, we don't need to handle NaT bit,
   1.316  	// because OS handler must assign it before access it
   1.317 -	ld8 r16=[r2],16;
   1.318 +	ld8 r16=[r2],16
   1.319  	ld8 r17=[r3],16;;
   1.320 -	ld8 r18=[r2],16;
   1.321 +	ld8 r18=[r2],16
   1.322  	ld8 r19=[r3],16;;
   1.323 -	ld8 r20=[r2],16;
   1.324 +	ld8 r20=[r2],16
   1.325  	ld8 r21=[r3],16;;
   1.326 -	ld8 r22=[r2],16;
   1.327 +	ld8 r22=[r2],16
   1.328  	ld8 r23=[r3],16;;
   1.329  #endif
   1.330  	;;
   1.331  	bsw.0 ;;
   1.332 -	mov r24=ar.unat;
   1.333 +	mov r24=ar.unat
   1.334  	mov r2=r30
   1.335  	mov r3=r29
   1.336  #ifdef HANDLE_AR_UNAT
   1.337 -	mov ar.unat=r28;
   1.338 +	mov ar.unat=r28
   1.339  #endif
   1.340  	;;
   1.341 -	adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18 ;
   1.342 +	adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18
   1.343  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.344 -	st8 [r25]=r24;
   1.345 -	st4 [r20]=r0 ;;
   1.346 +	st8 [r25]=r24
   1.347 +	st4 [r20]=r0
   1.348  fast_tick_reflect_done:
   1.349  	mov pr=r31,-1 ;;
   1.350  	rfi
   1.351 @@ -557,13 +554,13 @@ GLOBAL_ENTRY(fast_break_reflect)
   1.352  #ifndef FAST_BREAK // see beginning of file
   1.353  	br.sptk.many dispatch_break_fault ;;
   1.354  #endif
   1.355 -	mov r30=cr.ipsr;;
   1.356 +	mov r30=cr.ipsr
   1.357  	mov r29=cr.iip;;
   1.358  	extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
   1.359 -	cmp.ne p7,p0=r21,r0 ;;
   1.360 +	cmp.ne p7,p0=r21,r0
   1.361  (p7)	br.spnt.few dispatch_break_fault ;;
   1.362  	extr.u r21=r30,IA64_PSR_PP_BIT,1 ;;
   1.363 -	cmp.ne p7,p0=r21,r0 ;;
   1.364 +	cmp.ne p7,p0=r21,r0
   1.365  (p7)	br.spnt.few dispatch_break_fault ;;
   1.366          movl r20=IA64_PSR_CPL ;; 
   1.367          and r22=r20,r30 ;;
   1.368 @@ -579,17 +576,17 @@ GLOBAL_ENTRY(fast_break_reflect)
   1.369  1:	
   1.370  #if 1 /* special handling in case running on simulator */
   1.371  	movl r20=first_break;;
   1.372 -	ld4 r23=[r20];;
   1.373 -	movl r21=0x80001;
   1.374 +	ld4 r23=[r20]
   1.375 +	movl r21=0x80001
   1.376  	movl r22=0x80002;;
   1.377 -	cmp.ne p7,p0=r23,r0;;
   1.378 +	cmp.ne p7,p0=r23,r0
   1.379  (p7)	br.spnt.few dispatch_break_fault ;;
   1.380 -	cmp.eq p7,p0=r21,r17;
   1.381 +	cmp.eq p7,p0=r21,r17
   1.382  (p7)	br.spnt.few dispatch_break_fault ;;
   1.383 -	cmp.eq p7,p0=r22,r17;
   1.384 +	cmp.eq p7,p0=r22,r17
   1.385  (p7)	br.spnt.few dispatch_break_fault ;;
   1.386  #endif
   1.387 -	movl r20=0x2c00;
   1.388 +	movl r20=0x2c00
   1.389  	// save iim in shared_info
   1.390  	adds r21=XSI_IIM_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.391  	st8 [r21]=r17;;
   1.392 @@ -606,7 +603,7 @@ END(fast_break_reflect)
   1.393  //	r31 == pr
   1.394  ENTRY(fast_reflect)
   1.395  #ifdef FAST_REFLECT_CNT
   1.396 -	movl r22=PERFC(fast_reflect);
   1.397 +	movl r22=PERFC(fast_reflect)
   1.398  	shr r23=r20,8-2;;
   1.399  	add r22=r22,r23;;
   1.400  	ld4 r21=[r22];;
   1.401 @@ -622,7 +619,7 @@ ENTRY(fast_reflect)
   1.402  	movl r21=THIS_CPU(current_psr_i_addr)
   1.403  	mov r29=r30 ;;
   1.404  	ld8 r21=[r21]
   1.405 -	movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT);;
   1.406 +	movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT)
   1.407  	movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0|IA64_PSR_CPL1);;
   1.408  	and r29=r29,r27;;
   1.409  	or r29=r29,r28;;
   1.410 @@ -635,30 +632,28 @@ ENTRY(fast_reflect)
   1.411  	extr.u r29=r30,IA64_PSR_CPL0_BIT,2;;
   1.412  	cmp.eq p7,p0=CONFIG_CPL0_EMUL,r29;;
   1.413  (p7)	dep r30=0,r30,IA64_PSR_CPL0_BIT,2
   1.414 -	;;
   1.415 -	movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT);;
   1.416 +	movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT)
   1.417  	movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN);;
   1.418  	or r30=r30,r28;;
   1.419 -	and r30=r30,r27;;
   1.420 +	and r30=r30,r27
   1.421  	// also set shared_mem ipsr.i and ipsr.ic appropriately
   1.422  	ld1 r22=[r21]
   1.423  	ld4 r24=[r18];;
   1.424  	cmp4.eq p6,p7=r24,r0;;
   1.425  (p6)	dep r30=0,r30,IA64_PSR_IC_BIT,1
   1.426 -(p7)	dep r30=-1,r30,IA64_PSR_IC_BIT,1 ;;
   1.427 +(p7)	dep r30=-1,r30,IA64_PSR_IC_BIT,1
   1.428  	mov r24=r21
   1.429  	cmp.ne p6,p7=r22,r0;;
   1.430  (p6)	dep r30=0,r30,IA64_PSR_I_BIT,1
   1.431 -(p7)	dep r30=-1,r30,IA64_PSR_I_BIT,1 ;;
   1.432 +(p7)	dep r30=-1,r30,IA64_PSR_I_BIT,1
   1.433  	mov r22=1
   1.434  	adds r21=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 
   1.435 -	;;
   1.436  	adds r27=XSI_VPSR_DFH_OFS-XSI_PSR_IC_OFS,r18;;
   1.437  	ld1 r28=[r27];;
   1.438  	st1 [r27]=r0
   1.439  	dep r30=r28,r30,IA64_PSR_DFH_BIT,1
   1.440  	;;
   1.441 -	st8 [r21]=r30 ;;
   1.442 +	st8 [r21]=r30
   1.443  	// set shared_mem interrupt_delivery_enabled to 0
   1.444  	// set shared_mem interrupt_collection_enabled to 0
   1.445  	st1 [r24]=r22
   1.446 @@ -666,11 +661,11 @@ ENTRY(fast_reflect)
   1.447  	// cover and set shared_mem precover_ifs to cr.ifs
   1.448  	// set shared_mem ifs to 0
   1.449  	cover ;;
   1.450 -	mov r24=cr.ifs;;
   1.451 +	mov r24=cr.ifs
   1.452  	adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.453  	st8 [r21]=r0 ;;
   1.454  	adds r21=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.455 -	st8 [r21]=r24 ;;
   1.456 +	st8 [r21]=r24
   1.457  	// FIXME: need to save iipa and isr to be arch-compliant
   1.458  	// set iip to go to domain IVA break instruction vector
   1.459  	movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
   1.460 @@ -678,59 +673,60 @@ ENTRY(fast_reflect)
   1.461  	adds r22=IA64_VCPU_IVA_OFFSET,r22;;
   1.462  	ld8 r23=[r22];;
   1.463  	add r20=r20,r23;;
   1.464 -	mov cr.iip=r20;;
   1.465 +	mov cr.iip=r20
   1.466  	// OK, now all set to go except for switch to virtual bank0
   1.467  	mov r30=r2
   1.468  	mov r29=r3
   1.469  #ifdef HANDLE_AR_UNAT
   1.470 -	mov r28=ar.unat;
   1.471 +	mov r28=ar.unat
   1.472  #endif
   1.473 -	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18;
   1.474 +	;;
   1.475 +	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18
   1.476  	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18
   1.477  	;;
   1.478  	bsw.1;;
   1.479 -	.mem.offset 0,0; st8.spill [r2]=r16,16;
   1.480 +	.mem.offset 0,0; st8.spill [r2]=r16,16
   1.481  	.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
   1.482 -	.mem.offset 0,0; st8.spill [r2]=r18,16;
   1.483 +	.mem.offset 0,0; st8.spill [r2]=r18,16
   1.484  	.mem.offset 8,0; st8.spill [r3]=r19,16 ;;
   1.485 -	.mem.offset 0,0; st8.spill [r2]=r20,16;
   1.486 +	.mem.offset 0,0; st8.spill [r2]=r20,16
   1.487  	.mem.offset 8,0; st8.spill [r3]=r21,16 ;;
   1.488 -	.mem.offset 0,0; st8.spill [r2]=r22,16;
   1.489 +	.mem.offset 0,0; st8.spill [r2]=r22,16
   1.490  	.mem.offset 8,0; st8.spill [r3]=r23,16 ;;
   1.491 -	.mem.offset 0,0; st8.spill [r2]=r24,16;
   1.492 +	.mem.offset 0,0; st8.spill [r2]=r24,16
   1.493  	.mem.offset 8,0; st8.spill [r3]=r25,16 ;;
   1.494 -	.mem.offset 0,0; st8.spill [r2]=r26,16;
   1.495 +	.mem.offset 0,0; st8.spill [r2]=r26,16
   1.496  	.mem.offset 8,0; st8.spill [r3]=r27,16 ;;
   1.497 -	.mem.offset 0,0; st8.spill [r2]=r28,16;
   1.498 +	.mem.offset 0,0; st8.spill [r2]=r28,16
   1.499  	.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
   1.500 -	.mem.offset 0,0; st8.spill [r2]=r30,16;
   1.501 +	.mem.offset 0,0; st8.spill [r2]=r30,16
   1.502  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
   1.503  #ifdef HANDLE_AR_UNAT
   1.504  	// r16~r23 are preserved regs in bank0 regs, we need to restore them,
   1.505  	// r24~r31 are scratch regs, we don't need to handle NaT bit,
   1.506  	// because OS handler must assign it before access it
   1.507 -	ld8 r16=[r2],16;
   1.508 +	ld8 r16=[r2],16
   1.509  	ld8 r17=[r3],16;;
   1.510 -	ld8 r18=[r2],16;
   1.511 +	ld8 r18=[r2],16
   1.512  	ld8 r19=[r3],16;;
   1.513 -	ld8 r20=[r2],16;
   1.514 +	ld8 r20=[r2],16
   1.515  	ld8 r21=[r3],16;;
   1.516 -	ld8 r22=[r2],16;
   1.517 +	ld8 r22=[r2],16
   1.518  	ld8 r23=[r3],16;;
   1.519  #endif
   1.520  	;;
   1.521  	bsw.0 ;;
   1.522 -	mov r24=ar.unat;
   1.523 +	mov r24=ar.unat
   1.524  	mov r2=r30
   1.525  	mov r3=r29
   1.526  #ifdef HANDLE_AR_UNAT
   1.527 -	mov ar.unat=r28;
   1.528 +	mov ar.unat=r28
   1.529  #endif
   1.530  	;;
   1.531 -	adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18 ;
   1.532 +	adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18
   1.533  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.534 -	st8 [r25]=r24;
   1.535 -	st4 [r20]=r0 ;;
   1.536 +	st8 [r25]=r24
   1.537 +	st4 [r20]=r0
   1.538  	mov pr=r31,-1 ;;
   1.539  	rfi
   1.540  	;;
   1.541 @@ -746,7 +742,7 @@ GLOBAL_ENTRY(fast_access_reflect)
   1.542  #ifndef FAST_ACCESS_REFLECT // see beginning of file
   1.543  	br.spnt.few dispatch_reflection ;;
   1.544  #endif
   1.545 -	mov r30=cr.ipsr;;
   1.546 +	mov r30=cr.ipsr
   1.547  	mov r29=cr.iip;;
   1.548  	extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
   1.549  	cmp.ne p7,p0=r21,r0
   1.550 @@ -763,7 +759,7 @@ GLOBAL_ENTRY(fast_access_reflect)
   1.551  	cmp.eq p7,p0=r0,r21
   1.552  (p7)	br.spnt.few dispatch_reflection ;;
   1.553  	// set shared_mem ifa, FIXME: should we validate it?
   1.554 -	mov r17=cr.ifa;;
   1.555 +	mov r17=cr.ifa
   1.556  	adds r21=XSI_IFA_OFS-XSI_PSR_IC_OFS,r18 ;; 
   1.557  	st8 [r21]=r17 ;;
   1.558  	// get rr[ifa] and save to itir in shared memory (extra bits ignored)
   1.559 @@ -827,17 +823,17 @@ GLOBAL_ENTRY(fast_tlb_miss_reflect)
   1.560  (p7)	br.spnt.few page_fault ;;
   1.561  fast_tlb_no_tr_match:
   1.562  	movl r27=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
   1.563 -	ld8 r27=[r27];;
   1.564 +	ld8 r27=[r27]
   1.565  	tbit.nz p6,p7=r16,IA64_ISR_X_BIT;;
   1.566 -(p6)	adds r25=IA64_VCPU_ITLB_OFFSET,r27;;
   1.567 +(p6)	adds r25=IA64_VCPU_ITLB_OFFSET,r27
   1.568  (p7)	adds r25=IA64_VCPU_DTLB_OFFSET,r27;;
   1.569  	ld8 r20=[r25],8;;
   1.570 -	tbit.z p7,p0=r20,0;;	// present?
   1.571 +	tbit.z p7,p0=r20,VTLB_PTE_P_BIT	// present?
   1.572  (p7)	br.cond.spnt.few 1f;;
   1.573  	// if ifa is in range of tlb, don't bother to check rid, go slow path
   1.574  	ld8 r21=[r25],8;;
   1.575  	mov r23=1
   1.576 -	extr.u r21=r21,2,6;;
   1.577 +	extr.u r21=r21,IA64_ITIR_PS,IA64_ITIR_PS_LEN;;
   1.578  	shl r22=r23,r21
   1.579  	ld8 r21=[r25],8;;
   1.580  	cmp.ltu p7,p0=r17,r21
   1.581 @@ -853,9 +849,9 @@ 1:	// check the guest VHPT
   1.582  (p7)	br.cond.spnt.few page_fault;;
   1.583  	// if (!rr.ve || !(pta & IA64_PTA_VE)) take slow way for now
   1.584  	// FIXME: later, we deliver an alt_d/i vector after thash and itir
   1.585 -	tbit.z p7,p0=r19,IA64_PTA_VE_BIT;;	// 
   1.586 +	tbit.z p7,p0=r19,IA64_PTA_VE_BIT
   1.587  (p7)	br.cond.spnt.few page_fault;;
   1.588 -	extr.u r25=r17,61,3;;
   1.589 +	extr.u r25=r17,61,3
   1.590  	adds r21=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.591  	shl r25=r25,3;;
   1.592  	add r21=r21,r25;;
   1.593 @@ -864,7 +860,7 @@ 1:	// check the guest VHPT
   1.594  (p7)	br.cond.spnt.few page_fault;;
   1.595  
   1.596  	// compute and save away itir (r22 & RR_PS_MASK)
   1.597 -	movl r21=0xfc;;
   1.598 +	movl r21=IA64_ITIR_PS_MASK;;
   1.599  	and r22=r22,r21;;
   1.600  	adds r21=XSI_ITIR_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.601  	st8 [r21]=r22;;
   1.602 @@ -887,17 +883,16 @@ 1:	// check the guest VHPT
   1.603  	ld8 r24 = [r19]			// pta
   1.604  	;;
   1.605  	ld8 r23 = [r27]			// rrs[vadr>>61]
   1.606 -	extr.u r26 = r24, 2, 6
   1.607 -	;;
   1.608 -	extr.u r22 = r23, 2, 6
   1.609 -	shl r30 = r25, r26
   1.610 +	extr.u r26 = r24, IA64_PTA_SIZE_BIT, IA64_PTA_SIZE_LEN
   1.611  	;;
   1.612 -	shr.u r19 = r17, r22
   1.613 -	shr.u r29 = r24, 15
   1.614 +	extr.u r22 = r23, IA64_RR_PS, IA64_RR_PS_LEN
   1.615 +	shl r30 = r25, r26		// pt size
   1.616  	;;
   1.617 -	adds r30 = -1, r30
   1.618 +	shr.u r19 = r17, r22		// ifa pg number
   1.619 +	shr.u r29 = r24, IA64_PTA_BASE_BIT
   1.620 +	adds r30 = -1, r30		// pt size mask
   1.621  	;;
   1.622 -	shladd r27 = r19, 3, r0
   1.623 +	shladd r27 = r19, 3, r0		// vhpt offset
   1.624  	extr.u r26 = r30, 15, 46
   1.625  	;;
   1.626  	andcm r24 = r29, r26
   1.627 @@ -916,7 +911,7 @@ 1:	// check the guest VHPT
   1.628  	or r19 = r19, r30
   1.629  	;;
   1.630  	adds r23=XSI_IHA_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.631 -	st8 [r23]=r19;;
   1.632 +	st8 [r23]=r19
   1.633  	// done with thash, check guest VHPT
   1.634  
   1.635  	adds r20 = XSI_PTA_OFS-XSI_PSR_IC_OFS, r18;;
   1.636 @@ -925,7 +920,7 @@ 1:	// check the guest VHPT
   1.637  	// if (((r17=address ^ r24=pta) & ((itir_mask(pta) << 3) >> 3)) != 0) {
   1.638  	mov r20=-8
   1.639  	xor r21=r17,r24
   1.640 -	extr.u r24=r24,2,6;;
   1.641 +	extr.u r24=r24,IA64_PTA_SIZE_BIT,IA64_PTA_SIZE_LEN;;
   1.642  	shl r20=r20,r24;;
   1.643  	shr.u r20=r20,3;;
   1.644  	and r21=r20,r21;;
   1.645 @@ -934,7 +929,7 @@ 1:	// check the guest VHPT
   1.646  	// __copy_from_user(&pte, r19=(void *)(*iha), sizeof(pte)=8)
   1.647  	// prepare for possible nested dtlb fault
   1.648  	mov r29=b0
   1.649 -	movl r30=guest_vhpt_miss;;
   1.650 +	movl r30=guest_vhpt_miss
   1.651  	// now go fetch the entry from the guest VHPT
   1.652  	ld8 r20=[r19];;
   1.653  	// if we wind up here, we successfully loaded the VHPT entry
   1.654 @@ -961,14 +956,14 @@ 1:	// check the guest VHPT
   1.655  //	r30 == recovery ip if failure occurs
   1.656  //	r31 == pr
   1.657  	tbit.nz p6,p7=r16,IA64_ISR_X_BIT;;
   1.658 -(p6)	mov r17=1;;
   1.659 -(p7)	mov r17=0;;
   1.660 +(p6)	mov r17=1
   1.661 +(p7)	mov r17=0
   1.662  	mov r16=r20
   1.663 -	mov r29=b0 ;;
   1.664 -	movl r30=recover_and_page_fault ;;
   1.665 +	mov r29=b0
   1.666 +	movl r30=recover_and_page_fault
   1.667  	adds r21=XSI_ITIR_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.668  	ld8 r24=[r21];;
   1.669 -	extr.u r24=r24,2,6;;
   1.670 +	extr.u r24=r24,IA64_ITIR_PS,IA64_ITIR_PS_LEN
   1.671  	// IFA already in PSCB
   1.672  	br.cond.sptk.many fast_insert;;
   1.673  END(fast_tlb_miss_reflect)
   1.674 @@ -981,13 +976,13 @@ ENTRY(recover_and_page_fault)
   1.675  	adds r22=1,r22;;
   1.676  	st4 [r21]=r22;;
   1.677  #endif
   1.678 -	mov b0=r29;;
   1.679 +	mov b0=r29
   1.680  	br.cond.sptk.many page_fault;;
   1.681  
   1.682  // if we wind up here, we missed in guest VHPT so recover
   1.683  // from nested dtlb fault and reflect a tlb fault to the guest
   1.684  guest_vhpt_miss:
   1.685 -	mov b0=r29;;
   1.686 +	mov b0=r29
   1.687  	// fault = IA64_VHPT_FAULT
   1.688  	mov r20=r0
   1.689  	br.cond.sptk.many 1f;
   1.690 @@ -998,18 +993,18 @@ guest_vhpt_miss:
   1.691  	// see vcpu_get_itir_on_fault: get ps,rid,(FIXME key) from rr[ifa]
   1.692  page_not_present:
   1.693  	tbit.nz p6,p7=r16,IA64_ISR_X_BIT;;
   1.694 -(p6)	movl r20=0x400;;
   1.695 -(p7)	movl r20=0x800;;
   1.696 +(p6)	movl r20=0x400
   1.697 +(p7)	movl r20=0x800
   1.698  
   1.699  1:	extr.u r25=r17,61,3;;
   1.700 -	adds r21=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.701 +	adds r21=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18
   1.702  	shl r25=r25,3;;
   1.703  	add r21=r21,r25;;
   1.704  	ld8 r22=[r21];;
   1.705 -	extr.u r22=r22,2,30;;
   1.706 -	dep.z r22=r22,2,30;;
   1.707 +	extr.u r22=r22,IA64_RR_PS,IA64_RR_PS_LEN+IA64_RR_RID_LEN;;
   1.708 +	dep.z r22=r22,IA64_RR_PS,IA64_RR_PS_LEN+IA64_RR_RID_LEN
   1.709  	adds r23=XSI_ITIR_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.710 -	st8 [r23]=r22;;
   1.711 +	st8 [r23]=r22
   1.712  
   1.713  	// fast reflect expects
   1.714  	//	r16 == cr.isr
   1.715 @@ -1160,36 +1155,39 @@ just_do_rfi:
   1.716  	cmp.ne p7,p0=r21,r0	// domain already did "bank 1 switch?"
   1.717  (p7)	br.cond.spnt.few 1f;
   1.718  	// OK, now all set to go except for switch to virtual bank1
   1.719 -	mov r22=1;; st4 [r20]=r22;
   1.720 -	mov r30=r2; mov r29=r3;;
   1.721 -    mov r17=ar.unat;;
   1.722 -    adds r16=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18
   1.723 -	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18;
   1.724 +	mov r22=1;;
   1.725 +	st4 [r20]=r22
   1.726 +	mov r30=r2
   1.727 +	mov r29=r3
   1.728 +	mov r17=ar.unat;;
   1.729 +	adds r16=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18
   1.730 +	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18
   1.731  	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18;;
   1.732 -    ld8 r16=[r16];;
   1.733 -    mov ar.unat=r16;;
   1.734 +	ld8 r16=[r16];;
   1.735 +	mov ar.unat=r16;;
   1.736  	bsw.1;;
   1.737  	// FIXME?: ar.unat is not really handled correctly,
   1.738  	// but may not matter if the OS is NaT-clean
   1.739 -	.mem.offset 0,0; ld8.fill r16=[r2],16 ;
   1.740 +	.mem.offset 0,0; ld8.fill r16=[r2],16
   1.741  	.mem.offset 8,0; ld8.fill r17=[r3],16 ;;
   1.742 -	.mem.offset 0,0; ld8.fill r18=[r2],16 ;
   1.743 +	.mem.offset 0,0; ld8.fill r18=[r2],16
   1.744  	.mem.offset 0,0; ld8.fill r19=[r3],16 ;;
   1.745 -	.mem.offset 8,0; ld8.fill r20=[r2],16 ;
   1.746 +	.mem.offset 8,0; ld8.fill r20=[r2],16
   1.747  	.mem.offset 8,0; ld8.fill r21=[r3],16 ;;
   1.748 -	.mem.offset 8,0; ld8.fill r22=[r2],16 ;
   1.749 +	.mem.offset 8,0; ld8.fill r22=[r2],16
   1.750  	.mem.offset 8,0; ld8.fill r23=[r3],16 ;;
   1.751 -	.mem.offset 8,0; ld8.fill r24=[r2],16 ;
   1.752 +	.mem.offset 8,0; ld8.fill r24=[r2],16
   1.753  	.mem.offset 8,0; ld8.fill r25=[r3],16 ;;
   1.754 -	.mem.offset 8,0; ld8.fill r26=[r2],16 ;
   1.755 +	.mem.offset 8,0; ld8.fill r26=[r2],16
   1.756  	.mem.offset 8,0; ld8.fill r27=[r3],16 ;;
   1.757 -	.mem.offset 8,0; ld8.fill r28=[r2],16 ;
   1.758 +	.mem.offset 8,0; ld8.fill r28=[r2],16
   1.759  	.mem.offset 8,0; ld8.fill r29=[r3],16 ;;
   1.760 -	.mem.offset 8,0; ld8.fill r30=[r2],16 ;
   1.761 +	.mem.offset 8,0; ld8.fill r30=[r2],16
   1.762  	.mem.offset 8,0; ld8.fill r31=[r3],16 ;;
   1.763  	bsw.0 ;;
   1.764 -    mov ar.unat=r17;;
   1.765 -	mov r2=r30; mov r3=r29;;
   1.766 +	mov ar.unat=r17
   1.767 +	mov r2=r30
   1.768 +	mov r3=r29
   1.769  1:	mov pr=r31,-1
   1.770  	;;
   1.771  	rfi
   1.772 @@ -1204,7 +1202,7 @@ ENTRY(rfi_check_extint)
   1.773  	// make sure none of these get trashed in case going to just_do_rfi
   1.774  	movl r30=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
   1.775  	ld8 r30=[r30];;
   1.776 -	adds r24=IA64_VCPU_INSVC3_OFFSET,r30;;
   1.777 +	adds r24=IA64_VCPU_INSVC3_OFFSET,r30
   1.778  	mov r25=192
   1.779  	adds r16=IA64_VCPU_IRR3_OFFSET,r30;;
   1.780  	ld8 r23=[r16];;
   1.781 @@ -1223,7 +1221,6 @@ ENTRY(rfi_check_extint)
   1.782  (p6)	adds r24=-8,r24;;
   1.783  (p6)	adds r25=-64,r25;;
   1.784  (p6)	ld8 r23=[r16];;
   1.785 -(p6)	cmp.eq p6,p0=r23,r0;;
   1.786  	cmp.eq p6,p0=r23,r0
   1.787  (p6)	br.cond.spnt.few just_do_rfi;	// this is actually an error
   1.788  	// r16 points to non-zero element of irr, r23 has value
   1.789 @@ -1279,25 +1276,25 @@ ENTRY(rfi_with_interrupt)
   1.790  	//	r21 == vipsr (ipsr in shared_mem)
   1.791  	//	r30 == IA64_KR(CURRENT)
   1.792  	//	r31 == pr
   1.793 -	mov r17=cr.ipsr;;
   1.794 +	mov r17=cr.ipsr
   1.795  	mov r16=cr.isr;;
   1.796  	// set shared_mem isr
   1.797 -	extr.u r16=r16,38,1;;	// grab cr.isr.ir bit
   1.798 -	dep r16=r16,r0,38,1 ;;	// insert into cr.isr (rest of bits zero)
   1.799 -	extr.u r20=r21,41,2 ;;	// get v(!)psr.ri
   1.800 -	dep r16=r20,r16,41,2 ;; // deposit cr.isr.ei
   1.801 +	extr.u r16=r16,IA64_ISR_IR_BIT,1;;	// grab cr.isr.ir bit
   1.802 +	dep r16=r16,r0,IA64_ISR_IR_BIT,1	// insert into cr.isr (rest of bits zero)
   1.803 +	extr.u r20=r21,IA64_PSR_RI_BIT,2 ;;	// get v(!)psr.ri
   1.804 +	dep r16=r20,r16,IA64_PSR_RI_BIT,2 ;; // deposit cr.isr.ei
   1.805  	adds r22=XSI_ISR_OFS-XSI_PSR_IC_OFS,r18 ;; 
   1.806  	st8 [r22]=r16;;
   1.807  	movl r22=THIS_CPU(current_psr_i_addr)
   1.808  	// set cr.ipsr (make sure cpl==2!)
   1.809  	mov r29=r17
   1.810  	movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0|IA64_PSR_CPL1)
   1.811 -	movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT);;
   1.812 +	movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT)
   1.813  	mov r20=1;;
   1.814  	ld8 r22=[r22]
   1.815  	and r29=r29,r27;;
   1.816  	or r29=r29,r28;;
   1.817 -	mov cr.ipsr=r29;;
   1.818 +	mov cr.ipsr=r29
   1.819  	// v.ipsr and v.iip are already set (and v.iip validated) as rfi target
   1.820  	// set shared_mem interrupt_delivery_enabled to 0
   1.821  	// set shared_mem interrupt_collection_enabled to 0
   1.822 @@ -1307,7 +1304,7 @@ ENTRY(rfi_with_interrupt)
   1.823  	// set shared_mem ifs to 0
   1.824  #if 0
   1.825  	cover ;;
   1.826 -	mov r20=cr.ifs;;
   1.827 +	mov r20=cr.ifs
   1.828  	adds r22=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.829  	st8 [r22]=r0 ;;
   1.830  	adds r22=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.831 @@ -1322,38 +1319,40 @@ ENTRY(rfi_with_interrupt)
   1.832  #endif
   1.833  	// set iip to go to domain IVA break instruction vector
   1.834  	adds r22=IA64_VCPU_IVA_OFFSET,r30;;
   1.835 -	ld8 r23=[r22];;
   1.836 +	ld8 r23=[r22]
   1.837  	movl r24=0x3000;;
   1.838  	add r24=r24,r23;;
   1.839  	mov cr.iip=r24;;
   1.840  #if 0
   1.841  	// OK, now all set to go except for switch to virtual bank0
   1.842 -	mov r30=r2; mov r29=r3;;
   1.843 -	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
   1.844 +	mov r30=r2
   1.845 +	mov r29=r3;;
   1.846 +	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18
   1.847  	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
   1.848  	bsw.1;;
   1.849  	// FIXME: need to handle ar.unat!
   1.850 -	.mem.offset 0,0; st8.spill [r2]=r16,16;
   1.851 +	.mem.offset 0,0; st8.spill [r2]=r16,16
   1.852  	.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
   1.853 -	.mem.offset 0,0; st8.spill [r2]=r18,16;
   1.854 +	.mem.offset 0,0; st8.spill [r2]=r18,16
   1.855  	.mem.offset 8,0; st8.spill [r3]=r19,16 ;;
   1.856 -	.mem.offset 0,0; st8.spill [r2]=r20,16;
   1.857 +	.mem.offset 0,0; st8.spill [r2]=r20,16
   1.858  	.mem.offset 8,0; st8.spill [r3]=r21,16 ;;
   1.859 -	.mem.offset 0,0; st8.spill [r2]=r22,16;
   1.860 +	.mem.offset 0,0; st8.spill [r2]=r22,16
   1.861  	.mem.offset 8,0; st8.spill [r3]=r23,16 ;;
   1.862 -	.mem.offset 0,0; st8.spill [r2]=r24,16;
   1.863 +	.mem.offset 0,0; st8.spill [r2]=r24,16
   1.864  	.mem.offset 8,0; st8.spill [r3]=r25,16 ;;
   1.865 -	.mem.offset 0,0; st8.spill [r2]=r26,16;
   1.866 +	.mem.offset 0,0; st8.spill [r2]=r26,16
   1.867  	.mem.offset 8,0; st8.spill [r3]=r27,16 ;;
   1.868 -	.mem.offset 0,0; st8.spill [r2]=r28,16;
   1.869 +	.mem.offset 0,0; st8.spill [r2]=r28,16
   1.870  	.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
   1.871 -	.mem.offset 0,0; st8.spill [r2]=r30,16;
   1.872 +	.mem.offset 0,0; st8.spill [r2]=r30,16
   1.873  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
   1.874  	bsw.0 ;;
   1.875 -	mov r2=r30; mov r3=r29;;
   1.876 +	mov r2=r30
   1.877 +	mov r3=r29;;
   1.878  #endif
   1.879  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.880 -	st4 [r20]=r0 ;;
   1.881 +	st4 [r20]=r0
   1.882  	mov pr=r31,-1 ;;
   1.883  	rfi
   1.884  END(rfi_with_interrupt)
   1.885 @@ -1372,8 +1371,8 @@ ENTRY(hyper_cover)
   1.886  	cover ;;
   1.887  	mov r30=cr.ifs
   1.888  	adds r22=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18;;
   1.889 -	st8 [r22]=r30;;
   1.890 -	mov cr.ifs=r0;;
   1.891 +	st8 [r22]=r30
   1.892 +	mov cr.ifs=r0
   1.893  	// adjust return address to skip over break instruction
   1.894  	extr.u r26=r24,41,2 ;;
   1.895  	cmp.eq p6,p7=2,r26 ;;
   1.896 @@ -1381,7 +1380,7 @@ ENTRY(hyper_cover)
   1.897  (p6)	adds r25=16,r25
   1.898  (p7)	adds r26=1,r26
   1.899  	;;
   1.900 -	dep r24=r26,r24,41,2
   1.901 +	dep r24=r26,r24,IA64_PSR_RI_BIT,2
   1.902  	;;
   1.903  	mov cr.ipsr=r24
   1.904  	mov cr.iip=r25
   1.905 @@ -1399,7 +1398,7 @@ ENTRY(hyper_ssm_dt)
   1.906  	st4 [r20]=r21;;
   1.907  #endif
   1.908  	mov r24=cr.ipsr
   1.909 -	mov r25=cr.iip;;
   1.910 +	mov r25=cr.iip
   1.911  	adds r20=XSI_METAPHYS_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.912  	ld4 r21=[r20];;
   1.913  	cmp.eq p7,p0=r21,r0	// meta==0?
   1.914 @@ -1410,15 +1409,15 @@ ENTRY(hyper_ssm_dt)
   1.915  	ld8 r23=[r22];;
   1.916  	mov rr[r0]=r23;;
   1.917  	srlz.i;;
   1.918 -	st4 [r20]=r0 ;;
   1.919 +	st4 [r20]=r0
   1.920  	// adjust return address to skip over break instruction
   1.921 -1:	extr.u r26=r24,41,2 ;;
   1.922 +1:	extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
   1.923  	cmp.eq p6,p7=2,r26 ;;
   1.924  (p6)	mov r26=0
   1.925  (p6)	adds r25=16,r25
   1.926  (p7)	adds r26=1,r26
   1.927  	;;
   1.928 -	dep r24=r26,r24,41,2
   1.929 +	dep r24=r26,r24,IA64_PSR_RI_BIT,2
   1.930  	;;
   1.931  	mov cr.ipsr=r24
   1.932  	mov cr.iip=r25
   1.933 @@ -1436,7 +1435,7 @@ ENTRY(hyper_rsm_dt)
   1.934  	st4 [r20]=r21;;
   1.935  #endif
   1.936  	mov r24=cr.ipsr
   1.937 -	mov r25=cr.iip;;
   1.938 +	mov r25=cr.iip
   1.939  	adds r20=XSI_METAPHYS_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.940  	ld4 r21=[r20];;
   1.941  	cmp.ne p7,p0=r21,r0	// meta==0?
   1.942 @@ -1448,15 +1447,15 @@ ENTRY(hyper_rsm_dt)
   1.943  	mov rr[r0]=r23;;
   1.944  	srlz.i;;
   1.945  	adds r21=1,r0 ;;
   1.946 -	st4 [r20]=r21 ;;
   1.947 +	st4 [r20]=r21
   1.948  	// adjust return address to skip over break instruction
   1.949 -1:	extr.u r26=r24,41,2 ;;
   1.950 +1:	extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
   1.951  	cmp.eq p6,p7=2,r26 ;;
   1.952  (p6)	mov r26=0
   1.953  (p6)	adds r25=16,r25
   1.954  (p7)	adds r26=1,r26
   1.955  	;;
   1.956 -	dep r24=r26,r24,41,2
   1.957 +	dep r24=r26,r24,IA64_PSR_RI_BIT,2
   1.958  	;;
   1.959  	mov cr.ipsr=r24
   1.960  	mov cr.iip=r25
   1.961 @@ -1480,9 +1479,9 @@ ENTRY(hyper_set_itm)
   1.962  	movl r20=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
   1.963  	ld8 r20=[r20];;
   1.964  	adds r20=IA64_VCPU_DOMAIN_ITM_OFFSET,r20;;
   1.965 -	st8 [r20]=r8;;
   1.966 +	st8 [r20]=r8
   1.967  	cmp.geu p6,p0=r21,r8;;
   1.968 -(p6)	mov r21=r8;;
   1.969 +(p6)	mov r21=r8
   1.970  	// now "safe set" cr.itm=r21
   1.971  	mov r23=100;;
   1.972  2:	mov cr.itm=r21;;
   1.973 @@ -1490,17 +1489,17 @@ 2:	mov cr.itm=r21;;
   1.974  	mov r22=ar.itc ;;
   1.975  	cmp.leu p6,p0=r21,r22;;
   1.976  	add r21=r21,r23;;
   1.977 -	shl r23=r23,1;;
   1.978 +	shl r23=r23,1
   1.979  (p6)	br.cond.spnt.few 2b;;
   1.980  1:	mov r24=cr.ipsr
   1.981  	mov r25=cr.iip;;
   1.982 -	extr.u r26=r24,41,2 ;;
   1.983 +	extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
   1.984  	cmp.eq p6,p7=2,r26 ;;
   1.985  (p6)	mov r26=0
   1.986  (p6)	adds r25=16,r25
   1.987  (p7)	adds r26=1,r26
   1.988  	;;
   1.989 -	dep r24=r26,r24,41,2
   1.990 +	dep r24=r26,r24,IA64_PSR_RI_BIT,2
   1.991  	;;
   1.992  	mov cr.ipsr=r24
   1.993  	mov cr.iip=r25
   1.994 @@ -1517,7 +1516,7 @@ ENTRY(hyper_get_psr)
   1.995  	st4 [r20]=r21;;
   1.996  #endif
   1.997  	mov r24=cr.ipsr
   1.998 -	movl r8=0x18ffffffff;;
   1.999 +	movl r8=0xffffffff | IA64_PSR_MC | IA64_PSR_IT;;
  1.1000  	// only return PSR{36:35,31:0}
  1.1001  	and r8=r8,r24
  1.1002  	// set vpsr.ic
  1.1003 @@ -1547,13 +1546,13 @@ ENTRY(hyper_get_psr)
  1.1004  	dep r8=r21,r8,IA64_PSR_DFH_BIT,1
  1.1005  	;;
  1.1006  	mov r25=cr.iip
  1.1007 -	extr.u r26=r24,41,2 ;;
  1.1008 +	extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
  1.1009  	cmp.eq p6,p7=2,r26 ;;
  1.1010  (p6)	mov r26=0
  1.1011  (p6)	adds r25=16,r25
  1.1012  (p7)	adds r26=1,r26
  1.1013  	;;
  1.1014 -	dep r24=r26,r24,41,2
  1.1015 +	dep r24=r26,r24,IA64_PSR_RI_BIT,2
  1.1016  	;;
  1.1017  	mov cr.ipsr=r24
  1.1018  	mov cr.iip=r25
  1.1019 @@ -1571,19 +1570,19 @@ ENTRY(hyper_get_rr)
  1.1020  	st4 [r20]=r21;;
  1.1021  #endif
  1.1022  	extr.u r25=r8,61,3;;
  1.1023 -	adds r20=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18 ;;
  1.1024 +	adds r20=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18
  1.1025  	shl r25=r25,3;;
  1.1026  	add r20=r20,r25;;
  1.1027 -	ld8 r8=[r20];;
  1.1028 +	ld8 r8=[r20]
  1.1029  1:	mov r24=cr.ipsr
  1.1030  	mov r25=cr.iip;;
  1.1031 -	extr.u r26=r24,41,2 ;;
  1.1032 +	extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
  1.1033  	cmp.eq p6,p7=2,r26 ;;
  1.1034  (p6)	mov r26=0
  1.1035  (p6)	adds r25=16,r25
  1.1036  (p7)	adds r26=1,r26
  1.1037  	;;
  1.1038 -	dep r24=r26,r24,41,2
  1.1039 +	dep r24=r26,r24,IA64_PSR_RI_BIT,2
  1.1040  	;;
  1.1041  	mov cr.ipsr=r24
  1.1042  	mov cr.iip=r25
  1.1043 @@ -1602,7 +1601,7 @@ ENTRY(hyper_set_rr)
  1.1044  	adds r21=1,r21;;
  1.1045  	st4 [r20]=r21;;
  1.1046  #endif
  1.1047 -	extr.u r26=r9,8,24	// r26 = r9.rid
  1.1048 +	extr.u r26=r9,IA64_RR_RID,IA64_RR_RID_LEN	// r26 = r9.rid
  1.1049  	movl r20=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
  1.1050  	ld8 r20=[r20];;
  1.1051  	adds r21=IA64_VCPU_STARTING_RID_OFFSET,r20;;
  1.1052 @@ -1614,7 +1613,7 @@ ENTRY(hyper_set_rr)
  1.1053  	cmp.geu p6,p0=r22,r23	// if r9.rid + starting_rid >= ending_rid
  1.1054  (p6)	br.cond.spnt.few 1f;	// this is an error, but just ignore/return
  1.1055  	// r21=starting_rid
  1.1056 -	adds r20=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18 ;;
  1.1057 +	adds r20=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18
  1.1058  	shl r25=r25,3;;
  1.1059  	add r20=r20,r25;;
  1.1060  	st8 [r20]=r9;;		// store away exactly what was passed
  1.1061 @@ -1624,7 +1623,7 @@ ENTRY(hyper_set_rr)
  1.1062  	extr.u r27=r22,0,8
  1.1063  	extr.u r28=r22,8,8
  1.1064  	extr.u r29=r22,16,8;;
  1.1065 -	dep.z r23=PAGE_SHIFT,2,6;;
  1.1066 +	dep.z r23=PAGE_SHIFT,IA64_RR_PS,IA64_RR_PS_LEN;;
  1.1067  	dep r23=-1,r23,0,1;;	// mangling is swapping bytes 1 & 3
  1.1068  	dep r23=r27,r23,24,8;;
  1.1069  	dep r23=r28,r23,16,8;;
  1.1070 @@ -1635,13 +1634,13 @@ ENTRY(hyper_set_rr)
  1.1071  	// done, mosey on back
  1.1072  1:	mov r24=cr.ipsr
  1.1073  	mov r25=cr.iip;;
  1.1074 -	extr.u r26=r24,41,2 ;;
  1.1075 +	extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
  1.1076  	cmp.eq p6,p7=2,r26 ;;
  1.1077  (p6)	mov r26=0
  1.1078  (p6)	adds r25=16,r25
  1.1079  (p7)	adds r26=1,r26
  1.1080  	;;
  1.1081 -	dep r24=r26,r24,41,2
  1.1082 +	dep r24=r26,r24,IA64_PSR_RI_BIT,2
  1.1083  	;;
  1.1084  	mov cr.ipsr=r24
  1.1085  	mov cr.iip=r25
  1.1086 @@ -1677,13 +1676,13 @@ ENTRY(hyper_set_rr0_to_rr4)
  1.1087  	adds r25=IA64_VCPU_ENDING_RID_OFFSET,r17
  1.1088  	;; 
  1.1089  	ld4 r22=[r21] // r22 = current->starting_rid
  1.1090 -	extr.u r26=r8,8,24	// r26 = r8.rid
  1.1091 -	extr.u r27=r9,8,24	// r27 = r9.rid
  1.1092 +	extr.u r26=r8,IA64_RR_RID,IA64_RR_RID_LEN	// r26 = r8.rid
  1.1093 +	extr.u r27=r9,IA64_RR_RID,IA64_RR_RID_LEN	// r27 = r9.rid
  1.1094  	ld4 r23=[r25] // r23 = current->ending_rid
  1.1095 -	extr.u r28=r10,8,24	// r28 = r10.rid
  1.1096 -	extr.u r29=r11,8,24	// r29 = r11.rid
  1.1097 +	extr.u r28=r10,IA64_RR_RID,IA64_RR_RID_LEN	// r28 = r10.rid
  1.1098 +	extr.u r29=r11,IA64_RR_RID,IA64_RR_RID_LEN	// r29 = r11.rid
  1.1099  	adds r24=IA64_VCPU_META_SAVED_RR0_OFFSET,r17
  1.1100 -	extr.u r30=r14,8,24	// r30 = r14.rid
  1.1101 +	extr.u r30=r14,IA64_RR_RID,IA64_RR_RID_LEN	// r30 = r14.rid
  1.1102  	;; 
  1.1103  	add r16=r26,r22
  1.1104  	add r17=r27,r22
  1.1105 @@ -1873,13 +1872,13 @@ ENTRY(hyper_set_rr0_to_rr4)
  1.1106  	// done, mosey on back
  1.1107  1:	mov r24=cr.ipsr
  1.1108  	mov r25=cr.iip;;
  1.1109 -	extr.u r26=r24,41,2 ;;
  1.1110 +	extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
  1.1111  	cmp.eq p6,p7=2,r26 ;;
  1.1112  (p6)	mov r26=0
  1.1113  (p6)	adds r25=16,r25
  1.1114  (p7)	adds r26=1,r26
  1.1115  	;;
  1.1116 -	dep r24=r26,r24,41,2
  1.1117 +	dep r24=r26,r24,IA64_PSR_RI_BIT,2
  1.1118  	;;
  1.1119  	mov cr.ipsr=r24
  1.1120  	mov cr.iip=r25
  1.1121 @@ -1898,7 +1897,7 @@ ENTRY(hyper_set_kr)
  1.1122  	adds r21=1,r21;;
  1.1123  	st4 [r20]=r21;;
  1.1124  #endif
  1.1125 -	adds r21=XSI_KR0_OFS-XSI_PSR_IC_OFS,r18 ;;
  1.1126 +	adds r21=XSI_KR0_OFS-XSI_PSR_IC_OFS,r18
  1.1127  	shl r20=r8,3;;
  1.1128  	add r22=r20,r21;;
  1.1129  	st8 [r22]=r9;;
  1.1130 @@ -1929,13 +1928,13 @@ ENTRY(hyper_set_kr)
  1.1131  	// done, mosey on back
  1.1132  1:	mov r24=cr.ipsr
  1.1133  	mov r25=cr.iip;;
  1.1134 -	extr.u r26=r24,41,2 ;;
  1.1135 +	extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
  1.1136  	cmp.eq p6,p7=2,r26 ;;
  1.1137  (p6)	mov r26=0
  1.1138  (p6)	adds r25=16,r25
  1.1139  (p7)	adds r26=1,r26
  1.1140  	;;
  1.1141 -	dep r24=r26,r24,41,2
  1.1142 +	dep r24=r26,r24,IA64_PSR_RI_BIT,2
  1.1143  	;;
  1.1144  	mov cr.ipsr=r24
  1.1145  	mov cr.iip=r25
  1.1146 @@ -1970,9 +1969,9 @@ ENTRY(hyper_thash)
  1.1147  	ld8 r24 = [r19]			// pta
  1.1148  	;;
  1.1149  	ld8 r23 = [r27]			// rrs[vadr>>61]
  1.1150 -	extr.u r26 = r24, 2, 6
  1.1151 +	extr.u r26 = r24, IA64_PTA_SIZE_BIT, IA64_PTA_SIZE_LEN
  1.1152  	;;
  1.1153 -	extr.u r22 = r23, 2, 6
  1.1154 +	extr.u r22 = r23, IA64_RR_PS, IA64_RR_PS_LEN
  1.1155  	shl r30 = r25, r26
  1.1156  	;;
  1.1157  	shr.u r19 = r8, r22
  1.1158 @@ -1999,13 +1998,13 @@ ENTRY(hyper_thash)
  1.1159  	// done, update iip/ipsr to next instruction
  1.1160  	mov r24=cr.ipsr
  1.1161  	mov r25=cr.iip;;
  1.1162 -	extr.u r26=r24,41,2 ;;
  1.1163 +	extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
  1.1164  	cmp.eq p6,p7=2,r26 ;;
  1.1165  (p6)	mov r26=0
  1.1166  (p6)	adds r25=16,r25
  1.1167  (p7)	adds r26=1,r26
  1.1168  	;;
  1.1169 -	dep r24=r26,r24,41,2
  1.1170 +	dep r24=r26,r24,IA64_PSR_RI_BIT,2
  1.1171  	;;
  1.1172  	mov cr.ipsr=r24
  1.1173  	mov cr.iip=r25
  1.1174 @@ -2072,13 +2071,13 @@ 2:
  1.1175  	st8 [r25]=r24			// set 1-entry i/dtlb as not present
  1.1176  	st8 [r26]=r27 ;;
  1.1177  	// increment to point to next instruction
  1.1178 -	extr.u r26=r29,41,2 ;;
  1.1179 +	extr.u r26=r29,IA64_PSR_RI_BIT,2 ;;
  1.1180  	cmp.eq p6,p7=2,r26 ;;
  1.1181  (p6)	mov r26=0
  1.1182  (p6)	adds r30=16,r30
  1.1183  (p7)	adds r26=1,r26
  1.1184  	;;
  1.1185 -	dep r29=r26,r29,41,2
  1.1186 +	dep r29=r26,r29,IA64_PSR_RI_BIT,2
  1.1187  	;;
  1.1188  	mov cr.ipsr=r29
  1.1189  	mov cr.iip=r30
  1.1190 @@ -2113,7 +2112,7 @@ hyper_itc_d:
  1.1191  	// ensure itir.ps >= xen's pagesize
  1.1192  	adds r23=XSI_ITIR_OFS-XSI_PSR_IC_OFS,r18 ;;
  1.1193  	ld8 r23=[r23];;
  1.1194 -	extr.u r24=r23,2,6;;		// r24==logps
  1.1195 +	extr.u r24=r23,IA64_ITIR_PS,IA64_ITIR_PS_LEN;;		// r24==logps
  1.1196  	cmp.gt p7,p0=PAGE_SHIFT,r24
  1.1197  (p7)	br.spnt.many dispatch_break_fault ;;
  1.1198  	adds r21=XSI_IFA_OFS-XSI_PSR_IC_OFS,r18 ;;
  1.1199 @@ -2125,7 +2124,7 @@ hyper_itc_d:
  1.1200  	movl r27=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
  1.1201  	ld8 r27=[r27];;
  1.1202  	adds r27=IA64_VCPU_DOMAIN_OFFSET,r27;;
  1.1203 -	ld8 r27=[r27];;
  1.1204 +	ld8 r27=[r27]
  1.1205  // FIXME: is the global var dom0 always pinned? assume so for now
  1.1206  	movl r28=dom0;;
  1.1207  	ld8 r28=[r28];;
  1.1208 @@ -2134,7 +2133,7 @@ hyper_itc_d:
  1.1209  (p7)	br.spnt.many dispatch_break_fault ;;
  1.1210  #ifdef FAST_HYPERPRIVOP_CNT
  1.1211  	cmp.eq p6,p7=HYPERPRIVOP_ITC_D,r17;;
  1.1212 -(p6)	movl r20=FAST_HYPERPRIVOP_PERFC(HYPERPRIVOP_ITC_D);;
  1.1213 +(p6)	movl r20=FAST_HYPERPRIVOP_PERFC(HYPERPRIVOP_ITC_D)
  1.1214  (p7)	movl r20=FAST_HYPERPRIVOP_PERFC(HYPERPRIVOP_ITC_I);;
  1.1215  	ld4 r21=[r20];;
  1.1216  	adds r21=1,r21;;
  1.1217 @@ -2163,10 +2162,10 @@ ENTRY(fast_insert)
  1.1218  	// translate_domain_pte(r16=pteval,PSCB(ifa)=address,r24=itir)
  1.1219  	mov r19=1;;
  1.1220  	shl r20=r19,r24;;
  1.1221 -	adds r20=-1,r20;;	// r20 == mask
  1.1222 +	adds r20=-1,r20		// r20 == mask
  1.1223  	movl r19=_PAGE_PPN_MASK;;
  1.1224  	and r22=r16,r19;;	// r22 == pteval & _PAGE_PPN_MASK
  1.1225 -	andcm r19=r22,r20;;
  1.1226 +	andcm r19=r22,r20
  1.1227  	adds r21=XSI_IFA_OFS-XSI_PSR_IC_OFS,r18 ;;
  1.1228  	ld8 r21=[r21];;
  1.1229  	and r20=r21,r20;;
  1.1230 @@ -2178,7 +2177,7 @@ ENTRY(fast_insert)
  1.1231  	// r16=pteval,r20=pteval2
  1.1232  	movl r19=_PAGE_PPN_MASK
  1.1233  	movl r21=_PAGE_PL_PRIV;;
  1.1234 -	andcm r25=r16,r19;;	// r25==pteval & ~_PAGE_PPN_MASK
  1.1235 +	andcm r25=r16,r19	// r25==pteval & ~_PAGE_PPN_MASK
  1.1236  	and r22=r20,r19;;
  1.1237  	or r22=r22,r21;;
  1.1238  	or r22=r22,r25;;	// r22==return value from translate_domain_pte
  1.1239 @@ -2188,12 +2187,12 @@ ENTRY(fast_insert)
  1.1240  	// psr.ic already cleared
  1.1241  	// NOTE: r24 still contains ps (from above)
  1.1242  	shladd r24=r24,2,r0;;
  1.1243 -	mov cr.itir=r24;;
  1.1244 +	mov cr.itir=r24
  1.1245  	adds r23=XSI_IFA_OFS-XSI_PSR_IC_OFS,r18 ;;
  1.1246  	ld8 r23=[r23];;
  1.1247 -	mov cr.ifa=r23;;
  1.1248 +	mov cr.ifa=r23
  1.1249  	tbit.z p6,p7=r17,0;;
  1.1250 -(p6)	itc.d r22;;
  1.1251 +(p6)	itc.d r22
  1.1252  (p7)	itc.i r22;;
  1.1253  	dv_serialize_data
  1.1254  	// vhpt_insert(r23=vaddr,r22=pte,r24=logps<<2)
  1.1255 @@ -2208,30 +2207,30 @@ ENTRY(fast_insert)
  1.1256  	st8 [r20]=r21;;
  1.1257  	// vcpu_set_tr_entry(trp,r22=pte|1,r24=itir,r23=ifa)
  1.1258  	// TR_ENTRY = {page_flags,itir,addr,rid}
  1.1259 -	tbit.z p6,p7=r17,0;;
  1.1260 +	tbit.z p6,p7=r17,0
  1.1261  	movl r27=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
  1.1262  	ld8 r27=[r27];;
  1.1263  	adds r28=IA64_VCPU_STARTING_RID_OFFSET,r27
  1.1264  (p6)	adds r27=IA64_VCPU_DTLB_OFFSET,r27
  1.1265  (p7)	adds r27=IA64_VCPU_ITLB_OFFSET,r27;;
  1.1266  	st8 [r27]=r22,8;;	// page_flags: already has pl >= 2 and p==1
  1.1267 -	st8 [r27]=r24,8;;	// itir
  1.1268 +	st8 [r27]=r24,8		// itir
  1.1269  	mov r19=-4096;;
  1.1270  	and r23=r23,r19;;
  1.1271 -	st8 [r27]=r23,8;;	// ifa & ~0xfff
  1.1272 +	st8 [r27]=r23,8		// ifa & ~0xfff
  1.1273  	adds r29 = XSI_RR0_OFS-XSI_PSR_IC_OFS,r18
  1.1274  	extr.u r25=r23,61,3;;
  1.1275  	shladd r29=r25,3,r29;;
  1.1276 -	ld8 r29=[r29];;
  1.1277 -	movl r20=0xffffff00;;
  1.1278 +	ld8 r29=[r29]
  1.1279 +	movl r20=IA64_RR_RID_MASK;;
  1.1280  	and r29=r29,r20;;
  1.1281  	st8 [r27]=r29,-8;;		// rid
  1.1282  	//if ps > 12
  1.1283 -	cmp.eq p7,p0=12<<2,r24
  1.1284 +	cmp.eq p7,p0=12<<IA64_ITIR_PS,r24
  1.1285  (p7)	br.cond.sptk.many 1f;;
  1.1286  	// if (ps > 12) {
  1.1287  	// trp->ppn &= ~((1UL<<(ps-12))-1); trp->vadr &= ~((1UL<<ps)-1); }
  1.1288 -	extr.u r29=r24,2,6
  1.1289 +	extr.u r29=r24,IA64_ITIR_PS,IA64_ITIR_PS_LEN
  1.1290  	mov r28=1;;
  1.1291  	shl r26=r28,r29;;
  1.1292  	adds r29=-12,r29;;
  1.1293 @@ -2268,13 +2267,13 @@ 1:	// done with vcpu_set_tr_entry
  1.1294  
  1.1295  	mov r29=cr.ipsr
  1.1296  	mov r30=cr.iip;;
  1.1297 -	extr.u r26=r29,41,2 ;;
  1.1298 +	extr.u r26=r29,IA64_PSR_RI_BIT,2 ;;
  1.1299  	cmp.eq p6,p7=2,r26 ;;
  1.1300  (p6)	mov r26=0
  1.1301  (p6)	adds r30=16,r30
  1.1302  (p7)	adds r26=1,r26
  1.1303  	;;
  1.1304 -	dep r29=r26,r29,41,2
  1.1305 +	dep r29=r26,r29,IA64_PSR_RI_BIT,2
  1.1306  	;;
  1.1307  	mov cr.ipsr=r29
  1.1308  	mov cr.iip=r30;;
     2.1 --- a/xen/include/asm-ia64/vmmu.h	Wed Aug 08 20:48:11 2007 -0600
     2.2 +++ b/xen/include/asm-ia64/vmmu.h	Sun Aug 12 12:06:43 2007 -0600
     2.3 @@ -33,6 +33,7 @@
     2.4  #define     VTLB(v,_x)          (v->arch.vtlb._x)
     2.5  #define     VHPT(v,_x)          (v->arch.vhpt._x)
     2.6  #define     _PAGE_PL_PRIV       (CONFIG_CPL0_EMUL << 7)
     2.7 +
     2.8  #ifndef __ASSEMBLY__
     2.9  
    2.10  #include <xen/config.h>
    2.11 @@ -75,10 +76,14 @@ enum {
    2.12      ISIDE_TLB=0,
    2.13      DSIDE_TLB=1
    2.14  };
    2.15 +#endif /* __ASSEMBLY__ */
    2.16 +
    2.17  #define VTLB_PTE_P_BIT      0
    2.18  #define VTLB_PTE_IO_BIT     60
    2.19  #define VTLB_PTE_IO         (1UL<<VTLB_PTE_IO_BIT)
    2.20  #define VTLB_PTE_P         (1UL<<VTLB_PTE_P_BIT)
    2.21 +
    2.22 +#ifndef __ASSEMBLY__
    2.23  typedef struct thash_data {
    2.24      union {
    2.25          struct {
     3.1 --- a/xen/include/asm-ia64/xenkregs.h	Wed Aug 08 20:48:11 2007 -0600
     3.2 +++ b/xen/include/asm-ia64/xenkregs.h	Sun Aug 12 12:06:43 2007 -0600
     3.3 @@ -27,11 +27,13 @@
     3.4  /* Page Table Address */
     3.5  #define IA64_PTA_VE_BIT 0
     3.6  #define IA64_PTA_SIZE_BIT 2
     3.7 +#define IA64_PTA_SIZE_LEN 6
     3.8  #define IA64_PTA_VF_BIT 8
     3.9  #define IA64_PTA_BASE_BIT 15
    3.10  
    3.11  #define IA64_PTA_VE     (__IA64_UL(1) << IA64_PTA_VE_BIT)
    3.12 -#define IA64_PTA_SIZE   (__IA64_UL(0x3f) << IA64_PTA_SIZE_BIT)
    3.13 +#define IA64_PTA_SIZE   (__IA64_UL((1 << IA64_PTA_SIZE_LEN) - 1) <<	\
    3.14 +			 IA64_PTA_SIZE_BIT)
    3.15  #define IA64_PTA_VF     (__IA64_UL(1) << IA64_PTA_VF_BIT)
    3.16  #define IA64_PTA_BASE   (__IA64_UL(0) - ((__IA64_UL(1) << IA64_PTA_BASE_BIT)))
    3.17  
    3.18 @@ -47,6 +49,14 @@
    3.19  #define	IA64_ITIR_PS_KEY(_ps, _key)	(((_ps) << IA64_ITIR_PS) | \
    3.20  					 (((_key) << IA64_ITIR_KEY)))
    3.21  
    3.22 +/* Region Register Bits */
    3.23 +#define IA64_RR_PS		2
    3.24 +#define IA64_RR_PS_LEN		6
    3.25 +#define IA64_RR_RID		8
    3.26 +#define IA64_RR_RID_LEN		24
    3.27 +#define IA64_RR_RID_MASK	(((__IA64_UL(1) << IA64_RR_RID_LEN) - 1) << \
    3.28 +				IA64_RR_RID
    3.29 +
    3.30  /* Define Protection Key Register (PKR) */
    3.31  #define	IA64_PKR_V		0
    3.32  #define	IA64_PKR_WD		1