ia64/xen-unstable

changeset 5806:816b9b3ced2f

Fix ar.unat handling for fast paths
author djm@kirby.fc.hp.com
date Fri Jul 15 15:27:06 2005 -0700 (2005-07-15)
parents a83ac0806d6b
children a6b64aed65c3
files xen/arch/ia64/domain.c xen/arch/ia64/hyperprivop.S xen/arch/ia64/xenmisc.c xen/common/xmalloc.c
line diff
     1.1 --- a/xen/arch/ia64/domain.c	Fri Jul 15 06:39:50 2005 -0700
     1.2 +++ b/xen/arch/ia64/domain.c	Fri Jul 15 15:27:06 2005 -0700
     1.3 @@ -311,9 +311,10 @@ int arch_set_info_guest(struct vcpu *v, 
     1.4  	init_all_rr(v);
     1.5  
     1.6  	// this should be in userspace
     1.7 -	regs->r28 = dom_fw_setup(v->domain,"nomca nosmp xencons=ttyS console=ttyS0",256L);  //FIXME
     1.8 +	regs->r28 = dom_fw_setup(v->domain,"nomca nosmp xencons=tty0 console=tty0",256L);  //FIXME
     1.9  	v->vcpu_info->arch.banknum = 1;
    1.10  	v->vcpu_info->arch.metaphysical_mode = 1;
    1.11 +	v->arch.domain_itm_last = -1L;
    1.12  
    1.13  	v->domain->shared_info->arch = c->shared;
    1.14  	return 0;
     2.1 --- a/xen/arch/ia64/hyperprivop.S	Fri Jul 15 06:39:50 2005 -0700
     2.2 +++ b/xen/arch/ia64/hyperprivop.S	Fri Jul 15 15:27:06 2005 -0700
     2.3 @@ -21,6 +21,8 @@
     2.4  #define FAST_TICK
     2.5  #define FAST_BREAK
     2.6  #define FAST_ACCESS_REFLECT
     2.7 +#define FAST_RFI
     2.8 +#define FAST_SSM_I
     2.9  #undef RFI_TO_INTERRUPT // not working yet
    2.10  #endif
    2.11  
    2.12 @@ -183,6 +185,9 @@ 1:	// when we get to here r20=~=interrup
    2.13  //	r19 == vpsr.ic (low 32 bits) | vpsr.i (high 32 bits)
    2.14  //	r31 == pr
    2.15  ENTRY(hyper_ssm_i)
    2.16 +#ifndef FAST_SSM_I
    2.17 +	br.spnt.few dispatch_break_fault ;;
    2.18 +#endif
    2.19  	// give up for now if: ipsr.be==1, ipsr.pp==1
    2.20  	mov r30=cr.ipsr;;
    2.21  	mov r29=cr.iip;;
    2.22 @@ -259,7 +264,8 @@ ENTRY(hyper_ssm_i)
    2.23  	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
    2.24  	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
    2.25  	bsw.1;;
    2.26 -	// FIXME: need to handle ar.unat!
    2.27 +	// FIXME?: ar.unat is not really handled correctly,
    2.28 +	// but may not matter if the OS is NaT-clean
    2.29  	.mem.offset 0,0; st8.spill [r2]=r16,16;
    2.30  	.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
    2.31  	.mem.offset 0,0; st8.spill [r2]=r18,16;
    2.32 @@ -424,11 +430,10 @@ GLOBAL_ENTRY(fast_tick_reflect)
    2.33  	add r24=r24,r23;;
    2.34  	mov cr.iip=r24;;
    2.35  	// OK, now all set to go except for switch to virtual bank0
    2.36 -	mov r30=r2; mov r29=r3;;
    2.37 +	mov r30=r2; mov r29=r3;; mov r28=ar.unat;
    2.38  	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
    2.39  	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
    2.40  	bsw.1;;
    2.41 -	// FIXME: need to handle ar.unat!
    2.42  	.mem.offset 0,0; st8.spill [r2]=r16,16;
    2.43  	.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
    2.44  	.mem.offset 0,0; st8.spill [r2]=r18,16;
    2.45 @@ -447,7 +452,11 @@ GLOBAL_ENTRY(fast_tick_reflect)
    2.46  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
    2.47  	movl r31=XSI_IPSR;;
    2.48  	bsw.0 ;;
    2.49 -	mov r2=r30; mov r3=r29;;
    2.50 +	// bank0 regs have no NaT bit, so ensure they are NaT clean
    2.51 +	mov r16=r0; mov r17=r0; mov r19=r0;
    2.52 +	mov r21=r0; mov r22=r0; mov r23=r0;
    2.53 +	mov r24=r0; mov r25=r0; mov r26=r0; mov r27=r0;
    2.54 +	mov r2=r30; mov r3=r29; mov ar.unat=r28;
    2.55  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    2.56  	st4 [r20]=r0 ;;
    2.57  fast_tick_reflect_done:
    2.58 @@ -566,11 +575,10 @@ ENTRY(fast_reflect)
    2.59  	add r20=r20,r23;;
    2.60  	mov cr.iip=r20;;
    2.61  	// OK, now all set to go except for switch to virtual bank0
    2.62 -	mov r30=r2; mov r29=r3;;
    2.63 +	mov r30=r2; mov r29=r3;; mov r28=ar.unat;
    2.64  	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
    2.65  	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
    2.66  	bsw.1;;
    2.67 -	// FIXME: need to handle ar.unat!
    2.68  	.mem.offset 0,0; st8.spill [r2]=r16,16;
    2.69  	.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
    2.70  	.mem.offset 0,0; st8.spill [r2]=r18,16;
    2.71 @@ -589,7 +597,11 @@ ENTRY(fast_reflect)
    2.72  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
    2.73  	movl r31=XSI_IPSR;;
    2.74  	bsw.0 ;;
    2.75 -	mov r2=r30; mov r3=r29;;
    2.76 +	// bank0 regs have no NaT bit, so ensure they are NaT clean
    2.77 +	mov r16=r0; mov r17=r0; mov r19=r0;
    2.78 +	mov r21=r0; mov r22=r0; mov r23=r0;
    2.79 +	mov r24=r0; mov r25=r0; mov r26=r0; mov r27=r0;
    2.80 +	mov r2=r30; mov r3=r29; mov ar.unat=r28;
    2.81  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    2.82  	st4 [r20]=r0 ;;
    2.83  	mov pr=r31,-1 ;;
    2.84 @@ -637,6 +649,9 @@ GLOBAL_ENTRY(fast_access_reflect)
    2.85  
    2.86  // ensure that, if giving up, registers at entry to fast_hyperprivop unchanged
    2.87  ENTRY(hyper_rfi)
    2.88 +#ifndef FAST_RFI
    2.89 +	br.spnt.few dispatch_break_fault ;;
    2.90 +#endif
    2.91  	// if no interrupts pending, proceed
    2.92  	mov r30=r0
    2.93  	cmp.eq p7,p0=r20,r0
    2.94 @@ -736,7 +751,8 @@ just_do_rfi:
    2.95  	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
    2.96  	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
    2.97  	bsw.1;;
    2.98 -	// FIXME: need to handle ar.unat!
    2.99 +	// FIXME?: ar.unat is not really handled correctly,
   2.100 +	// but may not matter if the OS is NaT-clean
   2.101  	.mem.offset 0,0; ld8.fill r16=[r2],16 ;
   2.102  	.mem.offset 8,0; ld8.fill r17=[r3],16 ;;
   2.103  	.mem.offset 0,0; ld8.fill r18=[r2],16 ;
     3.1 --- a/xen/arch/ia64/xenmisc.c	Fri Jul 15 06:39:50 2005 -0700
     3.2 +++ b/xen/arch/ia64/xenmisc.c	Fri Jul 15 15:27:06 2005 -0700
     3.3 @@ -291,8 +291,8 @@ void context_switch(struct vcpu *prev, s
     3.4  static long cnt[16] = { 50,50,50,50,50,50,50,50,50,50,50,50,50,50,50,50};
     3.5  static int i = 100;
     3.6  int id = ((struct vcpu *)current)->domain->domain_id & 0xf;
     3.7 -if (!cnt[id]--) { printk("%x",id); cnt[id] = 500; }
     3.8 -if (!i--) { printk("+",id); cnt[id] = 1000; }
     3.9 +if (!cnt[id]--) { printk("%x",id); cnt[id] = 50000; }
    3.10 +if (!i--) { printk("+",id); i = 100000; }
    3.11  }
    3.12  	clear_bit(_VCPUF_running, &prev->vcpu_flags);
    3.13  	//if (!is_idle_task(next->domain) )
     4.1 --- a/xen/common/xmalloc.c	Fri Jul 15 06:39:50 2005 -0700
     4.2 +++ b/xen/common/xmalloc.c	Fri Jul 15 15:27:06 2005 -0700
     4.3 @@ -111,7 +111,9 @@ void *_xmalloc(size_t size, size_t align
     4.4      unsigned long flags;
     4.5  
     4.6      /* We currently always return cacheline aligned. */
     4.7 +#ifndef __ia64__
     4.8      BUG_ON(align > SMP_CACHE_BYTES);
     4.9 +#endif
    4.10  
    4.11      /* Add room for header, pad to align next header. */
    4.12      size += sizeof(struct xmalloc_hdr);