ia64/xen-unstable

changeset 10677:7f4ec81761cf

[IA64] Add mca_asm.S to linux-xen

Signed-off-by: Akio Takebe <takebe_akio@jp.fujitsu.com>
Signed-off-by: Alex Williamson <alex.williamson@hp.com>
author awilliam@xenbuild.aw
date Thu Jul 06 10:48:21 2006 -0600 (2006-07-06)
parents d6b6d3defe81
children ac6f34b44e3f
files xen/arch/ia64/linux-xen/README.origin xen/arch/ia64/linux-xen/mca_asm.S
line diff
     1.1 --- a/xen/arch/ia64/linux-xen/README.origin	Thu Jul 06 10:42:13 2006 -0600
     1.2 +++ b/xen/arch/ia64/linux-xen/README.origin	Thu Jul 06 10:48:21 2006 -0600
     1.3 @@ -11,6 +11,7 @@ entry.S			-> linux/arch/ia64/kernel/entr
     1.4  head.S			-> linux/arch/ia64/kernel/head.S
     1.5  hpsim_ssc.h		-> linux/arch/ia64/hp/sim/hpsim_ssc.h
     1.6  irq_ia64.c		-> linux/arch/ia64/kernel/irq_ia64.c
     1.7 +mca_asm.S		-> linux/arch/ia64/kernel/mca_asm.S
     1.8  minstate.h		-> linux/arch/ia64/kernel/minstate.h
     1.9  mm_contig.c		-> linux/arch/ia64/mm/contig.c
    1.10  pal.S			-> linux/arch/ia64/kernel/pal.S
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/xen/arch/ia64/linux-xen/mca_asm.S	Thu Jul 06 10:48:21 2006 -0600
     2.3 @@ -0,0 +1,946 @@
     2.4 +//
     2.5 +// assembly portion of the IA64 MCA handling
     2.6 +//
     2.7 +// Mods by cfleck to integrate into kernel build
     2.8 +// 00/03/15 davidm Added various stop bits to get a clean compile
     2.9 +//
    2.10 +// 00/03/29 cfleck Added code to save INIT handoff state in pt_regs format, switch to temp
    2.11 +//		   kstack, switch modes, jump to C INIT handler
    2.12 +//
    2.13 +// 02/01/04 J.Hall <jenna.s.hall@intel.com>
    2.14 +//		   Before entering virtual mode code:
    2.15 +//		   1. Check for TLB CPU error
    2.16 +//		   2. Restore current thread pointer to kr6
    2.17 +//		   3. Move stack ptr 16 bytes to conform to C calling convention
    2.18 +//
    2.19 +// 04/11/12 Russ Anderson <rja@sgi.com>
    2.20 +//		   Added per cpu MCA/INIT stack save areas.
    2.21 +//
    2.22 +#include <linux/config.h>
    2.23 +#include <linux/threads.h>
    2.24 +
    2.25 +#include <asm/asmmacro.h>
    2.26 +#include <asm/pgtable.h>
    2.27 +#include <asm/processor.h>
    2.28 +#include <asm/mca_asm.h>
    2.29 +#include <asm/mca.h>
    2.30 +
    2.31 +/*
    2.32 + * When we get a machine check, the kernel stack pointer is no longer
    2.33 + * valid, so we need to set a new stack pointer.
    2.34 + */
    2.35 +#define	MINSTATE_PHYS	/* Make sure stack access is physical for MINSTATE */
    2.36 +
    2.37 +/*
    2.38 + * Needed for return context to SAL
    2.39 + */
    2.40 +#define IA64_MCA_SAME_CONTEXT	0
    2.41 +#define IA64_MCA_COLD_BOOT	-2
    2.42 +
    2.43 +#include "minstate.h"
    2.44 +
    2.45 +/*
    2.46 + * SAL_TO_OS_MCA_HANDOFF_STATE (SAL 3.0 spec)
    2.47 + *		1. GR1 = OS GP
    2.48 + *		2. GR8 = PAL_PROC physical address
    2.49 + *		3. GR9 = SAL_PROC physical address
    2.50 + *		4. GR10 = SAL GP (physical)
    2.51 + *		5. GR11 = Rendez state
    2.52 + *		6. GR12 = Return address to location within SAL_CHECK
    2.53 + */
    2.54 +#define SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(_tmp)		\
    2.55 +	LOAD_PHYSICAL(p0, _tmp, ia64_sal_to_os_handoff_state);; \
    2.56 +	st8	[_tmp]=r1,0x08;;			\
    2.57 +	st8	[_tmp]=r8,0x08;;			\
    2.58 +	st8	[_tmp]=r9,0x08;;			\
    2.59 +	st8	[_tmp]=r10,0x08;;			\
    2.60 +	st8	[_tmp]=r11,0x08;;			\
    2.61 +	st8	[_tmp]=r12,0x08;;			\
    2.62 +	st8	[_tmp]=r17,0x08;;			\
    2.63 +	st8	[_tmp]=r18,0x08
    2.64 +
    2.65 +/*
    2.66 + * OS_MCA_TO_SAL_HANDOFF_STATE (SAL 3.0 spec)
    2.67 + * (p6) is executed if we never entered virtual mode (TLB error)
    2.68 + * (p7) is executed if we entered virtual mode as expected (normal case)
    2.69 + *	1. GR8 = OS_MCA return status
    2.70 + *	2. GR9 = SAL GP (physical)
    2.71 + *	3. GR10 = 0/1 returning same/new context
    2.72 + *	4. GR22 = New min state save area pointer
    2.73 + *	returns ptr to SAL rtn save loc in _tmp
    2.74 + */
    2.75 +#define OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(_tmp)	\
    2.76 +	movl	_tmp=ia64_os_to_sal_handoff_state;;	\
    2.77 +	DATA_VA_TO_PA(_tmp);;				\
    2.78 +	ld8	r8=[_tmp],0x08;;			\
    2.79 +	ld8	r9=[_tmp],0x08;;			\
    2.80 +	ld8	r10=[_tmp],0x08;;			\
    2.81 +	ld8	r22=[_tmp],0x08;;
    2.82 +	// now _tmp is pointing to SAL rtn save location
    2.83 +
    2.84 +/*
    2.85 + * COLD_BOOT_HANDOFF_STATE() sets ia64_mca_os_to_sal_state
    2.86 + *	imots_os_status=IA64_MCA_COLD_BOOT
    2.87 + *	imots_sal_gp=SAL GP
    2.88 + *	imots_context=IA64_MCA_SAME_CONTEXT
    2.89 + *	imots_new_min_state=Min state save area pointer
    2.90 + *	imots_sal_check_ra=Return address to location within SAL_CHECK
    2.91 + *
    2.92 + */
    2.93 +#define COLD_BOOT_HANDOFF_STATE(sal_to_os_handoff,os_to_sal_handoff,tmp)\
    2.94 +	movl	tmp=IA64_MCA_COLD_BOOT;					\
    2.95 +	movl	sal_to_os_handoff=__pa(ia64_sal_to_os_handoff_state);	\
    2.96 +	movl	os_to_sal_handoff=__pa(ia64_os_to_sal_handoff_state);;	\
    2.97 +	st8	[os_to_sal_handoff]=tmp,8;;				\
    2.98 +	ld8	tmp=[sal_to_os_handoff],48;;				\
    2.99 +	st8	[os_to_sal_handoff]=tmp,8;;				\
   2.100 +	movl	tmp=IA64_MCA_SAME_CONTEXT;;				\
   2.101 +	st8	[os_to_sal_handoff]=tmp,8;;				\
   2.102 +	ld8	tmp=[sal_to_os_handoff],-8;;				\
   2.103 +	st8     [os_to_sal_handoff]=tmp,8;;				\
   2.104 +	ld8	tmp=[sal_to_os_handoff];;				\
   2.105 +	st8     [os_to_sal_handoff]=tmp;;
   2.106 +
   2.107 +#define GET_IA64_MCA_DATA(reg)						\
   2.108 +	GET_THIS_PADDR(reg, ia64_mca_data)				\
   2.109 +	;;								\
   2.110 +	ld8 reg=[reg]
   2.111 +
   2.112 +	.global ia64_os_mca_dispatch
   2.113 +	.global ia64_os_mca_dispatch_end
   2.114 +	.global ia64_sal_to_os_handoff_state
   2.115 +	.global	ia64_os_to_sal_handoff_state
   2.116 +	.global ia64_do_tlb_purge
   2.117 +
   2.118 +	.text
   2.119 +	.align 16
   2.120 +
   2.121 +/*
   2.122 + * Just the TLB purge part is moved to a separate function
   2.123 + * so we can re-use the code for cpu hotplug code as well
   2.124 + * Caller should now setup b1, so we can branch once the
   2.125 + * tlb flush is complete.
   2.126 + */
   2.127 +
   2.128 +ia64_do_tlb_purge:
   2.129 +#define O(member)	IA64_CPUINFO_##member##_OFFSET
   2.130 +
   2.131 +	GET_THIS_PADDR(r2, cpu_info)	// load phys addr of cpu_info into r2
   2.132 +	;;
   2.133 +	addl r17=O(PTCE_STRIDE),r2
   2.134 +	addl r2=O(PTCE_BASE),r2
   2.135 +	;;
   2.136 +	ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));;	// r18=ptce_base
   2.137 +	ld4 r19=[r2],4					// r19=ptce_count[0]
   2.138 +	ld4 r21=[r17],4					// r21=ptce_stride[0]
   2.139 +	;;
   2.140 +	ld4 r20=[r2]					// r20=ptce_count[1]
   2.141 +	ld4 r22=[r17]					// r22=ptce_stride[1]
   2.142 +	mov r24=0
   2.143 +	;;
   2.144 +	adds r20=-1,r20
   2.145 +	;;
   2.146 +#undef O
   2.147 +
   2.148 +2:
   2.149 +	cmp.ltu p6,p7=r24,r19
   2.150 +(p7)	br.cond.dpnt.few 4f
   2.151 +	mov ar.lc=r20
   2.152 +3:
   2.153 +	ptc.e r18
   2.154 +	;;
   2.155 +	add r18=r22,r18
   2.156 +	br.cloop.sptk.few 3b
   2.157 +	;;
   2.158 +	add r18=r21,r18
   2.159 +	add r24=1,r24
   2.160 +	;;
   2.161 +	br.sptk.few 2b
   2.162 +4:
   2.163 +	srlz.i 			// srlz.i implies srlz.d
   2.164 +	;;
   2.165 +
   2.166 +        // Now purge addresses formerly mapped by TR registers
   2.167 +	// 1. Purge ITR&DTR for kernel.
   2.168 +	movl r16=KERNEL_START
   2.169 +	mov r18=KERNEL_TR_PAGE_SHIFT<<2
   2.170 +	;;
   2.171 +	ptr.i r16, r18
   2.172 +	ptr.d r16, r18
   2.173 +	;;
   2.174 +	srlz.i
   2.175 +	;;
   2.176 +	srlz.d
   2.177 +	;;
   2.178 +	// 2. Purge DTR for PERCPU data.
   2.179 +	movl r16=PERCPU_ADDR
   2.180 +	mov r18=PERCPU_PAGE_SHIFT<<2
   2.181 +	;;
   2.182 +	ptr.d r16,r18
   2.183 +	;;
   2.184 +	srlz.d
   2.185 +	;;
   2.186 +	// 3. Purge ITR for PAL code.
   2.187 +	GET_THIS_PADDR(r2, ia64_mca_pal_base)
   2.188 +	;;
   2.189 +	ld8 r16=[r2]
   2.190 +	mov r18=IA64_GRANULE_SHIFT<<2
   2.191 +	;;
   2.192 +	ptr.i r16,r18
   2.193 +	;;
   2.194 +	srlz.i
   2.195 +	;;
   2.196 +	// 4. Purge DTR for stack.
   2.197 +	mov r16=IA64_KR(CURRENT_STACK)
   2.198 +	;;
   2.199 +	shl r16=r16,IA64_GRANULE_SHIFT
   2.200 +	movl r19=PAGE_OFFSET
   2.201 +	;;
   2.202 +	add r16=r19,r16
   2.203 +	mov r18=IA64_GRANULE_SHIFT<<2
   2.204 +	;;
   2.205 +	ptr.d r16,r18
   2.206 +	;;
   2.207 +	srlz.i
   2.208 +	;;
   2.209 +	// Now branch away to caller.
   2.210 +	br.sptk.many b1
   2.211 +	;;
   2.212 +
   2.213 +ia64_os_mca_dispatch:
   2.214 +
   2.215 +	// Serialize all MCA processing
   2.216 +	mov	r3=1;;
   2.217 +	LOAD_PHYSICAL(p0,r2,ia64_mca_serialize);;
   2.218 +ia64_os_mca_spin:
   2.219 +	xchg8	r4=[r2],r3;;
   2.220 +	cmp.ne	p6,p0=r4,r0
   2.221 +(p6)	br ia64_os_mca_spin
   2.222 +
   2.223 +	// Save the SAL to OS MCA handoff state as defined
   2.224 +	// by SAL SPEC 3.0
   2.225 +	// NOTE : The order in which the state gets saved
   2.226 +	//	  is dependent on the way the C-structure
   2.227 +	//	  for ia64_mca_sal_to_os_state_t has been
   2.228 +	//	  defined in include/asm/mca.h
   2.229 +	SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(r2)
   2.230 +	;;
   2.231 +
   2.232 +	// LOG PROCESSOR STATE INFO FROM HERE ON..
   2.233 +begin_os_mca_dump:
   2.234 +	br	ia64_os_mca_proc_state_dump;;
   2.235 +
   2.236 +ia64_os_mca_done_dump:
   2.237 +
   2.238 +	LOAD_PHYSICAL(p0,r16,ia64_sal_to_os_handoff_state+56)
   2.239 +	;;
   2.240 +	ld8 r18=[r16]		// Get processor state parameter on existing PALE_CHECK.
   2.241 +	;;
   2.242 +	tbit.nz p6,p7=r18,60
   2.243 +(p7)	br.spnt done_tlb_purge_and_reload
   2.244 +
   2.245 +	// The following code purges TC and TR entries. Then reload all TC entries.
   2.246 +	// Purge percpu data TC entries.
   2.247 +begin_tlb_purge_and_reload:
   2.248 +	movl r18=ia64_reload_tr;;
   2.249 +	LOAD_PHYSICAL(p0,r18,ia64_reload_tr);;
   2.250 +	mov b1=r18;;
   2.251 +	br.sptk.many ia64_do_tlb_purge;;
   2.252 +
   2.253 +ia64_reload_tr:
   2.254 +	// Finally reload the TR registers.
   2.255 +	// 1. Reload DTR/ITR registers for kernel.
   2.256 +	mov r18=KERNEL_TR_PAGE_SHIFT<<2
   2.257 +	movl r17=KERNEL_START
   2.258 +	;;
   2.259 +	mov cr.itir=r18
   2.260 +	mov cr.ifa=r17
   2.261 +        mov r16=IA64_TR_KERNEL
   2.262 +	mov r19=ip
   2.263 +	movl r18=PAGE_KERNEL
   2.264 +	;;
   2.265 +        dep r17=0,r19,0, KERNEL_TR_PAGE_SHIFT
   2.266 +	;;
   2.267 +	or r18=r17,r18
   2.268 +	;;
   2.269 +        itr.i itr[r16]=r18
   2.270 +	;;
   2.271 +        itr.d dtr[r16]=r18
   2.272 +        ;;
   2.273 +	srlz.i
   2.274 +	srlz.d
   2.275 +	;;
   2.276 +	// 2. Reload DTR register for PERCPU data.
   2.277 +	GET_THIS_PADDR(r2, ia64_mca_per_cpu_pte)
   2.278 +	;;
   2.279 +	movl r16=PERCPU_ADDR		// vaddr
   2.280 +	movl r18=PERCPU_PAGE_SHIFT<<2
   2.281 +	;;
   2.282 +	mov cr.itir=r18
   2.283 +	mov cr.ifa=r16
   2.284 +	;;
   2.285 +	ld8 r18=[r2]			// load per-CPU PTE
   2.286 +	mov r16=IA64_TR_PERCPU_DATA;
   2.287 +	;;
   2.288 +	itr.d dtr[r16]=r18
   2.289 +	;;
   2.290 +	srlz.d
   2.291 +	;;
   2.292 +	// 3. Reload ITR for PAL code.
   2.293 +	GET_THIS_PADDR(r2, ia64_mca_pal_pte)
   2.294 +	;;
   2.295 +	ld8 r18=[r2]			// load PAL PTE
   2.296 +	;;
   2.297 +	GET_THIS_PADDR(r2, ia64_mca_pal_base)
   2.298 +	;;
   2.299 +	ld8 r16=[r2]			// load PAL vaddr
   2.300 +	mov r19=IA64_GRANULE_SHIFT<<2
   2.301 +	;;
   2.302 +	mov cr.itir=r19
   2.303 +	mov cr.ifa=r16
   2.304 +	mov r20=IA64_TR_PALCODE
   2.305 +	;;
   2.306 +	itr.i itr[r20]=r18
   2.307 +	;;
   2.308 +	srlz.i
   2.309 +	;;
   2.310 +	// 4. Reload DTR for stack.
   2.311 +	mov r16=IA64_KR(CURRENT_STACK)
   2.312 +	;;
   2.313 +	shl r16=r16,IA64_GRANULE_SHIFT
   2.314 +	movl r19=PAGE_OFFSET
   2.315 +	;;
   2.316 +	add r18=r19,r16
   2.317 +	movl r20=PAGE_KERNEL
   2.318 +	;;
   2.319 +	add r16=r20,r16
   2.320 +	mov r19=IA64_GRANULE_SHIFT<<2
   2.321 +	;;
   2.322 +	mov cr.itir=r19
   2.323 +	mov cr.ifa=r18
   2.324 +	mov r20=IA64_TR_CURRENT_STACK
   2.325 +	;;
   2.326 +	itr.d dtr[r20]=r16
   2.327 +	;;
   2.328 +	srlz.d
   2.329 +	;;
   2.330 +	br.sptk.many done_tlb_purge_and_reload
   2.331 +err:
   2.332 +	COLD_BOOT_HANDOFF_STATE(r20,r21,r22)
   2.333 +	br.sptk.many ia64_os_mca_done_restore
   2.334 +
   2.335 +done_tlb_purge_and_reload:
   2.336 +
   2.337 +	// Setup new stack frame for OS_MCA handling
   2.338 +	GET_IA64_MCA_DATA(r2)
   2.339 +	;;
   2.340 +	add r3 = IA64_MCA_CPU_STACKFRAME_OFFSET, r2
   2.341 +	add r2 = IA64_MCA_CPU_RBSTORE_OFFSET, r2
   2.342 +	;;
   2.343 +	rse_switch_context(r6,r3,r2);;	// RSC management in this new context
   2.344 +
   2.345 +	GET_IA64_MCA_DATA(r2)
   2.346 +	;;
   2.347 +	add r2 = IA64_MCA_CPU_STACK_OFFSET+IA64_MCA_STACK_SIZE-16, r2
   2.348 +	;;
   2.349 +	mov r12=r2		// establish new stack-pointer
   2.350 +
   2.351 +        // Enter virtual mode from physical mode
   2.352 +	VIRTUAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_begin, r4)
   2.353 +ia64_os_mca_virtual_begin:
   2.354 +
   2.355 +	// Call virtual mode handler
   2.356 +	movl		r2=ia64_mca_ucmc_handler;;
   2.357 +	mov		b6=r2;;
   2.358 +	br.call.sptk.many    b0=b6;;
   2.359 +.ret0:
   2.360 +	// Revert back to physical mode before going back to SAL
   2.361 +	PHYSICAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_end, r4)
   2.362 +ia64_os_mca_virtual_end:
   2.363 +
   2.364 +	// restore the original stack frame here
   2.365 +	GET_IA64_MCA_DATA(r2)
   2.366 +	;;
   2.367 +	add r2 = IA64_MCA_CPU_STACKFRAME_OFFSET, r2
   2.368 +	;;
   2.369 +	movl    r4=IA64_PSR_MC
   2.370 +	;;
   2.371 +	rse_return_context(r4,r3,r2)	// switch from interrupt context for RSE
   2.372 +
   2.373 +	// let us restore all the registers from our PSI structure
   2.374 +	mov	r8=gp
   2.375 +	;;
   2.376 +begin_os_mca_restore:
   2.377 +	br	ia64_os_mca_proc_state_restore;;
   2.378 +
   2.379 +ia64_os_mca_done_restore:
   2.380 +	OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(r2);;
   2.381 +	// branch back to SALE_CHECK
   2.382 +	ld8		r3=[r2];;
   2.383 +	mov		b0=r3;;		// SAL_CHECK return address
   2.384 +
   2.385 +	// release lock
   2.386 +	movl		r3=ia64_mca_serialize;;
   2.387 +	DATA_VA_TO_PA(r3);;
   2.388 +	st8.rel		[r3]=r0
   2.389 +
   2.390 +	br		b0
   2.391 +	;;
   2.392 +ia64_os_mca_dispatch_end:
   2.393 +//EndMain//////////////////////////////////////////////////////////////////////
   2.394 +
   2.395 +
   2.396 +//++
   2.397 +// Name:
   2.398 +//      ia64_os_mca_proc_state_dump()
   2.399 +//
   2.400 +// Stub Description:
   2.401 +//
   2.402 +//       This stub dumps the processor state during MCHK to a data area
   2.403 +//
   2.404 +//--
   2.405 +
   2.406 +ia64_os_mca_proc_state_dump:
   2.407 +// Save bank 1 GRs 16-31 which will be used by c-language code when we switch
   2.408 +//  to virtual addressing mode.
   2.409 +	GET_IA64_MCA_DATA(r2)
   2.410 +	;;
   2.411 +	add r2 = IA64_MCA_CPU_PROC_STATE_DUMP_OFFSET, r2
   2.412 +	;;
   2.413 +// save ar.NaT
   2.414 +	mov		r5=ar.unat                  // ar.unat
   2.415 +
   2.416 +// save banked GRs 16-31 along with NaT bits
   2.417 +	bsw.1;;
   2.418 +	st8.spill	[r2]=r16,8;;
   2.419 +	st8.spill	[r2]=r17,8;;
   2.420 +	st8.spill	[r2]=r18,8;;
   2.421 +	st8.spill	[r2]=r19,8;;
   2.422 +	st8.spill	[r2]=r20,8;;
   2.423 +	st8.spill	[r2]=r21,8;;
   2.424 +	st8.spill	[r2]=r22,8;;
   2.425 +	st8.spill	[r2]=r23,8;;
   2.426 +	st8.spill	[r2]=r24,8;;
   2.427 +	st8.spill	[r2]=r25,8;;
   2.428 +	st8.spill	[r2]=r26,8;;
   2.429 +	st8.spill	[r2]=r27,8;;
   2.430 +	st8.spill	[r2]=r28,8;;
   2.431 +	st8.spill	[r2]=r29,8;;
   2.432 +	st8.spill	[r2]=r30,8;;
   2.433 +	st8.spill	[r2]=r31,8;;
   2.434 +
   2.435 +	mov		r4=ar.unat;;
   2.436 +	st8		[r2]=r4,8                // save User NaT bits for r16-r31
   2.437 +	mov		ar.unat=r5                  // restore original unat
   2.438 +	bsw.0;;
   2.439 +
   2.440 +//save BRs
   2.441 +	add		r4=8,r2                  // duplicate r2 in r4
   2.442 +	add		r6=2*8,r2                // duplicate r2 in r4
   2.443 +
   2.444 +	mov		r3=b0
   2.445 +	mov		r5=b1
   2.446 +	mov		r7=b2;;
   2.447 +	st8		[r2]=r3,3*8
   2.448 +	st8		[r4]=r5,3*8
   2.449 +	st8		[r6]=r7,3*8;;
   2.450 +
   2.451 +	mov		r3=b3
   2.452 +	mov		r5=b4
   2.453 +	mov		r7=b5;;
   2.454 +	st8		[r2]=r3,3*8
   2.455 +	st8		[r4]=r5,3*8
   2.456 +	st8		[r6]=r7,3*8;;
   2.457 +
   2.458 +	mov		r3=b6
   2.459 +	mov		r5=b7;;
   2.460 +	st8		[r2]=r3,2*8
   2.461 +	st8		[r4]=r5,2*8;;
   2.462 +
   2.463 +cSaveCRs:
   2.464 +// save CRs
   2.465 +	add		r4=8,r2                  // duplicate r2 in r4
   2.466 +	add		r6=2*8,r2                // duplicate r2 in r4
   2.467 +
   2.468 +	mov		r3=cr.dcr
   2.469 +	mov		r5=cr.itm
   2.470 +	mov		r7=cr.iva;;
   2.471 +
   2.472 +	st8		[r2]=r3,8*8
   2.473 +	st8		[r4]=r5,3*8
   2.474 +	st8		[r6]=r7,3*8;;            // 48 byte rements
   2.475 +
   2.476 +	mov		r3=cr.pta;;
   2.477 +	st8		[r2]=r3,8*8;;            // 64 byte rements
   2.478 +
   2.479 +// if PSR.ic=0, reading interruption registers causes an illegal operation fault
   2.480 +	mov		r3=psr;;
   2.481 +	tbit.nz.unc	p6,p0=r3,PSR_IC;;           // PSI Valid Log bit pos. test
   2.482 +(p6)    st8     [r2]=r0,9*8+160             // increment by 232 byte inc.
   2.483 +begin_skip_intr_regs:
   2.484 +(p6)	br		SkipIntrRegs;;
   2.485 +
   2.486 +	add		r4=8,r2                  // duplicate r2 in r4
   2.487 +	add		r6=2*8,r2                // duplicate r2 in r6
   2.488 +
   2.489 +	mov		r3=cr.ipsr
   2.490 +	mov		r5=cr.isr
   2.491 +	mov		r7=r0;;
   2.492 +	st8		[r2]=r3,3*8
   2.493 +	st8		[r4]=r5,3*8
   2.494 +	st8		[r6]=r7,3*8;;
   2.495 +
   2.496 +	mov		r3=cr.iip
   2.497 +	mov		r5=cr.ifa
   2.498 +	mov		r7=cr.itir;;
   2.499 +	st8		[r2]=r3,3*8
   2.500 +	st8		[r4]=r5,3*8
   2.501 +	st8		[r6]=r7,3*8;;
   2.502 +
   2.503 +	mov		r3=cr.iipa
   2.504 +	mov		r5=cr.ifs
   2.505 +	mov		r7=cr.iim;;
   2.506 +	st8		[r2]=r3,3*8
   2.507 +	st8		[r4]=r5,3*8
   2.508 +	st8		[r6]=r7,3*8;;
   2.509 +
   2.510 +	mov		r3=cr25;;                   // cr.iha
   2.511 +	st8		[r2]=r3,160;;               // 160 byte rement
   2.512 +
   2.513 +SkipIntrRegs:
   2.514 +	st8		[r2]=r0,152;;               // another 152 byte .
   2.515 +
   2.516 +	add		r4=8,r2                     // duplicate r2 in r4
   2.517 +	add		r6=2*8,r2                   // duplicate r2 in r6
   2.518 +
   2.519 +	mov		r3=cr.lid
   2.520 +//	mov		r5=cr.ivr                     // cr.ivr, don't read it
   2.521 +	mov		r7=cr.tpr;;
   2.522 +	st8		[r2]=r3,3*8
   2.523 +	st8		[r4]=r5,3*8
   2.524 +	st8		[r6]=r7,3*8;;
   2.525 +
   2.526 +	mov		r3=r0                       // cr.eoi => cr67
   2.527 +	mov		r5=r0                       // cr.irr0 => cr68
   2.528 +	mov		r7=r0;;                     // cr.irr1 => cr69
   2.529 +	st8		[r2]=r3,3*8
   2.530 +	st8		[r4]=r5,3*8
   2.531 +	st8		[r6]=r7,3*8;;
   2.532 +
   2.533 +	mov		r3=r0                       // cr.irr2 => cr70
   2.534 +	mov		r5=r0                       // cr.irr3 => cr71
   2.535 +	mov		r7=cr.itv;;
   2.536 +	st8		[r2]=r3,3*8
   2.537 +	st8		[r4]=r5,3*8
   2.538 +	st8		[r6]=r7,3*8;;
   2.539 +
   2.540 +	mov		r3=cr.pmv
   2.541 +	mov		r5=cr.cmcv;;
   2.542 +	st8		[r2]=r3,7*8
   2.543 +	st8		[r4]=r5,7*8;;
   2.544 +
   2.545 +	mov		r3=r0                       // cr.lrr0 => cr80
   2.546 +	mov		r5=r0;;                     // cr.lrr1 => cr81
   2.547 +	st8		[r2]=r3,23*8
   2.548 +	st8		[r4]=r5,23*8;;
   2.549 +
   2.550 +	adds		r2=25*8,r2;;
   2.551 +
   2.552 +cSaveARs:
   2.553 +// save ARs
   2.554 +	add		r4=8,r2                  // duplicate r2 in r4
   2.555 +	add		r6=2*8,r2                // duplicate r2 in r6
   2.556 +
   2.557 +	mov		r3=ar.k0
   2.558 +	mov		r5=ar.k1
   2.559 +	mov		r7=ar.k2;;
   2.560 +	st8		[r2]=r3,3*8
   2.561 +	st8		[r4]=r5,3*8
   2.562 +	st8		[r6]=r7,3*8;;
   2.563 +
   2.564 +	mov		r3=ar.k3
   2.565 +	mov		r5=ar.k4
   2.566 +	mov		r7=ar.k5;;
   2.567 +	st8		[r2]=r3,3*8
   2.568 +	st8		[r4]=r5,3*8
   2.569 +	st8		[r6]=r7,3*8;;
   2.570 +
   2.571 +	mov		r3=ar.k6
   2.572 +	mov		r5=ar.k7
   2.573 +	mov		r7=r0;;                     // ar.kr8
   2.574 +	st8		[r2]=r3,10*8
   2.575 +	st8		[r4]=r5,10*8
   2.576 +	st8		[r6]=r7,10*8;;           // rement by 72 bytes
   2.577 +
   2.578 +	mov		r3=ar.rsc
   2.579 +	mov		ar.rsc=r0			    // put RSE in enforced lazy mode
   2.580 +	mov		r5=ar.bsp
   2.581 +	;;
   2.582 +	mov		r7=ar.bspstore;;
   2.583 +	st8		[r2]=r3,3*8
   2.584 +	st8		[r4]=r5,3*8
   2.585 +	st8		[r6]=r7,3*8;;
   2.586 +
   2.587 +	mov		r3=ar.rnat;;
   2.588 +	st8		[r2]=r3,8*13             // increment by 13x8 bytes
   2.589 +
   2.590 +	mov		r3=ar.ccv;;
   2.591 +	st8		[r2]=r3,8*4
   2.592 +
   2.593 +	mov		r3=ar.unat;;
   2.594 +	st8		[r2]=r3,8*4
   2.595 +
   2.596 +	mov		r3=ar.fpsr;;
   2.597 +	st8		[r2]=r3,8*4
   2.598 +
   2.599 +	mov		r3=ar.itc;;
   2.600 +	st8		[r2]=r3,160                 // 160
   2.601 +
   2.602 +	mov		r3=ar.pfs;;
   2.603 +	st8		[r2]=r3,8
   2.604 +
   2.605 +	mov		r3=ar.lc;;
   2.606 +	st8		[r2]=r3,8
   2.607 +
   2.608 +	mov		r3=ar.ec;;
   2.609 +	st8		[r2]=r3
   2.610 +	add		r2=8*62,r2               //padding
   2.611 +
   2.612 +// save RRs
   2.613 +	mov		ar.lc=0x08-1
   2.614 +	movl		r4=0x00;;
   2.615 +
   2.616 +cStRR:
   2.617 +	dep.z		r5=r4,61,3;;
   2.618 +	mov		r3=rr[r5];;
   2.619 +	st8		[r2]=r3,8
   2.620 +	add		r4=1,r4
   2.621 +	br.cloop.sptk.few	cStRR
   2.622 +	;;
   2.623 +end_os_mca_dump:
   2.624 +	br	ia64_os_mca_done_dump;;
   2.625 +
   2.626 +//EndStub//////////////////////////////////////////////////////////////////////
   2.627 +
   2.628 +
   2.629 +//++
   2.630 +// Name:
   2.631 +//       ia64_os_mca_proc_state_restore()
   2.632 +//
   2.633 +// Stub Description:
   2.634 +//
   2.635 +//       This is a stub to restore the saved processor state during MCHK
   2.636 +//
   2.637 +//--
   2.638 +
   2.639 +ia64_os_mca_proc_state_restore:
   2.640 +
   2.641 +// Restore bank1 GR16-31
   2.642 +	GET_IA64_MCA_DATA(r2)
   2.643 +	;;
   2.644 +	add r2 = IA64_MCA_CPU_PROC_STATE_DUMP_OFFSET, r2
   2.645 +
   2.646 +restore_GRs:                                    // restore bank-1 GRs 16-31
   2.647 +	bsw.1;;
   2.648 +	add		r3=16*8,r2;;                // to get to NaT of GR 16-31
   2.649 +	ld8		r3=[r3];;
   2.650 +	mov		ar.unat=r3;;                // first restore NaT
   2.651 +
   2.652 +	ld8.fill	r16=[r2],8;;
   2.653 +	ld8.fill	r17=[r2],8;;
   2.654 +	ld8.fill	r18=[r2],8;;
   2.655 +	ld8.fill	r19=[r2],8;;
   2.656 +	ld8.fill	r20=[r2],8;;
   2.657 +	ld8.fill	r21=[r2],8;;
   2.658 +	ld8.fill	r22=[r2],8;;
   2.659 +	ld8.fill	r23=[r2],8;;
   2.660 +	ld8.fill	r24=[r2],8;;
   2.661 +	ld8.fill	r25=[r2],8;;
   2.662 +	ld8.fill	r26=[r2],8;;
   2.663 +	ld8.fill	r27=[r2],8;;
   2.664 +	ld8.fill	r28=[r2],8;;
   2.665 +	ld8.fill	r29=[r2],8;;
   2.666 +	ld8.fill	r30=[r2],8;;
   2.667 +	ld8.fill	r31=[r2],8;;
   2.668 +
   2.669 +	ld8		r3=[r2],8;;              // increment to skip NaT
   2.670 +	bsw.0;;
   2.671 +
   2.672 +restore_BRs:
   2.673 +	add		r4=8,r2                  // duplicate r2 in r4
   2.674 +	add		r6=2*8,r2;;              // duplicate r2 in r4
   2.675 +
   2.676 +	ld8		r3=[r2],3*8
   2.677 +	ld8		r5=[r4],3*8
   2.678 +	ld8		r7=[r6],3*8;;
   2.679 +	mov		b0=r3
   2.680 +	mov		b1=r5
   2.681 +	mov		b2=r7;;
   2.682 +
   2.683 +	ld8		r3=[r2],3*8
   2.684 +	ld8		r5=[r4],3*8
   2.685 +	ld8		r7=[r6],3*8;;
   2.686 +	mov		b3=r3
   2.687 +	mov		b4=r5
   2.688 +	mov		b5=r7;;
   2.689 +
   2.690 +	ld8		r3=[r2],2*8
   2.691 +	ld8		r5=[r4],2*8;;
   2.692 +	mov		b6=r3
   2.693 +	mov		b7=r5;;
   2.694 +
   2.695 +restore_CRs:
   2.696 +	add		r4=8,r2                  // duplicate r2 in r4
   2.697 +	add		r6=2*8,r2;;              // duplicate r2 in r4
   2.698 +
   2.699 +	ld8		r3=[r2],8*8
   2.700 +	ld8		r5=[r4],3*8
   2.701 +	ld8		r7=[r6],3*8;;            // 48 byte increments
   2.702 +	mov		cr.dcr=r3
   2.703 +	mov		cr.itm=r5
   2.704 +	mov		cr.iva=r7;;
   2.705 +
   2.706 +	ld8		r3=[r2],8*8;;            // 64 byte increments
   2.707 +//      mov		cr.pta=r3
   2.708 +
   2.709 +
   2.710 +// if PSR.ic=1, reading interruption registers causes an illegal operation fault
   2.711 +	mov		r3=psr;;
   2.712 +	tbit.nz.unc	p6,p0=r3,PSR_IC;;           // PSI Valid Log bit pos. test
   2.713 +(p6)    st8     [r2]=r0,9*8+160             // increment by 232 byte inc.
   2.714 +
   2.715 +begin_rskip_intr_regs:
   2.716 +(p6)	br		rSkipIntrRegs;;
   2.717 +
   2.718 +	add		r4=8,r2                  // duplicate r2 in r4
   2.719 +	add		r6=2*8,r2;;              // duplicate r2 in r4
   2.720 +
   2.721 +	ld8		r3=[r2],3*8
   2.722 +	ld8		r5=[r4],3*8
   2.723 +	ld8		r7=[r6],3*8;;
   2.724 +	mov		cr.ipsr=r3
   2.725 +//	mov		cr.isr=r5                   // cr.isr is read only
   2.726 +
   2.727 +	ld8		r3=[r2],3*8
   2.728 +	ld8		r5=[r4],3*8
   2.729 +	ld8		r7=[r6],3*8;;
   2.730 +	mov		cr.iip=r3
   2.731 +	mov		cr.ifa=r5
   2.732 +	mov		cr.itir=r7;;
   2.733 +
   2.734 +	ld8		r3=[r2],3*8
   2.735 +	ld8		r5=[r4],3*8
   2.736 +	ld8		r7=[r6],3*8;;
   2.737 +	mov		cr.iipa=r3
   2.738 +	mov		cr.ifs=r5
   2.739 +	mov		cr.iim=r7
   2.740 +
   2.741 +	ld8		r3=[r2],160;;               // 160 byte increment
   2.742 +	mov		cr.iha=r3
   2.743 +
   2.744 +rSkipIntrRegs:
   2.745 +	ld8		r3=[r2],152;;               // another 152 byte inc.
   2.746 +
   2.747 +	add		r4=8,r2                     // duplicate r2 in r4
   2.748 +	add		r6=2*8,r2;;                 // duplicate r2 in r6
   2.749 +
   2.750 +	ld8		r3=[r2],8*3
   2.751 +	ld8		r5=[r4],8*3
   2.752 +	ld8		r7=[r6],8*3;;
   2.753 +	mov		cr.lid=r3
   2.754 +//	mov		cr.ivr=r5                   // cr.ivr is read only
   2.755 +	mov		cr.tpr=r7;;
   2.756 +
   2.757 +	ld8		r3=[r2],8*3
   2.758 +	ld8		r5=[r4],8*3
   2.759 +	ld8		r7=[r6],8*3;;
   2.760 +//	mov		cr.eoi=r3
   2.761 +//	mov		cr.irr0=r5                  // cr.irr0 is read only
   2.762 +//	mov		cr.irr1=r7;;                // cr.irr1 is read only
   2.763 +
   2.764 +	ld8		r3=[r2],8*3
   2.765 +	ld8		r5=[r4],8*3
   2.766 +	ld8		r7=[r6],8*3;;
   2.767 +//	mov		cr.irr2=r3                  // cr.irr2 is read only
   2.768 +//	mov		cr.irr3=r5                  // cr.irr3 is read only
   2.769 +	mov		cr.itv=r7;;
   2.770 +
   2.771 +	ld8		r3=[r2],8*7
   2.772 +	ld8		r5=[r4],8*7;;
   2.773 +	mov		cr.pmv=r3
   2.774 +	mov		cr.cmcv=r5;;
   2.775 +
   2.776 +	ld8		r3=[r2],8*23
   2.777 +	ld8		r5=[r4],8*23;;
   2.778 +	adds		r2=8*23,r2
   2.779 +	adds		r4=8*23,r4;;
   2.780 +//	mov		cr.lrr0=r3
   2.781 +//	mov		cr.lrr1=r5
   2.782 +
   2.783 +	adds		r2=8*2,r2;;
   2.784 +
   2.785 +restore_ARs:
   2.786 +	add		r4=8,r2                  // duplicate r2 in r4
   2.787 +	add		r6=2*8,r2;;              // duplicate r2 in r4
   2.788 +
   2.789 +	ld8		r3=[r2],3*8
   2.790 +	ld8		r5=[r4],3*8
   2.791 +	ld8		r7=[r6],3*8;;
   2.792 +	mov		ar.k0=r3
   2.793 +	mov		ar.k1=r5
   2.794 +	mov		ar.k2=r7;;
   2.795 +
   2.796 +	ld8		r3=[r2],3*8
   2.797 +	ld8		r5=[r4],3*8
   2.798 +	ld8		r7=[r6],3*8;;
   2.799 +	mov		ar.k3=r3
   2.800 +	mov		ar.k4=r5
   2.801 +	mov		ar.k5=r7;;
   2.802 +
   2.803 +	ld8		r3=[r2],10*8
   2.804 +	ld8		r5=[r4],10*8
   2.805 +	ld8		r7=[r6],10*8;;
   2.806 +	mov		ar.k6=r3
   2.807 +	mov		ar.k7=r5
   2.808 +	;;
   2.809 +
   2.810 +	ld8		r3=[r2],3*8
   2.811 +	ld8		r5=[r4],3*8
   2.812 +	ld8		r7=[r6],3*8;;
   2.813 +//	mov		ar.rsc=r3
   2.814 +//	mov		ar.bsp=r5                   // ar.bsp is read only
   2.815 +	mov		ar.rsc=r0			    // make sure that RSE is in enforced lazy mode
   2.816 +	;;
   2.817 +	mov		ar.bspstore=r7;;
   2.818 +
   2.819 +	ld8		r9=[r2],8*13;;
   2.820 +	mov		ar.rnat=r9
   2.821 +
   2.822 +	mov		ar.rsc=r3
   2.823 +	ld8		r3=[r2],8*4;;
   2.824 +	mov		ar.ccv=r3
   2.825 +
   2.826 +	ld8		r3=[r2],8*4;;
   2.827 +	mov		ar.unat=r3
   2.828 +
   2.829 +	ld8		r3=[r2],8*4;;
   2.830 +	mov		ar.fpsr=r3
   2.831 +
   2.832 +	ld8		r3=[r2],160;;               // 160
   2.833 +//      mov		ar.itc=r3
   2.834 +
   2.835 +	ld8		r3=[r2],8;;
   2.836 +	mov		ar.pfs=r3
   2.837 +
   2.838 +	ld8		r3=[r2],8;;
   2.839 +	mov		ar.lc=r3
   2.840 +
   2.841 +	ld8		r3=[r2];;
   2.842 +	mov		ar.ec=r3
   2.843 +	add		r2=8*62,r2;;             // padding
   2.844 +
   2.845 +restore_RRs:
   2.846 +	mov		r5=ar.lc
   2.847 +	mov		ar.lc=0x08-1
   2.848 +	movl		r4=0x00;;
   2.849 +cStRRr:
   2.850 +	dep.z		r7=r4,61,3
   2.851 +	ld8		r3=[r2],8;;
   2.852 +	mov		rr[r7]=r3                   // what are its access previledges?
   2.853 +	add		r4=1,r4
   2.854 +	br.cloop.sptk.few	cStRRr
   2.855 +	;;
   2.856 +	mov		ar.lc=r5
   2.857 +	;;
   2.858 +end_os_mca_restore:
   2.859 +	br	ia64_os_mca_done_restore;;
   2.860 +
   2.861 +//EndStub//////////////////////////////////////////////////////////////////////
   2.862 +
   2.863 +
   2.864 +// ok, the issue here is that we need to save state information so
   2.865 +// it can be useable by the kernel debugger and show regs routines.
   2.866 +// In order to do this, our best bet is save the current state (plus
   2.867 +// the state information obtain from the MIN_STATE_AREA) into a pt_regs
   2.868 +// format.  This way we can pass it on in a useable format.
   2.869 +//
   2.870 +
   2.871 +//
   2.872 +// SAL to OS entry point for INIT on the monarch processor
   2.873 +// This has been defined for registration purposes with SAL
   2.874 +// as a part of ia64_mca_init.
   2.875 +//
   2.876 +// When we get here, the following registers have been
   2.877 +// set by the SAL for our use
   2.878 +//
   2.879 +//		1. GR1 = OS INIT GP
   2.880 +//		2. GR8 = PAL_PROC physical address
   2.881 +//		3. GR9 = SAL_PROC physical address
   2.882 +//		4. GR10 = SAL GP (physical)
   2.883 +//		5. GR11 = Init Reason
   2.884 +//			0 = Received INIT for event other than crash dump switch
   2.885 +//			1 = Received wakeup at the end of an OS_MCA corrected machine check
   2.886 +//			2 = Received INIT dude to CrashDump switch assertion
   2.887 +//
   2.888 +//		6. GR12 = Return address to location within SAL_INIT procedure
   2.889 +
   2.890 +
   2.891 +GLOBAL_ENTRY(ia64_monarch_init_handler)
   2.892 +	.prologue
   2.893 +	// stash the information the SAL passed to os
   2.894 +	SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(r2)
   2.895 +	;;
   2.896 +	SAVE_MIN_WITH_COVER
   2.897 +	;;
   2.898 +	mov r8=cr.ifa
   2.899 +	mov r9=cr.isr
   2.900 +	adds r3=8,r2				// set up second base pointer
   2.901 +	;;
   2.902 +	SAVE_REST
   2.903 +
   2.904 +// ok, enough should be saved at this point to be dangerous, and supply
   2.905 +// information for a dump
   2.906 +// We need to switch to Virtual mode before hitting the C functions.
   2.907 +
   2.908 +	movl	r2=IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN
   2.909 +	mov	r3=psr	// get the current psr, minimum enabled at this point
   2.910 +	;;
   2.911 +	or	r2=r2,r3
   2.912 +	;;
   2.913 +	movl	r3=IVirtual_Switch
   2.914 +	;;
   2.915 +	mov	cr.iip=r3	// short return to set the appropriate bits
   2.916 +	mov	cr.ipsr=r2	// need to do an rfi to set appropriate bits
   2.917 +	;;
   2.918 +	rfi
   2.919 +	;;
   2.920 +IVirtual_Switch:
   2.921 +	//
   2.922 +	// We should now be running virtual
   2.923 +	//
   2.924 +	// Let's call the C handler to get the rest of the state info
   2.925 +	//
   2.926 +	alloc r14=ar.pfs,0,0,2,0		// now it's safe (must be first in insn group!)
   2.927 +	;;
   2.928 +	adds out0=16,sp				// out0 = pointer to pt_regs
   2.929 +	;;
   2.930 +	DO_SAVE_SWITCH_STACK
   2.931 +	.body
   2.932 +	adds out1=16,sp				// out0 = pointer to switch_stack
   2.933 +
   2.934 +	br.call.sptk.many rp=ia64_init_handler
   2.935 +.ret1:
   2.936 +
   2.937 +return_from_init:
   2.938 +	br.sptk return_from_init
   2.939 +END(ia64_monarch_init_handler)
   2.940 +
   2.941 +//
   2.942 +// SAL to OS entry point for INIT on the slave processor
   2.943 +// This has been defined for registration purposes with SAL
   2.944 +// as a part of ia64_mca_init.
   2.945 +//
   2.946 +
   2.947 +GLOBAL_ENTRY(ia64_slave_init_handler)
   2.948 +1:	br.sptk 1b
   2.949 +END(ia64_slave_init_handler)