ia64/xen-unstable

changeset 13441:7e9077dd4010

[IA64] Passing address of PSCB is not needed

Since the address of PSCB is decided by xenolinux now,
passing address of PSCB to xenolinux is not needed.

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild2.aw
date Wed Jan 17 19:55:48 2007 -0700 (2007-01-17)
parents efaf9c2de07e
children 26c75e0e48ed
files xen/arch/ia64/xen/faults.c xen/arch/ia64/xen/hyperprivop.S
line diff
     1.1 --- a/xen/arch/ia64/xen/faults.c	Wed Jan 17 19:51:40 2007 -0700
     1.2 +++ b/xen/arch/ia64/xen/faults.c	Wed Jan 17 19:55:48 2007 -0700
     1.3 @@ -91,7 +91,6 @@ void reflect_interruption(unsigned long 
     1.4  
     1.5  	regs->cr_iip = ((unsigned long)PSCBX(v, iva) + vector) & ~0xffUL;
     1.6  	regs->cr_ipsr = (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
     1.7 -	regs->r31 = current->domain->arch.shared_info_va + XSI_IPSR_OFS;
     1.8  
     1.9  	v->vcpu_info->evtchn_upcall_mask = 1;
    1.10  	PSCB(v, interrupt_collection_enabled) = 0;
    1.11 @@ -152,7 +151,6 @@ void reflect_event(void)
    1.12  
    1.13  	regs->cr_iip = v->arch.event_callback_ip;
    1.14  	regs->cr_ipsr = (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
    1.15 -	regs->r31 = current->domain->arch.shared_info_va + XSI_IPSR_OFS;
    1.16  
    1.17  	v->vcpu_info->evtchn_upcall_mask = 1;
    1.18  	PSCB(v, interrupt_collection_enabled) = 0;
    1.19 @@ -263,8 +261,6 @@ void ia64_do_page_fault(unsigned long ad
    1.20  		    ((unsigned long)PSCBX(current, iva) + fault) & ~0xffUL;
    1.21  		regs->cr_ipsr =
    1.22  		    (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
    1.23 -		// NOTE: nested trap must NOT pass PSCB address
    1.24 -		//regs->r31 = (unsigned long) &PSCB(current);
    1.25  		perfc_incra(slow_reflect, fault >> 8);
    1.26  		return;
    1.27  	}
     2.1 --- a/xen/arch/ia64/xen/hyperprivop.S	Wed Jan 17 19:51:40 2007 -0700
     2.2 +++ b/xen/arch/ia64/xen/hyperprivop.S	Wed Jan 17 19:55:48 2007 -0700
     2.3 @@ -292,11 +292,9 @@ ENTRY(hyper_ssm_i)
     2.4  	// OK, now all set to go except for switch to virtual bank0
     2.5  	mov r30=r2
     2.6  	mov r29=r3
     2.7 -	mov r28=r4
     2.8  	;;
     2.9  	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18;
    2.10  	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18;;
    2.11 -	adds r4=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18
    2.12  	bsw.1;;
    2.13  	// FIXME?: ar.unat is not really handled correctly,
    2.14  	// but may not matter if the OS is NaT-clean
    2.15 @@ -316,11 +314,9 @@ ENTRY(hyper_ssm_i)
    2.16  	.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
    2.17  	.mem.offset 0,0; st8.spill [r2]=r30,16;
    2.18  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
    2.19 -	mov r31=r4
    2.20  	bsw.0 ;;
    2.21  	mov r2=r30
    2.22  	mov r3=r29
    2.23 -	mov r4=r28
    2.24  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    2.25  	st4 [r20]=r0 ;;
    2.26  	mov pr=r31,-1 ;;
    2.27 @@ -477,14 +473,12 @@ GLOBAL_ENTRY(fast_tick_reflect)
    2.28  	// OK, now all set to go except for switch to virtual bank0
    2.29  	mov r30=r2
    2.30  	mov r29=r3
    2.31 -	mov r27=r4
    2.32  #ifdef HANDLE_AR_UNAT
    2.33  	mov r28=ar.unat;
    2.34  #endif
    2.35  	;;
    2.36  	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18
    2.37  	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18
    2.38 -	adds r4=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18
    2.39  	;;
    2.40  	bsw.1;;
    2.41  	.mem.offset 0,0; st8.spill [r2]=r16,16;
    2.42 @@ -516,13 +510,11 @@ GLOBAL_ENTRY(fast_tick_reflect)
    2.43  	ld8 r22=[r2],16;
    2.44  	ld8 r23=[r3],16;;
    2.45  #endif
    2.46 -	mov r31=r4
    2.47  	;;
    2.48  	bsw.0 ;;
    2.49  	mov r24=ar.unat;
    2.50  	mov r2=r30
    2.51  	mov r3=r29
    2.52 -	mov r4=r27
    2.53  #ifdef HANDLE_AR_UNAT
    2.54  	mov ar.unat=r28;
    2.55  #endif
    2.56 @@ -665,10 +657,8 @@ ENTRY(fast_reflect)
    2.57  #ifdef HANDLE_AR_UNAT
    2.58  	mov r28=ar.unat;
    2.59  #endif
    2.60 -	mov r27=r4
    2.61  	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18;
    2.62  	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18
    2.63 -	adds r4=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18
    2.64  	;;
    2.65  	bsw.1;;
    2.66  	.mem.offset 0,0; st8.spill [r2]=r16,16;
    2.67 @@ -700,7 +690,6 @@ ENTRY(fast_reflect)
    2.68  	ld8 r22=[r2],16;
    2.69  	ld8 r23=[r3],16;;
    2.70  #endif
    2.71 -	mov r31=r4
    2.72  	;;
    2.73  	bsw.0 ;;
    2.74  	mov r24=ar.unat;
    2.75 @@ -709,7 +698,6 @@ ENTRY(fast_reflect)
    2.76  #ifdef HANDLE_AR_UNAT
    2.77  	mov ar.unat=r28;
    2.78  #endif
    2.79 -	mov r4=r27
    2.80  	;;
    2.81  	adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18 ;
    2.82  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    2.83 @@ -1311,13 +1299,8 @@ ENTRY(rfi_with_interrupt)
    2.84  	.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
    2.85  	.mem.offset 0,0; st8.spill [r2]=r30,16;
    2.86  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
    2.87 -	movl r31=XSI_IPSR;;
    2.88  	bsw.0 ;;
    2.89  	mov r2=r30; mov r3=r29;;
    2.90 -#else
    2.91 -	bsw.1;;
    2.92 -	movl r31=XSI_IPSR;;
    2.93 -	bsw.0 ;;
    2.94  #endif
    2.95  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    2.96  	st4 [r20]=r0 ;;